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289569f9 SG |
1 | /* |
2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
7e4ac676 OR |
3 | * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de> |
4 | * Add Alphascale ASM9260 support. | |
289569f9 SG |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/irq.h> | |
41a83e06 | 24 | #include <linux/irqchip.h> |
83a84efc | 25 | #include <linux/irqdomain.h> |
289569f9 | 26 | #include <linux/io.h> |
83a84efc | 27 | #include <linux/of.h> |
8256aa71 | 28 | #include <linux/of_address.h> |
83a84efc | 29 | #include <linux/of_irq.h> |
cec6bae8 | 30 | #include <linux/stmp_device.h> |
4e0a1b8c | 31 | #include <asm/exception.h> |
289569f9 | 32 | |
7e4ac676 OR |
33 | #include "alphascale_asm9260-icoll.h" |
34 | ||
25e34b44 OR |
35 | /* |
36 | * this device provide 4 offsets for each register: | |
37 | * 0x0 - plain read write mode | |
38 | * 0x4 - set mode, OR logic. | |
39 | * 0x8 - clr mode, XOR logic. | |
40 | * 0xc - togle mode. | |
41 | */ | |
42 | #define SET_REG 4 | |
43 | #define CLR_REG 8 | |
44 | ||
289569f9 SG |
45 | #define HW_ICOLL_VECTOR 0x0000 |
46 | #define HW_ICOLL_LEVELACK 0x0010 | |
47 | #define HW_ICOLL_CTRL 0x0020 | |
4e0a1b8c | 48 | #define HW_ICOLL_STAT_OFFSET 0x0070 |
25e34b44 OR |
49 | #define HW_ICOLL_INTERRUPT0 0x0120 |
50 | #define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10) | |
51 | #define BM_ICOLL_INTR_ENABLE BIT(2) | |
289569f9 SG |
52 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 |
53 | ||
83a84efc SG |
54 | #define ICOLL_NUM_IRQS 128 |
55 | ||
7e4ac676 OR |
56 | enum icoll_type { |
57 | ICOLL, | |
58 | ASM9260_ICOLL, | |
59 | }; | |
60 | ||
25e34b44 OR |
61 | struct icoll_priv { |
62 | void __iomem *vector; | |
63 | void __iomem *levelack; | |
64 | void __iomem *ctrl; | |
65 | void __iomem *stat; | |
66 | void __iomem *intr; | |
7e4ac676 OR |
67 | void __iomem *clear; |
68 | enum icoll_type type; | |
25e34b44 OR |
69 | }; |
70 | ||
71 | static struct icoll_priv icoll_priv; | |
83a84efc | 72 | static struct irq_domain *icoll_domain; |
289569f9 | 73 | |
7e4ac676 OR |
74 | /* calculate bit offset depending on number of intterupt per register */ |
75 | static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit) | |
76 | { | |
77 | /* | |
78 | * mask lower part of hwirq to convert it | |
79 | * in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3) | |
80 | */ | |
81 | return bit << ((d->hwirq & 3) << 3); | |
82 | } | |
83 | ||
84 | /* calculate mem offset depending on number of intterupt per register */ | |
85 | static void __iomem *icoll_intr_reg(struct irq_data *d) | |
86 | { | |
87 | /* offset = hwirq / intr_per_reg * 0x10 */ | |
88 | return icoll_priv.intr + ((d->hwirq >> 2) * 0x10); | |
89 | } | |
90 | ||
bf0c1118 | 91 | static void icoll_ack_irq(struct irq_data *d) |
289569f9 SG |
92 | { |
93 | /* | |
94 | * The Interrupt Collector is able to prioritize irqs. | |
95 | * Currently only level 0 is used. So acking can use | |
96 | * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally. | |
97 | */ | |
98 | __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, | |
25e34b44 | 99 | icoll_priv.levelack); |
289569f9 SG |
100 | } |
101 | ||
bf0c1118 | 102 | static void icoll_mask_irq(struct irq_data *d) |
289569f9 | 103 | { |
25e34b44 OR |
104 | __raw_writel(BM_ICOLL_INTR_ENABLE, |
105 | icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); | |
289569f9 SG |
106 | } |
107 | ||
bf0c1118 | 108 | static void icoll_unmask_irq(struct irq_data *d) |
289569f9 | 109 | { |
25e34b44 OR |
110 | __raw_writel(BM_ICOLL_INTR_ENABLE, |
111 | icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); | |
289569f9 SG |
112 | } |
113 | ||
7e4ac676 OR |
114 | static void asm9260_mask_irq(struct irq_data *d) |
115 | { | |
116 | __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE), | |
117 | icoll_intr_reg(d) + CLR_REG); | |
118 | } | |
119 | ||
120 | static void asm9260_unmask_irq(struct irq_data *d) | |
121 | { | |
122 | __raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq), | |
123 | icoll_priv.clear + | |
124 | ASM9260_HW_ICOLL_CLEARn(d->hwirq)); | |
125 | ||
126 | __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE), | |
127 | icoll_intr_reg(d) + SET_REG); | |
128 | } | |
129 | ||
289569f9 | 130 | static struct irq_chip mxs_icoll_chip = { |
bf0c1118 UKK |
131 | .irq_ack = icoll_ack_irq, |
132 | .irq_mask = icoll_mask_irq, | |
133 | .irq_unmask = icoll_unmask_irq, | |
289569f9 SG |
134 | }; |
135 | ||
7e4ac676 OR |
136 | static struct irq_chip asm9260_icoll_chip = { |
137 | .irq_ack = icoll_ack_irq, | |
138 | .irq_mask = asm9260_mask_irq, | |
139 | .irq_unmask = asm9260_unmask_irq, | |
140 | }; | |
141 | ||
4e0a1b8c SG |
142 | asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs) |
143 | { | |
144 | u32 irqnr; | |
145 | ||
25e34b44 OR |
146 | irqnr = __raw_readl(icoll_priv.stat); |
147 | __raw_writel(irqnr, icoll_priv.vector); | |
b3410e5f | 148 | handle_domain_irq(icoll_domain, irqnr, regs); |
4e0a1b8c SG |
149 | } |
150 | ||
83a84efc SG |
151 | static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq, |
152 | irq_hw_number_t hw) | |
289569f9 | 153 | { |
7e4ac676 OR |
154 | struct irq_chip *chip; |
155 | ||
156 | if (icoll_priv.type == ICOLL) | |
157 | chip = &mxs_icoll_chip; | |
158 | else | |
159 | chip = &asm9260_icoll_chip; | |
160 | ||
161 | irq_set_chip_and_handler(virq, chip, handle_level_irq); | |
83a84efc SG |
162 | |
163 | return 0; | |
164 | } | |
289569f9 | 165 | |
96009736 | 166 | static const struct irq_domain_ops icoll_irq_domain_ops = { |
83a84efc SG |
167 | .map = icoll_irq_domain_map, |
168 | .xlate = irq_domain_xlate_onecell, | |
169 | }; | |
170 | ||
25e34b44 OR |
171 | static void __init icoll_add_domain(struct device_node *np, |
172 | int num) | |
173 | { | |
174 | icoll_domain = irq_domain_add_linear(np, num, | |
175 | &icoll_irq_domain_ops, NULL); | |
176 | ||
177 | if (!icoll_domain) | |
178 | panic("%s: unable to create irq domain", np->full_name); | |
179 | } | |
180 | ||
181 | static void __iomem * __init icoll_init_iobase(struct device_node *np) | |
83a84efc | 182 | { |
25e34b44 OR |
183 | void __iomem *icoll_base; |
184 | ||
185 | icoll_base = of_io_request_and_map(np, 0, np->name); | |
edf8fcdc | 186 | if (IS_ERR(icoll_base)) |
e59a8451 | 187 | panic("%s: unable to map resource", np->full_name); |
25e34b44 OR |
188 | return icoll_base; |
189 | } | |
190 | ||
191 | static int __init icoll_of_init(struct device_node *np, | |
192 | struct device_node *interrupt_parent) | |
193 | { | |
194 | void __iomem *icoll_base; | |
195 | ||
7e4ac676 OR |
196 | icoll_priv.type = ICOLL; |
197 | ||
25e34b44 OR |
198 | icoll_base = icoll_init_iobase(np); |
199 | icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR; | |
200 | icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK; | |
201 | icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL; | |
202 | icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET; | |
203 | icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0; | |
7e4ac676 | 204 | icoll_priv.clear = NULL; |
8256aa71 | 205 | |
289569f9 SG |
206 | /* |
207 | * Interrupt Collector reset, which initializes the priority | |
208 | * for each irq to level 0. | |
209 | */ | |
25e34b44 | 210 | stmp_reset_block(icoll_priv.ctrl); |
289569f9 | 211 | |
25e34b44 | 212 | icoll_add_domain(np, ICOLL_NUM_IRQS); |
e59a8451 OR |
213 | |
214 | return 0; | |
83a84efc | 215 | } |
6a8e95b0 | 216 | IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init); |
7e4ac676 OR |
217 | |
218 | static int __init asm9260_of_init(struct device_node *np, | |
219 | struct device_node *interrupt_parent) | |
220 | { | |
221 | void __iomem *icoll_base; | |
222 | int i; | |
223 | ||
224 | icoll_priv.type = ASM9260_ICOLL; | |
225 | ||
226 | icoll_base = icoll_init_iobase(np); | |
227 | icoll_priv.vector = icoll_base + ASM9260_HW_ICOLL_VECTOR; | |
228 | icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK; | |
229 | icoll_priv.ctrl = icoll_base + ASM9260_HW_ICOLL_CTRL; | |
230 | icoll_priv.stat = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET; | |
231 | icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0; | |
232 | icoll_priv.clear = icoll_base + ASM9260_HW_ICOLL_CLEAR0; | |
233 | ||
234 | writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE, | |
235 | icoll_priv.ctrl); | |
236 | /* | |
237 | * ASM9260 don't provide reset bit. So, we need to set level 0 | |
238 | * manually. | |
239 | */ | |
240 | for (i = 0; i < 16 * 0x10; i += 0x10) | |
241 | writel(0, icoll_priv.intr + i); | |
242 | ||
243 | icoll_add_domain(np, ASM9260_NUM_IRQS); | |
c5b63520 | 244 | set_handle_irq(icoll_handle_irq); |
7e4ac676 OR |
245 | |
246 | return 0; | |
247 | } | |
248 | IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init); |