Commit | Line | Data |
---|---|---|
1dbae815 | 1 | /* |
f30c2269 | 2 | * linux/arch/arm/mach-omap2/irq.c |
1dbae815 TL |
3 | * |
4 | * Interrupt handler for OMAP2 boards. | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
8 | * | |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
52fa2120 | 14 | #include <linux/module.h> |
1dbae815 | 15 | #include <linux/init.h> |
1dbae815 | 16 | #include <linux/interrupt.h> |
2e7509e5 | 17 | #include <linux/io.h> |
ee0839c2 | 18 | |
2db14997 | 19 | #include <asm/exception.h> |
52fa2120 BC |
20 | #include <linux/irqdomain.h> |
21 | #include <linux/of.h> | |
22 | #include <linux/of_address.h> | |
c4082d49 | 23 | #include <linux/of_irq.h> |
1dbae815 | 24 | |
8598066c FB |
25 | #include "irqchip.h" |
26 | ||
27 | /* Define these here for now until we drop all board-files */ | |
28 | #define OMAP24XX_IC_BASE 0x480fe000 | |
29 | #define OMAP34XX_IC_BASE 0x48200000 | |
2e7509e5 PW |
30 | |
31 | /* selected INTC register offsets */ | |
32 | ||
33 | #define INTC_REVISION 0x0000 | |
34 | #define INTC_SYSCONFIG 0x0010 | |
35 | #define INTC_SYSSTATUS 0x0014 | |
6ccc4c0d | 36 | #define INTC_SIR 0x0040 |
2e7509e5 | 37 | #define INTC_CONTROL 0x0048 |
0addd61b RN |
38 | #define INTC_PROTECTION 0x004C |
39 | #define INTC_IDLE 0x0050 | |
40 | #define INTC_THRESHOLD 0x0068 | |
41 | #define INTC_MIR0 0x0084 | |
2e7509e5 PW |
42 | #define INTC_MIR_CLEAR0 0x0088 |
43 | #define INTC_MIR_SET0 0x008c | |
44 | #define INTC_PENDING_IRQ0 0x0098 | |
11983656 FB |
45 | #define INTC_PENDING_IRQ1 0x00b8 |
46 | #define INTC_PENDING_IRQ2 0x00d8 | |
47 | #define INTC_PENDING_IRQ3 0x00f8 | |
33c7c7b7 | 48 | #define INTC_ILR0 0x0100 |
1dbae815 | 49 | |
2db14997 | 50 | #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ |
a88ab430 | 51 | #define INTCPS_NR_ILR_REGS 128 |
3003ce3e | 52 | #define INTCPS_NR_MIR_REGS 3 |
2db14997 | 53 | |
1dbae815 TL |
54 | /* |
55 | * OMAP2 has a number of different interrupt controllers, each interrupt | |
56 | * controller is identified as its own "bank". Register definitions are | |
57 | * fairly consistent for each bank, but not all registers are implemented | |
58 | * for each bank.. when in doubt, consult the TRM. | |
59 | */ | |
1dbae815 | 60 | |
0addd61b | 61 | /* Structure to save interrupt controller context */ |
272a8b04 | 62 | struct omap_intc_regs { |
0addd61b RN |
63 | u32 sysconfig; |
64 | u32 protection; | |
65 | u32 idle; | |
66 | u32 threshold; | |
a88ab430 | 67 | u32 ilr[INTCPS_NR_ILR_REGS]; |
0addd61b RN |
68 | u32 mir[INTCPS_NR_MIR_REGS]; |
69 | }; | |
131b48c0 FB |
70 | static struct omap_intc_regs intc_context; |
71 | ||
72 | static struct irq_domain *domain; | |
73 | static void __iomem *omap_irq_base; | |
52b1e129 | 74 | static int omap_nr_pending = 3; |
131b48c0 | 75 | static int omap_nr_irqs = 96; |
0addd61b | 76 | |
2e7509e5 | 77 | /* INTC bank register get/set */ |
71be00c9 | 78 | static void intc_writel(u32 reg, u32 val) |
2e7509e5 | 79 | { |
71be00c9 | 80 | writel_relaxed(val, omap_irq_base + reg); |
2e7509e5 PW |
81 | } |
82 | ||
71be00c9 | 83 | static u32 intc_readl(u32 reg) |
2e7509e5 | 84 | { |
71be00c9 | 85 | return readl_relaxed(omap_irq_base + reg); |
2e7509e5 PW |
86 | } |
87 | ||
131b48c0 FB |
88 | void omap_intc_save_context(void) |
89 | { | |
90 | int i; | |
91 | ||
92 | intc_context.sysconfig = | |
93 | intc_readl(INTC_SYSCONFIG); | |
94 | intc_context.protection = | |
95 | intc_readl(INTC_PROTECTION); | |
96 | intc_context.idle = | |
97 | intc_readl(INTC_IDLE); | |
98 | intc_context.threshold = | |
99 | intc_readl(INTC_THRESHOLD); | |
100 | ||
101 | for (i = 0; i < omap_nr_irqs; i++) | |
102 | intc_context.ilr[i] = | |
103 | intc_readl((INTC_ILR0 + 0x4 * i)); | |
104 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | |
105 | intc_context.mir[i] = | |
106 | intc_readl(INTC_MIR0 + (0x20 * i)); | |
107 | } | |
108 | ||
109 | void omap_intc_restore_context(void) | |
110 | { | |
111 | int i; | |
112 | ||
113 | intc_writel(INTC_SYSCONFIG, intc_context.sysconfig); | |
114 | intc_writel(INTC_PROTECTION, intc_context.protection); | |
115 | intc_writel(INTC_IDLE, intc_context.idle); | |
116 | intc_writel(INTC_THRESHOLD, intc_context.threshold); | |
117 | ||
118 | for (i = 0; i < omap_nr_irqs; i++) | |
119 | intc_writel(INTC_ILR0 + 0x4 * i, | |
120 | intc_context.ilr[i]); | |
121 | ||
122 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | |
123 | intc_writel(INTC_MIR0 + 0x20 * i, | |
124 | intc_context.mir[i]); | |
125 | /* MIRs are saved and restore with other PRCM registers */ | |
126 | } | |
127 | ||
128 | void omap3_intc_prepare_idle(void) | |
129 | { | |
130 | /* | |
131 | * Disable autoidle as it can stall interrupt controller, | |
132 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) | |
133 | */ | |
134 | intc_writel(INTC_SYSCONFIG, 0); | |
135 | } | |
136 | ||
137 | void omap3_intc_resume_idle(void) | |
138 | { | |
139 | /* Re-enable autoidle */ | |
140 | intc_writel(INTC_SYSCONFIG, 1); | |
141 | } | |
142 | ||
1dbae815 | 143 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ |
df303477 | 144 | static void omap_ack_irq(struct irq_data *d) |
1dbae815 | 145 | { |
71be00c9 | 146 | intc_writel(INTC_CONTROL, 0x1); |
1dbae815 TL |
147 | } |
148 | ||
df303477 | 149 | static void omap_mask_ack_irq(struct irq_data *d) |
1dbae815 | 150 | { |
667a11fa | 151 | irq_gc_mask_disable_reg(d); |
df303477 | 152 | omap_ack_irq(d); |
1dbae815 TL |
153 | } |
154 | ||
a88ab430 | 155 | static void __init omap_irq_soft_reset(void) |
1dbae815 TL |
156 | { |
157 | unsigned long tmp; | |
158 | ||
71be00c9 | 159 | tmp = intc_readl(INTC_REVISION) & 0xff; |
a88ab430 | 160 | |
7852ec05 | 161 | pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", |
a88ab430 | 162 | omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs); |
1dbae815 | 163 | |
71be00c9 | 164 | tmp = intc_readl(INTC_SYSCONFIG); |
1dbae815 | 165 | tmp |= 1 << 1; /* soft reset */ |
71be00c9 | 166 | intc_writel(INTC_SYSCONFIG, tmp); |
1dbae815 | 167 | |
71be00c9 | 168 | while (!(intc_readl(INTC_SYSSTATUS) & 0x1)) |
1dbae815 | 169 | /* Wait for reset to complete */; |
375e12ab JY |
170 | |
171 | /* Enable autoidle */ | |
71be00c9 | 172 | intc_writel(INTC_SYSCONFIG, 1 << 0); |
1dbae815 TL |
173 | } |
174 | ||
94434535 JH |
175 | int omap_irq_pending(void) |
176 | { | |
6bd0f16e | 177 | int i; |
94434535 | 178 | |
6bd0f16e FB |
179 | for (i = 0; i < omap_nr_pending; i++) |
180 | if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i))) | |
a88ab430 | 181 | return 1; |
94434535 JH |
182 | return 0; |
183 | } | |
184 | ||
131b48c0 FB |
185 | void omap3_intc_suspend(void) |
186 | { | |
187 | /* A pending interrupt would prevent OMAP from entering suspend */ | |
188 | omap_ack_irq(NULL); | |
189 | } | |
190 | ||
55601c9f FB |
191 | static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base) |
192 | { | |
193 | int ret; | |
194 | int i; | |
195 | ||
196 | ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC", | |
197 | handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE, | |
198 | IRQ_LEVEL, 0); | |
199 | if (ret) { | |
200 | pr_warn("Failed to allocate irq chips\n"); | |
201 | return ret; | |
202 | } | |
203 | ||
204 | for (i = 0; i < omap_nr_pending; i++) { | |
205 | struct irq_chip_generic *gc; | |
206 | struct irq_chip_type *ct; | |
207 | ||
208 | gc = irq_get_domain_generic_chip(d, 32 * i); | |
209 | gc->reg_base = base; | |
210 | ct = gc->chip_types; | |
211 | ||
212 | ct->type = IRQ_TYPE_LEVEL_MASK; | |
213 | ct->handler = handle_level_irq; | |
214 | ||
215 | ct->chip.irq_ack = omap_mask_ack_irq; | |
216 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | |
217 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
218 | ||
219 | ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; | |
220 | ||
221 | ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i; | |
222 | ct->regs.disable = INTC_MIR_SET0 + 32 * i; | |
223 | } | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | static void __init omap_alloc_gc_legacy(void __iomem *base, | |
229 | unsigned int irq_start, unsigned int num) | |
667a11fa TL |
230 | { |
231 | struct irq_chip_generic *gc; | |
232 | struct irq_chip_type *ct; | |
233 | ||
234 | gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, | |
55601c9f | 235 | handle_level_irq); |
667a11fa TL |
236 | ct = gc->chip_types; |
237 | ct->chip.irq_ack = omap_mask_ack_irq; | |
238 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | |
239 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
e3c83c2d | 240 | ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; |
667a11fa | 241 | |
667a11fa TL |
242 | ct->regs.enable = INTC_MIR_CLEAR0; |
243 | ct->regs.disable = INTC_MIR_SET0; | |
244 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
55601c9f | 245 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); |
667a11fa TL |
246 | } |
247 | ||
55601c9f FB |
248 | static int __init omap_init_irq_of(struct device_node *node) |
249 | { | |
250 | int ret; | |
251 | ||
252 | omap_irq_base = of_iomap(node, 0); | |
253 | if (WARN_ON(!omap_irq_base)) | |
254 | return -ENOMEM; | |
255 | ||
256 | domain = irq_domain_add_linear(node, omap_nr_irqs, | |
257 | &irq_generic_chip_ops, NULL); | |
258 | ||
259 | omap_irq_soft_reset(); | |
260 | ||
261 | ret = omap_alloc_gc_of(domain, omap_irq_base); | |
262 | if (ret < 0) | |
263 | irq_domain_remove(domain); | |
264 | ||
265 | return ret; | |
266 | } | |
267 | ||
268 | static int __init omap_init_irq_legacy(u32 base) | |
1dbae815 | 269 | { |
a88ab430 | 270 | int j, irq_base; |
1dbae815 | 271 | |
741e3a89 TL |
272 | omap_irq_base = ioremap(base, SZ_4K); |
273 | if (WARN_ON(!omap_irq_base)) | |
55601c9f | 274 | return -ENOMEM; |
741e3a89 | 275 | |
a74f0a17 | 276 | irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0); |
52fa2120 BC |
277 | if (irq_base < 0) { |
278 | pr_warn("Couldn't allocate IRQ numbers\n"); | |
279 | irq_base = 0; | |
280 | } | |
281 | ||
55601c9f | 282 | domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0, |
a88ab430 | 283 | &irq_domain_simple_ops, NULL); |
1dbae815 | 284 | |
a88ab430 | 285 | omap_irq_soft_reset(); |
667a11fa | 286 | |
a88ab430 | 287 | for (j = 0; j < omap_nr_irqs; j += 32) |
55601c9f FB |
288 | omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32); |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
293 | static int __init omap_init_irq(u32 base, struct device_node *node) | |
294 | { | |
295 | if (node) | |
296 | return omap_init_irq_of(node); | |
297 | else | |
298 | return omap_init_irq_legacy(base); | |
1dbae815 TL |
299 | } |
300 | ||
2aced892 FB |
301 | static asmlinkage void __exception_irq_entry |
302 | omap_intc_handle_irq(struct pt_regs *regs) | |
2db14997 | 303 | { |
d6a7c5c8 | 304 | u32 irqnr = 0; |
698b4853 | 305 | int handled_irq = 0; |
d6a7c5c8 | 306 | int i; |
2db14997 MZ |
307 | |
308 | do { | |
d6a7c5c8 FB |
309 | for (i = 0; i < omap_nr_pending; i++) { |
310 | irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)); | |
311 | if (irqnr) | |
312 | goto out; | |
313 | } | |
2db14997 MZ |
314 | |
315 | out: | |
316 | if (!irqnr) | |
317 | break; | |
318 | ||
11983656 | 319 | irqnr = intc_readl(INTC_SIR); |
2db14997 MZ |
320 | irqnr &= ACTIVEIRQ_MASK; |
321 | ||
52fa2120 BC |
322 | if (irqnr) { |
323 | irqnr = irq_find_mapping(domain, irqnr); | |
2db14997 | 324 | handle_IRQ(irqnr, regs); |
698b4853 | 325 | handled_irq = 1; |
52fa2120 | 326 | } |
2db14997 | 327 | } while (irqnr); |
698b4853 | 328 | |
503b8d12 FB |
329 | /* |
330 | * If an irq is masked or deasserted while active, we will | |
698b4853 | 331 | * keep ending up here with no irq handled. So remove it from |
503b8d12 FB |
332 | * the INTC with an ack. |
333 | */ | |
698b4853 SS |
334 | if (!handled_irq) |
335 | omap_ack_irq(NULL); | |
2db14997 MZ |
336 | } |
337 | ||
a4d3c5d9 FB |
338 | void __init omap2_init_irq(void) |
339 | { | |
a74f0a17 | 340 | omap_nr_irqs = 96; |
52b1e129 | 341 | omap_nr_pending = 3; |
a74f0a17 | 342 | omap_init_irq(OMAP24XX_IC_BASE, NULL); |
2aced892 | 343 | set_handle_irq(omap_intc_handle_irq); |
a4d3c5d9 FB |
344 | } |
345 | ||
346 | void __init omap3_init_irq(void) | |
347 | { | |
a74f0a17 | 348 | omap_nr_irqs = 96; |
52b1e129 | 349 | omap_nr_pending = 3; |
a74f0a17 | 350 | omap_init_irq(OMAP34XX_IC_BASE, NULL); |
2aced892 | 351 | set_handle_irq(omap_intc_handle_irq); |
a4d3c5d9 FB |
352 | } |
353 | ||
354 | void __init ti81xx_init_irq(void) | |
355 | { | |
a74f0a17 | 356 | omap_nr_irqs = 96; |
52b1e129 | 357 | omap_nr_pending = 4; |
a74f0a17 | 358 | omap_init_irq(OMAP34XX_IC_BASE, NULL); |
2aced892 | 359 | set_handle_irq(omap_intc_handle_irq); |
a4d3c5d9 FB |
360 | } |
361 | ||
00b6b031 | 362 | static int __init intc_of_init(struct device_node *node, |
52fa2120 BC |
363 | struct device_node *parent) |
364 | { | |
55601c9f | 365 | int ret; |
a74f0a17 | 366 | |
52b1e129 | 367 | omap_nr_pending = 3; |
a74f0a17 | 368 | omap_nr_irqs = 96; |
52fa2120 BC |
369 | |
370 | if (WARN_ON(!node)) | |
371 | return -ENODEV; | |
372 | ||
52b1e129 | 373 | if (of_device_is_compatible(node, "ti,am33xx-intc")) { |
a74f0a17 | 374 | omap_nr_irqs = 128; |
52b1e129 FB |
375 | omap_nr_pending = 4; |
376 | } | |
470f30de | 377 | |
55601c9f FB |
378 | ret = omap_init_irq(-1, of_node_get(node)); |
379 | if (ret < 0) | |
380 | return ret; | |
52fa2120 | 381 | |
2aced892 | 382 | set_handle_irq(omap_intc_handle_irq); |
b15c76b7 | 383 | |
52fa2120 BC |
384 | return 0; |
385 | } | |
386 | ||
a35db9a4 FB |
387 | IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init); |
388 | IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init); | |
389 | IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init); |