[deliverable/linux.git] / drivers / irqchip / irq-renesas-intc-irqpin.c

/*
 * Renesas INTC External IRQ Pin Driver
 *
 *  Copyright (C) 2013 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_data/irq-renesas-intc-irqpin.h>

#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */

#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
#define INTC_IRQPIN_REG_NR 5

/* INTC external IRQ PIN hardware register access:
 *
 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
 *
 * (*) May be accessed by more than one driver instance - lock needed
 * (**) Read-modify-write access by one driver instance - lock needed
 * (***) Accessed by one driver instance only - no locking needed
 */

struct intc_irqpin_iomem {
	void __iomem *iomem;
	unsigned long (*read)(void __iomem *iomem);
	void (*write)(void __iomem *iomem, unsigned long data);
	int width;
};

struct intc_irqpin_irq {
	int hw_irq;
	int irq;
	struct intc_irqpin_priv *p;
};

struct intc_irqpin_priv {
	struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
	struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
	struct renesas_intc_irqpin_config config;
	unsigned int number_of_irqs;
	struct platform_device *pdev;
	struct irq_chip irq_chip;
	struct irq_domain *irq_domain;
};

static unsigned long intc_irqpin_read32(void __iomem *iomem)
{
	return ioread32(iomem);
}

static unsigned long intc_irqpin_read8(void __iomem *iomem)
{
	return ioread8(iomem);
}

static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
{
	iowrite32(data, iomem);
}

static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
{
	iowrite8(data, iomem);
}

static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
					     int reg)
{
	struct intc_irqpin_iomem *i = &p->iomem[reg];

	return i->read(i->iomem);
}

static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
				     int reg, unsigned long data)
{
	struct intc_irqpin_iomem *i = &p->iomem[reg];

	i->write(i->iomem, data);
}

static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
						   int reg, int hw_irq)
{
	return BIT((p->iomem[reg].width - 1) - hw_irq);
}

static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
					       int reg, int hw_irq)
{
	intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
}

static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */

static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
					  int reg, int shift,
					  int width, int value)
{
	unsigned long flags;
	unsigned long tmp;

	raw_spin_lock_irqsave(&intc_irqpin_lock, flags);

	tmp = intc_irqpin_read(p, reg);
	tmp &= ~(((1 << width) - 1) << shift);
	tmp |= value << shift;
	intc_irqpin_write(p, reg, tmp);

	raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
}

static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
					 int irq, int do_mask)
{
	int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
	int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */

	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
				      shift, bitfield_width,
				      do_mask ? 0 : (1 << bitfield_width) - 1);
}

static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
{
	int bitfield_width = p->config.sense_bitfield_width;
	int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */

	dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);

	if (value >= (1 << bitfield_width))
		return -EINVAL;

	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
				      bitfield_width, value);
	return 0;
}

static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
{
	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
		str, i->irq, i->hw_irq,
		irq_find_mapping(i->p->irq_domain, i->hw_irq));
}

static void intc_irqpin_irq_enable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "enable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
}

static void intc_irqpin_irq_disable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "disable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
}

static void intc_irqpin_irq_enable_force(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int irq = p->irq[irqd_to_hwirq(d)].irq;

	intc_irqpin_irq_enable(d);
	irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
}

static void intc_irqpin_irq_disable_force(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int irq = p->irq[irqd_to_hwirq(d)].irq;

	irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
	intc_irqpin_irq_disable(d);
}

#define INTC_IRQ_SENSE_VALID 0x10
#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)

static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
	[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
	[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
	[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
	[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
};

static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
{
	unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);

	if (!(value & INTC_IRQ_SENSE_VALID))
		return -EINVAL;

	return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
				     value ^ INTC_IRQ_SENSE_VALID);
}

static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
{
	struct intc_irqpin_irq *i = dev_id;
	struct intc_irqpin_priv *p = i->p;
	unsigned long bit;

	intc_irqpin_dbg(i, "demux1");
	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);

	if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
		intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
		intc_irqpin_dbg(i, "demux2");
		generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq));
		return IRQ_HANDLED;
	}
	return IRQ_NONE;
}

static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
				      irq_hw_number_t hw)
{
	struct intc_irqpin_priv *p = h->host_data;

	intc_irqpin_dbg(&p->irq[hw], "map");
	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	set_irq_flags(virq, IRQF_VALID); /* kill me now */
	return 0;
}

static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
	.map	= intc_irqpin_irq_domain_map,
};

static int intc_irqpin_probe(struct platform_device *pdev)
{
	struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data;
	struct intc_irqpin_priv *p;
	struct intc_irqpin_iomem *i;
	struct resource *io[INTC_IRQPIN_REG_NR];
	struct resource *irq;
	struct irq_chip *irq_chip;
	void (*enable_fn)(struct irq_data *d);
	void (*disable_fn)(struct irq_data *d);
	const char *name = dev_name(&pdev->dev);
	int ret;
	int k;

	p = kzalloc(sizeof(*p), GFP_KERNEL);
	if (!p) {
		dev_err(&pdev->dev, "failed to allocate driver data\n");
		ret = -ENOMEM;
		goto err0;
	}

	/* deal with driver instance configuration */
	if (pdata)
		memcpy(&p->config, pdata, sizeof(*pdata));
	if (!p->config.sense_bitfield_width)
		p->config.sense_bitfield_width = 4; /* default to 4 bits */

	p->pdev = pdev;
	platform_set_drvdata(pdev, p);

	/* get hold of manadatory IOMEM */
	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
		io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
		if (!io[k]) {
			dev_err(&pdev->dev, "not enough IOMEM resources\n");
			ret = -EINVAL;
			goto err1;
		}
	}

	/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
	for (k = 0; k < INTC_IRQPIN_MAX; k++) {
		irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
		if (!irq)
			break;

		p->irq[k].hw_irq = k;
		p->irq[k].p = p;
		p->irq[k].irq = irq->start;
	}

	p->number_of_irqs = k;
	if (p->number_of_irqs < 1) {
		dev_err(&pdev->dev, "not enough IRQ resources\n");
		ret = -EINVAL;
		goto err1;
	}

	/* ioremap IOMEM and setup read/write callbacks */
	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
		i = &p->iomem[k];

		switch (resource_size(io[k])) {
		case 1:
			i->width = 8;
			i->read = intc_irqpin_read8;
			i->write = intc_irqpin_write8;
			break;
		case 4:
			i->width = 32;
			i->read = intc_irqpin_read32;
			i->write = intc_irqpin_write32;
			break;
		default:
			dev_err(&pdev->dev, "IOMEM size mismatch\n");
			ret = -EINVAL;
			goto err2;
		}

		i->iomem = ioremap_nocache(io[k]->start, resource_size(io[k]));
		if (!i->iomem) {
			dev_err(&pdev->dev, "failed to remap IOMEM\n");
			ret = -ENXIO;
			goto err2;
		}
	}

	/* mask all interrupts using priority */
	for (k = 0; k < p->number_of_irqs; k++)
		intc_irqpin_mask_unmask_prio(p, k, 1);

	/* use more severe masking method if requested */
	if (p->config.control_parent) {
		enable_fn = intc_irqpin_irq_enable_force;
		disable_fn = intc_irqpin_irq_disable_force;
	} else {
		enable_fn = intc_irqpin_irq_enable;
		disable_fn = intc_irqpin_irq_disable;
	}

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->irq_mask = disable_fn;
	irq_chip->irq_unmask = enable_fn;
	irq_chip->irq_enable = enable_fn;
	irq_chip->irq_disable = disable_fn;
	irq_chip->irq_set_type = intc_irqpin_irq_set_type;
	irq_chip->flags	= IRQCHIP_SKIP_SET_WAKE;

	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
					      p->number_of_irqs,
					      p->config.irq_base,
					      &intc_irqpin_irq_domain_ops, p);
	if (!p->irq_domain) {
		ret = -ENXIO;
		dev_err(&pdev->dev, "cannot initialize irq domain\n");
		goto err2;
	}

	/* request and set priority on interrupts one by one */
	for (k = 0; k < p->number_of_irqs; k++) {
		if (request_irq(p->irq[k].irq, intc_irqpin_irq_handler,
				0, name, &p->irq[k])) {
			dev_err(&pdev->dev, "failed to request low IRQ\n");
			ret = -ENOENT;
			goto err3;
		}
		intc_irqpin_mask_unmask_prio(p, k, 0);
	}

	dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);

	/* warn in case of mismatch if irq base is specified */
	if (p->config.irq_base) {
		k = irq_find_mapping(p->irq_domain, 0);
		if (p->config.irq_base != k)
			dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
				 p->config.irq_base, k);
	}

	return 0;

err3:
	for (; k >= 0; k--)
		free_irq(p->irq[k - 1].irq, &p->irq[k - 1]);

	irq_domain_remove(p->irq_domain);
err2:
	for (k = 0; k < INTC_IRQPIN_REG_NR; k++)
		iounmap(p->iomem[k].iomem);
err1:
	kfree(p);
err0:
	return ret;
}

static int intc_irqpin_remove(struct platform_device *pdev)
{
	struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
	int k;

	for (k = 0; k < p->number_of_irqs; k++)
		free_irq(p->irq[k].irq, &p->irq[k]);

	irq_domain_remove(p->irq_domain);

	for (k = 0; k < INTC_IRQPIN_REG_NR; k++)
		iounmap(p->iomem[k].iomem);

	kfree(p);
	return 0;
}

static struct platform_driver intc_irqpin_device_driver = {
	.probe		= intc_irqpin_probe,
	.remove		= intc_irqpin_remove,
	.driver		= {
		.name	= "renesas_intc_irqpin",
	}
};

static int __init intc_irqpin_init(void)
{
	return platform_driver_register(&intc_irqpin_device_driver);
}
postcore_initcall(intc_irqpin_init);

static void __exit intc_irqpin_exit(void)
{
	platform_driver_unregister(&intc_irqpin_device_driver);
}
module_exit(intc_irqpin_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
44358048 MD	1	/*
	2	* Renesas INTC External IRQ Pin Driver
	3	*
	4	* Copyright (C) 2013 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
	25	#include <linux/io.h>
	26	#include <linux/irq.h>
	27	#include <linux/irqdomain.h>
	28	#include <linux/err.h>
	29	#include <linux/slab.h>
	30	#include <linux/module.h>
	31	#include <linux/platform_data/irq-renesas-intc-irqpin.h>
	32
	33	#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
	34
	35	#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
	36	#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
	37	#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
	38	#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
	39	#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
	40	#define INTC_IRQPIN_REG_NR 5
	41
	42	/* INTC external IRQ PIN hardware register access:
	43	*
	44	* SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
	45	* PRIO is read-write 32-bit with 4-bits per IRQ (**)
	46	* SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
	47	* MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
	48	* CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
	49	*
	50	* (*) May be accessed by more than one driver instance - lock needed
	51	* (**) Read-modify-write access by one driver instance - lock needed
	52	* (***) Accessed by one driver instance only - no locking needed
	53	*/
	54
	55	struct intc_irqpin_iomem {
	56	void __iomem *iomem;
	57	unsigned long (read)(void __iomem iomem);
	58	void (write)(void __iomem iomem, unsigned long data);
	59	int width;
862d3098	60	};
44358048 MD	61
	62	struct intc_irqpin_irq {
	63	int hw_irq;
	64	int irq;
	65	struct intc_irqpin_priv *p;
862d3098	66	};
44358048 MD	67
	68	struct intc_irqpin_priv {
	69	struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
	70	struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
	71	struct renesas_intc_irqpin_config config;
	72	unsigned int number_of_irqs;
	73	struct platform_device *pdev;
	74	struct irq_chip irq_chip;
	75	struct irq_domain *irq_domain;
	76	};
	77
	78	static unsigned long intc_irqpin_read32(void __iomem *iomem)
	79	{
	80	return ioread32(iomem);
	81	}
	82
	83	static unsigned long intc_irqpin_read8(void __iomem *iomem)
	84	{
	85	return ioread8(iomem);
	86	}
	87
	88	static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
	89	{
	90	iowrite32(data, iomem);
	91	}
	92
	93	static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
	94	{
	95	iowrite8(data, iomem);
	96	}
	97
	98	static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
	99	int reg)
	100	{
	101	struct intc_irqpin_iomem *i = &p->iomem[reg];
862d3098	102
44358048 MD	103	return i->read(i->iomem);
	104	}
	105
	106	static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
	107	int reg, unsigned long data)
	108	{
	109	struct intc_irqpin_iomem *i = &p->iomem[reg];
862d3098	110
44358048 MD	111	i->write(i->iomem, data);
	112	}
	113
	114	static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
	115	int reg, int hw_irq)
	116	{
	117	return BIT((p->iomem[reg].width - 1) - hw_irq);
	118	}
	119
	120	static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
	121	int reg, int hw_irq)
	122	{
	123	intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
	124	}
	125
	126	static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
	127
	128	static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
	129	int reg, int shift,
	130	int width, int value)
	131	{
	132	unsigned long flags;
	133	unsigned long tmp;
	134
	135	raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
	136
	137	tmp = intc_irqpin_read(p, reg);
	138	tmp &= ~(((1 << width) - 1) << shift);
	139	tmp \|= value << shift;
	140	intc_irqpin_write(p, reg, tmp);
	141
	142	raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
	143	}
	144
	145	static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
	146	int irq, int do_mask)
	147	{
	148	int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
	149	int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
	150
	151	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
	152	shift, bitfield_width,
	153	do_mask ? 0 : (1 << bitfield_width) - 1);
	154	}
	155
	156	static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
	157	{
	158	int bitfield_width = p->config.sense_bitfield_width;
	159	int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
	160
	161	dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
	162
	163	if (value >= (1 << bitfield_width))
	164	return -EINVAL;
	165
	166	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
	167	bitfield_width, value);
	168	return 0;
	169	}
	170
	171	static void intc_irqpin_dbg(struct intc_irqpin_irq i, char str)
	172	{
	173	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
	174	str, i->irq, i->hw_irq,
175	irq_find_mapping(i->p->irq_domain, i->hw_irq));
176	}
177
178	static void intc_irqpin_irq_enable(struct irq_data *d)
179	{
180	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
181	int hw_irq = irqd_to_hwirq(d);
182
183	intc_irqpin_dbg(&p->irq[hw_irq], "enable");
184	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
185	}
186
187	static void intc_irqpin_irq_disable(struct irq_data *d)
188	{
189	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
190	int hw_irq = irqd_to_hwirq(d);
191
192	intc_irqpin_dbg(&p->irq[hw_irq], "disable");
193	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
194	}
195
196	static void intc_irqpin_irq_enable_force(struct irq_data *d)
197	{
198	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
199	int irq = p->irq[irqd_to_hwirq(d)].irq;
200
201	intc_irqpin_irq_enable(d);
202	irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
203	}
204
205	static void intc_irqpin_irq_disable_force(struct irq_data *d)
206	{
207	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
208	int irq = p->irq[irqd_to_hwirq(d)].irq;
209
210	irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
211	intc_irqpin_irq_disable(d);
212	}
213
214	#define INTC_IRQ_SENSE_VALID 0x10
215	#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
216
217	static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
218	[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
219	[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
220	[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
221	[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
222	[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
223	};
224
225	static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
226	{
227	unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
228	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
229
230	if (!(value & INTC_IRQ_SENSE_VALID))
231	return -EINVAL;
232
233	return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
234	value ^ INTC_IRQ_SENSE_VALID);
235	}
236
237	static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
238	{
239	struct intc_irqpin_irq *i = dev_id;
240	struct intc_irqpin_priv *p = i->p;
241	unsigned long bit;
242
243	intc_irqpin_dbg(i, "demux1");
244	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
245
246	if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
247	intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
248	intc_irqpin_dbg(i, "demux2");
249	generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq));
250	return IRQ_HANDLED;
251	}
252	return IRQ_NONE;
253	}
254
255	static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
256	irq_hw_number_t hw)
257	{
258	struct intc_irqpin_priv *p = h->host_data;
259
260	intc_irqpin_dbg(&p->irq[hw], "map");
261	irq_set_chip_data(virq, h->host_data);
262	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
263	set_irq_flags(virq, IRQF_VALID); /* kill me now */
264	return 0;
265	}
266
267	static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
268	.map = intc_irqpin_irq_domain_map,
269	};
270
271	static int intc_irqpin_probe(struct platform_device *pdev)
272	{
273	struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data;
274	struct intc_irqpin_priv *p;
275	struct intc_irqpin_iomem *i;
276	struct resource *io[INTC_IRQPIN_REG_NR];
277	struct resource *irq;
278	struct irq_chip *irq_chip;
279	void (enable_fn)(struct irq_data d);
280	void (disable_fn)(struct irq_data d);
281	const char *name = dev_name(&pdev->dev);
282	int ret;
283	int k;
284
285	p = kzalloc(sizeof(*p), GFP_KERNEL);
286	if (!p) {
287	dev_err(&pdev->dev, "failed to allocate driver data\n");
288	ret = -ENOMEM;
289	goto err0;
290	}
291
292	/* deal with driver instance configuration */
293	if (pdata)
294	memcpy(&p->config, pdata, sizeof(*pdata));
295	if (!p->config.sense_bitfield_width)
296	p->config.sense_bitfield_width = 4; /* default to 4 bits */
297
298	p->pdev = pdev;
299	platform_set_drvdata(pdev, p);
300
301	/* get hold of manadatory IOMEM */
302	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
303	io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
304	if (!io[k]) {
305	dev_err(&pdev->dev, "not enough IOMEM resources\n");
306	ret = -EINVAL;
307	goto err1;
308	}
309	}
310
311	/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
312	for (k = 0; k < INTC_IRQPIN_MAX; k++) {
313	irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
314	if (!irq)
315	break;
316
317	p->irq[k].hw_irq = k;
318	p->irq[k].p = p;
319	p->irq[k].irq = irq->start;
320	}
321
322	p->number_of_irqs = k;
323	if (p->number_of_irqs < 1) {
324	dev_err(&pdev->dev, "not enough IRQ resources\n");
325	ret = -EINVAL;
326	goto err1;
327	}
328
329	/* ioremap IOMEM and setup read/write callbacks */
330	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
331	i = &p->iomem[k];
332
333	switch (resource_size(io[k])) {
334	case 1:
335	i->width = 8;
336	i->read = intc_irqpin_read8;
337	i->write = intc_irqpin_write8;
338	break;
339	case 4:
340	i->width = 32;
341	i->read = intc_irqpin_read32;
342	i->write = intc_irqpin_write32;
343	break;
344	default:
345	dev_err(&pdev->dev, "IOMEM size mismatch\n");
346	ret = -EINVAL;
347	goto err2;
348	}
349
350	i->iomem = ioremap_nocache(io[k]->start, resource_size(io[k]));
351	if (!i->iomem) {
352	dev_err(&pdev->dev, "failed to remap IOMEM\n");
353	ret = -ENXIO;
354	goto err2;
355	}
356	}
357
358	/* mask all interrupts using priority */
359	for (k = 0; k < p->number_of_irqs; k++)
360	intc_irqpin_mask_unmask_prio(p, k, 1);
361
362	/* use more severe masking method if requested */
363	if (p->config.control_parent) {
364	enable_fn = intc_irqpin_irq_enable_force;
365	disable_fn = intc_irqpin_irq_disable_force;
366	} else {
367	enable_fn = intc_irqpin_irq_enable;
368	disable_fn = intc_irqpin_irq_disable;
369	}
370
371	irq_chip = &p->irq_chip;
372	irq_chip->name = name;
373	irq_chip->irq_mask = disable_fn;
374	irq_chip->irq_unmask = enable_fn;
375	irq_chip->irq_enable = enable_fn;
376	irq_chip->irq_disable = disable_fn;
377	irq_chip->irq_set_type = intc_irqpin_irq_set_type;
378	irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
379
380	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
381	p->number_of_irqs,
382	p->config.irq_base,
383	&intc_irqpin_irq_domain_ops, p);
384	if (!p->irq_domain) {
385	ret = -ENXIO;
386	dev_err(&pdev->dev, "cannot initialize irq domain\n");
387	goto err2;
388	}
389
390	/* request and set priority on interrupts one by one */
391	for (k = 0; k < p->number_of_irqs; k++) {
392	if (request_irq(p->irq[k].irq, intc_irqpin_irq_handler,
393	0, name, &p->irq[k])) {
394	dev_err(&pdev->dev, "failed to request low IRQ\n");
395	ret = -ENOENT;
396	goto err3;
397	}
398	intc_irqpin_mask_unmask_prio(p, k, 0);
399	}
400
401	dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
402
403	/* warn in case of mismatch if irq base is specified */
404	if (p->config.irq_base) {
405	k = irq_find_mapping(p->irq_domain, 0);
406	if (p->config.irq_base != k)
407	dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
408	p->config.irq_base, k);
409	}
862d3098	410
44358048 MD	411	return 0;
	412
	413	err3:
	414	for (; k >= 0; k--)
	415	free_irq(p->irq[k - 1].irq, &p->irq[k - 1]);
	416
	417	irq_domain_remove(p->irq_domain);
	418	err2:
	419	for (k = 0; k < INTC_IRQPIN_REG_NR; k++)
	420	iounmap(p->iomem[k].iomem);
	421	err1:
	422	kfree(p);
	423	err0:
	424	return ret;
	425	}
	426
	427	static int intc_irqpin_remove(struct platform_device *pdev)
	428	{
	429	struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
	430	int k;
	431
	432	for (k = 0; k < p->number_of_irqs; k++)
	433	free_irq(p->irq[k].irq, &p->irq[k]);
	434
	435	irq_domain_remove(p->irq_domain);
	436
	437	for (k = 0; k < INTC_IRQPIN_REG_NR; k++)
	438	iounmap(p->iomem[k].iomem);
	439
	440	kfree(p);
	441	return 0;
	442	}
	443
	444	static struct platform_driver intc_irqpin_device_driver = {
	445	.probe = intc_irqpin_probe,
	446	.remove = intc_irqpin_remove,
	447	.driver = {
	448	.name = "renesas_intc_irqpin",
	449	}
	450	};
	451
	452	static int __init intc_irqpin_init(void)
	453	{
	454	return platform_driver_register(&intc_irqpin_device_driver);
	455	}
	456	postcore_initcall(intc_irqpin_init);
	457
	458	static void __exit intc_irqpin_exit(void)
	459	{
	460	platform_driver_unregister(&intc_irqpin_device_driver);
	461	}
	462	module_exit(intc_irqpin_exit);
	463
	464	MODULE_AUTHOR("Magnus Damm");
	465	MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
	466	MODULE_LICENSE("GPL v2");