[deliverable/linux.git] / drivers / irqchip / spear-shirq.c

/*
 * SPEAr platform shared irq layer source file
 *
 * Copyright (C) 2009-2012 ST Microelectronics
 * Viresh Kumar <viresh.linux@gmail.com>
 *
 * Copyright (C) 2012 ST Microelectronics
 * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/err.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/spinlock.h>

#include "irqchip.h"

/*
 * struct shirq_regs: shared irq register configuration
 *
 * enb_reg: enable register offset
 * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
 * status_reg: status register offset
 * status_reg_mask: status register valid mask
 * clear_reg: clear register offset
 * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
 */
struct shirq_regs {
	u32 enb_reg;
	u32 reset_to_enb;
	u32 status_reg;
	u32 clear_reg;
	u32 reset_to_clear;
};

/*
 * struct spear_shirq: shared irq structure
 *
 * base:	Base register address
 * regs:	Register configuration for shared irq block
 * virq_base:	Base virtual interrupt number
 * nr_irqs:	Number of interrupts handled by this block
 * offset:	Bit offset of the first interrupt
 * disabled:	Group is disabled, but accounted
 */
struct spear_shirq {
	void __iomem		*base;
	struct shirq_regs	regs;
	u32			virq_base;
	u32			nr_irqs;
	u32			offset;
	bool			disabled;
};

static DEFINE_SPINLOCK(lock);

/* spear300 shared irq registers offsets and masks */
#define SPEAR300_INT_ENB_MASK_REG	0x54
#define SPEAR300_INT_STS_MASK_REG	0x58

static struct spear_shirq spear300_shirq_ras1 = {
	.offset		= 0,
	.nr_irqs	= 9,
	.regs = {
		.enb_reg = SPEAR300_INT_ENB_MASK_REG,
		.status_reg = SPEAR300_INT_STS_MASK_REG,
		.clear_reg = -1,
	},
};

static struct spear_shirq *spear300_shirq_blocks[] = {
	&spear300_shirq_ras1,
};

/* spear310 shared irq registers offsets and masks */
#define SPEAR310_INT_STS_MASK_REG	0x04

static struct spear_shirq spear310_shirq_ras1 = {
	.offset		= 0,
	.nr_irqs	= 8,
	.regs = {
		.enb_reg = -1,
		.status_reg = SPEAR310_INT_STS_MASK_REG,
		.clear_reg = -1,
	},
};

static struct spear_shirq spear310_shirq_ras2 = {
	.offset		= 8,
	.nr_irqs	= 5,
	.regs = {
		.enb_reg = -1,
		.status_reg = SPEAR310_INT_STS_MASK_REG,
		.clear_reg = -1,
	},
};

static struct spear_shirq spear310_shirq_ras3 = {
	.offset		= 13,
	.nr_irqs	= 1,
	.regs = {
		.enb_reg = -1,
		.status_reg = SPEAR310_INT_STS_MASK_REG,
		.clear_reg = -1,
	},
};

static struct spear_shirq spear310_shirq_intrcomm_ras = {
	.offset		= 14,
	.nr_irqs	= 3,
	.regs = {
		.enb_reg = -1,
		.status_reg = SPEAR310_INT_STS_MASK_REG,
		.clear_reg = -1,
	},
};

static struct spear_shirq *spear310_shirq_blocks[] = {
	&spear310_shirq_ras1,
	&spear310_shirq_ras2,
	&spear310_shirq_ras3,
	&spear310_shirq_intrcomm_ras,
};

/* spear320 shared irq registers offsets and masks */
#define SPEAR320_INT_STS_MASK_REG		0x04
#define SPEAR320_INT_CLR_MASK_REG		0x04
#define SPEAR320_INT_ENB_MASK_REG		0x08

static struct spear_shirq spear320_shirq_ras3 = {
	.offset		= 0,
	.nr_irqs	= 7,
	.disabled	= 1,
	.regs = {
		.enb_reg = SPEAR320_INT_ENB_MASK_REG,
		.reset_to_enb = 1,
		.status_reg = SPEAR320_INT_STS_MASK_REG,
		.clear_reg = SPEAR320_INT_CLR_MASK_REG,
		.reset_to_clear = 1,
	},
};

static struct spear_shirq spear320_shirq_ras1 = {
	.offset		= 7,
	.nr_irqs	= 3,
	.regs = {
		.enb_reg = -1,
		.status_reg = SPEAR320_INT_STS_MASK_REG,
		.clear_reg = SPEAR320_INT_CLR_MASK_REG,
		.reset_to_clear = 1,
	},
};

static struct spear_shirq spear320_shirq_ras2 = {
	.offset		= 10,
	.nr_irqs	= 1,
	.regs = {
		.enb_reg = -1,
		.status_reg = SPEAR320_INT_STS_MASK_REG,
		.clear_reg = SPEAR320_INT_CLR_MASK_REG,
		.reset_to_clear = 1,
	},
};

static struct spear_shirq spear320_shirq_intrcomm_ras = {
	.offset		= 11,
	.nr_irqs	= 11,
	.regs = {
		.enb_reg = -1,
		.status_reg = SPEAR320_INT_STS_MASK_REG,
		.clear_reg = SPEAR320_INT_CLR_MASK_REG,
		.reset_to_clear = 1,
	},
};

static struct spear_shirq *spear320_shirq_blocks[] = {
	&spear320_shirq_ras3,
	&spear320_shirq_ras1,
	&spear320_shirq_ras2,
	&spear320_shirq_intrcomm_ras,
};

static void shirq_irq_mask_unmask(struct irq_data *d, bool mask)
{
	struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
	u32 val, offset = d->irq - shirq->virq_base;
	unsigned long flags;

	if (shirq->regs.enb_reg == -1)
		return;

	spin_lock_irqsave(&lock, flags);
	val = readl(shirq->base + shirq->regs.enb_reg);

	if (mask ^ shirq->regs.reset_to_enb)
		val &= ~(0x1 << shirq->offset << offset);
	else
		val |= 0x1 << shirq->offset << offset;

	writel(val, shirq->base + shirq->regs.enb_reg);
	spin_unlock_irqrestore(&lock, flags);

}

static void shirq_irq_mask(struct irq_data *d)
{
	shirq_irq_mask_unmask(d, 1);
}

static void shirq_irq_unmask(struct irq_data *d)
{
	shirq_irq_mask_unmask(d, 0);
}

static struct irq_chip shirq_chip = {
	.name		= "spear-shirq",
	.irq_ack	= shirq_irq_mask,
	.irq_mask	= shirq_irq_mask,
	.irq_unmask	= shirq_irq_unmask,
};

static void shirq_handler(unsigned irq, struct irq_desc *desc)
{
	struct spear_shirq *shirq = irq_get_handler_data(irq);
	struct irq_data *idata = irq_desc_get_irq_data(desc);
	struct irq_chip *chip = irq_data_get_irq_chip(idata);
	u32 i, j, val, mask, tmp;

	chip->irq_ack(idata);

	mask = ((0x1 << shirq->nr_irqs) - 1) << shirq->offset;
	while ((val = readl(shirq->base + shirq->regs.status_reg) &
				mask)) {

		val >>= shirq->offset;
		for (i = 0, j = 1; i < shirq->nr_irqs; i++, j <<= 1) {

			if (!(j & val))
				continue;

			generic_handle_irq(shirq->virq_base + i);

			/* clear interrupt */
			if (shirq->regs.clear_reg == -1)
				continue;

			tmp = readl(shirq->base + shirq->regs.clear_reg);
			if (shirq->regs.reset_to_clear)
				tmp &= ~(j << shirq->offset);
			else
				tmp |= (j << shirq->offset);
			writel(tmp, shirq->base + shirq->regs.clear_reg);
		}
	}
	chip->irq_unmask(idata);
}

static void __init spear_shirq_register(struct spear_shirq *shirq,
					int parent_irq)
{
	int i;

	if (shirq->disabled)
		return;

	irq_set_chained_handler(parent_irq, shirq_handler);
	irq_set_handler_data(parent_irq, shirq);

	for (i = 0; i < shirq->nr_irqs; i++) {
		irq_set_chip_and_handler(shirq->virq_base + i,
					 &shirq_chip, handle_simple_irq);
		set_irq_flags(shirq->virq_base + i, IRQF_VALID);
		irq_set_chip_data(shirq->virq_base + i, shirq);
	}
}

static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
		struct device_node *np)
{
	int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0;
	struct irq_domain *shirq_domain;
	void __iomem *base;

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("%s: failed to map shirq registers\n", __func__);
		return -ENXIO;
	}

	for (i = 0; i < block_nr; i++)
		nr_irqs += shirq_blocks[i]->nr_irqs;

	virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
	if (IS_ERR_VALUE(virq_base)) {
		pr_err("%s: irq desc alloc failed\n", __func__);
		goto err_unmap;
	}

	shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0,
			&irq_domain_simple_ops, NULL);
	if (WARN_ON(!shirq_domain)) {
		pr_warn("%s: irq domain init failed\n", __func__);
		goto err_free_desc;
	}

	for (i = 0; i < block_nr; i++) {
		shirq_blocks[i]->base = base;
		shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain,
				hwirq);

		parent_irq = irq_of_parse_and_map(np, i);
		spear_shirq_register(shirq_blocks[i], parent_irq);
		hwirq += shirq_blocks[i]->nr_irqs;
	}

	return 0;

err_free_desc:
	irq_free_descs(virq_base, nr_irqs);
err_unmap:
	iounmap(base);
	return -ENXIO;
}

static int __init spear300_shirq_of_init(struct device_node *np,
					 struct device_node *parent)
{
	return shirq_init(spear300_shirq_blocks,
			ARRAY_SIZE(spear300_shirq_blocks), np);
}
IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init);

static int __init spear310_shirq_of_init(struct device_node *np,
					 struct device_node *parent)
{
	return shirq_init(spear310_shirq_blocks,
			ARRAY_SIZE(spear310_shirq_blocks), np);
}
IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init);

static int __init spear320_shirq_of_init(struct device_node *np,
					 struct device_node *parent)
{
	return shirq_init(spear320_shirq_blocks,
			ARRAY_SIZE(spear320_shirq_blocks), np);
}
IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init);
Commit	Line	Data
4c18e77f	1	/*
4c18e77f	2	* SPEAr platform shared irq layer source file
4c18e77f	3	*
df1590d9	4	* Copyright (C) 2009-2012 ST Microelectronics
10d8935f	5	* Viresh Kumar <viresh.linux@gmail.com>
4c18e77f	6	*
df1590d9	7	* Copyright (C) 2012 ST Microelectronics
9cc23682	8	* Shiraz Hashim <shiraz.linux.kernel@gmail.com>
df1590d9	9	*
4c18e77f	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*/
80515a5a	14	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
4c18e77f	15
4c18e77f	16	#include <linux/err.h>
80515a5a SH	17	#include <linux/export.h>
80515a5a SH	18	#include <linux/interrupt.h>
4c18e77f	19	#include <linux/io.h>
4c18e77f	20	#include <linux/irq.h>
80515a5a SH	21	#include <linux/irqdomain.h>
	22	#include <linux/of.h>
	23	#include <linux/of_address.h>
	24	#include <linux/of_irq.h>
4c18e77f	25	#include <linux/spinlock.h>
4c18e77f	26
e9c51558 RH	27	#include "irqchip.h"
e9c51558 RH	28
078bc005 TG	29	/*
	30	* struct shirq_regs: shared irq register configuration
	31	*
	32	* enb_reg: enable register offset
	33	* reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
	34	* status_reg: status register offset
	35	* status_reg_mask: status register valid mask
	36	* clear_reg: clear register offset
	37	* reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
	38	*/
	39	struct shirq_regs {
	40	u32 enb_reg;
	41	u32 reset_to_enb;
	42	u32 status_reg;
	43	u32 clear_reg;
	44	u32 reset_to_clear;
	45	};
	46
	47	/*
	48	* struct spear_shirq: shared irq structure
	49	*
c5d1d857 TG	50	* base: Base register address
	51	* regs: Register configuration for shared irq block
	52	* virq_base: Base virtual interrupt number
	53	* nr_irqs: Number of interrupts handled by this block
	54	* offset: Bit offset of the first interrupt
	55	* disabled: Group is disabled, but accounted
078bc005 TG	56	*/
078bc005 TG	57	struct spear_shirq {
c5d1d857 TG	58	void __iomem *base;
	59	struct shirq_regs regs;
	60	u32 virq_base;
	61	u32 nr_irqs;
	62	u32 offset;
	63	bool disabled;
078bc005 TG	64	};
078bc005 TG	65
4c18e77f	66	static DEFINE_SPINLOCK(lock);
4c18e77f	67
80515a5a SH	68	/* spear300 shared irq registers offsets and masks */
	69	#define SPEAR300_INT_ENB_MASK_REG 0x54
	70	#define SPEAR300_INT_STS_MASK_REG 0x58
	71
	72	static struct spear_shirq spear300_shirq_ras1 = {
c5d1d857 TG	73	.offset = 0,
c5d1d857 TG	74	.nr_irqs = 9,
80515a5a SH	75	.regs = {
	76	.enb_reg = SPEAR300_INT_ENB_MASK_REG,
	77	.status_reg = SPEAR300_INT_STS_MASK_REG,
	78	.clear_reg = -1,
	79	},
	80	};
	81
	82	static struct spear_shirq *spear300_shirq_blocks[] = {
	83	&spear300_shirq_ras1,
	84	};
	85
	86	/* spear310 shared irq registers offsets and masks */
	87	#define SPEAR310_INT_STS_MASK_REG 0x04
	88
	89	static struct spear_shirq spear310_shirq_ras1 = {
c5d1d857 TG	90	.offset = 0,
c5d1d857 TG	91	.nr_irqs = 8,
80515a5a SH	92	.regs = {
	93	.enb_reg = -1,
	94	.status_reg = SPEAR310_INT_STS_MASK_REG,
	95	.clear_reg = -1,
	96	},
	97	};
	98
	99	static struct spear_shirq spear310_shirq_ras2 = {
c5d1d857 TG	100	.offset = 8,
c5d1d857 TG	101	.nr_irqs = 5,
80515a5a SH	102	.regs = {
	103	.enb_reg = -1,
	104	.status_reg = SPEAR310_INT_STS_MASK_REG,
	105	.clear_reg = -1,
	106	},
	107	};
	108
	109	static struct spear_shirq spear310_shirq_ras3 = {
c5d1d857 TG	110	.offset = 13,
c5d1d857 TG	111	.nr_irqs = 1,
80515a5a SH	112	.regs = {
	113	.enb_reg = -1,
	114	.status_reg = SPEAR310_INT_STS_MASK_REG,
	115	.clear_reg = -1,
	116	},
	117	};
	118
	119	static struct spear_shirq spear310_shirq_intrcomm_ras = {
c5d1d857 TG	120	.offset = 14,
c5d1d857 TG	121	.nr_irqs = 3,
80515a5a SH	122	.regs = {
	123	.enb_reg = -1,
	124	.status_reg = SPEAR310_INT_STS_MASK_REG,
	125	.clear_reg = -1,
	126	},
	127	};
	128
	129	static struct spear_shirq *spear310_shirq_blocks[] = {
	130	&spear310_shirq_ras1,
	131	&spear310_shirq_ras2,
	132	&spear310_shirq_ras3,
	133	&spear310_shirq_intrcomm_ras,
	134	};
	135
	136	/* spear320 shared irq registers offsets and masks */
	137	#define SPEAR320_INT_STS_MASK_REG 0x04
	138	#define SPEAR320_INT_CLR_MASK_REG 0x04
	139	#define SPEAR320_INT_ENB_MASK_REG 0x08
	140
03319a1a TG	141	static struct spear_shirq spear320_shirq_ras3 = {
	142	.offset = 0,
	143	.nr_irqs = 7,
	144	.disabled = 1,
80515a5a	145	.regs = {
03319a1a TG	146	.enb_reg = SPEAR320_INT_ENB_MASK_REG,
03319a1a TG	147	.reset_to_enb = 1,
80515a5a SH	148	.status_reg = SPEAR320_INT_STS_MASK_REG,
	149	.clear_reg = SPEAR320_INT_CLR_MASK_REG,
	150	.reset_to_clear = 1,
	151	},
	152	};
	153
03319a1a TG	154	static struct spear_shirq spear320_shirq_ras1 = {
	155	.offset = 7,
	156	.nr_irqs = 3,
80515a5a SH	157	.regs = {
	158	.enb_reg = -1,
	159	.status_reg = SPEAR320_INT_STS_MASK_REG,
	160	.clear_reg = SPEAR320_INT_CLR_MASK_REG,
	161	.reset_to_clear = 1,
	162	},
	163	};
	164
03319a1a TG	165	static struct spear_shirq spear320_shirq_ras2 = {
	166	.offset = 10,
	167	.nr_irqs = 1,
80515a5a	168	.regs = {
03319a1a	169	.enb_reg = -1,
80515a5a SH	170	.status_reg = SPEAR320_INT_STS_MASK_REG,
	171	.clear_reg = SPEAR320_INT_CLR_MASK_REG,
	172	.reset_to_clear = 1,
	173	},
	174	};
	175
	176	static struct spear_shirq spear320_shirq_intrcomm_ras = {
c5d1d857 TG	177	.offset = 11,
c5d1d857 TG	178	.nr_irqs = 11,
80515a5a SH	179	.regs = {
	180	.enb_reg = -1,
	181	.status_reg = SPEAR320_INT_STS_MASK_REG,
	182	.clear_reg = SPEAR320_INT_CLR_MASK_REG,
	183	.reset_to_clear = 1,
	184	},
	185	};
	186
	187	static struct spear_shirq *spear320_shirq_blocks[] = {
	188	&spear320_shirq_ras3,
	189	&spear320_shirq_ras1,
	190	&spear320_shirq_ras2,
	191	&spear320_shirq_intrcomm_ras,
	192	};
	193
	194	static void shirq_irq_mask_unmask(struct irq_data *d, bool mask)
4c18e77f	195	{
0e60e117	196	struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
c5d1d857	197	u32 val, offset = d->irq - shirq->virq_base;
4c18e77f	198	unsigned long flags;
4c18e77f	199
80515a5a	200	if (shirq->regs.enb_reg == -1)
4c18e77f	201	return;
	202
	203	spin_lock_irqsave(&lock, flags);
80515a5a SH	204	val = readl(shirq->base + shirq->regs.enb_reg);
	205
	206	if (mask ^ shirq->regs.reset_to_enb)
c5d1d857	207	val &= ~(0x1 << shirq->offset << offset);
4c18e77f	208	else
c5d1d857	209	val \|= 0x1 << shirq->offset << offset;
80515a5a SH	210
80515a5a SH	211	writel(val, shirq->base + shirq->regs.enb_reg);
4c18e77f	212	spin_unlock_irqrestore(&lock, flags);
80515a5a	213
4c18e77f	214	}
4c18e77f	215
80515a5a	216	static void shirq_irq_mask(struct irq_data *d)
4c18e77f	217	{
80515a5a SH	218	shirq_irq_mask_unmask(d, 1);
80515a5a SH	219	}
4c18e77f	220
80515a5a SH	221	static void shirq_irq_unmask(struct irq_data *d)
	222	{
	223	shirq_irq_mask_unmask(d, 0);
4c18e77f	224	}
	225
	226	static struct irq_chip shirq_chip = {
80515a5a	227	.name = "spear-shirq",
0e60e117 LB	228	.irq_ack = shirq_irq_mask,
	229	.irq_mask = shirq_irq_mask,
	230	.irq_unmask = shirq_irq_unmask,
4c18e77f	231	};
	232
	233	static void shirq_handler(unsigned irq, struct irq_desc *desc)
	234	{
6845664a	235	struct spear_shirq *shirq = irq_get_handler_data(irq);
e3c871ab TG	236	struct irq_data *idata = irq_desc_get_irq_data(desc);
	237	struct irq_chip *chip = irq_data_get_irq_chip(idata);
	238	u32 i, j, val, mask, tmp;
4c18e77f	239
e3c871ab	240	chip->irq_ack(idata);
80515a5a	241
c5d1d857	242	mask = ((0x1 << shirq->nr_irqs) - 1) << shirq->offset;
80515a5a SH	243	while ((val = readl(shirq->base + shirq->regs.status_reg) &
	244	mask)) {
	245
c5d1d857 TG	246	val >>= shirq->offset;
c5d1d857 TG	247	for (i = 0, j = 1; i < shirq->nr_irqs; i++, j <<= 1) {
80515a5a SH	248
80515a5a SH	249	if (!(j & val))
4c18e77f	250	continue;
4c18e77f	251
c5d1d857	252	generic_handle_irq(shirq->virq_base + i);
4c18e77f	253
4c18e77f	254	/* clear interrupt */
80515a5a	255	if (shirq->regs.clear_reg == -1)
4c18e77f	256	continue;
80515a5a SH	257
80515a5a SH	258	tmp = readl(shirq->base + shirq->regs.clear_reg);
4c18e77f	259	if (shirq->regs.reset_to_clear)
c5d1d857	260	tmp &= ~(j << shirq->offset);
4c18e77f	261	else
c5d1d857	262	tmp \|= (j << shirq->offset);
80515a5a	263	writel(tmp, shirq->base + shirq->regs.clear_reg);
4c18e77f	264	}
4c18e77f	265	}
e3c871ab	266	chip->irq_unmask(idata);
4c18e77f	267	}
4c18e77f	268
f37ecbce TG	269	static void __init spear_shirq_register(struct spear_shirq *shirq,
f37ecbce TG	270	int parent_irq)
4c18e77f	271	{
	272	int i;
	273
c5d1d857	274	if (shirq->disabled)
80515a5a	275	return;
4c18e77f	276
f37ecbce TG	277	irq_set_chained_handler(parent_irq, shirq_handler);
	278	irq_set_handler_data(parent_irq, shirq);
	279
c5d1d857 TG	280	for (i = 0; i < shirq->nr_irqs; i++) {
c5d1d857 TG	281	irq_set_chip_and_handler(shirq->virq_base + i,
f38c02f3	282	&shirq_chip, handle_simple_irq);
c5d1d857 TG	283	set_irq_flags(shirq->virq_base + i, IRQF_VALID);
c5d1d857 TG	284	irq_set_chip_data(shirq->virq_base + i, shirq);
4c18e77f	285	}
80515a5a SH	286	}
	287
	288	static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
	289	struct device_node *np)
	290	{
c5d1d857	291	int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0;
a26c06f9	292	struct irq_domain *shirq_domain;
80515a5a SH	293	void __iomem *base;
	294
	295	base = of_iomap(np, 0);
	296	if (!base) {
	297	pr_err("%s: failed to map shirq registers\n", __func__);
	298	return -ENXIO;
	299	}
	300
	301	for (i = 0; i < block_nr; i++)
c5d1d857	302	nr_irqs += shirq_blocks[i]->nr_irqs;
80515a5a	303
c5d1d857 TG	304	virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
c5d1d857 TG	305	if (IS_ERR_VALUE(virq_base)) {
80515a5a SH	306	pr_err("%s: irq desc alloc failed\n", __func__);
	307	goto err_unmap;
	308	}
	309
c5d1d857	310	shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0,
80515a5a SH	311	&irq_domain_simple_ops, NULL);
	312	if (WARN_ON(!shirq_domain)) {
	313	pr_warn("%s: irq domain init failed\n", __func__);
	314	goto err_free_desc;
	315	}
	316
	317	for (i = 0; i < block_nr; i++) {
	318	shirq_blocks[i]->base = base;
c5d1d857	319	shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain,
80515a5a	320	hwirq);
80515a5a	321
f37ecbce TG	322	parent_irq = irq_of_parse_and_map(np, i);
f37ecbce TG	323	spear_shirq_register(shirq_blocks[i], parent_irq);
c5d1d857	324	hwirq += shirq_blocks[i]->nr_irqs;
80515a5a SH	325	}
80515a5a SH	326
4c18e77f	327	return 0;
80515a5a SH	328
80515a5a SH	329	err_free_desc:
c5d1d857	330	irq_free_descs(virq_base, nr_irqs);
80515a5a SH	331	err_unmap:
	332	iounmap(base);
	333	return -ENXIO;
	334	}
	335
078bc005 TG	336	static int __init spear300_shirq_of_init(struct device_node *np,
078bc005 TG	337	struct device_node *parent)
80515a5a SH	338	{
	339	return shirq_init(spear300_shirq_blocks,
	340	ARRAY_SIZE(spear300_shirq_blocks), np);
	341	}
e9c51558	342	IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init);
80515a5a	343
078bc005 TG	344	static int __init spear310_shirq_of_init(struct device_node *np,
078bc005 TG	345	struct device_node *parent)
80515a5a SH	346	{
	347	return shirq_init(spear310_shirq_blocks,
	348	ARRAY_SIZE(spear310_shirq_blocks), np);
	349	}
e9c51558	350	IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init);
80515a5a	351
078bc005 TG	352	static int __init spear320_shirq_of_init(struct device_node *np,
078bc005 TG	353	struct device_node *parent)
80515a5a SH	354	{
	355	return shirq_init(spear320_shirq_blocks,
	356	ARRAY_SIZE(spear320_shirq_blocks), np);
4c18e77f	357	}
e9c51558	358	IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init);