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mISDN: Allow to set a minimum length for transparent data
[deliverable/linux.git] / drivers / isdn / hardware / mISDN / netjet.c
CommitLineData
a900845e
KK		 1/*
2 * NETJet mISDN driver
3 *
4 * Author Karsten Keil <keil@isdn4linux.de>
5 *
6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
a6b7a407 23#include <linux/interrupt.h>
a900845e
KK		 24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/mISDNhw.h>
5a0e3ad6 28#include <linux/slab.h>
a900845e
KK		 29#include "ipac.h"
30#include "iohelper.h"
31#include "netjet.h"
32#include <linux/isdn/hdlc.h>
33
34#define NETJET_REV "2.0"
35
36enum nj_types {
37 NETJET_S_TJ300,
38 NETJET_S_TJ320,
39 ENTERNOW__TJ320,
40};
41
42struct tiger_dma {
43 size_t size;
44 u32 *start;
45 int idx;
46 u32 dmastart;
47 u32 dmairq;
48 u32 dmaend;
49 u32 dmacur;
50};
51
52struct tiger_hw;
53
54struct tiger_ch {
55 struct bchannel bch;
56 struct tiger_hw *nj;
57 int idx;
58 int free;
59 int lastrx;
60 u16 rxstate;
61 u16 txstate;
62 struct isdnhdlc_vars hsend;
63 struct isdnhdlc_vars hrecv;
64 u8 *hsbuf;
65 u8 *hrbuf;
66};
67
68#define TX_INIT 0x0001
69#define TX_IDLE 0x0002
70#define TX_RUN 0x0004
71#define TX_UNDERRUN 0x0100
72#define RX_OVERRUN 0x0100
73
74#define LOG_SIZE 64
75
76struct tiger_hw {
77 struct list_head list;
78 struct pci_dev *pdev;
79 char name[MISDN_MAX_IDLEN];
80 enum nj_types typ;
81 int irq;
82 u32 irqcnt;
83 u32 base;
84 size_t base_s;
85 dma_addr_t dma;
86 void *dma_p;
87 spinlock_t lock; /* lock HW */
88 struct isac_hw isac;
89 struct tiger_dma send;
90 struct tiger_dma recv;
91 struct tiger_ch bc[2];
92 u8 ctrlreg;
93 u8 dmactrl;
94 u8 auxd;
95 u8 last_is0;
96 u8 irqmask0;
97 char log[LOG_SIZE];
98};
99
100static LIST_HEAD(Cards);
101static DEFINE_RWLOCK(card_lock); /* protect Cards */
102static u32 debug;
103static int nj_cnt;
104
105static void
106_set_debug(struct tiger_hw *card)
107{
108 card->isac.dch.debug = debug;
109 card->bc[0].bch.debug = debug;
110 card->bc[1].bch.debug = debug;
111}
112
113static int
114set_debug(const char *val, struct kernel_param *kp)
115{
116 int ret;
117 struct tiger_hw *card;
118
119 ret = param_set_uint(val, kp);
120 if (!ret) {
121 read_lock(&card_lock);
122 list_for_each_entry(card, &Cards, list)
123 _set_debug(card);
124 read_unlock(&card_lock);
125 }
126 return ret;
127}
128
129MODULE_AUTHOR("Karsten Keil");
130MODULE_LICENSE("GPL v2");
131MODULE_VERSION(NETJET_REV);
132module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
133MODULE_PARM_DESC(debug, "Netjet debug mask");
134
135static void
136nj_disable_hwirq(struct tiger_hw *card)
137{
138 outb(0, card->base + NJ_IRQMASK0);
139 outb(0, card->base + NJ_IRQMASK1);
140}
141
142
143static u8
144ReadISAC_nj(void *p, u8 offset)
145{
146 struct tiger_hw *card = p;
147 u8 ret;
148
149 card->auxd &= 0xfc;
150 card->auxd |= (offset >> 4) & 3;
151 outb(card->auxd, card->base + NJ_AUXDATA);
152 ret = inb(card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
153 return ret;
154}
155
156static void
157WriteISAC_nj(void *p, u8 offset, u8 value)
158{
159 struct tiger_hw *card = p;
160
161 card->auxd &= 0xfc;
162 card->auxd |= (offset >> 4) & 3;
163 outb(card->auxd, card->base + NJ_AUXDATA);
164 outb(value, card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
165}
166
167static void
168ReadFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
169{
170 struct tiger_hw *card = p;
171
172 card->auxd &= 0xfc;
173 outb(card->auxd, card->base + NJ_AUXDATA);
174 insb(card->base + NJ_ISAC_OFF, data, size);
175}
176
177static void
178WriteFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
179{
180 struct tiger_hw *card = p;
181
182 card->auxd &= 0xfc;
183 outb(card->auxd, card->base + NJ_AUXDATA);
184 outsb(card->base + NJ_ISAC_OFF, data, size);
185}
186
187static void
188fill_mem(struct tiger_ch *bc, u32 idx, u32 cnt, u32 fill)
189{
190 struct tiger_hw *card = bc->bch.hw;
191 u32 mask = 0xff, val;
192
193 pr_debug("%s: B%1d fill %02x len %d idx %d/%d\n", card->name,
475be4d8 194 bc->bch.nr, fill, cnt, idx, card->send.idx);
a900845e
KK		 195 if (bc->bch.nr & 2) {
196 fill <<= 8;
197 mask <<= 8;
198 }
199 mask ^= 0xffffffff;
200 while (cnt--) {
201 val = card->send.start[idx];
202 val &= mask;
203 val |= fill;
204 card->send.start[idx++] = val;
205 if (idx >= card->send.size)
206 idx = 0;
207 }
208}
209
210static int
211mode_tiger(struct tiger_ch *bc, u32 protocol)
212{
213 struct tiger_hw *card = bc->bch.hw;
214
215 pr_debug("%s: B%1d protocol %x-->%x\n", card->name,
475be4d8 216 bc->bch.nr, bc->bch.state, protocol);
a900845e
KK		 217 switch (protocol) {
218 case ISDN_P_NONE:
219 if (bc->bch.state == ISDN_P_NONE)
220 break;
221 fill_mem(bc, 0, card->send.size, 0xff);
222 bc->bch.state = protocol;
223 /* only stop dma and interrupts if both channels NULL */
224 if ((card->bc[0].bch.state == ISDN_P_NONE) &&
225 (card->bc[1].bch.state == ISDN_P_NONE)) {
226 card->dmactrl = 0;
227 outb(card->dmactrl, card->base + NJ_DMACTRL);
228 outb(0, card->base + NJ_IRQMASK0);
229 }
230 test_and_clear_bit(FLG_HDLC, &bc->bch.Flags);
231 test_and_clear_bit(FLG_TRANSPARENT, &bc->bch.Flags);
232 bc->txstate = 0;
233 bc->rxstate = 0;
234 bc->lastrx = -1;
235 break;
236 case ISDN_P_B_RAW:
237 test_and_set_bit(FLG_TRANSPARENT, &bc->bch.Flags);
238 bc->bch.state = protocol;
239 bc->idx = 0;
475be4d8 240 bc->free = card->send.size / 2;
a900845e
KK		 241 bc->rxstate = 0;
242 bc->txstate = TX_INIT | TX_IDLE;
243 bc->lastrx = -1;
244 if (!card->dmactrl) {
245 card->dmactrl = 1;
246 outb(card->dmactrl, card->base + NJ_DMACTRL);
247 outb(0x0f, card->base + NJ_IRQMASK0);
248 }
249 break;
250 case ISDN_P_B_HDLC:
251 test_and_set_bit(FLG_HDLC, &bc->bch.Flags);
252 bc->bch.state = protocol;
253 bc->idx = 0;
475be4d8 254 bc->free = card->send.size / 2;
a900845e
KK		 255 bc->rxstate = 0;
256 bc->txstate = TX_INIT | TX_IDLE;
257 isdnhdlc_rcv_init(&bc->hrecv, 0);
258 isdnhdlc_out_init(&bc->hsend, 0);
259 bc->lastrx = -1;
260 if (!card->dmactrl) {
261 card->dmactrl = 1;
262 outb(card->dmactrl, card->base + NJ_DMACTRL);
263 outb(0x0f, card->base + NJ_IRQMASK0);
264 }
265 break;
266 default:
267 pr_info("%s: %s protocol %x not handled\n", card->name,
268 __func__, protocol);
269 return -ENOPROTOOPT;
270 }
271 card->send.dmacur = inl(card->base + NJ_DMA_READ_ADR);
272 card->recv.dmacur = inl(card->base + NJ_DMA_WRITE_ADR);
273 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
274 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
275 pr_debug("%s: %s ctrl %x irq %02x/%02x idx %d/%d\n",
475be4d8
JP		 276 card->name, __func__,
277 inb(card->base + NJ_DMACTRL),
278 inb(card->base + NJ_IRQMASK0),
279 inb(card->base + NJ_IRQSTAT0),
280 card->send.idx,
281 card->recv.idx);
a900845e
KK		 282 return 0;
283}
284
285static void
286nj_reset(struct tiger_hw *card)
287{
288 outb(0xff, card->base + NJ_CTRL); /* Reset On */
289 mdelay(1);
290
291 /* now edge triggered for TJ320 GE 13/07/00 */
292 /* see comment in IRQ function */
293 if (card->typ == NETJET_S_TJ320) /* TJ320 */
294 card->ctrlreg = 0x40; /* Reset Off and status read clear */
295 else
296 card->ctrlreg = 0x00; /* Reset Off and status read clear */
297 outb(card->ctrlreg, card->base + NJ_CTRL);
298 mdelay(10);
299
300 /* configure AUX pins (all output except ISAC IRQ pin) */
301 card->auxd = 0;
302 card->dmactrl = 0;
303 outb(~NJ_ISACIRQ, card->base + NJ_AUXCTRL);
304 outb(NJ_ISACIRQ, card->base + NJ_IRQMASK1);
305 outb(card->auxd, card->base + NJ_AUXDATA);
306}
307
308static int
309inittiger(struct tiger_hw *card)
310{
311 int i;
312
313 card->dma_p = pci_alloc_consistent(card->pdev, NJ_DMA_SIZE,
475be4d8 314 &card->dma);
a900845e
KK		 315 if (!card->dma_p) {
316 pr_info("%s: No DMA memory\n", card->name);
317 return -ENOMEM;
318 }
319 if ((u64)card->dma > 0xffffffff) {
320 pr_info("%s: DMA outside 32 bit\n", card->name);
321 return -ENOMEM;
322 }
323 for (i = 0; i < 2; i++) {
b42d9165 324 card->bc[i].hsbuf = kmalloc(NJ_DMA_TXSIZE, GFP_ATOMIC);
a900845e
KK		 325 if (!card->bc[i].hsbuf) {
326 pr_info("%s: no B%d send buffer\n", card->name, i + 1);
327 return -ENOMEM;
328 }
b42d9165 329 card->bc[i].hrbuf = kmalloc(NJ_DMA_RXSIZE, GFP_ATOMIC);
a900845e
KK		 330 if (!card->bc[i].hrbuf) {
331 pr_info("%s: no B%d recv buffer\n", card->name, i + 1);
332 return -ENOMEM;
333 }
334 }
335 memset(card->dma_p, 0xff, NJ_DMA_SIZE);
336
337 card->send.start = card->dma_p;
338 card->send.dmastart = (u32)card->dma;
339 card->send.dmaend = card->send.dmastart +
340 (4 * (NJ_DMA_TXSIZE - 1));
341 card->send.dmairq = card->send.dmastart +
342 (4 * ((NJ_DMA_TXSIZE / 2) - 1));
343 card->send.size = NJ_DMA_TXSIZE;
344
345 if (debug & DEBUG_HW)
346 pr_notice("%s: send buffer phy %#x - %#x - %#x virt %p"
475be4d8
JP		 347 " size %zu u32\n", card->name,
348 card->send.dmastart, card->send.dmairq,
349 card->send.dmaend, card->send.start, card->send.size);
a900845e
KK		 350
351 outl(card->send.dmastart, card->base + NJ_DMA_READ_START);
352 outl(card->send.dmairq, card->base + NJ_DMA_READ_IRQ);
353 outl(card->send.dmaend, card->base + NJ_DMA_READ_END);
354
355 card->recv.start = card->dma_p + (NJ_DMA_SIZE / 2);
356 card->recv.dmastart = (u32)card->dma + (NJ_DMA_SIZE / 2);
357 card->recv.dmaend = card->recv.dmastart +
358 (4 * (NJ_DMA_RXSIZE - 1));
359 card->recv.dmairq = card->recv.dmastart +
360 (4 * ((NJ_DMA_RXSIZE / 2) - 1));
361 card->recv.size = NJ_DMA_RXSIZE;
362
363 if (debug & DEBUG_HW)
364 pr_notice("%s: recv buffer phy %#x - %#x - %#x virt %p"
475be4d8
JP		 365 " size %zu u32\n", card->name,
366 card->recv.dmastart, card->recv.dmairq,
367 card->recv.dmaend, card->recv.start, card->recv.size);
a900845e
KK		 368
369 outl(card->recv.dmastart, card->base + NJ_DMA_WRITE_START);
370 outl(card->recv.dmairq, card->base + NJ_DMA_WRITE_IRQ);
371 outl(card->recv.dmaend, card->base + NJ_DMA_WRITE_END);
372 return 0;
373}
374
375static void
376read_dma(struct tiger_ch *bc, u32 idx, int cnt)
377{
378 struct tiger_hw *card = bc->bch.hw;
379 int i, stat;
380 u32 val;
381 u8 *p, *pn;
382
383 if (bc->lastrx == idx) {
384 bc->rxstate |= RX_OVERRUN;
385 pr_info("%s: B%1d overrun at idx %d\n", card->name,
386 bc->bch.nr, idx);
387 }
388 bc->lastrx = idx;
7206e659
KK		 389 stat = bchannel_get_rxbuf(&bc->bch, cnt);
390 /* only transparent use the count here, HDLC overun is detected later */
391 if (stat == ENOMEM) {
392 pr_warning("%s.B%d: No memory for %d bytes\n",
393 card->name, bc->bch.nr, cnt);
394 return;
a900845e 395 }
7206e659 396 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags))
a900845e 397 p = skb_put(bc->bch.rx_skb, cnt);
7206e659 398 else
a900845e
KK		 399 p = bc->hrbuf;
400
401 for (i = 0; i < cnt; i++) {
402 val = card->recv.start[idx++];
403 if (bc->bch.nr & 2)
404 val >>= 8;
405 if (idx >= card->recv.size)
406 idx = 0;
407 p[i] = val & 0xff;
408 }
7206e659
KK		 409
410 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags)) {
034005a0 411 recv_Bchannel(&bc->bch, 0, false);
7206e659
KK		 412 return;
413 }
414
a900845e 415 pn = bc->hrbuf;
7206e659 416 while (cnt > 0) {
a900845e 417 stat = isdnhdlc_decode(&bc->hrecv, pn, cnt, &i,
475be4d8 418 bc->bch.rx_skb->data, bc->bch.maxlen);
7206e659 419 if (stat > 0) { /* valid frame received */
a900845e 420 p = skb_put(bc->bch.rx_skb, stat);
7206e659
KK		 421 if (debug & DEBUG_HW_BFIFO) {
422 snprintf(card->log, LOG_SIZE,
423 "B%1d-recv %s %d ", bc->bch.nr,
424 card->name, stat);
425 print_hex_dump_bytes(card->log,
426 DUMP_PREFIX_OFFSET, p,
427 stat);
428 }
034005a0 429 recv_Bchannel(&bc->bch, 0, false);
7206e659
KK		 430 stat = bchannel_get_rxbuf(&bc->bch, bc->bch.maxlen);
431 if (stat < 0) {
432 pr_warning("%s.B%d: No memory for %d bytes\n",
433 card->name, bc->bch.nr, cnt);
434 return;
435 }
436 } else if (stat == -HDLC_CRC_ERROR) {
a900845e
KK		 437 pr_info("%s: B%1d receive frame CRC error\n",
438 card->name, bc->bch.nr);
7206e659 439 } else if (stat == -HDLC_FRAMING_ERROR) {
a900845e
KK		 440 pr_info("%s: B%1d receive framing error\n",
441 card->name, bc->bch.nr);
7206e659 442 } else if (stat == -HDLC_LENGTH_ERROR) {
a900845e
KK		 443 pr_info("%s: B%1d receive frame too long (> %d)\n",
444 card->name, bc->bch.nr, bc->bch.maxlen);
a900845e 445 }
a900845e
KK		 446 pn += i;
447 cnt -= i;
a900845e
KK		 448 }
449}
450
451static void
452recv_tiger(struct tiger_hw *card, u8 irq_stat)
453{
454 u32 idx;
455 int cnt = card->recv.size / 2;
456
457 /* Note receive is via the WRITE DMA channel */
458 card->last_is0 &= ~NJ_IRQM0_WR_MASK;
459 card->last_is0 |= (irq_stat & NJ_IRQM0_WR_MASK);
460
461 if (irq_stat & NJ_IRQM0_WR_END)
462 idx = cnt - 1;
463 else
464 idx = card->recv.size - 1;
465
466 if (test_bit(FLG_ACTIVE, &card->bc[0].bch.Flags))
467 read_dma(&card->bc[0], idx, cnt);
468 if (test_bit(FLG_ACTIVE, &card->bc[1].bch.Flags))
469 read_dma(&card->bc[1], idx, cnt);
470}
471
472/* sync with current DMA address at start or after exception */
473static void
474resync(struct tiger_ch *bc, struct tiger_hw *card)
475{
476 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
477 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
478 if (bc->free > card->send.size / 2)
479 bc->free = card->send.size / 2;
480 /* currently we simple sync to the next complete free area
481 * this hast the advantage that we have always maximum time to
482 * handle TX irq
483 */
484 if (card->send.idx < ((card->send.size / 2) - 1))
485 bc->idx = (card->recv.size / 2) - 1;
486 else
487 bc->idx = card->recv.size - 1;
488 bc->txstate = TX_RUN;
489 pr_debug("%s: %s B%1d free %d idx %d/%d\n", card->name,
475be4d8 490 __func__, bc->bch.nr, bc->free, bc->idx, card->send.idx);
a900845e
KK		 491}
492
493static int bc_next_frame(struct tiger_ch *);
494
495static void
496fill_hdlc_flag(struct tiger_ch *bc)
497{
498 struct tiger_hw *card = bc->bch.hw;
499 int count, i;
500 u32 m, v;
501 u8 *p;
502
503 if (bc->free == 0)
504 return;
505 pr_debug("%s: %s B%1d %d state %x idx %d/%d\n", card->name,
475be4d8
JP		 506 __func__, bc->bch.nr, bc->free, bc->txstate,
507 bc->idx, card->send.idx);
a900845e
KK		 508 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
509 resync(bc, card);
510 count = isdnhdlc_encode(&bc->hsend, NULL, 0, &i,
475be4d8 511 bc->hsbuf, bc->free);
a900845e 512 pr_debug("%s: B%1d hdlc encoded %d flags\n", card->name,
475be4d8 513 bc->bch.nr, count);
a900845e
KK		 514 bc->free -= count;
515 p = bc->hsbuf;
516 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
517 for (i = 0; i < count; i++) {
518 if (bc->idx >= card->send.size)
519 bc->idx = 0;
520 v = card->send.start[bc->idx];
521 v &= m;
522 v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8;
523 card->send.start[bc->idx++] = v;
524 }
525 if (debug & DEBUG_HW_BFIFO) {
526 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
475be4d8 527 bc->bch.nr, card->name, count);
a900845e
KK		 528 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
529 }
530}
531
532static void
533fill_dma(struct tiger_ch *bc)
534{
535 struct tiger_hw *card = bc->bch.hw;
536 int count, i;
537 u32 m, v;
538 u8 *p;
539
540 if (bc->free == 0)
541 return;
542 count = bc->bch.tx_skb->len - bc->bch.tx_idx;
543 if (count <= 0)
544 return;
545 pr_debug("%s: %s B%1d %d/%d/%d/%d state %x idx %d/%d\n", card->name,
475be4d8
JP		 546 __func__, bc->bch.nr, count, bc->free, bc->bch.tx_idx,
547 bc->bch.tx_skb->len, bc->txstate, bc->idx, card->send.idx);
a900845e
KK		 548 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
549 resync(bc, card);
550 p = bc->bch.tx_skb->data + bc->bch.tx_idx;
551 if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
552 count = isdnhdlc_encode(&bc->hsend, p, count, &i,
475be4d8 553 bc->hsbuf, bc->free);
a900845e 554 pr_debug("%s: B%1d hdlc encoded %d in %d\n", card->name,
475be4d8 555 bc->bch.nr, i, count);
a900845e
KK		 556 bc->bch.tx_idx += i;
557 bc->free -= count;
558 p = bc->hsbuf;
559 } else {
560 if (count > bc->free)
561 count = bc->free;
562 bc->bch.tx_idx += count;
563 bc->free -= count;
564 }
565 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
566 for (i = 0; i < count; i++) {
567 if (bc->idx >= card->send.size)
568 bc->idx = 0;
569 v = card->send.start[bc->idx];
570 v &= m;
571 v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8;
572 card->send.start[bc->idx++] = v;
573 }
574 if (debug & DEBUG_HW_BFIFO) {
575 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
475be4d8 576 bc->bch.nr, card->name, count);
a900845e
KK		 577 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
578 }
579 if (bc->free)
580 bc_next_frame(bc);
581}
582
583
584static int
585bc_next_frame(struct tiger_ch *bc)
586{
8bfddfbe 587 if (bc->bch.tx_skb && bc->bch.tx_idx < bc->bch.tx_skb->len) {
a900845e 588 fill_dma(bc);
8bfddfbe
KK		 589 } else {
590 if (bc->bch.tx_skb)
a900845e 591 dev_kfree_skb(bc->bch.tx_skb);
a900845e
KK		 592 if (get_next_bframe(&bc->bch))
593 fill_dma(bc);
594 else
595 return 0;
596 }
597 return 1;
598}
599
600static void
601send_tiger_bc(struct tiger_hw *card, struct tiger_ch *bc)
602{
603 int ret;
604
605 bc->free += card->send.size / 2;
606 if (bc->free >= card->send.size) {
607 if (!(bc->txstate & (TX_UNDERRUN | TX_INIT))) {
608 pr_info("%s: B%1d TX underrun state %x\n", card->name,
609 bc->bch.nr, bc->txstate);
610 bc->txstate |= TX_UNDERRUN;
611 }
612 bc->free = card->send.size;
613 }
614 ret = bc_next_frame(bc);
615 if (!ret) {
616 if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
617 fill_hdlc_flag(bc);
618 return;
619 }
620 pr_debug("%s: B%1d TX no data free %d idx %d/%d\n", card->name,
475be4d8 621 bc->bch.nr, bc->free, bc->idx, card->send.idx);
a900845e
KK		 622 if (!(bc->txstate & (TX_IDLE | TX_INIT))) {
623 fill_mem(bc, bc->idx, bc->free, 0xff);
624 if (bc->free == card->send.size)
625 bc->txstate |= TX_IDLE;
626 }
627 }
628}
629
630static void
631send_tiger(struct tiger_hw *card, u8 irq_stat)
632{
633 int i;
634
635 /* Note send is via the READ DMA channel */
636 if ((irq_stat & card->last_is0) & NJ_IRQM0_RD_MASK) {
637 pr_info("%s: tiger warn write double dma %x/%x\n",
638 card->name, irq_stat, card->last_is0);
639 return;
640 } else {
641 card->last_is0 &= ~NJ_IRQM0_RD_MASK;
642 card->last_is0 |= (irq_stat & NJ_IRQM0_RD_MASK);
643 }
644 for (i = 0; i < 2; i++) {
645 if (test_bit(FLG_ACTIVE, &card->bc[i].bch.Flags))
646 send_tiger_bc(card, &card->bc[i]);
647 }
648}
649
650static irqreturn_t
651nj_irq(int intno, void *dev_id)
652{
653 struct tiger_hw *card = dev_id;
654 u8 val, s1val, s0val;
655
656 spin_lock(&card->lock);
657 s0val = inb(card->base | NJ_IRQSTAT0);
658 s1val = inb(card->base | NJ_IRQSTAT1);
659 if ((s1val & NJ_ISACIRQ) && (s0val == 0)) {
660 /* shared IRQ */
661 spin_unlock(&card->lock);
662 return IRQ_NONE;
663 }
664 pr_debug("%s: IRQSTAT0 %02x IRQSTAT1 %02x\n", card->name, s0val, s1val);
665 card->irqcnt++;
666 if (!(s1val & NJ_ISACIRQ)) {
667 val = ReadISAC_nj(card, ISAC_ISTA);
668 if (val)
669 mISDNisac_irq(&card->isac, val);
670 }
671
672 if (s0val)
673 /* write to clear */
674 outb(s0val, card->base | NJ_IRQSTAT0);
675 else
676 goto end;
677 s1val = s0val;
678 /* set bits in sval to indicate which page is free */
679 card->recv.dmacur = inl(card->base | NJ_DMA_WRITE_ADR);
680 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
681 if (card->recv.dmacur < card->recv.dmairq)
682 s0val = 0x08; /* the 2nd write area is free */
683 else
684 s0val = 0x04; /* the 1st write area is free */
685
686 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
687 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
688 if (card->send.dmacur < card->send.dmairq)
689 s0val |= 0x02; /* the 2nd read area is free */
690 else
691 s0val |= 0x01; /* the 1st read area is free */
692
693 pr_debug("%s: DMA Status %02x/%02x/%02x %d/%d\n", card->name,
475be4d8
JP		 694 s1val, s0val, card->last_is0,
695 card->recv.idx, card->send.idx);
a900845e
KK		 696 /* test if we have a DMA interrupt */
697 if (s0val != card->last_is0) {
698 if ((s0val & NJ_IRQM0_RD_MASK) !=
699 (card->last_is0 & NJ_IRQM0_RD_MASK))
700 /* got a write dma int */
701 send_tiger(card, s0val);
702 if ((s0val & NJ_IRQM0_WR_MASK) !=
703 (card->last_is0 & NJ_IRQM0_WR_MASK))
704 /* got a read dma int */
705 recv_tiger(card, s0val);
706 }
707end:
708 spin_unlock(&card->lock);
709 return IRQ_HANDLED;
710}
711
712static int
713nj_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
714{
715 int ret = -EINVAL;
716 struct bchannel *bch = container_of(ch, struct bchannel, ch);
717 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
718 struct tiger_hw *card = bch->hw;
719 struct mISDNhead *hh = mISDN_HEAD_P(skb);
8bfddfbe 720 unsigned long flags;
a900845e
KK		 721
722 switch (hh->prim) {
723 case PH_DATA_REQ:
724 spin_lock_irqsave(&card->lock, flags);
725 ret = bchannel_senddata(bch, skb);
726 if (ret > 0) { /* direct TX */
a900845e
KK		 727 fill_dma(bc);
728 ret = 0;
8bfddfbe
KK		 729 }
730 spin_unlock_irqrestore(&card->lock, flags);
a900845e
KK		 731 return ret;
732 case PH_ACTIVATE_REQ:
733 spin_lock_irqsave(&card->lock, flags);
734 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
735 ret = mode_tiger(bc, ch->protocol);
736 else
737 ret = 0;
738 spin_unlock_irqrestore(&card->lock, flags);
739 if (!ret)
740 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
475be4d8 741 NULL, GFP_KERNEL);
a900845e
KK		 742 break;
743 case PH_DEACTIVATE_REQ:
744 spin_lock_irqsave(&card->lock, flags);
745 mISDN_clear_bchannel(bch);
746 mode_tiger(bc, ISDN_P_NONE);
747 spin_unlock_irqrestore(&card->lock, flags);
748 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
475be4d8 749 NULL, GFP_KERNEL);
a900845e
KK		 750 ret = 0;
751 break;
752 }
753 if (!ret)
754 dev_kfree_skb(skb);
755 return ret;
756}
757
758static int
759channel_bctrl(struct tiger_ch *bc, struct mISDN_ctrl_req *cq)
760{
034005a0 761 return mISDN_ctrl_bchannel(&bc->bch, cq);
a900845e
KK		 762}
763
764static int
765nj_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
766{
767 struct bchannel *bch = container_of(ch, struct bchannel, ch);
768 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
769 struct tiger_hw *card = bch->hw;
770 int ret = -EINVAL;
771 u_long flags;
772
773 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
774 switch (cmd) {
775 case CLOSE_CHANNEL:
776 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1368112c
KK		 777 spin_lock_irqsave(&card->lock, flags);
778 mISDN_freebchannel(bch);
779 mode_tiger(bc, ISDN_P_NONE);
780 spin_unlock_irqrestore(&card->lock, flags);
a900845e
KK		 781 ch->protocol = ISDN_P_NONE;
782 ch->peer = NULL;
783 module_put(THIS_MODULE);
784 ret = 0;
785 break;
786 case CONTROL_CHANNEL:
787 ret = channel_bctrl(bc, arg);
788 break;
789 default:
790 pr_info("%s: %s unknown prim(%x)\n", card->name, __func__, cmd);
791 }
792 return ret;
793}
794
795static int
796channel_ctrl(struct tiger_hw *card, struct mISDN_ctrl_req *cq)
797{
798 int ret = 0;
799
800 switch (cq->op) {
801 case MISDN_CTRL_GETOP:
c626c127 802 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3;
a900845e
KK		 803 break;
804 case MISDN_CTRL_LOOP:
805 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
806 if (cq->channel < 0 || cq->channel > 3) {
807 ret = -EINVAL;
808 break;
809 }
810 ret = card->isac.ctrl(&card->isac, HW_TESTLOOP, cq->channel);
811 break;
c626c127
KK		 812 case MISDN_CTRL_L1_TIMER3:
813 ret = card->isac.ctrl(&card->isac, HW_TIMER3_VALUE, cq->p1);
814 break;
a900845e
KK		 815 default:
816 pr_info("%s: %s unknown Op %x\n", card->name, __func__, cq->op);
817 ret = -EINVAL;
818 break;
819 }
820 return ret;
821}
822
823static int
824open_bchannel(struct tiger_hw *card, struct channel_req *rq)
825{
826 struct bchannel *bch;
827
819a1008 828 if (rq->adr.channel == 0 || rq->adr.channel > 2)
a900845e
KK		 829 return -EINVAL;
830 if (rq->protocol == ISDN_P_NONE)
831 return -EINVAL;
832 bch = &card->bc[rq->adr.channel - 1].bch;
833 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
834 return -EBUSY; /* b-channel can be only open once */
835 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
836 bch->ch.protocol = rq->protocol;
837 rq->ch = &bch->ch;
838 return 0;
839}
840
841/*
842 * device control function
843 */
844static int
845nj_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
846{
847 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
848 struct dchannel *dch = container_of(dev, struct dchannel, dev);
849 struct tiger_hw *card = dch->hw;
850 struct channel_req *rq;
851 int err = 0;
852
853 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
854 switch (cmd) {
855 case OPEN_CHANNEL:
856 rq = arg;
857 if (rq->protocol == ISDN_P_TE_S0)
858 err = card->isac.open(&card->isac, rq);
859 else
860 err = open_bchannel(card, rq);
861 if (err)
862 break;
863 if (!try_module_get(THIS_MODULE))
864 pr_info("%s: cannot get module\n", card->name);
865 break;
866 case CLOSE_CHANNEL:
867 pr_debug("%s: dev(%d) close from %p\n", card->name, dch->dev.id,
475be4d8 868 __builtin_return_address(0));
a900845e
KK		 869 module_put(THIS_MODULE);
870 break;
871 case CONTROL_CHANNEL:
872 err = channel_ctrl(card, arg);
873 break;
874 default:
875 pr_debug("%s: %s unknown command %x\n",
475be4d8 876 card->name, __func__, cmd);
a900845e
KK		 877 return -EINVAL;
878 }
879 return err;
880}
881
882static int
883nj_init_card(struct tiger_hw *card)
884{
885 u_long flags;
886 int ret;
887
888 spin_lock_irqsave(&card->lock, flags);
889 nj_disable_hwirq(card);
890 spin_unlock_irqrestore(&card->lock, flags);
891
892 card->irq = card->pdev->irq;
893 if (request_irq(card->irq, nj_irq, IRQF_SHARED, card->name, card)) {
894 pr_info("%s: couldn't get interrupt %d\n",
895 card->name, card->irq);
896 card->irq = -1;
897 return -EIO;
898 }
899
900 spin_lock_irqsave(&card->lock, flags);
901 nj_reset(card);
902 ret = card->isac.init(&card->isac);
903 if (ret)
904 goto error;
905 ret = inittiger(card);
906 if (ret)
907 goto error;
908 mode_tiger(&card->bc[0], ISDN_P_NONE);
909 mode_tiger(&card->bc[1], ISDN_P_NONE);
910error:
911 spin_unlock_irqrestore(&card->lock, flags);
912 return ret;
913}
914
915
916static void
917nj_release(struct tiger_hw *card)
918{
919 u_long flags;
920 int i;
921
922 if (card->base_s) {
923 spin_lock_irqsave(&card->lock, flags);
924 nj_disable_hwirq(card);
925 mode_tiger(&card->bc[0], ISDN_P_NONE);
926 mode_tiger(&card->bc[1], ISDN_P_NONE);
927 card->isac.release(&card->isac);
928 spin_unlock_irqrestore(&card->lock, flags);
929 release_region(card->base, card->base_s);
930 card->base_s = 0;
931 }
932 if (card->irq > 0)
933 free_irq(card->irq, card);
934 if (card->isac.dch.dev.dev.class)
935 mISDN_unregister_device(&card->isac.dch.dev);
475be4d8 936
a900845e
KK		 937 for (i = 0; i < 2; i++) {
938 mISDN_freebchannel(&card->bc[i].bch);
939 kfree(card->bc[i].hsbuf);
940 kfree(card->bc[i].hrbuf);
941 }
942 if (card->dma_p)
943 pci_free_consistent(card->pdev, NJ_DMA_SIZE,
475be4d8 944 card->dma_p, card->dma);
a900845e
KK		 945 write_lock_irqsave(&card_lock, flags);
946 list_del(&card->list);
947 write_unlock_irqrestore(&card_lock, flags);
948 pci_clear_master(card->pdev);
949 pci_disable_device(card->pdev);
950 pci_set_drvdata(card->pdev, NULL);
951 kfree(card);
952}
953
954
955static int
956nj_setup(struct tiger_hw *card)
957{
958 card->base = pci_resource_start(card->pdev, 0);
959 card->base_s = pci_resource_len(card->pdev, 0);
960 if (!request_region(card->base, card->base_s, card->name)) {
961 pr_info("%s: NETjet config port %#x-%#x already in use\n",
962 card->name, card->base,
963 (u32)(card->base + card->base_s - 1));
964 card->base_s = 0;
965 return -EIO;
966 }
967 ASSIGN_FUNC(nj, ISAC, card->isac);
968 return 0;
969}
970
971
972static int __devinit
973setup_instance(struct tiger_hw *card)
974{
975 int i, err;
976 u_long flags;
977
978 snprintf(card->name, MISDN_MAX_IDLEN - 1, "netjet.%d", nj_cnt + 1);
979 write_lock_irqsave(&card_lock, flags);
980 list_add_tail(&card->list, &Cards);
981 write_unlock_irqrestore(&card_lock, flags);
982
983 _set_debug(card);
984 card->isac.name = card->name;
985 spin_lock_init(&card->lock);
986 card->isac.hwlock = &card->lock;
987 mISDNisac_init(&card->isac, card);
988
989 card->isac.dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
990 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
991 card->isac.dch.dev.D.ctrl = nj_dctrl;
992 for (i = 0; i < 2; i++) {
993 card->bc[i].bch.nr = i + 1;
994 set_channelmap(i + 1, card->isac.dch.dev.channelmap);
034005a0
KK		 995 mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM,
996 NJ_DMA_RXSIZE >> 1);
a900845e
KK		 997 card->bc[i].bch.hw = card;
998 card->bc[i].bch.ch.send = nj_l2l1B;
999 card->bc[i].bch.ch.ctrl = nj_bctrl;
1000 card->bc[i].bch.ch.nr = i + 1;
1001 list_add(&card->bc[i].bch.ch.list,
475be4d8 1002 &card->isac.dch.dev.bchannels);
a900845e
KK		 1003 card->bc[i].bch.hw = card;
1004 }
1005 err = nj_setup(card);
1006 if (err)
1007 goto error;
1008 err = mISDN_register_device(&card->isac.dch.dev, &card->pdev->dev,
475be4d8 1009 card->name);
a900845e
KK		 1010 if (err)
1011 goto error;
1012 err = nj_init_card(card);
1013 if (!err) {
1014 nj_cnt++;
1015 pr_notice("Netjet %d cards installed\n", nj_cnt);
1016 return 0;
1017 }
1018error:
1019 nj_release(card);
1020 return err;
1021}
1022
1023static int __devinit
1024nj_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1025{
1026 int err = -ENOMEM;
1027 int cfg;
1028 struct tiger_hw *card;
1029
1030 if (pdev->subsystem_vendor == 0x8086 &&
1031 pdev->subsystem_device == 0x0003) {
1032 pr_notice("Netjet: Digium X100P/X101P not handled\n");
1033 return -ENODEV;
1034 }
1035
1036 if (pdev->subsystem_vendor == 0x55 &&
1037 pdev->subsystem_device == 0x02) {
1038 pr_notice("Netjet: Enter!Now not handled yet\n");
1039 return -ENODEV;
1040 }
1041
367bbf2a 1042 if (pdev->subsystem_vendor == 0xb100 &&
475be4d8 1043 pdev->subsystem_device == 0x0003) {
367bbf2a
PB		 1044 pr_notice("Netjet: Digium TDM400P not handled yet\n");
1045 return -ENODEV;
1046 }
1047
a900845e
KK		 1048 card = kzalloc(sizeof(struct tiger_hw), GFP_ATOMIC);
1049 if (!card) {
1050 pr_info("No kmem for Netjet\n");
1051 return err;
1052 }
1053
1054 card->pdev = pdev;
1055
1056 err = pci_enable_device(pdev);
1057 if (err) {
1058 kfree(card);
1059 return err;
1060 }
1061
1062 printk(KERN_INFO "nj_probe(mISDN): found adapter at %s\n",
475be4d8 1063 pci_name(pdev));
a900845e
KK		 1064
1065 pci_set_master(pdev);
1066
1067 /* the TJ300 and TJ320 must be detected, the IRQ handling is different
1068 * unfortunately the chips use the same device ID, but the TJ320 has
1069 * the bit20 in status PCI cfg register set
1070 */
1071 pci_read_config_dword(pdev, 0x04, &cfg);
1072 if (cfg & 0x00100000)
1073 card->typ = NETJET_S_TJ320;
1074 else
1075 card->typ = NETJET_S_TJ300;
1076
1077 card->base = pci_resource_start(pdev, 0);
1078 card->irq = pdev->irq;
1079 pci_set_drvdata(pdev, card);
1080 err = setup_instance(card);
1081 if (err)
1082 pci_set_drvdata(pdev, NULL);
1083
1084 return err;
1085}
1086
1087
1088static void __devexit nj_remove(struct pci_dev *pdev)
1089{
1090 struct tiger_hw *card = pci_get_drvdata(pdev);
1091
1092 if (card)
1093 nj_release(card);
1094 else
1095 pr_info("%s drvdata already removed\n", __func__);
1096}
1097
1098/* We cannot select cards with PCI_SUB... IDs, since here are cards with
1099 * SUB IDs set to PCI_ANY_ID, so we need to match all and reject
1100 * known other cards which not work with this driver - see probe function */
1101static struct pci_device_id nj_pci_ids[] __devinitdata = {
1102 { PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_300,
1103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1104 { }
1105};
1106MODULE_DEVICE_TABLE(pci, nj_pci_ids);
1107
1108static struct pci_driver nj_driver = {
1109 .name = "netjet",
1110 .probe = nj_probe,
1111 .remove = __devexit_p(nj_remove),
1112 .id_table = nj_pci_ids,
1113};
1114
1115static int __init nj_init(void)
1116{
1117 int err;
1118
1119 pr_notice("Netjet PCI driver Rev. %s\n", NETJET_REV);
1120 err = pci_register_driver(&nj_driver);
1121 return err;
1122}
1123
1124static void __exit nj_cleanup(void)
1125{
1126 pci_unregister_driver(&nj_driver);
1127}
1128
1129module_init(nj_init);
1130module_exit(nj_cleanup);
Linux kernel - Deliverables
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