[deliverable/linux.git] / drivers / kvm / irq.h

/*
 * irq.h: in kernel interrupt controller related definitions
 * Copyright (c) 2007, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 * Authors:
 *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
 *
 */

#ifndef __IRQ_H
#define __IRQ_H

#include "kvm.h"

typedef void irq_request_func(void *opaque, int level);

struct kvm_kpic_state {
	u8 last_irr;	/* edge detection */
	u8 irr;		/* interrupt request register */
	u8 imr;		/* interrupt mask register */
	u8 isr;		/* interrupt service register */
	u8 priority_add;	/* highest irq priority */
	u8 irq_base;
	u8 read_reg_select;
	u8 poll;
	u8 special_mask;
	u8 init_state;
	u8 auto_eoi;
	u8 rotate_on_auto_eoi;
	u8 special_fully_nested_mode;
	u8 init4;		/* true if 4 byte init */
	u8 elcr;		/* PIIX edge/trigger selection */
	u8 elcr_mask;
	struct kvm_pic *pics_state;
};

struct kvm_pic {
	struct kvm_kpic_state pics[2]; /* 0 is master pic, 1 is slave pic */
	irq_request_func *irq_request;
	void *irq_request_opaque;
	int output;		/* intr from master PIC */
	struct kvm_io_device dev;
};

struct kvm_pic *kvm_create_pic(struct kvm *kvm);
void kvm_pic_set_irq(void *opaque, int irq, int level);
int kvm_pic_read_irq(struct kvm_pic *s);
int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
int kvm_cpu_has_interrupt(struct kvm_vcpu *v);

#define IOAPIC_NUM_PINS  24
#define IOAPIC_VERSION_ID 0x11	/* IOAPIC version */
#define IOAPIC_EDGE_TRIG  0
#define IOAPIC_LEVEL_TRIG 1

#define IOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
#define IOAPIC_MEM_LENGTH            0x100

/* Direct registers. */
#define IOAPIC_REG_SELECT  0x00
#define IOAPIC_REG_WINDOW  0x10
#define IOAPIC_REG_EOI     0x40	/* IA64 IOSAPIC only */

/* Indirect registers. */
#define IOAPIC_REG_APIC_ID 0x00	/* x86 IOAPIC only */
#define IOAPIC_REG_VERSION 0x01
#define IOAPIC_REG_ARB_ID  0x02	/* x86 IOAPIC only */

struct kvm_ioapic {
	u64 base_address;
	u32 ioregsel;
	u32 id;
	u32 irr;
	u32 pad;
	union ioapic_redir_entry {
		u64 bits;
		struct {
			u8 vector;
			u8 delivery_mode:3;
			u8 dest_mode:1;
			u8 delivery_status:1;
			u8 polarity:1;
			u8 remote_irr:1;
			u8 trig_mode:1;
			u8 mask:1;
			u8 reserve:7;
			u8 reserved[4];
			u8 dest_id;
		} fields;
	} redirtbl[IOAPIC_NUM_PINS];
	struct kvm_io_device dev;
	struct kvm *kvm;
};

struct kvm_lapic {
	unsigned long base_address;
	struct kvm_io_device dev;
	struct {
		atomic_t pending;
		s64 period;	/* unit: ns */
		u32 divide_count;
		ktime_t last_update;
		struct hrtimer dev;
	} timer;
	struct kvm_vcpu *vcpu;
	struct page *regs_page;
	void *regs;
};

#ifdef DEBUG
#define ASSERT(x)  							\
do {									\
	if (!(x)) {							\
		printk(KERN_EMERG "assertion failed %s: %d: %s\n",	\
		       __FILE__, __LINE__, #x);				\
		BUG();							\
	}								\
} while (0)
#else
#define ASSERT(x) do { } while (0)
#endif

void kvm_vcpu_kick(struct kvm_vcpu *vcpu);
int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
int kvm_create_lapic(struct kvm_vcpu *vcpu);
void kvm_free_apic(struct kvm_lapic *apic);
u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
				       unsigned long bitmap);
u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
void kvm_ioapic_update_eoi(struct kvm *kvm, int vector);
int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
int kvm_apic_set_irq(struct kvm_lapic *apic, u8 vec, u8 trig);
int kvm_ioapic_init(struct kvm *kvm);
void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level);

#endif
Commit	Line	Data
85f455f7 ED	1	/*
	2	* irq.h: in kernel interrupt controller related definitions
	3	* Copyright (c) 2007, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	16	* Place - Suite 330, Boston, MA 02111-1307 USA.
	17	* Authors:
	18	* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
	19	*
	20	*/
	21
	22	#ifndef __IRQ_H
	23	#define __IRQ_H
	24
	25	#include "kvm.h"
	26
	27	typedef void irq_request_func(void *opaque, int level);
	28
85f455f7 ED	29	struct kvm_kpic_state {
	30	u8 last_irr; /* edge detection */
	31	u8 irr; /* interrupt request register */
	32	u8 imr; /* interrupt mask register */
	33	u8 isr; /* interrupt service register */
	34	u8 priority_add; /* highest irq priority */
	35	u8 irq_base;
	36	u8 read_reg_select;
	37	u8 poll;
	38	u8 special_mask;
	39	u8 init_state;
	40	u8 auto_eoi;
	41	u8 rotate_on_auto_eoi;
	42	u8 special_fully_nested_mode;
	43	u8 init4; /* true if 4 byte init */
	44	u8 elcr; /* PIIX edge/trigger selection */
	45	u8 elcr_mask;
	46	struct kvm_pic *pics_state;
	47	};
	48
	49	struct kvm_pic {
	50	struct kvm_kpic_state pics[2]; /* 0 is master pic, 1 is slave pic */
	51	irq_request_func *irq_request;
	52	void *irq_request_opaque;
	53	int output; /* intr from master PIC */
	54	struct kvm_io_device dev;
	55	};
	56
	57	struct kvm_pic kvm_create_pic(struct kvm kvm);
	58	void kvm_pic_set_irq(void *opaque, int irq, int level);
	59	int kvm_pic_read_irq(struct kvm_pic *s);
	60	int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
	61	int kvm_cpu_has_interrupt(struct kvm_vcpu *v);
	62
1fd4f2a5 ED	63	#define IOAPIC_NUM_PINS 24
	64	#define IOAPIC_VERSION_ID 0x11 /* IOAPIC version */
	65	#define IOAPIC_EDGE_TRIG 0
	66	#define IOAPIC_LEVEL_TRIG 1
	67
	68	#define IOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000
	69	#define IOAPIC_MEM_LENGTH 0x100
	70
	71	/* Direct registers. */
	72	#define IOAPIC_REG_SELECT 0x00
	73	#define IOAPIC_REG_WINDOW 0x10
	74	#define IOAPIC_REG_EOI 0x40 /* IA64 IOSAPIC only */
	75
	76	/* Indirect registers. */
	77	#define IOAPIC_REG_APIC_ID 0x00 /* x86 IOAPIC only */
	78	#define IOAPIC_REG_VERSION 0x01
	79	#define IOAPIC_REG_ARB_ID 0x02 /* x86 IOAPIC only */
	80
	81	struct kvm_ioapic {
	82	u64 base_address;
	83	u32 ioregsel;
	84	u32 id;
	85	u32 irr;
	86	u32 pad;
	87	union ioapic_redir_entry {
	88	u64 bits;
	89	struct {
	90	u8 vector;
	91	u8 delivery_mode:3;
	92	u8 dest_mode:1;
	93	u8 delivery_status:1;
	94	u8 polarity:1;
	95	u8 remote_irr:1;
	96	u8 trig_mode:1;
	97	u8 mask:1;
	98	u8 reserve:7;
	99	u8 reserved[4];
	100	u8 dest_id;
	101	} fields;
	102	} redirtbl[IOAPIC_NUM_PINS];
	103	struct kvm_io_device dev;
	104	struct kvm *kvm;
	105	};
	106
97222cc8 ED	107	struct kvm_lapic {
	108	unsigned long base_address;
	109	struct kvm_io_device dev;
	110	struct {
	111	atomic_t pending;
	112	s64 period; /* unit: ns */
	113	u32 divide_count;
	114	ktime_t last_update;
	115	struct hrtimer dev;
	116	} timer;
	117	struct kvm_vcpu *vcpu;
	118	struct page *regs_page;
	119	void *regs;
	120	};
	121
	122	#ifdef DEBUG
	123	#define ASSERT(x) \
	124	do { \
	125	if (!(x)) { \
	126	printk(KERN_EMERG "assertion failed %s: %d: %s\n", \
	127	__FILE__, __LINE__, #x); \
	128	BUG(); \
	129	} \
	130	} while (0)
	131	#else
	132	#define ASSERT(x) do { } while (0)
	133	#endif
	134
	135	void kvm_vcpu_kick(struct kvm_vcpu *vcpu);
	136	int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
	137	int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
	138	int kvm_create_lapic(struct kvm_vcpu *vcpu);
	139	void kvm_free_apic(struct kvm_lapic *apic);
	140	u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
	141	void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
	142	void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
1fd4f2a5 ED	143	struct kvm_lapic kvm_apic_round_robin(struct kvm kvm, u8 vector,
1fd4f2a5 ED	144	unsigned long bitmap);
97222cc8 ED	145	u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
97222cc8 ED	146	void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
1fd4f2a5	147	int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
97222cc8	148	void kvm_ioapic_update_eoi(struct kvm *kvm, int vector);
1fd4f2a5 ED	149	int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
	150	int kvm_apic_set_irq(struct kvm_lapic *apic, u8 vec, u8 trig);
	151	int kvm_ioapic_init(struct kvm *kvm);
	152	void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level);
97222cc8	153
85f455f7	154	#endif