[deliverable/linux.git] / drivers / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT64_LEVEL_BITS
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#else
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT32_LEVEL_BITS
	#define PT_MAX_FULL_LEVELS 2
#else
	#error Invalid PTTYPE value
#endif

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t *table;
	pt_element_t pte;
	pt_element_t *ptep;
	struct page *page;
	int index;
	pt_element_t inherited_ar;
	gfn_t gfn;
	u32 error_code;
};

/*
 * Fetch a guest pte for a guest virtual address
 */
static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
			    int write_fault, int user_fault, int fetch_fault)
{
	hpa_t hpa;
	struct kvm_memory_slot *slot;
	pt_element_t *ptep;
	pt_element_t root;
	gfn_t table_gfn;

	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
	walker->level = vcpu->mmu.root_level;
	walker->table = NULL;
	walker->page = NULL;
	walker->ptep = NULL;
	root = vcpu->cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
		root = *walker->ptep;
		walker->pte = root;
		if (!(root & PT_PRESENT_MASK))
			goto not_present;
		--walker->level;
	}
#endif
	table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	walker->table_gfn[walker->level - 1] = table_gfn;
	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
		 walker->level - 1, table_gfn);
	slot = gfn_to_memslot(vcpu->kvm, table_gfn);
	hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
	walker->page = pfn_to_page(hpa >> PAGE_SHIFT);
	walker->table = kmap_atomic(walker->page, KM_USER0);

	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);

	walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;

	for (;;) {
		int index = PT_INDEX(addr, walker->level);
		hpa_t paddr;

		ptep = &walker->table[index];
		walker->index = index;
		ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
		       ((unsigned long)ptep & PAGE_MASK));

		if (!is_present_pte(*ptep))
			goto not_present;

		if (write_fault && !is_writeble_pte(*ptep))
			if (user_fault || is_write_protection(vcpu))
				goto access_error;

		if (user_fault && !(*ptep & PT_USER_MASK))
			goto access_error;

#if PTTYPE == 64
		if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK))
			goto access_error;
#endif

		if (!(*ptep & PT_ACCESSED_MASK)) {
			mark_page_dirty(vcpu->kvm, table_gfn);
			*ptep |= PT_ACCESSED_MASK;
		}

		if (walker->level == PT_PAGE_TABLE_LEVEL) {
			walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
		    && (*ptep & PT_PAGE_SIZE_MASK)
		    && (PTTYPE == 64 || is_pse(vcpu))) {
			walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
			break;
		}

		walker->inherited_ar &= walker->table[index];
		table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
		kunmap_atomic(walker->table, KM_USER0);
		paddr = safe_gpa_to_hpa(vcpu, table_gfn << PAGE_SHIFT);
		walker->page = pfn_to_page(paddr >> PAGE_SHIFT);
		walker->table = kmap_atomic(walker->page, KM_USER0);
		--walker->level;
		walker->table_gfn[walker->level - 1 ] = table_gfn;
		pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
			 walker->level - 1, table_gfn);
	}
	walker->pte = *ptep;
	if (walker->page)
		walker->ptep = NULL;
	if (walker->table)
		kunmap_atomic(walker->table, KM_USER0);
	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
	if (walker->table)
		kunmap_atomic(walker->table, KM_USER0);
	return 0;
}

static void FNAME(mark_pagetable_dirty)(struct kvm *kvm,
					struct guest_walker *walker)
{
	mark_page_dirty(kvm, walker->table_gfn[walker->level - 1]);
}

static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
				  u64 *shadow_pte,
				  gpa_t gaddr,
				  pt_element_t gpte,
				  u64 access_bits,
				  int user_fault,
				  int write_fault,
				  int *ptwrite,
				  struct guest_walker *walker,
				  gfn_t gfn)
{
	hpa_t paddr;
	int dirty = gpte & PT_DIRTY_MASK;
	u64 spte;
	int was_rmapped = is_rmap_pte(*shadow_pte);

	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
		 " user_fault %d gfn %lx\n",
		 __FUNCTION__, *shadow_pte, (u64)gpte, access_bits,
		 write_fault, user_fault, gfn);

	if (write_fault && !dirty) {
		pt_element_t *guest_ent, *tmp = NULL;

		if (walker->ptep)
			guest_ent = walker->ptep;
		else {
			tmp = kmap_atomic(walker->page, KM_USER0);
			guest_ent = &tmp[walker->index];
		}

		*guest_ent |= PT_DIRTY_MASK;
		if (!walker->ptep)
			kunmap_atomic(tmp, KM_USER0);
		dirty = 1;
		FNAME(mark_pagetable_dirty)(vcpu->kvm, walker);
	}

	/*
	 * We don't set the accessed bit, since we sometimes want to see
	 * whether the guest actually used the pte (in order to detect
	 * demand paging).
	 */
	spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
	spte |= gpte & PT64_NX_MASK;
	if (!dirty)
		access_bits &= ~PT_WRITABLE_MASK;

	paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);

	spte |= PT_PRESENT_MASK;
	if (access_bits & PT_USER_MASK)
		spte |= PT_USER_MASK;

	if (is_error_hpa(paddr)) {
		set_shadow_pte(shadow_pte,
			       shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK);
		return;
	}

	spte |= paddr;

	if ((access_bits & PT_WRITABLE_MASK)
	    || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
		struct kvm_mmu_page *shadow;

		spte |= PT_WRITABLE_MASK;
		if (user_fault) {
			mmu_unshadow(vcpu, gfn);
			goto unshadowed;
		}

		shadow = kvm_mmu_lookup_page(vcpu, gfn);
		if (shadow) {
			pgprintk("%s: found shadow page for %lx, marking ro\n",
				 __FUNCTION__, gfn);
			access_bits &= ~PT_WRITABLE_MASK;
			if (is_writeble_pte(spte)) {
				spte &= ~PT_WRITABLE_MASK;
				kvm_x86_ops->tlb_flush(vcpu);
			}
			if (write_fault)
				*ptwrite = 1;
		}
	}

unshadowed:

	if (access_bits & PT_WRITABLE_MASK)
		mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);

	pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
	set_shadow_pte(shadow_pte, spte);
	page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
	if (!was_rmapped)
		rmap_add(vcpu, shadow_pte);
	if (!ptwrite || !*ptwrite)
		vcpu->last_pte_updated = shadow_pte;
}

static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
			   u64 *shadow_pte, u64 access_bits,
			   int user_fault, int write_fault, int *ptwrite,
			   struct guest_walker *walker, gfn_t gfn)
{
	access_bits &= gpte;
	FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK,
			      gpte, access_bits, user_fault, write_fault,
			      ptwrite, walker, gfn);
}

static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
			      u64 *spte, const void *pte, int bytes,
			      int offset_in_pte)
{
	pt_element_t gpte;

	gpte = *(const pt_element_t *)pte;
	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
		if (!offset_in_pte && !is_present_pte(gpte))
			set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
		return;
	}
	if (bytes < sizeof(pt_element_t))
		return;
	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
	FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
		       0, NULL, NULL,
		       (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
}

static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde,
			   u64 *shadow_pte, u64 access_bits,
			   int user_fault, int write_fault, int *ptwrite,
			   struct guest_walker *walker, gfn_t gfn)
{
	gpa_t gaddr;

	access_bits &= gpde;
	gaddr = (gpa_t)gfn << PAGE_SHIFT;
	if (PTTYPE == 32 && is_cpuid_PSE36())
		gaddr |= (gpde & PT32_DIR_PSE36_MASK) <<
			(32 - PT32_DIR_PSE36_SHIFT);
	FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
			      gpde, access_bits, user_fault, write_fault,
			      ptwrite, walker, gfn);
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			 struct guest_walker *walker,
			 int user_fault, int write_fault, int *ptwrite)
{
	hpa_t shadow_addr;
	int level;
	u64 *shadow_ent;
	u64 *prev_shadow_ent = NULL;

	if (!is_present_pte(walker->pte))
		return NULL;

	shadow_addr = vcpu->mmu.root_hpa;
	level = vcpu->mmu.shadow_root_level;
	if (level == PT32E_ROOT_LEVEL) {
		shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
		shadow_addr &= PT64_BASE_ADDR_MASK;
		--level;
	}

	for (; ; level--) {
		u32 index = SHADOW_PT_INDEX(addr, level);
		struct kvm_mmu_page *shadow_page;
		u64 shadow_pte;
		int metaphysical;
		gfn_t table_gfn;
		unsigned hugepage_access = 0;

		shadow_ent = ((u64 *)__va(shadow_addr)) + index;
		if (is_shadow_present_pte(*shadow_ent)) {
			if (level == PT_PAGE_TABLE_LEVEL)
				break;
			shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
			prev_shadow_ent = shadow_ent;
			continue;
		}

		if (level == PT_PAGE_TABLE_LEVEL)
			break;

		if (level - 1 == PT_PAGE_TABLE_LEVEL
		    && walker->level == PT_DIRECTORY_LEVEL) {
			metaphysical = 1;
			hugepage_access = walker->pte;
			hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
			if (walker->pte & PT64_NX_MASK)
				hugepage_access |= (1 << 2);
			hugepage_access >>= PT_WRITABLE_SHIFT;
			table_gfn = (walker->pte & PT_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
		} else {
			metaphysical = 0;
			table_gfn = walker->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
					       metaphysical, hugepage_access,
					       shadow_ent);
		shadow_addr = __pa(shadow_page->spt);
		shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
		*shadow_ent = shadow_pte;
		prev_shadow_ent = shadow_ent;
	}

	if (walker->level == PT_DIRECTORY_LEVEL) {
		FNAME(set_pde)(vcpu, walker->pte, shadow_ent,
			       walker->inherited_ar, user_fault, write_fault,
			       ptwrite, walker, walker->gfn);
	} else {
		ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
		FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
			       walker->inherited_ar, user_fault, write_fault,
			       ptwrite, walker, walker->gfn);
	}
	return shadow_ent;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	int fetch_fault = error_code & PFERR_FETCH_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int write_pt = 0;
	int r;

	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	/*
	 * Look up the shadow pte for the faulting address.
	 */
	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!r) {
		pgprintk("%s: guest page fault\n", __FUNCTION__);
		inject_page_fault(vcpu, addr, walker.error_code);
		vcpu->last_pt_write_count = 0; /* reset fork detector */
		return 0;
	}

	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
				  &write_pt);
	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
		 shadow_pte, *shadow_pte, write_pt);

	if (!write_pt)
		vcpu->last_pt_write_count = 0; /* reset fork detector */

	/*
	 * mmio: emulate if accessible, otherwise its a guest fault.
	 */
	if (is_io_pte(*shadow_pte))
		return 1;

	++vcpu->stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");

	return write_pt;
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	gpa_t gpa = UNMAPPED_GVA;
	int r;

	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);

	if (r) {
		gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
		gpa |= vaddr & ~PAGE_MASK;
	}

	return gpa;
}

static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
				 struct kvm_mmu_page *sp)
{
	int i;
	pt_element_t *gpt;

	if (sp->role.metaphysical || PTTYPE == 32) {
		nonpaging_prefetch_page(vcpu, sp);
		return;
	}

	gpt = kmap_atomic(gfn_to_page(vcpu->kvm, sp->gfn), KM_USER0);
	for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
		if (is_present_pte(gpt[i]))
			sp->spt[i] = shadow_trap_nonpresent_pte;
		else
			sp->spt[i] = shadow_notrap_nonpresent_pte;
	kunmap_atomic(gpt, KM_USER0);
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef SHADOW_PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_DIR_BASE_ADDR_MASK
#undef PT_LEVEL_BITS
#undef PT_MAX_FULL_LEVELS
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
	28	#define FNAME(name) paging##64_##name
	29	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	30	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	31	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	32	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	33	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
c7addb90	34	#define PT_LEVEL_BITS PT64_LEVEL_BITS
cea0f0e7 AK	35	#ifdef CONFIG_X86_64
	36	#define PT_MAX_FULL_LEVELS 4
	37	#else
	38	#define PT_MAX_FULL_LEVELS 2
	39	#endif
6aa8b732 AK	40	#elif PTTYPE == 32
	41	#define pt_element_t u32
	42	#define guest_walker guest_walker32
	43	#define FNAME(name) paging##32_##name
	44	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	45	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	46	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	47	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	48	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
c7addb90	49	#define PT_LEVEL_BITS PT32_LEVEL_BITS
cea0f0e7	50	#define PT_MAX_FULL_LEVELS 2
6aa8b732 AK	51	#else
	52	#error Invalid PTTYPE value
	53	#endif
	54
	55	/*
	56	* The guest_walker structure emulates the behavior of the hardware page
	57	* table walker.
	58	*/
	59	struct guest_walker {
	60	int level;
cea0f0e7	61	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
6aa8b732	62	pt_element_t *table;
fe551881	63	pt_element_t pte;
ac79c978	64	pt_element_t *ptep;
fe551881 SL	65	struct page *page;
fe551881 SL	66	int index;
6aa8b732	67	pt_element_t inherited_ar;
815af8d4	68	gfn_t gfn;
7993ba43	69	u32 error_code;
6aa8b732 AK	70	};
6aa8b732 AK	71
ac79c978 AK	72	/*
	73	* Fetch a guest pte for a guest virtual address
	74	*/
7993ba43 AK	75	static int FNAME(walk_addr)(struct guest_walker *walker,
7993ba43 AK	76	struct kvm_vcpu *vcpu, gva_t addr,
73b1087e	77	int write_fault, int user_fault, int fetch_fault)
6aa8b732 AK	78	{
	79	hpa_t hpa;
	80	struct kvm_memory_slot *slot;
ac79c978	81	pt_element_t *ptep;
1b0973bd	82	pt_element_t root;
cea0f0e7	83	gfn_t table_gfn;
6aa8b732	84
cea0f0e7	85	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
6aa8b732	86	walker->level = vcpu->mmu.root_level;
1b0973bd	87	walker->table = NULL;
fe551881 SL	88	walker->page = NULL;
fe551881 SL	89	walker->ptep = NULL;
1b0973bd AK	90	root = vcpu->cr3;
	91	#if PTTYPE == 64
	92	if (!is_long_mode(vcpu)) {
	93	walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
	94	root = *walker->ptep;
fe551881	95	walker->pte = root;
1b0973bd	96	if (!(root & PT_PRESENT_MASK))
7993ba43	97	goto not_present;
1b0973bd AK	98	--walker->level;
	99	}
	100	#endif
cea0f0e7 AK	101	table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	102	walker->table_gfn[walker->level - 1] = table_gfn;
	103	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	104	walker->level - 1, table_gfn);
	105	slot = gfn_to_memslot(vcpu->kvm, table_gfn);
1b0973bd	106	hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
fe551881 SL	107	walker->page = pfn_to_page(hpa >> PAGE_SHIFT);
fe551881 SL	108	walker->table = kmap_atomic(walker->page, KM_USER0);
6aa8b732	109
a9058ecd	110	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
f802a307	111	(vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732	112
6aa8b732	113	walker->inherited_ar = PT_USER_MASK \| PT_WRITABLE_MASK;
ac79c978 AK	114
	115	for (;;) {
	116	int index = PT_INDEX(addr, walker->level);
	117	hpa_t paddr;
	118
	119	ptep = &walker->table[index];
fe551881	120	walker->index = index;
ac79c978 AK	121	ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
	122	((unsigned long)ptep & PAGE_MASK));
	123
815af8d4	124	if (!is_present_pte(*ptep))
7993ba43 AK	125	goto not_present;
	126
	127	if (write_fault && !is_writeble_pte(*ptep))
	128	if (user_fault \|\| is_write_protection(vcpu))
	129	goto access_error;
	130
	131	if (user_fault && !(*ptep & PT_USER_MASK))
	132	goto access_error;
	133
73b1087e AK	134	#if PTTYPE == 64
	135	if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK))
	136	goto access_error;
	137	#endif
	138
bf3f8e86 AK	139	if (!(*ptep & PT_ACCESSED_MASK)) {
	140	mark_page_dirty(vcpu->kvm, table_gfn);
	141	*ptep \|= PT_ACCESSED_MASK;
	142	}
815af8d4 AK	143
	144	if (walker->level == PT_PAGE_TABLE_LEVEL) {
	145	walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
	146	>> PAGE_SHIFT;
	147	break;
	148	}
	149
	150	if (walker->level == PT_DIRECTORY_LEVEL
	151	&& (*ptep & PT_PAGE_SIZE_MASK)
	152	&& (PTTYPE == 64 \|\| is_pse(vcpu))) {
	153	walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
	154	>> PAGE_SHIFT;
	155	walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
ac79c978	156	break;
815af8d4	157	}
ac79c978	158
ca5aac1f	159	walker->inherited_ar &= walker->table[index];
cea0f0e7	160	table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
ac79c978	161	kunmap_atomic(walker->table, KM_USER0);
fe551881 SL	162	paddr = safe_gpa_to_hpa(vcpu, table_gfn << PAGE_SHIFT);
	163	walker->page = pfn_to_page(paddr >> PAGE_SHIFT);
	164	walker->table = kmap_atomic(walker->page, KM_USER0);
ac79c978	165	--walker->level;
cea0f0e7 AK	166	walker->table_gfn[walker->level - 1 ] = table_gfn;
	167	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	168	walker->level - 1, table_gfn);
ac79c978	169	}
fe551881 SL	170	walker->pte = *ptep;
	171	if (walker->page)
	172	walker->ptep = NULL;
	173	if (walker->table)
	174	kunmap_atomic(walker->table, KM_USER0);
374cbac0	175	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
7993ba43 AK	176	return 1;
	177
	178	not_present:
	179	walker->error_code = 0;
	180	goto err;
	181
	182	access_error:
	183	walker->error_code = PFERR_PRESENT_MASK;
	184
	185	err:
	186	if (write_fault)
	187	walker->error_code \|= PFERR_WRITE_MASK;
	188	if (user_fault)
	189	walker->error_code \|= PFERR_USER_MASK;
73b1087e AK	190	if (fetch_fault)
73b1087e AK	191	walker->error_code \|= PFERR_FETCH_MASK;
1b0973bd AK	192	if (walker->table)
1b0973bd AK	193	kunmap_atomic(walker->table, KM_USER0);
fe551881	194	return 0;
6aa8b732 AK	195	}
6aa8b732 AK	196
bf3f8e86 AK	197	static void FNAME(mark_pagetable_dirty)(struct kvm *kvm,
	198	struct guest_walker *walker)
	199	{
	200	mark_page_dirty(kvm, walker->table_gfn[walker->level - 1]);
	201	}
	202
e60d75ea AK	203	static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
	204	u64 *shadow_pte,
	205	gpa_t gaddr,
fe551881	206	pt_element_t gpte,
e60d75ea	207	u64 access_bits,
97a0a01e	208	int user_fault,
63b1ad24	209	int write_fault,
97a0a01e AK	210	int *ptwrite,
97a0a01e AK	211	struct guest_walker *walker,
e60d75ea AK	212	gfn_t gfn)
	213	{
	214	hpa_t paddr;
fe551881	215	int dirty = gpte & PT_DIRTY_MASK;
c7addb90 AK	216	u64 spte;
c7addb90 AK	217	int was_rmapped = is_rmap_pte(*shadow_pte);
97a0a01e AK	218
	219	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
	220	" user_fault %d gfn %lx\n",
c7addb90	221	__FUNCTION__, *shadow_pte, (u64)gpte, access_bits,
97a0a01e AK	222	write_fault, user_fault, gfn);
	223
	224	if (write_fault && !dirty) {
fe551881 SL	225	pt_element_t guest_ent, tmp = NULL;
	226
	227	if (walker->ptep)
	228	guest_ent = walker->ptep;
	229	else {
	230	tmp = kmap_atomic(walker->page, KM_USER0);
	231	guest_ent = &tmp[walker->index];
	232	}
	233
	234	*guest_ent \|= PT_DIRTY_MASK;
	235	if (!walker->ptep)
	236	kunmap_atomic(tmp, KM_USER0);
97a0a01e AK	237	dirty = 1;
	238	FNAME(mark_pagetable_dirty)(vcpu->kvm, walker);
	239	}
e60d75ea	240
12b7d28f AK	241	/*
	242	* We don't set the accessed bit, since we sometimes want to see
	243	* whether the guest actually used the pte (in order to detect
	244	* demand paging).
	245	*/
	246	spte = PT_PRESENT_MASK \| PT_DIRTY_MASK;
fe551881	247	spte \|= gpte & PT64_NX_MASK;
e60d75ea AK	248	if (!dirty)
	249	access_bits &= ~PT_WRITABLE_MASK;
	250
	251	paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);
	252
0d551bb6	253	spte \|= PT_PRESENT_MASK;
97a0a01e	254	if (access_bits & PT_USER_MASK)
0d551bb6	255	spte \|= PT_USER_MASK;
e60d75ea AK	256
e60d75ea AK	257	if (is_error_hpa(paddr)) {
c7addb90 AK	258	set_shadow_pte(shadow_pte,
c7addb90 AK	259	shadow_trap_nonpresent_pte \| PT_SHADOW_IO_MARK);
e60d75ea AK	260	return;
	261	}
	262
0d551bb6	263	spte \|= paddr;
e60d75ea	264
97a0a01e AK	265	if ((access_bits & PT_WRITABLE_MASK)
97a0a01e AK	266	\|\| (write_fault && !is_write_protection(vcpu) && !user_fault)) {
e60d75ea AK	267	struct kvm_mmu_page *shadow;
e60d75ea AK	268
0d551bb6	269	spte \|= PT_WRITABLE_MASK;
97a0a01e AK	270	if (user_fault) {
	271	mmu_unshadow(vcpu, gfn);
	272	goto unshadowed;
	273	}
	274
e60d75ea AK	275	shadow = kvm_mmu_lookup_page(vcpu, gfn);
	276	if (shadow) {
	277	pgprintk("%s: found shadow page for %lx, marking ro\n",
	278	__FUNCTION__, gfn);
	279	access_bits &= ~PT_WRITABLE_MASK;
0d551bb6 AK	280	if (is_writeble_pte(spte)) {
0d551bb6 AK	281	spte &= ~PT_WRITABLE_MASK;
cbdd1bea	282	kvm_x86_ops->tlb_flush(vcpu);
e60d75ea	283	}
97a0a01e AK	284	if (write_fault)
97a0a01e AK	285	*ptwrite = 1;
e60d75ea AK	286	}
	287	}
	288
97a0a01e AK	289	unshadowed:
97a0a01e AK	290
e60d75ea AK	291	if (access_bits & PT_WRITABLE_MASK)
	292	mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);
	293
c7addb90	294	pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
e663ee64	295	set_shadow_pte(shadow_pte, spte);
e60d75ea	296	page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
97a0a01e AK	297	if (!was_rmapped)
97a0a01e AK	298	rmap_add(vcpu, shadow_pte);
12b7d28f AK	299	if (!ptwrite \|\| !*ptwrite)
12b7d28f AK	300	vcpu->last_pte_updated = shadow_pte;
e60d75ea AK	301	}
e60d75ea AK	302
fe551881	303	static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
63b1ad24	304	u64 *shadow_pte, u64 access_bits,
97a0a01e AK	305	int user_fault, int write_fault, int *ptwrite,
97a0a01e AK	306	struct guest_walker *walker, gfn_t gfn)
6aa8b732	307	{
fe551881 SL	308	access_bits &= gpte;
fe551881 SL	309	FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK,
97a0a01e AK	310	gpte, access_bits, user_fault, write_fault,
97a0a01e AK	311	ptwrite, walker, gfn);
6aa8b732 AK	312	}
6aa8b732 AK	313
0028425f	314	static void FNAME(update_pte)(struct kvm_vcpu vcpu, struct kvm_mmu_page page,
c7addb90 AK	315	u64 spte, const void pte, int bytes,
c7addb90 AK	316	int offset_in_pte)
0028425f AK	317	{
	318	pt_element_t gpte;
	319
0028425f	320	gpte = (const pt_element_t )pte;
c7addb90 AK	321	if (~gpte & (PT_PRESENT_MASK \| PT_ACCESSED_MASK)) {
	322	if (!offset_in_pte && !is_present_pte(gpte))
	323	set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
	324	return;
	325	}
	326	if (bytes < sizeof(pt_element_t))
0028425f AK	327	return;
0028425f AK	328	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
fe551881	329	FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK \| PT_WRITABLE_MASK, 0,
97a0a01e	330	0, NULL, NULL,
0028425f AK	331	(gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
	332	}
	333
fe551881	334	static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde,
97a0a01e AK	335	u64 *shadow_pte, u64 access_bits,
	336	int user_fault, int write_fault, int *ptwrite,
	337	struct guest_walker *walker, gfn_t gfn)
6aa8b732 AK	338	{
	339	gpa_t gaddr;
	340
fe551881	341	access_bits &= gpde;
815af8d4	342	gaddr = (gpa_t)gfn << PAGE_SHIFT;
6aa8b732	343	if (PTTYPE == 32 && is_cpuid_PSE36())
fe551881	344	gaddr \|= (gpde & PT32_DIR_PSE36_MASK) <<
6aa8b732	345	(32 - PT32_DIR_PSE36_SHIFT);
e60d75ea	346	FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
97a0a01e AK	347	gpde, access_bits, user_fault, write_fault,
97a0a01e AK	348	ptwrite, walker, gfn);
6aa8b732 AK	349	}
6aa8b732 AK	350
6aa8b732 AK	351	/*
	352	* Fetch a shadow pte for a specific level in the paging hierarchy.
	353	*/
	354	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
97a0a01e AK	355	struct guest_walker *walker,
97a0a01e AK	356	int user_fault, int write_fault, int *ptwrite)
6aa8b732 AK	357	{
	358	hpa_t shadow_addr;
	359	int level;
ef0197e8	360	u64 *shadow_ent;
6aa8b732	361	u64 *prev_shadow_ent = NULL;
ac79c978	362
fe551881	363	if (!is_present_pte(walker->pte))
ac79c978	364	return NULL;
6aa8b732 AK	365
	366	shadow_addr = vcpu->mmu.root_hpa;
	367	level = vcpu->mmu.shadow_root_level;
aef3d3fe AK	368	if (level == PT32E_ROOT_LEVEL) {
	369	shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
	370	shadow_addr &= PT64_BASE_ADDR_MASK;
	371	--level;
	372	}
6aa8b732 AK	373
	374	for (; ; level--) {
	375	u32 index = SHADOW_PT_INDEX(addr, level);
25c0de2c	376	struct kvm_mmu_page *shadow_page;
8c7bb723	377	u64 shadow_pte;
cea0f0e7 AK	378	int metaphysical;
cea0f0e7 AK	379	gfn_t table_gfn;
d28c6cfb	380	unsigned hugepage_access = 0;
6aa8b732	381
ef0197e8	382	shadow_ent = ((u64 *)__va(shadow_addr)) + index;
c7addb90	383	if (is_shadow_present_pte(*shadow_ent)) {
6aa8b732	384	if (level == PT_PAGE_TABLE_LEVEL)
97a0a01e	385	break;
6aa8b732 AK	386	shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
	387	prev_shadow_ent = shadow_ent;
	388	continue;
	389	}
	390
ef0197e8 AK	391	if (level == PT_PAGE_TABLE_LEVEL)
ef0197e8 AK	392	break;
6aa8b732	393
cea0f0e7 AK	394	if (level - 1 == PT_PAGE_TABLE_LEVEL
	395	&& walker->level == PT_DIRECTORY_LEVEL) {
	396	metaphysical = 1;
fe551881	397	hugepage_access = walker->pte;
d28c6cfb	398	hugepage_access &= PT_USER_MASK \| PT_WRITABLE_MASK;
fe551881	399	if (walker->pte & PT64_NX_MASK)
d55e2cb2	400	hugepage_access \|= (1 << 2);
d28c6cfb	401	hugepage_access >>= PT_WRITABLE_SHIFT;
fe551881	402	table_gfn = (walker->pte & PT_BASE_ADDR_MASK)
cea0f0e7 AK	403	>> PAGE_SHIFT;
	404	} else {
	405	metaphysical = 0;
	406	table_gfn = walker->table_gfn[level - 2];
	407	}
	408	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
d28c6cfb AK	409	metaphysical, hugepage_access,
d28c6cfb AK	410	shadow_ent);
47ad8e68	411	shadow_addr = __pa(shadow_page->spt);
aef3d3fe AK	412	shadow_pte = shadow_addr \| PT_PRESENT_MASK \| PT_ACCESSED_MASK
aef3d3fe AK	413	\| PT_WRITABLE_MASK \| PT_USER_MASK;
8c7bb723	414	*shadow_ent = shadow_pte;
6aa8b732 AK	415	prev_shadow_ent = shadow_ent;
6aa8b732 AK	416	}
ef0197e8 AK	417
ef0197e8 AK	418	if (walker->level == PT_DIRECTORY_LEVEL) {
fe551881	419	FNAME(set_pde)(vcpu, walker->pte, shadow_ent,
97a0a01e AK	420	walker->inherited_ar, user_fault, write_fault,
97a0a01e AK	421	ptwrite, walker, walker->gfn);
ef0197e8 AK	422	} else {
ef0197e8 AK	423	ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
fe551881	424	FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
97a0a01e AK	425	walker->inherited_ar, user_fault, write_fault,
97a0a01e AK	426	ptwrite, walker, walker->gfn);
ef0197e8 AK	427	}
ef0197e8 AK	428	return shadow_ent;
6aa8b732 AK	429	}
6aa8b732 AK	430
6aa8b732 AK	431	/*
	432	* Page fault handler. There are several causes for a page fault:
	433	* - there is no shadow pte for the guest pte
	434	* - write access through a shadow pte marked read only so that we can set
	435	* the dirty bit
	436	* - write access to a shadow pte marked read only so we can update the page
	437	* dirty bitmap, when userspace requests it
	438	* - mmio access; in this case we will never install a present shadow pte
	439	* - normal guest page fault due to the guest pte marked not present, not
	440	* writable, or not executable
	441	*
e2dec939 AK	442	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
e2dec939 AK	443	* a negative value on error.
6aa8b732 AK	444	*/
	445	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	446	u32 error_code)
	447	{
	448	int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732	449	int user_fault = error_code & PFERR_USER_MASK;
73b1087e	450	int fetch_fault = error_code & PFERR_FETCH_MASK;
6aa8b732 AK	451	struct guest_walker walker;
6aa8b732 AK	452	u64 *shadow_pte;
cea0f0e7	453	int write_pt = 0;
e2dec939	454	int r;
6aa8b732	455
cea0f0e7	456	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
37a7d8b0	457	kvm_mmu_audit(vcpu, "pre page fault");
714b93da	458
e2dec939 AK	459	r = mmu_topup_memory_caches(vcpu);
	460	if (r)
	461	return r;
714b93da	462
6aa8b732 AK	463	/*
	464	* Look up the shadow pte for the faulting address.
	465	*/
73b1087e AK	466	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
73b1087e AK	467	fetch_fault);
6aa8b732 AK	468
	469	/*
	470	* The page is not mapped by the guest. Let the guest handle it.
	471	*/
7993ba43 AK	472	if (!r) {
	473	pgprintk("%s: guest page fault\n", __FUNCTION__);
	474	inject_page_fault(vcpu, addr, walker.error_code);
a25f7e1f	475	vcpu->last_pt_write_count = 0; /* reset fork detector */
6aa8b732 AK	476	return 0;
	477	}
	478
97a0a01e AK	479	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
	480	&write_pt);
	481	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
	482	shadow_pte, *shadow_pte, write_pt);
cea0f0e7	483
a25f7e1f AK	484	if (!write_pt)
	485	vcpu->last_pt_write_count = 0; /* reset fork detector */
	486
6aa8b732 AK	487	/*
	488	* mmio: emulate if accessible, otherwise its a guest fault.
	489	*/
d27d4aca	490	if (is_io_pte(*shadow_pte))
7993ba43	491	return 1;
6aa8b732	492
1165f5fe	493	++vcpu->stat.pf_fixed;
37a7d8b0	494	kvm_mmu_audit(vcpu, "post page fault (fixed)");
6aa8b732	495
cea0f0e7	496	return write_pt;
6aa8b732 AK	497	}
	498
	499	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
	500	{
	501	struct guest_walker walker;
e119d117 AK	502	gpa_t gpa = UNMAPPED_GVA;
e119d117 AK	503	int r;
6aa8b732	504
e119d117	505	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
6aa8b732	506
e119d117 AK	507	if (r) {
	508	gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
	509	gpa \|= vaddr & ~PAGE_MASK;
6aa8b732 AK	510	}
	511
	512	return gpa;
	513	}
	514
c7addb90 AK	515	static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
	516	struct kvm_mmu_page *sp)
	517	{
	518	int i;
	519	pt_element_t *gpt;
	520
	521	if (sp->role.metaphysical \|\| PTTYPE == 32) {
	522	nonpaging_prefetch_page(vcpu, sp);
	523	return;
	524	}
	525
	526	gpt = kmap_atomic(gfn_to_page(vcpu->kvm, sp->gfn), KM_USER0);
	527	for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
	528	if (is_present_pte(gpt[i]))
	529	sp->spt[i] = shadow_trap_nonpresent_pte;
	530	else
	531	sp->spt[i] = shadow_notrap_nonpresent_pte;
	532	kunmap_atomic(gpt, KM_USER0);
	533	}
	534
6aa8b732 AK	535	#undef pt_element_t
	536	#undef guest_walker
	537	#undef FNAME
	538	#undef PT_BASE_ADDR_MASK
	539	#undef PT_INDEX
	540	#undef SHADOW_PT_INDEX
	541	#undef PT_LEVEL_MASK
6aa8b732	542	#undef PT_DIR_BASE_ADDR_MASK
c7addb90	543	#undef PT_LEVEL_BITS
cea0f0e7	544	#undef PT_MAX_FULL_LEVELS