[deliverable/linux.git] / drivers / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT64_LEVEL_BITS
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#else
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT32_LEVEL_BITS
	#define PT_MAX_FULL_LEVELS 2
#else
	#error Invalid PTTYPE value
#endif

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t pte;
	pt_element_t inherited_ar;
	gfn_t gfn;
	u32 error_code;
};

/*
 * Fetch a guest pte for a guest virtual address
 */
static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
			    int write_fault, int user_fault, int fetch_fault)
{
	pt_element_t pte;
	gfn_t table_gfn;
	unsigned index;
	gpa_t pte_gpa;

	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
	walker->level = vcpu->mmu.root_level;
	pte = vcpu->cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		pte = vcpu->pdptrs[(addr >> 30) & 3];
		if (!is_present_pte(pte))
			goto not_present;
		--walker->level;
	}
#endif
	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);

	walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;

	for (;;) {
		index = PT_INDEX(addr, walker->level);

		table_gfn = (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
		pte_gpa = table_gfn << PAGE_SHIFT;
		pte_gpa += index * sizeof(pt_element_t);
		walker->table_gfn[walker->level - 1] = table_gfn;
		pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
			 walker->level - 1, table_gfn);

		kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));

		if (!is_present_pte(pte))
			goto not_present;

		if (write_fault && !is_writeble_pte(pte))
			if (user_fault || is_write_protection(vcpu))
				goto access_error;

		if (user_fault && !(pte & PT_USER_MASK))
			goto access_error;

#if PTTYPE == 64
		if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
			goto access_error;
#endif

		if (!(pte & PT_ACCESSED_MASK)) {
			mark_page_dirty(vcpu->kvm, table_gfn);
			pte |= PT_ACCESSED_MASK;
			kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
		}

		if (walker->level == PT_PAGE_TABLE_LEVEL) {
			walker->gfn = (pte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
		    && (pte & PT_PAGE_SIZE_MASK)
		    && (PTTYPE == 64 || is_pse(vcpu))) {
			walker->gfn = (pte & PT_DIR_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
			break;
		}

		walker->inherited_ar &= pte;
		--walker->level;
	}

	if (write_fault && !is_dirty_pte(pte)) {
		mark_page_dirty(vcpu->kvm, table_gfn);
		pte |= PT_DIRTY_MASK;
		kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
		kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
	}

	walker->pte = pte;
	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)pte);
	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
	return 0;
}

static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
				  u64 *shadow_pte,
				  gpa_t gaddr,
				  pt_element_t gpte,
				  u64 access_bits,
				  int user_fault,
				  int write_fault,
				  int *ptwrite,
				  struct guest_walker *walker,
				  gfn_t gfn)
{
	hpa_t paddr;
	int dirty = gpte & PT_DIRTY_MASK;
	u64 spte;
	int was_rmapped = is_rmap_pte(*shadow_pte);

	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
		 " user_fault %d gfn %lx\n",
		 __FUNCTION__, *shadow_pte, (u64)gpte, access_bits,
		 write_fault, user_fault, gfn);

	/*
	 * We don't set the accessed bit, since we sometimes want to see
	 * whether the guest actually used the pte (in order to detect
	 * demand paging).
	 */
	spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
	spte |= gpte & PT64_NX_MASK;
	if (!dirty)
		access_bits &= ~PT_WRITABLE_MASK;

	paddr = gpa_to_hpa(vcpu->kvm, gaddr & PT64_BASE_ADDR_MASK);

	spte |= PT_PRESENT_MASK;
	if (access_bits & PT_USER_MASK)
		spte |= PT_USER_MASK;

	if (is_error_hpa(paddr)) {
		set_shadow_pte(shadow_pte,
			       shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK);
		kvm_release_page(pfn_to_page((paddr & PT64_BASE_ADDR_MASK)
					     >> PAGE_SHIFT));
		return;
	}

	spte |= paddr;

	if ((access_bits & PT_WRITABLE_MASK)
	    || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
		struct kvm_mmu_page *shadow;

		spte |= PT_WRITABLE_MASK;
		if (user_fault) {
			mmu_unshadow(vcpu->kvm, gfn);
			goto unshadowed;
		}

		shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
		if (shadow) {
			pgprintk("%s: found shadow page for %lx, marking ro\n",
				 __FUNCTION__, gfn);
			access_bits &= ~PT_WRITABLE_MASK;
			if (is_writeble_pte(spte)) {
				spte &= ~PT_WRITABLE_MASK;
				kvm_x86_ops->tlb_flush(vcpu);
			}
			if (write_fault)
				*ptwrite = 1;
		}
	}

unshadowed:

	if (access_bits & PT_WRITABLE_MASK)
		mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);

	pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
	set_shadow_pte(shadow_pte, spte);
	page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
	if (!was_rmapped) {
		rmap_add(vcpu, shadow_pte, (gaddr & PT64_BASE_ADDR_MASK)
			 >> PAGE_SHIFT);
		if (!is_rmap_pte(*shadow_pte)) {
			struct page *page;

			page = pfn_to_page((paddr & PT64_BASE_ADDR_MASK)
					   >> PAGE_SHIFT);
			kvm_release_page(page);
		}
	}
	else
		kvm_release_page(pfn_to_page((paddr & PT64_BASE_ADDR_MASK)
				 >> PAGE_SHIFT));
	if (!ptwrite || !*ptwrite)
		vcpu->last_pte_updated = shadow_pte;
}

static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
			   u64 *shadow_pte, u64 access_bits,
			   int user_fault, int write_fault, int *ptwrite,
			   struct guest_walker *walker, gfn_t gfn)
{
	access_bits &= gpte;
	FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK,
			      gpte, access_bits, user_fault, write_fault,
			      ptwrite, walker, gfn);
}

static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
			      u64 *spte, const void *pte, int bytes,
			      int offset_in_pte)
{
	pt_element_t gpte;

	gpte = *(const pt_element_t *)pte;
	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
		if (!offset_in_pte && !is_present_pte(gpte))
			set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
		return;
	}
	if (bytes < sizeof(pt_element_t))
		return;
	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
	FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
		       0, NULL, NULL,
		       (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
}

static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde,
			   u64 *shadow_pte, u64 access_bits,
			   int user_fault, int write_fault, int *ptwrite,
			   struct guest_walker *walker, gfn_t gfn)
{
	gpa_t gaddr;

	access_bits &= gpde;
	gaddr = (gpa_t)gfn << PAGE_SHIFT;
	if (PTTYPE == 32 && is_cpuid_PSE36())
		gaddr |= (gpde & PT32_DIR_PSE36_MASK) <<
			(32 - PT32_DIR_PSE36_SHIFT);
	FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
			      gpde, access_bits, user_fault, write_fault,
			      ptwrite, walker, gfn);
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			 struct guest_walker *walker,
			 int user_fault, int write_fault, int *ptwrite)
{
	hpa_t shadow_addr;
	int level;
	u64 *shadow_ent;
	u64 *prev_shadow_ent = NULL;

	if (!is_present_pte(walker->pte))
		return NULL;

	shadow_addr = vcpu->mmu.root_hpa;
	level = vcpu->mmu.shadow_root_level;
	if (level == PT32E_ROOT_LEVEL) {
		shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
		shadow_addr &= PT64_BASE_ADDR_MASK;
		--level;
	}

	for (; ; level--) {
		u32 index = SHADOW_PT_INDEX(addr, level);
		struct kvm_mmu_page *shadow_page;
		u64 shadow_pte;
		int metaphysical;
		gfn_t table_gfn;
		unsigned hugepage_access = 0;

		shadow_ent = ((u64 *)__va(shadow_addr)) + index;
		if (is_shadow_present_pte(*shadow_ent)) {
			if (level == PT_PAGE_TABLE_LEVEL)
				break;
			shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
			prev_shadow_ent = shadow_ent;
			continue;
		}

		if (level == PT_PAGE_TABLE_LEVEL)
			break;

		if (level - 1 == PT_PAGE_TABLE_LEVEL
		    && walker->level == PT_DIRECTORY_LEVEL) {
			metaphysical = 1;
			hugepage_access = walker->pte;
			hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
			if (!is_dirty_pte(walker->pte))
				hugepage_access &= ~PT_WRITABLE_MASK;
			hugepage_access >>= PT_WRITABLE_SHIFT;
			if (walker->pte & PT64_NX_MASK)
				hugepage_access |= (1 << 2);
			table_gfn = (walker->pte & PT_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
		} else {
			metaphysical = 0;
			table_gfn = walker->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
					       metaphysical, hugepage_access,
					       shadow_ent);
		shadow_addr = __pa(shadow_page->spt);
		shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
		*shadow_ent = shadow_pte;
		prev_shadow_ent = shadow_ent;
	}

	if (walker->level == PT_DIRECTORY_LEVEL) {
		FNAME(set_pde)(vcpu, walker->pte, shadow_ent,
			       walker->inherited_ar, user_fault, write_fault,
			       ptwrite, walker, walker->gfn);
	} else {
		ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
		FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
			       walker->inherited_ar, user_fault, write_fault,
			       ptwrite, walker, walker->gfn);
	}
	return shadow_ent;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	int fetch_fault = error_code & PFERR_FETCH_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int write_pt = 0;
	int r;

	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	/*
	 * Look up the shadow pte for the faulting address.
	 */
	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!r) {
		pgprintk("%s: guest page fault\n", __FUNCTION__);
		inject_page_fault(vcpu, addr, walker.error_code);
		vcpu->last_pt_write_count = 0; /* reset fork detector */
		return 0;
	}

	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
				  &write_pt);
	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
		 shadow_pte, *shadow_pte, write_pt);

	if (!write_pt)
		vcpu->last_pt_write_count = 0; /* reset fork detector */

	/*
	 * mmio: emulate if accessible, otherwise its a guest fault.
	 */
	if (is_io_pte(*shadow_pte))
		return 1;

	++vcpu->stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");

	return write_pt;
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	gpa_t gpa = UNMAPPED_GVA;
	int r;

	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);

	if (r) {
		gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
		gpa |= vaddr & ~PAGE_MASK;
	}

	return gpa;
}

static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
				 struct kvm_mmu_page *sp)
{
	int i;
	pt_element_t *gpt;
	struct page *page;

	if (sp->role.metaphysical || PTTYPE == 32) {
		nonpaging_prefetch_page(vcpu, sp);
		return;
	}

	page = gfn_to_page(vcpu->kvm, sp->gfn);
	gpt = kmap_atomic(page, KM_USER0);
	for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
		if (is_present_pte(gpt[i]))
			sp->spt[i] = shadow_trap_nonpresent_pte;
		else
			sp->spt[i] = shadow_notrap_nonpresent_pte;
	kunmap_atomic(gpt, KM_USER0);
	kvm_release_page(page);
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef SHADOW_PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_DIR_BASE_ADDR_MASK
#undef PT_LEVEL_BITS
#undef PT_MAX_FULL_LEVELS
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
	28	#define FNAME(name) paging##64_##name
	29	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	30	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	31	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	32	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	33	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
c7addb90	34	#define PT_LEVEL_BITS PT64_LEVEL_BITS
cea0f0e7 AK	35	#ifdef CONFIG_X86_64
	36	#define PT_MAX_FULL_LEVELS 4
	37	#else
	38	#define PT_MAX_FULL_LEVELS 2
	39	#endif
6aa8b732 AK	40	#elif PTTYPE == 32
	41	#define pt_element_t u32
	42	#define guest_walker guest_walker32
	43	#define FNAME(name) paging##32_##name
	44	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	45	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	46	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	47	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	48	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
c7addb90	49	#define PT_LEVEL_BITS PT32_LEVEL_BITS
cea0f0e7	50	#define PT_MAX_FULL_LEVELS 2
6aa8b732 AK	51	#else
	52	#error Invalid PTTYPE value
	53	#endif
	54
	55	/*
	56	* The guest_walker structure emulates the behavior of the hardware page
	57	* table walker.
	58	*/
	59	struct guest_walker {
	60	int level;
cea0f0e7	61	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
fe551881	62	pt_element_t pte;
6aa8b732	63	pt_element_t inherited_ar;
815af8d4	64	gfn_t gfn;
7993ba43	65	u32 error_code;
6aa8b732 AK	66	};
6aa8b732 AK	67
ac79c978 AK	68	/*
	69	* Fetch a guest pte for a guest virtual address
	70	*/
7993ba43 AK	71	static int FNAME(walk_addr)(struct guest_walker *walker,
7993ba43 AK	72	struct kvm_vcpu *vcpu, gva_t addr,
73b1087e	73	int write_fault, int user_fault, int fetch_fault)
6aa8b732	74	{
42bf3f0a	75	pt_element_t pte;
cea0f0e7	76	gfn_t table_gfn;
42bf3f0a AK	77	unsigned index;
42bf3f0a AK	78	gpa_t pte_gpa;
6aa8b732	79
cea0f0e7	80	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
6aa8b732	81	walker->level = vcpu->mmu.root_level;
42bf3f0a	82	pte = vcpu->cr3;
1b0973bd AK	83	#if PTTYPE == 64
1b0973bd AK	84	if (!is_long_mode(vcpu)) {
42bf3f0a AK	85	pte = vcpu->pdptrs[(addr >> 30) & 3];
42bf3f0a AK	86	if (!is_present_pte(pte))
7993ba43	87	goto not_present;
1b0973bd AK	88	--walker->level;
	89	}
	90	#endif
a9058ecd	91	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
f802a307	92	(vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732	93
6aa8b732	94	walker->inherited_ar = PT_USER_MASK \| PT_WRITABLE_MASK;
ac79c978 AK	95
ac79c978 AK	96	for (;;) {
42bf3f0a	97	index = PT_INDEX(addr, walker->level);
ac79c978	98
42bf3f0a	99	table_gfn = (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
ec8d4eae IE	100	pte_gpa = table_gfn << PAGE_SHIFT;
ec8d4eae IE	101	pte_gpa += index * sizeof(pt_element_t);
42bf3f0a AK	102	walker->table_gfn[walker->level - 1] = table_gfn;
	103	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	104	walker->level - 1, table_gfn);
	105
ec8d4eae	106	kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
42bf3f0a AK	107
42bf3f0a AK	108	if (!is_present_pte(pte))
7993ba43 AK	109	goto not_present;
7993ba43 AK	110
42bf3f0a	111	if (write_fault && !is_writeble_pte(pte))
7993ba43 AK	112	if (user_fault \|\| is_write_protection(vcpu))
	113	goto access_error;
	114
42bf3f0a	115	if (user_fault && !(pte & PT_USER_MASK))
7993ba43 AK	116	goto access_error;
7993ba43 AK	117
73b1087e	118	#if PTTYPE == 64
42bf3f0a	119	if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
73b1087e AK	120	goto access_error;
	121	#endif
	122
42bf3f0a	123	if (!(pte & PT_ACCESSED_MASK)) {
bf3f8e86	124	mark_page_dirty(vcpu->kvm, table_gfn);
42bf3f0a	125	pte \|= PT_ACCESSED_MASK;
ec8d4eae	126	kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
bf3f8e86	127	}
815af8d4 AK	128
815af8d4 AK	129	if (walker->level == PT_PAGE_TABLE_LEVEL) {
42bf3f0a	130	walker->gfn = (pte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
815af8d4 AK	131	break;
	132	}
	133
	134	if (walker->level == PT_DIRECTORY_LEVEL
42bf3f0a	135	&& (pte & PT_PAGE_SIZE_MASK)
815af8d4	136	&& (PTTYPE == 64 \|\| is_pse(vcpu))) {
42bf3f0a	137	walker->gfn = (pte & PT_DIR_BASE_ADDR_MASK)
815af8d4 AK	138	>> PAGE_SHIFT;
815af8d4 AK	139	walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
ac79c978	140	break;
815af8d4	141	}
ac79c978	142
42bf3f0a	143	walker->inherited_ar &= pte;
ac79c978 AK	144	--walker->level;
ac79c978 AK	145	}
42bf3f0a AK	146
	147	if (write_fault && !is_dirty_pte(pte)) {
	148	mark_page_dirty(vcpu->kvm, table_gfn);
	149	pte \|= PT_DIRTY_MASK;
ec8d4eae	150	kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
42bf3f0a AK	151	kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
	152	}
	153
	154	walker->pte = pte;
	155	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)pte);
7993ba43 AK	156	return 1;
	157
	158	not_present:
	159	walker->error_code = 0;
	160	goto err;
	161
	162	access_error:
	163	walker->error_code = PFERR_PRESENT_MASK;
	164
	165	err:
	166	if (write_fault)
	167	walker->error_code \|= PFERR_WRITE_MASK;
	168	if (user_fault)
	169	walker->error_code \|= PFERR_USER_MASK;
73b1087e AK	170	if (fetch_fault)
73b1087e AK	171	walker->error_code \|= PFERR_FETCH_MASK;
fe551881	172	return 0;
6aa8b732 AK	173	}
6aa8b732 AK	174
e60d75ea AK	175	static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
	176	u64 *shadow_pte,
	177	gpa_t gaddr,
fe551881	178	pt_element_t gpte,
e60d75ea	179	u64 access_bits,
97a0a01e	180	int user_fault,
63b1ad24	181	int write_fault,
97a0a01e AK	182	int *ptwrite,
97a0a01e AK	183	struct guest_walker *walker,
e60d75ea AK	184	gfn_t gfn)
	185	{
	186	hpa_t paddr;
fe551881	187	int dirty = gpte & PT_DIRTY_MASK;
c7addb90 AK	188	u64 spte;
c7addb90 AK	189	int was_rmapped = is_rmap_pte(*shadow_pte);
97a0a01e AK	190
	191	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
	192	" user_fault %d gfn %lx\n",
c7addb90	193	__FUNCTION__, *shadow_pte, (u64)gpte, access_bits,
97a0a01e AK	194	write_fault, user_fault, gfn);
97a0a01e AK	195
12b7d28f AK	196	/*
	197	* We don't set the accessed bit, since we sometimes want to see
	198	* whether the guest actually used the pte (in order to detect
	199	* demand paging).
	200	*/
	201	spte = PT_PRESENT_MASK \| PT_DIRTY_MASK;
fe551881	202	spte \|= gpte & PT64_NX_MASK;
e60d75ea AK	203	if (!dirty)
	204	access_bits &= ~PT_WRITABLE_MASK;
	205
4a4c9924	206	paddr = gpa_to_hpa(vcpu->kvm, gaddr & PT64_BASE_ADDR_MASK);
e60d75ea	207
0d551bb6	208	spte \|= PT_PRESENT_MASK;
97a0a01e	209	if (access_bits & PT_USER_MASK)
0d551bb6	210	spte \|= PT_USER_MASK;
e60d75ea AK	211
e60d75ea AK	212	if (is_error_hpa(paddr)) {
c7addb90 AK	213	set_shadow_pte(shadow_pte,
c7addb90 AK	214	shadow_trap_nonpresent_pte \| PT_SHADOW_IO_MARK);
8a7ae055 IE	215	kvm_release_page(pfn_to_page((paddr & PT64_BASE_ADDR_MASK)
8a7ae055 IE	216	>> PAGE_SHIFT));
e60d75ea AK	217	return;
	218	}
	219
0d551bb6	220	spte \|= paddr;
e60d75ea	221
97a0a01e AK	222	if ((access_bits & PT_WRITABLE_MASK)
97a0a01e AK	223	\|\| (write_fault && !is_write_protection(vcpu) && !user_fault)) {
e60d75ea AK	224	struct kvm_mmu_page *shadow;
e60d75ea AK	225
0d551bb6	226	spte \|= PT_WRITABLE_MASK;
97a0a01e	227	if (user_fault) {
f67a46f4	228	mmu_unshadow(vcpu->kvm, gfn);
97a0a01e AK	229	goto unshadowed;
	230	}
	231
f67a46f4	232	shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
e60d75ea AK	233	if (shadow) {
	234	pgprintk("%s: found shadow page for %lx, marking ro\n",
	235	__FUNCTION__, gfn);
	236	access_bits &= ~PT_WRITABLE_MASK;
0d551bb6 AK	237	if (is_writeble_pte(spte)) {
0d551bb6 AK	238	spte &= ~PT_WRITABLE_MASK;
cbdd1bea	239	kvm_x86_ops->tlb_flush(vcpu);
e60d75ea	240	}
97a0a01e AK	241	if (write_fault)
97a0a01e AK	242	*ptwrite = 1;
e60d75ea AK	243	}
	244	}
	245
97a0a01e AK	246	unshadowed:
97a0a01e AK	247
e60d75ea AK	248	if (access_bits & PT_WRITABLE_MASK)
	249	mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);
	250
c7addb90	251	pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
e663ee64	252	set_shadow_pte(shadow_pte, spte);
e60d75ea	253	page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
8a7ae055	254	if (!was_rmapped) {
290fc38d IE	255	rmap_add(vcpu, shadow_pte, (gaddr & PT64_BASE_ADDR_MASK)
290fc38d IE	256	>> PAGE_SHIFT);
8a7ae055 IE	257	if (!is_rmap_pte(*shadow_pte)) {
	258	struct page *page;
	259
	260	page = pfn_to_page((paddr & PT64_BASE_ADDR_MASK)
	261	>> PAGE_SHIFT);
	262	kvm_release_page(page);
	263	}
	264	}
	265	else
	266	kvm_release_page(pfn_to_page((paddr & PT64_BASE_ADDR_MASK)
	267	>> PAGE_SHIFT));
12b7d28f AK	268	if (!ptwrite \|\| !*ptwrite)
12b7d28f AK	269	vcpu->last_pte_updated = shadow_pte;
e60d75ea AK	270	}
e60d75ea AK	271
fe551881	272	static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
63b1ad24	273	u64 *shadow_pte, u64 access_bits,
97a0a01e AK	274	int user_fault, int write_fault, int *ptwrite,
97a0a01e AK	275	struct guest_walker *walker, gfn_t gfn)
6aa8b732	276	{
fe551881 SL	277	access_bits &= gpte;
fe551881 SL	278	FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK,
97a0a01e AK	279	gpte, access_bits, user_fault, write_fault,
97a0a01e AK	280	ptwrite, walker, gfn);
6aa8b732 AK	281	}
6aa8b732 AK	282
0028425f	283	static void FNAME(update_pte)(struct kvm_vcpu vcpu, struct kvm_mmu_page page,
c7addb90 AK	284	u64 spte, const void pte, int bytes,
c7addb90 AK	285	int offset_in_pte)
0028425f AK	286	{
	287	pt_element_t gpte;
	288
0028425f	289	gpte = (const pt_element_t )pte;
c7addb90 AK	290	if (~gpte & (PT_PRESENT_MASK \| PT_ACCESSED_MASK)) {
	291	if (!offset_in_pte && !is_present_pte(gpte))
	292	set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
	293	return;
	294	}
	295	if (bytes < sizeof(pt_element_t))
0028425f AK	296	return;
0028425f AK	297	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
fe551881	298	FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK \| PT_WRITABLE_MASK, 0,
97a0a01e	299	0, NULL, NULL,
0028425f AK	300	(gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
	301	}
	302
fe551881	303	static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde,
97a0a01e AK	304	u64 *shadow_pte, u64 access_bits,
	305	int user_fault, int write_fault, int *ptwrite,
	306	struct guest_walker *walker, gfn_t gfn)
6aa8b732 AK	307	{
	308	gpa_t gaddr;
	309
fe551881	310	access_bits &= gpde;
815af8d4	311	gaddr = (gpa_t)gfn << PAGE_SHIFT;
6aa8b732	312	if (PTTYPE == 32 && is_cpuid_PSE36())
fe551881	313	gaddr \|= (gpde & PT32_DIR_PSE36_MASK) <<
6aa8b732	314	(32 - PT32_DIR_PSE36_SHIFT);
e60d75ea	315	FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
97a0a01e AK	316	gpde, access_bits, user_fault, write_fault,
97a0a01e AK	317	ptwrite, walker, gfn);
6aa8b732 AK	318	}
6aa8b732 AK	319
6aa8b732 AK	320	/*
	321	* Fetch a shadow pte for a specific level in the paging hierarchy.
	322	*/
	323	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
97a0a01e AK	324	struct guest_walker *walker,
97a0a01e AK	325	int user_fault, int write_fault, int *ptwrite)
6aa8b732 AK	326	{
	327	hpa_t shadow_addr;
	328	int level;
ef0197e8	329	u64 *shadow_ent;
6aa8b732	330	u64 *prev_shadow_ent = NULL;
ac79c978	331
fe551881	332	if (!is_present_pte(walker->pte))
ac79c978	333	return NULL;
6aa8b732 AK	334
	335	shadow_addr = vcpu->mmu.root_hpa;
	336	level = vcpu->mmu.shadow_root_level;
aef3d3fe AK	337	if (level == PT32E_ROOT_LEVEL) {
	338	shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
	339	shadow_addr &= PT64_BASE_ADDR_MASK;
	340	--level;
	341	}
6aa8b732 AK	342
	343	for (; ; level--) {
	344	u32 index = SHADOW_PT_INDEX(addr, level);
25c0de2c	345	struct kvm_mmu_page *shadow_page;
8c7bb723	346	u64 shadow_pte;
cea0f0e7 AK	347	int metaphysical;
cea0f0e7 AK	348	gfn_t table_gfn;
d28c6cfb	349	unsigned hugepage_access = 0;
6aa8b732	350
ef0197e8	351	shadow_ent = ((u64 *)__va(shadow_addr)) + index;
c7addb90	352	if (is_shadow_present_pte(*shadow_ent)) {
6aa8b732	353	if (level == PT_PAGE_TABLE_LEVEL)
97a0a01e	354	break;
6aa8b732 AK	355	shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
	356	prev_shadow_ent = shadow_ent;
	357	continue;
	358	}
	359
ef0197e8 AK	360	if (level == PT_PAGE_TABLE_LEVEL)
ef0197e8 AK	361	break;
6aa8b732	362
cea0f0e7 AK	363	if (level - 1 == PT_PAGE_TABLE_LEVEL
	364	&& walker->level == PT_DIRECTORY_LEVEL) {
	365	metaphysical = 1;
fe551881	366	hugepage_access = walker->pte;
d28c6cfb	367	hugepage_access &= PT_USER_MASK \| PT_WRITABLE_MASK;
cc70e737 AK	368	if (!is_dirty_pte(walker->pte))
cc70e737 AK	369	hugepage_access &= ~PT_WRITABLE_MASK;
c22e3514	370	hugepage_access >>= PT_WRITABLE_SHIFT;
fe551881	371	if (walker->pte & PT64_NX_MASK)
d55e2cb2	372	hugepage_access \|= (1 << 2);
fe551881	373	table_gfn = (walker->pte & PT_BASE_ADDR_MASK)
cea0f0e7 AK	374	>> PAGE_SHIFT;
	375	} else {
	376	metaphysical = 0;
	377	table_gfn = walker->table_gfn[level - 2];
	378	}
	379	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
d28c6cfb AK	380	metaphysical, hugepage_access,
d28c6cfb AK	381	shadow_ent);
47ad8e68	382	shadow_addr = __pa(shadow_page->spt);
aef3d3fe AK	383	shadow_pte = shadow_addr \| PT_PRESENT_MASK \| PT_ACCESSED_MASK
aef3d3fe AK	384	\| PT_WRITABLE_MASK \| PT_USER_MASK;
8c7bb723	385	*shadow_ent = shadow_pte;
6aa8b732 AK	386	prev_shadow_ent = shadow_ent;
6aa8b732 AK	387	}
ef0197e8 AK	388
ef0197e8 AK	389	if (walker->level == PT_DIRECTORY_LEVEL) {
fe551881	390	FNAME(set_pde)(vcpu, walker->pte, shadow_ent,
97a0a01e AK	391	walker->inherited_ar, user_fault, write_fault,
97a0a01e AK	392	ptwrite, walker, walker->gfn);
ef0197e8 AK	393	} else {
ef0197e8 AK	394	ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
fe551881	395	FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
97a0a01e AK	396	walker->inherited_ar, user_fault, write_fault,
97a0a01e AK	397	ptwrite, walker, walker->gfn);
ef0197e8 AK	398	}
ef0197e8 AK	399	return shadow_ent;
6aa8b732 AK	400	}
6aa8b732 AK	401
6aa8b732 AK	402	/*
	403	* Page fault handler. There are several causes for a page fault:
	404	* - there is no shadow pte for the guest pte
	405	* - write access through a shadow pte marked read only so that we can set
	406	* the dirty bit
	407	* - write access to a shadow pte marked read only so we can update the page
	408	* dirty bitmap, when userspace requests it
	409	* - mmio access; in this case we will never install a present shadow pte
	410	* - normal guest page fault due to the guest pte marked not present, not
	411	* writable, or not executable
	412	*
e2dec939 AK	413	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
e2dec939 AK	414	* a negative value on error.
6aa8b732 AK	415	*/
	416	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	417	u32 error_code)
	418	{
	419	int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732	420	int user_fault = error_code & PFERR_USER_MASK;
73b1087e	421	int fetch_fault = error_code & PFERR_FETCH_MASK;
6aa8b732 AK	422	struct guest_walker walker;
6aa8b732 AK	423	u64 *shadow_pte;
cea0f0e7	424	int write_pt = 0;
e2dec939	425	int r;
6aa8b732	426
cea0f0e7	427	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
37a7d8b0	428	kvm_mmu_audit(vcpu, "pre page fault");
714b93da	429
e2dec939 AK	430	r = mmu_topup_memory_caches(vcpu);
	431	if (r)
	432	return r;
714b93da	433
6aa8b732 AK	434	/*
	435	* Look up the shadow pte for the faulting address.
	436	*/
73b1087e AK	437	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
73b1087e AK	438	fetch_fault);
6aa8b732 AK	439
	440	/*
	441	* The page is not mapped by the guest. Let the guest handle it.
	442	*/
7993ba43 AK	443	if (!r) {
	444	pgprintk("%s: guest page fault\n", __FUNCTION__);
	445	inject_page_fault(vcpu, addr, walker.error_code);
a25f7e1f	446	vcpu->last_pt_write_count = 0; /* reset fork detector */
6aa8b732 AK	447	return 0;
	448	}
	449
97a0a01e AK	450	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
	451	&write_pt);
	452	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
	453	shadow_pte, *shadow_pte, write_pt);
cea0f0e7	454
a25f7e1f AK	455	if (!write_pt)
	456	vcpu->last_pt_write_count = 0; /* reset fork detector */
	457
6aa8b732 AK	458	/*
	459	* mmio: emulate if accessible, otherwise its a guest fault.
	460	*/
d27d4aca	461	if (is_io_pte(*shadow_pte))
7993ba43	462	return 1;
6aa8b732	463
1165f5fe	464	++vcpu->stat.pf_fixed;
37a7d8b0	465	kvm_mmu_audit(vcpu, "post page fault (fixed)");
6aa8b732	466
cea0f0e7	467	return write_pt;
6aa8b732 AK	468	}
	469
	470	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
	471	{
	472	struct guest_walker walker;
e119d117 AK	473	gpa_t gpa = UNMAPPED_GVA;
e119d117 AK	474	int r;
6aa8b732	475
e119d117	476	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
6aa8b732	477
e119d117 AK	478	if (r) {
	479	gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
	480	gpa \|= vaddr & ~PAGE_MASK;
6aa8b732 AK	481	}
	482
	483	return gpa;
	484	}
	485
c7addb90 AK	486	static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
	487	struct kvm_mmu_page *sp)
	488	{
	489	int i;
	490	pt_element_t *gpt;
8a7ae055	491	struct page *page;
c7addb90 AK	492
	493	if (sp->role.metaphysical \|\| PTTYPE == 32) {
	494	nonpaging_prefetch_page(vcpu, sp);
	495	return;
	496	}
	497
8a7ae055 IE	498	page = gfn_to_page(vcpu->kvm, sp->gfn);
8a7ae055 IE	499	gpt = kmap_atomic(page, KM_USER0);
c7addb90 AK	500	for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
	501	if (is_present_pte(gpt[i]))
	502	sp->spt[i] = shadow_trap_nonpresent_pte;
	503	else
	504	sp->spt[i] = shadow_notrap_nonpresent_pte;
	505	kunmap_atomic(gpt, KM_USER0);
8a7ae055	506	kvm_release_page(page);
c7addb90 AK	507	}
c7addb90 AK	508
6aa8b732 AK	509	#undef pt_element_t
	510	#undef guest_walker
	511	#undef FNAME
	512	#undef PT_BASE_ADDR_MASK
	513	#undef PT_INDEX
	514	#undef SHADOW_PT_INDEX
	515	#undef PT_LEVEL_MASK
6aa8b732	516	#undef PT_DIR_BASE_ADDR_MASK
c7addb90	517	#undef PT_LEVEL_BITS
cea0f0e7	518	#undef PT_MAX_FULL_LEVELS