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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
22 | * so the code in this file is compiled twice, once per pte size. | |
23 | */ | |
24 | ||
25 | #if PTTYPE == 64 | |
26 | #define pt_element_t u64 | |
27 | #define guest_walker guest_walker64 | |
28 | #define FNAME(name) paging##64_##name | |
29 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
30 | #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK | |
31 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
32 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
33 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) | |
34 | #define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK | |
6aa8b732 AK |
35 | #elif PTTYPE == 32 |
36 | #define pt_element_t u32 | |
37 | #define guest_walker guest_walker32 | |
38 | #define FNAME(name) paging##32_##name | |
39 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
40 | #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK | |
41 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) | |
42 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
43 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) | |
44 | #define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK | |
6aa8b732 AK |
45 | #else |
46 | #error Invalid PTTYPE value | |
47 | #endif | |
48 | ||
49 | /* | |
50 | * The guest_walker structure emulates the behavior of the hardware page | |
51 | * table walker. | |
52 | */ | |
53 | struct guest_walker { | |
54 | int level; | |
6bcbd6ab | 55 | gfn_t table_gfn; |
6aa8b732 | 56 | pt_element_t *table; |
ac79c978 | 57 | pt_element_t *ptep; |
6aa8b732 AK |
58 | pt_element_t inherited_ar; |
59 | }; | |
60 | ||
ac79c978 AK |
61 | /* |
62 | * Fetch a guest pte for a guest virtual address | |
63 | */ | |
64 | static void FNAME(walk_addr)(struct guest_walker *walker, | |
65 | struct kvm_vcpu *vcpu, gva_t addr) | |
6aa8b732 AK |
66 | { |
67 | hpa_t hpa; | |
68 | struct kvm_memory_slot *slot; | |
ac79c978 | 69 | pt_element_t *ptep; |
1b0973bd | 70 | pt_element_t root; |
6aa8b732 AK |
71 | |
72 | walker->level = vcpu->mmu.root_level; | |
1b0973bd AK |
73 | walker->table = NULL; |
74 | root = vcpu->cr3; | |
75 | #if PTTYPE == 64 | |
76 | if (!is_long_mode(vcpu)) { | |
77 | walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3]; | |
78 | root = *walker->ptep; | |
79 | if (!(root & PT_PRESENT_MASK)) | |
80 | return; | |
81 | --walker->level; | |
82 | } | |
83 | #endif | |
84 | walker->table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
6bcbd6ab | 85 | slot = gfn_to_memslot(vcpu->kvm, walker->table_gfn); |
1b0973bd | 86 | hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK); |
6aa8b732 AK |
87 | walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0); |
88 | ||
a9058ecd | 89 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
6aa8b732 AK |
90 | (vcpu->cr3 & ~(PAGE_MASK | CR3_FLAGS_MASK)) == 0); |
91 | ||
6aa8b732 | 92 | walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK; |
ac79c978 AK |
93 | |
94 | for (;;) { | |
95 | int index = PT_INDEX(addr, walker->level); | |
96 | hpa_t paddr; | |
97 | ||
98 | ptep = &walker->table[index]; | |
99 | ASSERT(((unsigned long)walker->table & PAGE_MASK) == | |
100 | ((unsigned long)ptep & PAGE_MASK)); | |
101 | ||
1b0973bd AK |
102 | if (is_present_pte(*ptep) && !(*ptep & PT_ACCESSED_MASK)) |
103 | *ptep |= PT_ACCESSED_MASK; | |
ac79c978 AK |
104 | |
105 | if (!is_present_pte(*ptep) || | |
106 | walker->level == PT_PAGE_TABLE_LEVEL || | |
107 | (walker->level == PT_DIRECTORY_LEVEL && | |
108 | (*ptep & PT_PAGE_SIZE_MASK) && | |
109 | (PTTYPE == 64 || is_pse(vcpu)))) | |
110 | break; | |
111 | ||
112 | if (walker->level != 3 || is_long_mode(vcpu)) | |
113 | walker->inherited_ar &= walker->table[index]; | |
114 | walker->table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
115 | paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK); | |
116 | kunmap_atomic(walker->table, KM_USER0); | |
117 | walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT), | |
118 | KM_USER0); | |
119 | --walker->level; | |
120 | } | |
121 | walker->ptep = ptep; | |
6aa8b732 AK |
122 | } |
123 | ||
124 | static void FNAME(release_walker)(struct guest_walker *walker) | |
125 | { | |
1b0973bd AK |
126 | if (walker->table) |
127 | kunmap_atomic(walker->table, KM_USER0); | |
6aa8b732 AK |
128 | } |
129 | ||
130 | static void FNAME(set_pte)(struct kvm_vcpu *vcpu, u64 guest_pte, | |
131 | u64 *shadow_pte, u64 access_bits) | |
132 | { | |
133 | ASSERT(*shadow_pte == 0); | |
134 | access_bits &= guest_pte; | |
135 | *shadow_pte = (guest_pte & PT_PTE_COPY_MASK); | |
136 | set_pte_common(vcpu, shadow_pte, guest_pte & PT_BASE_ADDR_MASK, | |
137 | guest_pte & PT_DIRTY_MASK, access_bits); | |
138 | } | |
139 | ||
140 | static void FNAME(set_pde)(struct kvm_vcpu *vcpu, u64 guest_pde, | |
141 | u64 *shadow_pte, u64 access_bits, | |
142 | int index) | |
143 | { | |
144 | gpa_t gaddr; | |
145 | ||
146 | ASSERT(*shadow_pte == 0); | |
147 | access_bits &= guest_pde; | |
148 | gaddr = (guest_pde & PT_DIR_BASE_ADDR_MASK) + PAGE_SIZE * index; | |
149 | if (PTTYPE == 32 && is_cpuid_PSE36()) | |
150 | gaddr |= (guest_pde & PT32_DIR_PSE36_MASK) << | |
151 | (32 - PT32_DIR_PSE36_SHIFT); | |
8c7bb723 | 152 | *shadow_pte = guest_pde & PT_PTE_COPY_MASK; |
6aa8b732 AK |
153 | set_pte_common(vcpu, shadow_pte, gaddr, |
154 | guest_pde & PT_DIRTY_MASK, access_bits); | |
155 | } | |
156 | ||
6aa8b732 AK |
157 | /* |
158 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
159 | */ | |
160 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, | |
161 | struct guest_walker *walker) | |
162 | { | |
163 | hpa_t shadow_addr; | |
164 | int level; | |
165 | u64 *prev_shadow_ent = NULL; | |
ac79c978 AK |
166 | pt_element_t *guest_ent = walker->ptep; |
167 | ||
168 | if (!is_present_pte(*guest_ent)) | |
169 | return NULL; | |
6aa8b732 AK |
170 | |
171 | shadow_addr = vcpu->mmu.root_hpa; | |
172 | level = vcpu->mmu.shadow_root_level; | |
aef3d3fe AK |
173 | if (level == PT32E_ROOT_LEVEL) { |
174 | shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3]; | |
175 | shadow_addr &= PT64_BASE_ADDR_MASK; | |
176 | --level; | |
177 | } | |
6aa8b732 AK |
178 | |
179 | for (; ; level--) { | |
180 | u32 index = SHADOW_PT_INDEX(addr, level); | |
181 | u64 *shadow_ent = ((u64 *)__va(shadow_addr)) + index; | |
25c0de2c | 182 | struct kvm_mmu_page *shadow_page; |
8c7bb723 | 183 | u64 shadow_pte; |
6aa8b732 AK |
184 | |
185 | if (is_present_pte(*shadow_ent) || is_io_pte(*shadow_ent)) { | |
186 | if (level == PT_PAGE_TABLE_LEVEL) | |
187 | return shadow_ent; | |
188 | shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK; | |
189 | prev_shadow_ent = shadow_ent; | |
190 | continue; | |
191 | } | |
192 | ||
6aa8b732 AK |
193 | if (level == PT_PAGE_TABLE_LEVEL) { |
194 | ||
195 | if (walker->level == PT_DIRECTORY_LEVEL) { | |
196 | if (prev_shadow_ent) | |
197 | *prev_shadow_ent |= PT_SHADOW_PS_MARK; | |
198 | FNAME(set_pde)(vcpu, *guest_ent, shadow_ent, | |
199 | walker->inherited_ar, | |
200 | PT_INDEX(addr, PT_PAGE_TABLE_LEVEL)); | |
201 | } else { | |
202 | ASSERT(walker->level == PT_PAGE_TABLE_LEVEL); | |
203 | FNAME(set_pte)(vcpu, *guest_ent, shadow_ent, walker->inherited_ar); | |
204 | } | |
205 | return shadow_ent; | |
206 | } | |
207 | ||
25c0de2c AK |
208 | shadow_page = kvm_mmu_alloc_page(vcpu, shadow_ent); |
209 | if (!shadow_page) | |
6aa8b732 | 210 | return ERR_PTR(-ENOMEM); |
25c0de2c | 211 | shadow_addr = shadow_page->page_hpa; |
aef3d3fe AK |
212 | shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK |
213 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
8c7bb723 | 214 | *shadow_ent = shadow_pte; |
6aa8b732 AK |
215 | prev_shadow_ent = shadow_ent; |
216 | } | |
217 | } | |
218 | ||
219 | /* | |
220 | * The guest faulted for write. We need to | |
221 | * | |
222 | * - check write permissions | |
223 | * - update the guest pte dirty bit | |
224 | * - update our own dirty page tracking structures | |
225 | */ | |
226 | static int FNAME(fix_write_pf)(struct kvm_vcpu *vcpu, | |
227 | u64 *shadow_ent, | |
228 | struct guest_walker *walker, | |
229 | gva_t addr, | |
230 | int user) | |
231 | { | |
232 | pt_element_t *guest_ent; | |
233 | int writable_shadow; | |
234 | gfn_t gfn; | |
235 | ||
236 | if (is_writeble_pte(*shadow_ent)) | |
237 | return 0; | |
238 | ||
239 | writable_shadow = *shadow_ent & PT_SHADOW_WRITABLE_MASK; | |
240 | if (user) { | |
241 | /* | |
242 | * User mode access. Fail if it's a kernel page or a read-only | |
243 | * page. | |
244 | */ | |
245 | if (!(*shadow_ent & PT_SHADOW_USER_MASK) || !writable_shadow) | |
246 | return 0; | |
247 | ASSERT(*shadow_ent & PT_USER_MASK); | |
248 | } else | |
249 | /* | |
250 | * Kernel mode access. Fail if it's a read-only page and | |
251 | * supervisor write protection is enabled. | |
252 | */ | |
253 | if (!writable_shadow) { | |
254 | if (is_write_protection(vcpu)) | |
255 | return 0; | |
256 | *shadow_ent &= ~PT_USER_MASK; | |
257 | } | |
258 | ||
ac79c978 | 259 | guest_ent = walker->ptep; |
6aa8b732 AK |
260 | |
261 | if (!is_present_pte(*guest_ent)) { | |
262 | *shadow_ent = 0; | |
263 | return 0; | |
264 | } | |
265 | ||
266 | gfn = (*guest_ent & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
267 | mark_page_dirty(vcpu->kvm, gfn); | |
268 | *shadow_ent |= PT_WRITABLE_MASK; | |
269 | *guest_ent |= PT_DIRTY_MASK; | |
cd4a4e53 | 270 | rmap_add(vcpu->kvm, shadow_ent); |
6aa8b732 AK |
271 | |
272 | return 1; | |
273 | } | |
274 | ||
275 | /* | |
276 | * Page fault handler. There are several causes for a page fault: | |
277 | * - there is no shadow pte for the guest pte | |
278 | * - write access through a shadow pte marked read only so that we can set | |
279 | * the dirty bit | |
280 | * - write access to a shadow pte marked read only so we can update the page | |
281 | * dirty bitmap, when userspace requests it | |
282 | * - mmio access; in this case we will never install a present shadow pte | |
283 | * - normal guest page fault due to the guest pte marked not present, not | |
284 | * writable, or not executable | |
285 | * | |
286 | * Returns: 1 if we need to emulate the instruction, 0 otherwise | |
287 | */ | |
288 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
289 | u32 error_code) | |
290 | { | |
291 | int write_fault = error_code & PFERR_WRITE_MASK; | |
292 | int pte_present = error_code & PFERR_PRESENT_MASK; | |
293 | int user_fault = error_code & PFERR_USER_MASK; | |
294 | struct guest_walker walker; | |
295 | u64 *shadow_pte; | |
296 | int fixed; | |
297 | ||
298 | /* | |
299 | * Look up the shadow pte for the faulting address. | |
300 | */ | |
301 | for (;;) { | |
ac79c978 | 302 | FNAME(walk_addr)(&walker, vcpu, addr); |
6aa8b732 AK |
303 | shadow_pte = FNAME(fetch)(vcpu, addr, &walker); |
304 | if (IS_ERR(shadow_pte)) { /* must be -ENOMEM */ | |
305 | nonpaging_flush(vcpu); | |
306 | FNAME(release_walker)(&walker); | |
307 | continue; | |
308 | } | |
309 | break; | |
310 | } | |
311 | ||
312 | /* | |
313 | * The page is not mapped by the guest. Let the guest handle it. | |
314 | */ | |
315 | if (!shadow_pte) { | |
316 | inject_page_fault(vcpu, addr, error_code); | |
317 | FNAME(release_walker)(&walker); | |
318 | return 0; | |
319 | } | |
320 | ||
321 | /* | |
322 | * Update the shadow pte. | |
323 | */ | |
324 | if (write_fault) | |
325 | fixed = FNAME(fix_write_pf)(vcpu, shadow_pte, &walker, addr, | |
326 | user_fault); | |
327 | else | |
328 | fixed = fix_read_pf(shadow_pte); | |
329 | ||
330 | FNAME(release_walker)(&walker); | |
331 | ||
332 | /* | |
333 | * mmio: emulate if accessible, otherwise its a guest fault. | |
334 | */ | |
335 | if (is_io_pte(*shadow_pte)) { | |
336 | if (may_access(*shadow_pte, write_fault, user_fault)) | |
337 | return 1; | |
338 | pgprintk("%s: io work, no access\n", __FUNCTION__); | |
339 | inject_page_fault(vcpu, addr, | |
340 | error_code | PFERR_PRESENT_MASK); | |
341 | return 0; | |
342 | } | |
343 | ||
344 | /* | |
345 | * pte not present, guest page fault. | |
346 | */ | |
347 | if (pte_present && !fixed) { | |
348 | inject_page_fault(vcpu, addr, error_code); | |
349 | return 0; | |
350 | } | |
351 | ||
352 | ++kvm_stat.pf_fixed; | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr) | |
358 | { | |
359 | struct guest_walker walker; | |
360 | pt_element_t guest_pte; | |
361 | gpa_t gpa; | |
362 | ||
ac79c978 AK |
363 | FNAME(walk_addr)(&walker, vcpu, vaddr); |
364 | guest_pte = *walker.ptep; | |
6aa8b732 AK |
365 | FNAME(release_walker)(&walker); |
366 | ||
367 | if (!is_present_pte(guest_pte)) | |
368 | return UNMAPPED_GVA; | |
369 | ||
370 | if (walker.level == PT_DIRECTORY_LEVEL) { | |
371 | ASSERT((guest_pte & PT_PAGE_SIZE_MASK)); | |
372 | ASSERT(PTTYPE == 64 || is_pse(vcpu)); | |
373 | ||
374 | gpa = (guest_pte & PT_DIR_BASE_ADDR_MASK) | (vaddr & | |
375 | (PT_LEVEL_MASK(PT_PAGE_TABLE_LEVEL) | ~PAGE_MASK)); | |
376 | ||
377 | if (PTTYPE == 32 && is_cpuid_PSE36()) | |
378 | gpa |= (guest_pte & PT32_DIR_PSE36_MASK) << | |
379 | (32 - PT32_DIR_PSE36_SHIFT); | |
380 | } else { | |
381 | gpa = (guest_pte & PT_BASE_ADDR_MASK); | |
382 | gpa |= (vaddr & ~PAGE_MASK); | |
383 | } | |
384 | ||
385 | return gpa; | |
386 | } | |
387 | ||
388 | #undef pt_element_t | |
389 | #undef guest_walker | |
390 | #undef FNAME | |
391 | #undef PT_BASE_ADDR_MASK | |
392 | #undef PT_INDEX | |
393 | #undef SHADOW_PT_INDEX | |
394 | #undef PT_LEVEL_MASK | |
395 | #undef PT_PTE_COPY_MASK | |
396 | #undef PT_NON_PTE_COPY_MASK | |
397 | #undef PT_DIR_BASE_ADDR_MASK |