KVM: MMU: Remove extra gaddr parameter from set_pte_common()
[deliverable/linux.git] / drivers / kvm / paging_tmpl.h
CommitLineData
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
19
20/*
21 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
22 * so the code in this file is compiled twice, once per pte size.
23 */
24
25#if PTTYPE == 64
26 #define pt_element_t u64
27 #define guest_walker guest_walker64
28 #define FNAME(name) paging##64_##name
29 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
30 #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
31 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
32 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
33 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
c7addb90 34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
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35 #ifdef CONFIG_X86_64
36 #define PT_MAX_FULL_LEVELS 4
37 #else
38 #define PT_MAX_FULL_LEVELS 2
39 #endif
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40#elif PTTYPE == 32
41 #define pt_element_t u32
42 #define guest_walker guest_walker32
43 #define FNAME(name) paging##32_##name
44 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
45 #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
46 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
47 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
48 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
c7addb90 49 #define PT_LEVEL_BITS PT32_LEVEL_BITS
cea0f0e7 50 #define PT_MAX_FULL_LEVELS 2
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51#else
52 #error Invalid PTTYPE value
53#endif
54
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55#define gpte_to_gfn FNAME(gpte_to_gfn)
56#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
57
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58/*
59 * The guest_walker structure emulates the behavior of the hardware page
60 * table walker.
61 */
62struct guest_walker {
63 int level;
cea0f0e7 64 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
fe551881 65 pt_element_t pte;
6aa8b732 66 pt_element_t inherited_ar;
815af8d4 67 gfn_t gfn;
7993ba43 68 u32 error_code;
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69};
70
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71static gfn_t gpte_to_gfn(pt_element_t gpte)
72{
73 return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
74}
75
76static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
77{
78 return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
79}
80
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81/*
82 * Fetch a guest pte for a guest virtual address
83 */
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84static int FNAME(walk_addr)(struct guest_walker *walker,
85 struct kvm_vcpu *vcpu, gva_t addr,
73b1087e 86 int write_fault, int user_fault, int fetch_fault)
6aa8b732 87{
42bf3f0a 88 pt_element_t pte;
cea0f0e7 89 gfn_t table_gfn;
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90 unsigned index;
91 gpa_t pte_gpa;
6aa8b732 92
cea0f0e7 93 pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
6aa8b732 94 walker->level = vcpu->mmu.root_level;
42bf3f0a 95 pte = vcpu->cr3;
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96#if PTTYPE == 64
97 if (!is_long_mode(vcpu)) {
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98 pte = vcpu->pdptrs[(addr >> 30) & 3];
99 if (!is_present_pte(pte))
7993ba43 100 goto not_present;
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101 --walker->level;
102 }
103#endif
a9058ecd 104 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
f802a307 105 (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732 106
6aa8b732 107 walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;
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108
109 for (;;) {
42bf3f0a 110 index = PT_INDEX(addr, walker->level);
ac79c978 111
5fb07ddb 112 table_gfn = gpte_to_gfn(pte);
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113 pte_gpa = table_gfn << PAGE_SHIFT;
114 pte_gpa += index * sizeof(pt_element_t);
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115 walker->table_gfn[walker->level - 1] = table_gfn;
116 pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
117 walker->level - 1, table_gfn);
118
ec8d4eae 119 kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
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120
121 if (!is_present_pte(pte))
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122 goto not_present;
123
42bf3f0a 124 if (write_fault && !is_writeble_pte(pte))
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125 if (user_fault || is_write_protection(vcpu))
126 goto access_error;
127
42bf3f0a 128 if (user_fault && !(pte & PT_USER_MASK))
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129 goto access_error;
130
73b1087e 131#if PTTYPE == 64
42bf3f0a 132 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
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133 goto access_error;
134#endif
135
42bf3f0a 136 if (!(pte & PT_ACCESSED_MASK)) {
bf3f8e86 137 mark_page_dirty(vcpu->kvm, table_gfn);
42bf3f0a 138 pte |= PT_ACCESSED_MASK;
ec8d4eae 139 kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
bf3f8e86 140 }
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141
142 if (walker->level == PT_PAGE_TABLE_LEVEL) {
5fb07ddb 143 walker->gfn = gpte_to_gfn(pte);
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144 break;
145 }
146
147 if (walker->level == PT_DIRECTORY_LEVEL
42bf3f0a 148 && (pte & PT_PAGE_SIZE_MASK)
815af8d4 149 && (PTTYPE == 64 || is_pse(vcpu))) {
5fb07ddb 150 walker->gfn = gpte_to_gfn_pde(pte);
815af8d4 151 walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
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152 if (PTTYPE == 32 && is_cpuid_PSE36())
153 walker->gfn += pse36_gfn_delta(pte);
ac79c978 154 break;
815af8d4 155 }
ac79c978 156
42bf3f0a 157 walker->inherited_ar &= pte;
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158 --walker->level;
159 }
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160
161 if (write_fault && !is_dirty_pte(pte)) {
162 mark_page_dirty(vcpu->kvm, table_gfn);
163 pte |= PT_DIRTY_MASK;
ec8d4eae 164 kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
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165 kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
166 }
167
168 walker->pte = pte;
169 pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)pte);
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170 return 1;
171
172not_present:
173 walker->error_code = 0;
174 goto err;
175
176access_error:
177 walker->error_code = PFERR_PRESENT_MASK;
178
179err:
180 if (write_fault)
181 walker->error_code |= PFERR_WRITE_MASK;
182 if (user_fault)
183 walker->error_code |= PFERR_USER_MASK;
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184 if (fetch_fault)
185 walker->error_code |= PFERR_FETCH_MASK;
fe551881 186 return 0;
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187}
188
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189static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
190 u64 *shadow_pte,
fe551881 191 pt_element_t gpte,
e60d75ea 192 u64 access_bits,
97a0a01e 193 int user_fault,
63b1ad24 194 int write_fault,
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195 int *ptwrite,
196 struct guest_walker *walker,
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197 gfn_t gfn)
198{
fe551881 199 int dirty = gpte & PT_DIRTY_MASK;
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200 u64 spte;
201 int was_rmapped = is_rmap_pte(*shadow_pte);
b238f7bc 202 struct page *page;
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203
204 pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
205 " user_fault %d gfn %lx\n",
c7addb90 206 __FUNCTION__, *shadow_pte, (u64)gpte, access_bits,
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207 write_fault, user_fault, gfn);
208
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209 /*
210 * We don't set the accessed bit, since we sometimes want to see
211 * whether the guest actually used the pte (in order to detect
212 * demand paging).
213 */
214 spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
fe551881 215 spte |= gpte & PT64_NX_MASK;
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216 if (!dirty)
217 access_bits &= ~PT_WRITABLE_MASK;
218
4e542370 219 page = gfn_to_page(vcpu->kvm, gfn);
b238f7bc 220
0d551bb6 221 spte |= PT_PRESENT_MASK;
97a0a01e 222 if (access_bits & PT_USER_MASK)
0d551bb6 223 spte |= PT_USER_MASK;
e60d75ea 224
4e542370 225 if (is_error_page(page)) {
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226 set_shadow_pte(shadow_pte,
227 shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK);
b238f7bc 228 kvm_release_page_clean(page);
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229 return;
230 }
231
4e542370 232 spte |= page_to_phys(page);
e60d75ea 233
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234 if ((access_bits & PT_WRITABLE_MASK)
235 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
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236 struct kvm_mmu_page *shadow;
237
0d551bb6 238 spte |= PT_WRITABLE_MASK;
97a0a01e 239 if (user_fault) {
f67a46f4 240 mmu_unshadow(vcpu->kvm, gfn);
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241 goto unshadowed;
242 }
243
f67a46f4 244 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
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245 if (shadow) {
246 pgprintk("%s: found shadow page for %lx, marking ro\n",
247 __FUNCTION__, gfn);
248 access_bits &= ~PT_WRITABLE_MASK;
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249 if (is_writeble_pte(spte)) {
250 spte &= ~PT_WRITABLE_MASK;
cbdd1bea 251 kvm_x86_ops->tlb_flush(vcpu);
e60d75ea 252 }
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253 if (write_fault)
254 *ptwrite = 1;
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255 }
256 }
257
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258unshadowed:
259
e60d75ea 260 if (access_bits & PT_WRITABLE_MASK)
4e542370 261 mark_page_dirty(vcpu->kvm, gfn);
e60d75ea 262
c7addb90 263 pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
e663ee64 264 set_shadow_pte(shadow_pte, spte);
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265 page_header_update_slot(vcpu->kvm, shadow_pte,
266 (gpa_t)gfn << PAGE_SHIFT);
8a7ae055 267 if (!was_rmapped) {
4e542370 268 rmap_add(vcpu, shadow_pte, gfn);
b238f7bc 269 if (!is_rmap_pte(*shadow_pte))
b4231d61 270 kvm_release_page_clean(page);
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271 }
272 else
b238f7bc 273 kvm_release_page_clean(page);
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274 if (!ptwrite || !*ptwrite)
275 vcpu->last_pte_updated = shadow_pte;
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276}
277
fe551881 278static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
63b1ad24 279 u64 *shadow_pte, u64 access_bits,
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280 int user_fault, int write_fault, int *ptwrite,
281 struct guest_walker *walker, gfn_t gfn)
6aa8b732 282{
fe551881 283 access_bits &= gpte;
4e542370 284 FNAME(set_pte_common)(vcpu, shadow_pte,
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285 gpte, access_bits, user_fault, write_fault,
286 ptwrite, walker, gfn);
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287}
288
0028425f 289static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
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290 u64 *spte, const void *pte, int bytes,
291 int offset_in_pte)
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292{
293 pt_element_t gpte;
294
0028425f 295 gpte = *(const pt_element_t *)pte;
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296 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
297 if (!offset_in_pte && !is_present_pte(gpte))
298 set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
299 return;
300 }
301 if (bytes < sizeof(pt_element_t))
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302 return;
303 pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
fe551881 304 FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
5fb07ddb 305 0, NULL, NULL, gpte_to_gfn(gpte));
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306}
307
fe551881 308static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde,
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309 u64 *shadow_pte, u64 access_bits,
310 int user_fault, int write_fault, int *ptwrite,
311 struct guest_walker *walker, gfn_t gfn)
6aa8b732 312{
fe551881 313 access_bits &= gpde;
4e542370 314 FNAME(set_pte_common)(vcpu, shadow_pte,
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315 gpde, access_bits, user_fault, write_fault,
316 ptwrite, walker, gfn);
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317}
318
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319/*
320 * Fetch a shadow pte for a specific level in the paging hierarchy.
321 */
322static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
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323 struct guest_walker *walker,
324 int user_fault, int write_fault, int *ptwrite)
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325{
326 hpa_t shadow_addr;
327 int level;
ef0197e8 328 u64 *shadow_ent;
6aa8b732 329 u64 *prev_shadow_ent = NULL;
ac79c978 330
fe551881 331 if (!is_present_pte(walker->pte))
ac79c978 332 return NULL;
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333
334 shadow_addr = vcpu->mmu.root_hpa;
335 level = vcpu->mmu.shadow_root_level;
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336 if (level == PT32E_ROOT_LEVEL) {
337 shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
338 shadow_addr &= PT64_BASE_ADDR_MASK;
339 --level;
340 }
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341
342 for (; ; level--) {
343 u32 index = SHADOW_PT_INDEX(addr, level);
25c0de2c 344 struct kvm_mmu_page *shadow_page;
8c7bb723 345 u64 shadow_pte;
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346 int metaphysical;
347 gfn_t table_gfn;
d28c6cfb 348 unsigned hugepage_access = 0;
6aa8b732 349
ef0197e8 350 shadow_ent = ((u64 *)__va(shadow_addr)) + index;
c7addb90 351 if (is_shadow_present_pte(*shadow_ent)) {
6aa8b732 352 if (level == PT_PAGE_TABLE_LEVEL)
97a0a01e 353 break;
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354 shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
355 prev_shadow_ent = shadow_ent;
356 continue;
357 }
358
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359 if (level == PT_PAGE_TABLE_LEVEL)
360 break;
6aa8b732 361
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362 if (level - 1 == PT_PAGE_TABLE_LEVEL
363 && walker->level == PT_DIRECTORY_LEVEL) {
364 metaphysical = 1;
fe551881 365 hugepage_access = walker->pte;
d28c6cfb 366 hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
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367 if (!is_dirty_pte(walker->pte))
368 hugepage_access &= ~PT_WRITABLE_MASK;
c22e3514 369 hugepage_access >>= PT_WRITABLE_SHIFT;
fe551881 370 if (walker->pte & PT64_NX_MASK)
d55e2cb2 371 hugepage_access |= (1 << 2);
5fb07ddb 372 table_gfn = gpte_to_gfn(walker->pte);
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373 } else {
374 metaphysical = 0;
375 table_gfn = walker->table_gfn[level - 2];
376 }
377 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
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378 metaphysical, hugepage_access,
379 shadow_ent);
47ad8e68 380 shadow_addr = __pa(shadow_page->spt);
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381 shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
382 | PT_WRITABLE_MASK | PT_USER_MASK;
8c7bb723 383 *shadow_ent = shadow_pte;
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384 prev_shadow_ent = shadow_ent;
385 }
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386
387 if (walker->level == PT_DIRECTORY_LEVEL) {
fe551881 388 FNAME(set_pde)(vcpu, walker->pte, shadow_ent,
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389 walker->inherited_ar, user_fault, write_fault,
390 ptwrite, walker, walker->gfn);
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391 } else {
392 ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
fe551881 393 FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
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394 walker->inherited_ar, user_fault, write_fault,
395 ptwrite, walker, walker->gfn);
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396 }
397 return shadow_ent;
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398}
399
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400/*
401 * Page fault handler. There are several causes for a page fault:
402 * - there is no shadow pte for the guest pte
403 * - write access through a shadow pte marked read only so that we can set
404 * the dirty bit
405 * - write access to a shadow pte marked read only so we can update the page
406 * dirty bitmap, when userspace requests it
407 * - mmio access; in this case we will never install a present shadow pte
408 * - normal guest page fault due to the guest pte marked not present, not
409 * writable, or not executable
410 *
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411 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
412 * a negative value on error.
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413 */
414static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
415 u32 error_code)
416{
417 int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732 418 int user_fault = error_code & PFERR_USER_MASK;
73b1087e 419 int fetch_fault = error_code & PFERR_FETCH_MASK;
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420 struct guest_walker walker;
421 u64 *shadow_pte;
cea0f0e7 422 int write_pt = 0;
e2dec939 423 int r;
6aa8b732 424
cea0f0e7 425 pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
37a7d8b0 426 kvm_mmu_audit(vcpu, "pre page fault");
714b93da 427
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428 r = mmu_topup_memory_caches(vcpu);
429 if (r)
430 return r;
714b93da 431
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432 /*
433 * Look up the shadow pte for the faulting address.
434 */
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435 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
436 fetch_fault);
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437
438 /*
439 * The page is not mapped by the guest. Let the guest handle it.
440 */
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441 if (!r) {
442 pgprintk("%s: guest page fault\n", __FUNCTION__);
443 inject_page_fault(vcpu, addr, walker.error_code);
a25f7e1f 444 vcpu->last_pt_write_count = 0; /* reset fork detector */
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445 return 0;
446 }
447
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448 shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
449 &write_pt);
450 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
451 shadow_pte, *shadow_pte, write_pt);
cea0f0e7 452
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453 if (!write_pt)
454 vcpu->last_pt_write_count = 0; /* reset fork detector */
455
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456 /*
457 * mmio: emulate if accessible, otherwise its a guest fault.
458 */
d27d4aca 459 if (is_io_pte(*shadow_pte))
7993ba43 460 return 1;
6aa8b732 461
1165f5fe 462 ++vcpu->stat.pf_fixed;
37a7d8b0 463 kvm_mmu_audit(vcpu, "post page fault (fixed)");
6aa8b732 464
cea0f0e7 465 return write_pt;
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466}
467
468static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
469{
470 struct guest_walker walker;
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471 gpa_t gpa = UNMAPPED_GVA;
472 int r;
6aa8b732 473
e119d117 474 r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
6aa8b732 475
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476 if (r) {
477 gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
478 gpa |= vaddr & ~PAGE_MASK;
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479 }
480
481 return gpa;
482}
483
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484static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
485 struct kvm_mmu_page *sp)
486{
e5a4c8ca 487 int i, offset = 0;
c7addb90 488 pt_element_t *gpt;
8a7ae055 489 struct page *page;
c7addb90 490
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491 if (sp->role.metaphysical
492 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
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493 nonpaging_prefetch_page(vcpu, sp);
494 return;
495 }
496
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497 if (PTTYPE == 32)
498 offset = sp->role.quadrant << PT64_LEVEL_BITS;
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499 page = gfn_to_page(vcpu->kvm, sp->gfn);
500 gpt = kmap_atomic(page, KM_USER0);
c7addb90 501 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
e5a4c8ca 502 if (is_present_pte(gpt[offset + i]))
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503 sp->spt[i] = shadow_trap_nonpresent_pte;
504 else
505 sp->spt[i] = shadow_notrap_nonpresent_pte;
506 kunmap_atomic(gpt, KM_USER0);
b4231d61 507 kvm_release_page_clean(page);
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508}
509
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510#undef pt_element_t
511#undef guest_walker
512#undef FNAME
513#undef PT_BASE_ADDR_MASK
514#undef PT_INDEX
515#undef SHADOW_PT_INDEX
516#undef PT_LEVEL_MASK
6aa8b732 517#undef PT_DIR_BASE_ADDR_MASK
c7addb90 518#undef PT_LEVEL_BITS
cea0f0e7 519#undef PT_MAX_FULL_LEVELS
5fb07ddb
AK
520#undef gpte_to_gfn
521#undef gpte_to_gfn_pde
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