[deliverable/linux.git] / drivers / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#else
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_MAX_FULL_LEVELS 2
#else
	#error Invalid PTTYPE value
#endif

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t *table;
	pt_element_t pte;
	pt_element_t *ptep;
	struct page *page;
	int index;
	pt_element_t inherited_ar;
	gfn_t gfn;
	u32 error_code;
};

/*
 * Fetch a guest pte for a guest virtual address
 */
static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
			    int write_fault, int user_fault, int fetch_fault)
{
	hpa_t hpa;
	struct kvm_memory_slot *slot;
	pt_element_t *ptep;
	pt_element_t root;
	gfn_t table_gfn;

	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
	walker->level = vcpu->mmu.root_level;
	walker->table = NULL;
	walker->page = NULL;
	walker->ptep = NULL;
	root = vcpu->cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
		root = *walker->ptep;
		walker->pte = root;
		if (!(root & PT_PRESENT_MASK))
			goto not_present;
		--walker->level;
	}
#endif
	table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	walker->table_gfn[walker->level - 1] = table_gfn;
	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
		 walker->level - 1, table_gfn);
	slot = gfn_to_memslot(vcpu->kvm, table_gfn);
	hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
	walker->page = pfn_to_page(hpa >> PAGE_SHIFT);
	walker->table = kmap_atomic(walker->page, KM_USER0);

	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);

	walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;

	for (;;) {
		int index = PT_INDEX(addr, walker->level);
		hpa_t paddr;

		ptep = &walker->table[index];
		walker->index = index;
		ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
		       ((unsigned long)ptep & PAGE_MASK));

		if (!is_present_pte(*ptep))
			goto not_present;

		if (write_fault && !is_writeble_pte(*ptep))
			if (user_fault || is_write_protection(vcpu))
				goto access_error;

		if (user_fault && !(*ptep & PT_USER_MASK))
			goto access_error;

#if PTTYPE == 64
		if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK))
			goto access_error;
#endif

		if (!(*ptep & PT_ACCESSED_MASK)) {
			mark_page_dirty(vcpu->kvm, table_gfn);
			*ptep |= PT_ACCESSED_MASK;
		}

		if (walker->level == PT_PAGE_TABLE_LEVEL) {
			walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
		    && (*ptep & PT_PAGE_SIZE_MASK)
		    && (PTTYPE == 64 || is_pse(vcpu))) {
			walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
			break;
		}

		walker->inherited_ar &= walker->table[index];
		table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
		kunmap_atomic(walker->table, KM_USER0);
		paddr = safe_gpa_to_hpa(vcpu, table_gfn << PAGE_SHIFT);
		walker->page = pfn_to_page(paddr >> PAGE_SHIFT);
		walker->table = kmap_atomic(walker->page, KM_USER0);
		--walker->level;
		walker->table_gfn[walker->level - 1 ] = table_gfn;
		pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
			 walker->level - 1, table_gfn);
	}
	walker->pte = *ptep;
	if (walker->page)
		walker->ptep = NULL;
	if (walker->table)
		kunmap_atomic(walker->table, KM_USER0);
	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
	if (walker->table)
		kunmap_atomic(walker->table, KM_USER0);
	return 0;
}

static void FNAME(mark_pagetable_dirty)(struct kvm *kvm,
					struct guest_walker *walker)
{
	mark_page_dirty(kvm, walker->table_gfn[walker->level - 1]);
}

static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
				  u64 *shadow_pte,
				  gpa_t gaddr,
				  pt_element_t gpte,
				  u64 access_bits,
				  int user_fault,
				  int write_fault,
				  int *ptwrite,
				  struct guest_walker *walker,
				  gfn_t gfn)
{
	hpa_t paddr;
	int dirty = gpte & PT_DIRTY_MASK;
	u64 spte = *shadow_pte;
	int was_rmapped = is_rmap_pte(spte);

	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
		 " user_fault %d gfn %lx\n",
		 __FUNCTION__, spte, (u64)gpte, access_bits,
		 write_fault, user_fault, gfn);

	if (write_fault && !dirty) {
		pt_element_t *guest_ent, *tmp = NULL;

		if (walker->ptep)
			guest_ent = walker->ptep;
		else {
			tmp = kmap_atomic(walker->page, KM_USER0);
			guest_ent = &tmp[walker->index];
		}

		*guest_ent |= PT_DIRTY_MASK;
		if (!walker->ptep)
			kunmap_atomic(tmp, KM_USER0);
		dirty = 1;
		FNAME(mark_pagetable_dirty)(vcpu->kvm, walker);
	}

	spte |= PT_PRESENT_MASK | PT_ACCESSED_MASK | PT_DIRTY_MASK;
	spte |= gpte & PT64_NX_MASK;
	if (!dirty)
		access_bits &= ~PT_WRITABLE_MASK;

	paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);

	spte |= PT_PRESENT_MASK;
	if (access_bits & PT_USER_MASK)
		spte |= PT_USER_MASK;

	if (is_error_hpa(paddr)) {
		spte |= gaddr;
		spte |= PT_SHADOW_IO_MARK;
		spte &= ~PT_PRESENT_MASK;
		set_shadow_pte(shadow_pte, spte);
		return;
	}

	spte |= paddr;

	if ((access_bits & PT_WRITABLE_MASK)
	    || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
		struct kvm_mmu_page *shadow;

		spte |= PT_WRITABLE_MASK;
		if (user_fault) {
			mmu_unshadow(vcpu, gfn);
			goto unshadowed;
		}

		shadow = kvm_mmu_lookup_page(vcpu, gfn);
		if (shadow) {
			pgprintk("%s: found shadow page for %lx, marking ro\n",
				 __FUNCTION__, gfn);
			access_bits &= ~PT_WRITABLE_MASK;
			if (is_writeble_pte(spte)) {
				spte &= ~PT_WRITABLE_MASK;
				kvm_x86_ops->tlb_flush(vcpu);
			}
			if (write_fault)
				*ptwrite = 1;
		}
	}

unshadowed:

	if (access_bits & PT_WRITABLE_MASK)
		mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);

	set_shadow_pte(shadow_pte, spte);
	page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
	if (!was_rmapped)
		rmap_add(vcpu, shadow_pte);
}

static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
			   u64 *shadow_pte, u64 access_bits,
			   int user_fault, int write_fault, int *ptwrite,
			   struct guest_walker *walker, gfn_t gfn)
{
	access_bits &= gpte;
	FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK,
			      gpte, access_bits, user_fault, write_fault,
			      ptwrite, walker, gfn);
}

static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
			      u64 *spte, const void *pte, int bytes)
{
	pt_element_t gpte;

	if (bytes < sizeof(pt_element_t))
		return;
	gpte = *(const pt_element_t *)pte;
	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK))
		return;
	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
	FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
		       0, NULL, NULL,
		       (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
}

static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde,
			   u64 *shadow_pte, u64 access_bits,
			   int user_fault, int write_fault, int *ptwrite,
			   struct guest_walker *walker, gfn_t gfn)
{
	gpa_t gaddr;

	access_bits &= gpde;
	gaddr = (gpa_t)gfn << PAGE_SHIFT;
	if (PTTYPE == 32 && is_cpuid_PSE36())
		gaddr |= (gpde & PT32_DIR_PSE36_MASK) <<
			(32 - PT32_DIR_PSE36_SHIFT);
	FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
			      gpde, access_bits, user_fault, write_fault,
			      ptwrite, walker, gfn);
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			 struct guest_walker *walker,
			 int user_fault, int write_fault, int *ptwrite)
{
	hpa_t shadow_addr;
	int level;
	u64 *shadow_ent;
	u64 *prev_shadow_ent = NULL;

	if (!is_present_pte(walker->pte))
		return NULL;

	shadow_addr = vcpu->mmu.root_hpa;
	level = vcpu->mmu.shadow_root_level;
	if (level == PT32E_ROOT_LEVEL) {
		shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
		shadow_addr &= PT64_BASE_ADDR_MASK;
		--level;
	}

	for (; ; level--) {
		u32 index = SHADOW_PT_INDEX(addr, level);
		struct kvm_mmu_page *shadow_page;
		u64 shadow_pte;
		int metaphysical;
		gfn_t table_gfn;
		unsigned hugepage_access = 0;

		shadow_ent = ((u64 *)__va(shadow_addr)) + index;
		if (is_present_pte(*shadow_ent) || is_io_pte(*shadow_ent)) {
			if (level == PT_PAGE_TABLE_LEVEL)
				break;
			shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
			prev_shadow_ent = shadow_ent;
			continue;
		}

		if (level == PT_PAGE_TABLE_LEVEL)
			break;

		if (level - 1 == PT_PAGE_TABLE_LEVEL
		    && walker->level == PT_DIRECTORY_LEVEL) {
			metaphysical = 1;
			hugepage_access = walker->pte;
			hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
			if (walker->pte & PT64_NX_MASK)
				hugepage_access |= (1 << 2);
			hugepage_access >>= PT_WRITABLE_SHIFT;
			table_gfn = (walker->pte & PT_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
		} else {
			metaphysical = 0;
			table_gfn = walker->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
					       metaphysical, hugepage_access,
					       shadow_ent);
		shadow_addr = __pa(shadow_page->spt);
		shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
		*shadow_ent = shadow_pte;
		prev_shadow_ent = shadow_ent;
	}

	if (walker->level == PT_DIRECTORY_LEVEL) {
		FNAME(set_pde)(vcpu, walker->pte, shadow_ent,
			       walker->inherited_ar, user_fault, write_fault,
			       ptwrite, walker, walker->gfn);
	} else {
		ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
		FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
			       walker->inherited_ar, user_fault, write_fault,
			       ptwrite, walker, walker->gfn);
	}
	return shadow_ent;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	int fetch_fault = error_code & PFERR_FETCH_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int write_pt = 0;
	int r;

	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	/*
	 * Look up the shadow pte for the faulting address.
	 */
	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!r) {
		pgprintk("%s: guest page fault\n", __FUNCTION__);
		inject_page_fault(vcpu, addr, walker.error_code);
		vcpu->last_pt_write_count = 0; /* reset fork detector */
		return 0;
	}

	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
				  &write_pt);
	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
		 shadow_pte, *shadow_pte, write_pt);

	if (!write_pt)
		vcpu->last_pt_write_count = 0; /* reset fork detector */

	/*
	 * mmio: emulate if accessible, otherwise its a guest fault.
	 */
	if (is_io_pte(*shadow_pte))
		return 1;

	++vcpu->stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");

	return write_pt;
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	gpa_t gpa = UNMAPPED_GVA;
	int r;

	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);

	if (r) {
		gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
		gpa |= vaddr & ~PAGE_MASK;
	}

	return gpa;
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef SHADOW_PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_DIR_BASE_ADDR_MASK
#undef PT_MAX_FULL_LEVELS
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
	28	#define FNAME(name) paging##64_##name
	29	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	30	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	31	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	32	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	33	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
cea0f0e7 AK	34	#ifdef CONFIG_X86_64
	35	#define PT_MAX_FULL_LEVELS 4
	36	#else
	37	#define PT_MAX_FULL_LEVELS 2
	38	#endif
6aa8b732 AK	39	#elif PTTYPE == 32
	40	#define pt_element_t u32
	41	#define guest_walker guest_walker32
	42	#define FNAME(name) paging##32_##name
	43	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	44	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	45	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	46	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	47	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
cea0f0e7	48	#define PT_MAX_FULL_LEVELS 2
6aa8b732 AK	49	#else
	50	#error Invalid PTTYPE value
	51	#endif
	52
	53	/*
	54	* The guest_walker structure emulates the behavior of the hardware page
	55	* table walker.
	56	*/
	57	struct guest_walker {
	58	int level;
cea0f0e7	59	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
6aa8b732	60	pt_element_t *table;
fe551881	61	pt_element_t pte;
ac79c978	62	pt_element_t *ptep;
fe551881 SL	63	struct page *page;
fe551881 SL	64	int index;
6aa8b732	65	pt_element_t inherited_ar;
815af8d4	66	gfn_t gfn;
7993ba43	67	u32 error_code;
6aa8b732 AK	68	};
6aa8b732 AK	69
ac79c978 AK	70	/*
	71	* Fetch a guest pte for a guest virtual address
	72	*/
7993ba43 AK	73	static int FNAME(walk_addr)(struct guest_walker *walker,
7993ba43 AK	74	struct kvm_vcpu *vcpu, gva_t addr,
73b1087e	75	int write_fault, int user_fault, int fetch_fault)
6aa8b732 AK	76	{
	77	hpa_t hpa;
	78	struct kvm_memory_slot *slot;
ac79c978	79	pt_element_t *ptep;
1b0973bd	80	pt_element_t root;
cea0f0e7	81	gfn_t table_gfn;
6aa8b732	82
cea0f0e7	83	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
6aa8b732	84	walker->level = vcpu->mmu.root_level;
1b0973bd	85	walker->table = NULL;
fe551881 SL	86	walker->page = NULL;
fe551881 SL	87	walker->ptep = NULL;
1b0973bd AK	88	root = vcpu->cr3;
	89	#if PTTYPE == 64
	90	if (!is_long_mode(vcpu)) {
	91	walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
	92	root = *walker->ptep;
fe551881	93	walker->pte = root;
1b0973bd	94	if (!(root & PT_PRESENT_MASK))
7993ba43	95	goto not_present;
1b0973bd AK	96	--walker->level;
	97	}
	98	#endif
cea0f0e7 AK	99	table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	100	walker->table_gfn[walker->level - 1] = table_gfn;
	101	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	102	walker->level - 1, table_gfn);
	103	slot = gfn_to_memslot(vcpu->kvm, table_gfn);
1b0973bd	104	hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
fe551881 SL	105	walker->page = pfn_to_page(hpa >> PAGE_SHIFT);
fe551881 SL	106	walker->table = kmap_atomic(walker->page, KM_USER0);
6aa8b732	107
a9058ecd	108	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
f802a307	109	(vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732	110
6aa8b732	111	walker->inherited_ar = PT_USER_MASK \| PT_WRITABLE_MASK;
ac79c978 AK	112
	113	for (;;) {
	114	int index = PT_INDEX(addr, walker->level);
	115	hpa_t paddr;
	116
	117	ptep = &walker->table[index];
fe551881	118	walker->index = index;
ac79c978 AK	119	ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
	120	((unsigned long)ptep & PAGE_MASK));
	121
815af8d4	122	if (!is_present_pte(*ptep))
7993ba43 AK	123	goto not_present;
	124
	125	if (write_fault && !is_writeble_pte(*ptep))
	126	if (user_fault \|\| is_write_protection(vcpu))
	127	goto access_error;
	128
	129	if (user_fault && !(*ptep & PT_USER_MASK))
	130	goto access_error;
	131
73b1087e AK	132	#if PTTYPE == 64
	133	if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK))
	134	goto access_error;
	135	#endif
	136
bf3f8e86 AK	137	if (!(*ptep & PT_ACCESSED_MASK)) {
	138	mark_page_dirty(vcpu->kvm, table_gfn);
	139	*ptep \|= PT_ACCESSED_MASK;
	140	}
815af8d4 AK	141
	142	if (walker->level == PT_PAGE_TABLE_LEVEL) {
	143	walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
	144	>> PAGE_SHIFT;
	145	break;
	146	}
	147
	148	if (walker->level == PT_DIRECTORY_LEVEL
	149	&& (*ptep & PT_PAGE_SIZE_MASK)
	150	&& (PTTYPE == 64 \|\| is_pse(vcpu))) {
	151	walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
	152	>> PAGE_SHIFT;
	153	walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
ac79c978	154	break;
815af8d4	155	}
ac79c978	156
ca5aac1f	157	walker->inherited_ar &= walker->table[index];
cea0f0e7	158	table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
ac79c978	159	kunmap_atomic(walker->table, KM_USER0);
fe551881 SL	160	paddr = safe_gpa_to_hpa(vcpu, table_gfn << PAGE_SHIFT);
	161	walker->page = pfn_to_page(paddr >> PAGE_SHIFT);
	162	walker->table = kmap_atomic(walker->page, KM_USER0);
ac79c978	163	--walker->level;
cea0f0e7 AK	164	walker->table_gfn[walker->level - 1 ] = table_gfn;
	165	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	166	walker->level - 1, table_gfn);
ac79c978	167	}
fe551881 SL	168	walker->pte = *ptep;
	169	if (walker->page)
	170	walker->ptep = NULL;
	171	if (walker->table)
	172	kunmap_atomic(walker->table, KM_USER0);
374cbac0	173	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
7993ba43 AK	174	return 1;
	175
	176	not_present:
	177	walker->error_code = 0;
	178	goto err;
	179
	180	access_error:
	181	walker->error_code = PFERR_PRESENT_MASK;
	182
	183	err:
	184	if (write_fault)
	185	walker->error_code \|= PFERR_WRITE_MASK;
	186	if (user_fault)
	187	walker->error_code \|= PFERR_USER_MASK;
73b1087e AK	188	if (fetch_fault)
73b1087e AK	189	walker->error_code \|= PFERR_FETCH_MASK;
1b0973bd AK	190	if (walker->table)
1b0973bd AK	191	kunmap_atomic(walker->table, KM_USER0);
fe551881	192	return 0;
6aa8b732 AK	193	}
6aa8b732 AK	194
bf3f8e86 AK	195	static void FNAME(mark_pagetable_dirty)(struct kvm *kvm,
	196	struct guest_walker *walker)
	197	{
	198	mark_page_dirty(kvm, walker->table_gfn[walker->level - 1]);
	199	}
	200
e60d75ea AK	201	static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
	202	u64 *shadow_pte,
	203	gpa_t gaddr,
fe551881	204	pt_element_t gpte,
e60d75ea	205	u64 access_bits,
97a0a01e	206	int user_fault,
63b1ad24	207	int write_fault,
97a0a01e AK	208	int *ptwrite,
97a0a01e AK	209	struct guest_walker *walker,
e60d75ea AK	210	gfn_t gfn)
	211	{
	212	hpa_t paddr;
fe551881	213	int dirty = gpte & PT_DIRTY_MASK;
0d551bb6 AK	214	u64 spte = *shadow_pte;
0d551bb6 AK	215	int was_rmapped = is_rmap_pte(spte);
97a0a01e AK	216
	217	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
	218	" user_fault %d gfn %lx\n",
fe551881	219	__FUNCTION__, spte, (u64)gpte, access_bits,
97a0a01e AK	220	write_fault, user_fault, gfn);
	221
	222	if (write_fault && !dirty) {
fe551881 SL	223	pt_element_t guest_ent, tmp = NULL;
	224
	225	if (walker->ptep)
	226	guest_ent = walker->ptep;
	227	else {
	228	tmp = kmap_atomic(walker->page, KM_USER0);
	229	guest_ent = &tmp[walker->index];
	230	}
	231
	232	*guest_ent \|= PT_DIRTY_MASK;
	233	if (!walker->ptep)
	234	kunmap_atomic(tmp, KM_USER0);
97a0a01e AK	235	dirty = 1;
	236	FNAME(mark_pagetable_dirty)(vcpu->kvm, walker);
	237	}
e60d75ea	238
fd97dc51	239	spte \|= PT_PRESENT_MASK \| PT_ACCESSED_MASK \| PT_DIRTY_MASK;
fe551881	240	spte \|= gpte & PT64_NX_MASK;
e60d75ea AK	241	if (!dirty)
	242	access_bits &= ~PT_WRITABLE_MASK;
	243
	244	paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);
	245
0d551bb6	246	spte \|= PT_PRESENT_MASK;
97a0a01e	247	if (access_bits & PT_USER_MASK)
0d551bb6	248	spte \|= PT_USER_MASK;
e60d75ea AK	249
e60d75ea AK	250	if (is_error_hpa(paddr)) {
0d551bb6 AK	251	spte \|= gaddr;
	252	spte \|= PT_SHADOW_IO_MARK;
	253	spte &= ~PT_PRESENT_MASK;
e663ee64	254	set_shadow_pte(shadow_pte, spte);
e60d75ea AK	255	return;
	256	}
	257
0d551bb6	258	spte \|= paddr;
e60d75ea	259
97a0a01e AK	260	if ((access_bits & PT_WRITABLE_MASK)
97a0a01e AK	261	\|\| (write_fault && !is_write_protection(vcpu) && !user_fault)) {
e60d75ea AK	262	struct kvm_mmu_page *shadow;
e60d75ea AK	263
0d551bb6	264	spte \|= PT_WRITABLE_MASK;
97a0a01e AK	265	if (user_fault) {
	266	mmu_unshadow(vcpu, gfn);
	267	goto unshadowed;
	268	}
	269
e60d75ea AK	270	shadow = kvm_mmu_lookup_page(vcpu, gfn);
	271	if (shadow) {
	272	pgprintk("%s: found shadow page for %lx, marking ro\n",
	273	__FUNCTION__, gfn);
	274	access_bits &= ~PT_WRITABLE_MASK;
0d551bb6 AK	275	if (is_writeble_pte(spte)) {
0d551bb6 AK	276	spte &= ~PT_WRITABLE_MASK;
cbdd1bea	277	kvm_x86_ops->tlb_flush(vcpu);
e60d75ea	278	}
97a0a01e AK	279	if (write_fault)
97a0a01e AK	280	*ptwrite = 1;
e60d75ea AK	281	}
	282	}
	283
97a0a01e AK	284	unshadowed:
97a0a01e AK	285
e60d75ea AK	286	if (access_bits & PT_WRITABLE_MASK)
	287	mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);
	288
e663ee64	289	set_shadow_pte(shadow_pte, spte);
e60d75ea	290	page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
97a0a01e AK	291	if (!was_rmapped)
97a0a01e AK	292	rmap_add(vcpu, shadow_pte);
e60d75ea AK	293	}
e60d75ea AK	294
fe551881	295	static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
63b1ad24	296	u64 *shadow_pte, u64 access_bits,
97a0a01e AK	297	int user_fault, int write_fault, int *ptwrite,
97a0a01e AK	298	struct guest_walker *walker, gfn_t gfn)
6aa8b732	299	{
fe551881 SL	300	access_bits &= gpte;
fe551881 SL	301	FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK,
97a0a01e AK	302	gpte, access_bits, user_fault, write_fault,
97a0a01e AK	303	ptwrite, walker, gfn);
6aa8b732 AK	304	}
6aa8b732 AK	305
0028425f AK	306	static void FNAME(update_pte)(struct kvm_vcpu vcpu, struct kvm_mmu_page page,
	307	u64 spte, const void pte, int bytes)
	308	{
	309	pt_element_t gpte;
	310
	311	if (bytes < sizeof(pt_element_t))
	312	return;
	313	gpte = (const pt_element_t )pte;
	314	if (~gpte & (PT_PRESENT_MASK \| PT_ACCESSED_MASK))
	315	return;
	316	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
fe551881	317	FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK \| PT_WRITABLE_MASK, 0,
97a0a01e	318	0, NULL, NULL,
0028425f AK	319	(gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
	320	}
	321
fe551881	322	static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde,
97a0a01e AK	323	u64 *shadow_pte, u64 access_bits,
	324	int user_fault, int write_fault, int *ptwrite,
	325	struct guest_walker *walker, gfn_t gfn)
6aa8b732 AK	326	{
	327	gpa_t gaddr;
	328
fe551881	329	access_bits &= gpde;
815af8d4	330	gaddr = (gpa_t)gfn << PAGE_SHIFT;
6aa8b732	331	if (PTTYPE == 32 && is_cpuid_PSE36())
fe551881	332	gaddr \|= (gpde & PT32_DIR_PSE36_MASK) <<
6aa8b732	333	(32 - PT32_DIR_PSE36_SHIFT);
e60d75ea	334	FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
97a0a01e AK	335	gpde, access_bits, user_fault, write_fault,
97a0a01e AK	336	ptwrite, walker, gfn);
6aa8b732 AK	337	}
6aa8b732 AK	338
6aa8b732 AK	339	/*
	340	* Fetch a shadow pte for a specific level in the paging hierarchy.
	341	*/
	342	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
97a0a01e AK	343	struct guest_walker *walker,
97a0a01e AK	344	int user_fault, int write_fault, int *ptwrite)
6aa8b732 AK	345	{
	346	hpa_t shadow_addr;
	347	int level;
ef0197e8	348	u64 *shadow_ent;
6aa8b732	349	u64 *prev_shadow_ent = NULL;
ac79c978	350
fe551881	351	if (!is_present_pte(walker->pte))
ac79c978	352	return NULL;
6aa8b732 AK	353
	354	shadow_addr = vcpu->mmu.root_hpa;
	355	level = vcpu->mmu.shadow_root_level;
aef3d3fe AK	356	if (level == PT32E_ROOT_LEVEL) {
	357	shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
	358	shadow_addr &= PT64_BASE_ADDR_MASK;
	359	--level;
	360	}
6aa8b732 AK	361
	362	for (; ; level--) {
	363	u32 index = SHADOW_PT_INDEX(addr, level);
25c0de2c	364	struct kvm_mmu_page *shadow_page;
8c7bb723	365	u64 shadow_pte;
cea0f0e7 AK	366	int metaphysical;
cea0f0e7 AK	367	gfn_t table_gfn;
d28c6cfb	368	unsigned hugepage_access = 0;
6aa8b732	369
ef0197e8	370	shadow_ent = ((u64 *)__va(shadow_addr)) + index;
6aa8b732 AK	371	if (is_present_pte(shadow_ent) \|\| is_io_pte(shadow_ent)) {
6aa8b732 AK	372	if (level == PT_PAGE_TABLE_LEVEL)
97a0a01e	373	break;
6aa8b732 AK	374	shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
	375	prev_shadow_ent = shadow_ent;
	376	continue;
	377	}
	378
ef0197e8 AK	379	if (level == PT_PAGE_TABLE_LEVEL)
ef0197e8 AK	380	break;
6aa8b732	381
cea0f0e7 AK	382	if (level - 1 == PT_PAGE_TABLE_LEVEL
	383	&& walker->level == PT_DIRECTORY_LEVEL) {
	384	metaphysical = 1;
fe551881	385	hugepage_access = walker->pte;
d28c6cfb	386	hugepage_access &= PT_USER_MASK \| PT_WRITABLE_MASK;
fe551881	387	if (walker->pte & PT64_NX_MASK)
d55e2cb2	388	hugepage_access \|= (1 << 2);
d28c6cfb	389	hugepage_access >>= PT_WRITABLE_SHIFT;
fe551881	390	table_gfn = (walker->pte & PT_BASE_ADDR_MASK)
cea0f0e7 AK	391	>> PAGE_SHIFT;
	392	} else {
	393	metaphysical = 0;
	394	table_gfn = walker->table_gfn[level - 2];
	395	}
	396	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
d28c6cfb AK	397	metaphysical, hugepage_access,
d28c6cfb AK	398	shadow_ent);
47ad8e68	399	shadow_addr = __pa(shadow_page->spt);
aef3d3fe AK	400	shadow_pte = shadow_addr \| PT_PRESENT_MASK \| PT_ACCESSED_MASK
aef3d3fe AK	401	\| PT_WRITABLE_MASK \| PT_USER_MASK;
8c7bb723	402	*shadow_ent = shadow_pte;
6aa8b732 AK	403	prev_shadow_ent = shadow_ent;
6aa8b732 AK	404	}
ef0197e8 AK	405
ef0197e8 AK	406	if (walker->level == PT_DIRECTORY_LEVEL) {
fe551881	407	FNAME(set_pde)(vcpu, walker->pte, shadow_ent,
97a0a01e AK	408	walker->inherited_ar, user_fault, write_fault,
97a0a01e AK	409	ptwrite, walker, walker->gfn);
ef0197e8 AK	410	} else {
ef0197e8 AK	411	ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
fe551881	412	FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
97a0a01e AK	413	walker->inherited_ar, user_fault, write_fault,
97a0a01e AK	414	ptwrite, walker, walker->gfn);
ef0197e8 AK	415	}
ef0197e8 AK	416	return shadow_ent;
6aa8b732 AK	417	}
6aa8b732 AK	418
6aa8b732 AK	419	/*
	420	* Page fault handler. There are several causes for a page fault:
	421	* - there is no shadow pte for the guest pte
	422	* - write access through a shadow pte marked read only so that we can set
	423	* the dirty bit
	424	* - write access to a shadow pte marked read only so we can update the page
	425	* dirty bitmap, when userspace requests it
	426	* - mmio access; in this case we will never install a present shadow pte
	427	* - normal guest page fault due to the guest pte marked not present, not
	428	* writable, or not executable
	429	*
e2dec939 AK	430	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
e2dec939 AK	431	* a negative value on error.
6aa8b732 AK	432	*/
	433	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	434	u32 error_code)
	435	{
	436	int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732	437	int user_fault = error_code & PFERR_USER_MASK;
73b1087e	438	int fetch_fault = error_code & PFERR_FETCH_MASK;
6aa8b732 AK	439	struct guest_walker walker;
6aa8b732 AK	440	u64 *shadow_pte;
cea0f0e7	441	int write_pt = 0;
e2dec939	442	int r;
6aa8b732	443
cea0f0e7	444	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
37a7d8b0	445	kvm_mmu_audit(vcpu, "pre page fault");
714b93da	446
e2dec939 AK	447	r = mmu_topup_memory_caches(vcpu);
	448	if (r)
	449	return r;
714b93da	450
6aa8b732 AK	451	/*
	452	* Look up the shadow pte for the faulting address.
	453	*/
73b1087e AK	454	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
73b1087e AK	455	fetch_fault);
6aa8b732 AK	456
	457	/*
	458	* The page is not mapped by the guest. Let the guest handle it.
	459	*/
7993ba43 AK	460	if (!r) {
	461	pgprintk("%s: guest page fault\n", __FUNCTION__);
	462	inject_page_fault(vcpu, addr, walker.error_code);
a25f7e1f	463	vcpu->last_pt_write_count = 0; /* reset fork detector */
6aa8b732 AK	464	return 0;
	465	}
	466
97a0a01e AK	467	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
	468	&write_pt);
	469	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
	470	shadow_pte, *shadow_pte, write_pt);
cea0f0e7	471
a25f7e1f AK	472	if (!write_pt)
	473	vcpu->last_pt_write_count = 0; /* reset fork detector */
	474
6aa8b732 AK	475	/*
	476	* mmio: emulate if accessible, otherwise its a guest fault.
	477	*/
d27d4aca	478	if (is_io_pte(*shadow_pte))
7993ba43	479	return 1;
6aa8b732	480
1165f5fe	481	++vcpu->stat.pf_fixed;
37a7d8b0	482	kvm_mmu_audit(vcpu, "post page fault (fixed)");
6aa8b732	483
cea0f0e7	484	return write_pt;
6aa8b732 AK	485	}
	486
	487	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
	488	{
	489	struct guest_walker walker;
e119d117 AK	490	gpa_t gpa = UNMAPPED_GVA;
e119d117 AK	491	int r;
6aa8b732	492
e119d117	493	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
6aa8b732	494
e119d117 AK	495	if (r) {
	496	gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
	497	gpa \|= vaddr & ~PAGE_MASK;
6aa8b732 AK	498	}
	499
	500	return gpa;
	501	}
	502
	503	#undef pt_element_t
	504	#undef guest_walker
	505	#undef FNAME
	506	#undef PT_BASE_ADDR_MASK
	507	#undef PT_INDEX
	508	#undef SHADOW_PT_INDEX
	509	#undef PT_LEVEL_MASK
6aa8b732	510	#undef PT_DIR_BASE_ADDR_MASK
cea0f0e7	511	#undef PT_MAX_FULL_LEVELS