[deliverable/linux.git] / drivers / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#else
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK
	#define PT_MAX_FULL_LEVELS 2
#else
	#error Invalid PTTYPE value
#endif

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t *table;
	pt_element_t *ptep;
	pt_element_t inherited_ar;
	gfn_t gfn;
};

/*
 * Fetch a guest pte for a guest virtual address
 */
static void FNAME(walk_addr)(struct guest_walker *walker,
			     struct kvm_vcpu *vcpu, gva_t addr)
{
	hpa_t hpa;
	struct kvm_memory_slot *slot;
	pt_element_t *ptep;
	pt_element_t root;
	gfn_t table_gfn;

	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
	walker->level = vcpu->mmu.root_level;
	walker->table = NULL;
	root = vcpu->cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
		root = *walker->ptep;
		if (!(root & PT_PRESENT_MASK))
			return;
		--walker->level;
	}
#endif
	table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	walker->table_gfn[walker->level - 1] = table_gfn;
	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
		 walker->level - 1, table_gfn);
	slot = gfn_to_memslot(vcpu->kvm, table_gfn);
	hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
	walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0);

	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->cr3 & ~(PAGE_MASK | CR3_FLAGS_MASK)) == 0);

	walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;

	for (;;) {
		int index = PT_INDEX(addr, walker->level);
		hpa_t paddr;

		ptep = &walker->table[index];
		ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
		       ((unsigned long)ptep & PAGE_MASK));

		if (is_present_pte(*ptep) && !(*ptep &  PT_ACCESSED_MASK))
			*ptep |= PT_ACCESSED_MASK;

		if (!is_present_pte(*ptep))
			break;

		if (walker->level == PT_PAGE_TABLE_LEVEL) {
			walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
		    && (*ptep & PT_PAGE_SIZE_MASK)
		    && (PTTYPE == 64 || is_pse(vcpu))) {
			walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
			break;
		}

		if (walker->level != 3 || is_long_mode(vcpu))
			walker->inherited_ar &= walker->table[index];
		table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
		paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK);
		kunmap_atomic(walker->table, KM_USER0);
		walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT),
					    KM_USER0);
		--walker->level;
		walker->table_gfn[walker->level - 1 ] = table_gfn;
		pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
			 walker->level - 1, table_gfn);
	}
	walker->ptep = ptep;
	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
}

static void FNAME(release_walker)(struct guest_walker *walker)
{
	if (walker->table)
		kunmap_atomic(walker->table, KM_USER0);
}

static void FNAME(set_pte)(struct kvm_vcpu *vcpu, u64 guest_pte,
			   u64 *shadow_pte, u64 access_bits, gfn_t gfn)
{
	ASSERT(*shadow_pte == 0);
	access_bits &= guest_pte;
	*shadow_pte = (guest_pte & PT_PTE_COPY_MASK);
	set_pte_common(vcpu, shadow_pte, guest_pte & PT_BASE_ADDR_MASK,
		       guest_pte & PT_DIRTY_MASK, access_bits, gfn);
}

static void FNAME(set_pde)(struct kvm_vcpu *vcpu, u64 guest_pde,
			   u64 *shadow_pte, u64 access_bits, gfn_t gfn)
{
	gpa_t gaddr;

	ASSERT(*shadow_pte == 0);
	access_bits &= guest_pde;
	gaddr = (gpa_t)gfn << PAGE_SHIFT;
	if (PTTYPE == 32 && is_cpuid_PSE36())
		gaddr |= (guest_pde & PT32_DIR_PSE36_MASK) <<
			(32 - PT32_DIR_PSE36_SHIFT);
	*shadow_pte = guest_pde & PT_PTE_COPY_MASK;
	set_pte_common(vcpu, shadow_pte, gaddr,
		       guest_pde & PT_DIRTY_MASK, access_bits, gfn);
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			      struct guest_walker *walker)
{
	hpa_t shadow_addr;
	int level;
	u64 *prev_shadow_ent = NULL;
	pt_element_t *guest_ent = walker->ptep;

	if (!is_present_pte(*guest_ent))
		return NULL;

	shadow_addr = vcpu->mmu.root_hpa;
	level = vcpu->mmu.shadow_root_level;
	if (level == PT32E_ROOT_LEVEL) {
		shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
		shadow_addr &= PT64_BASE_ADDR_MASK;
		--level;
	}

	for (; ; level--) {
		u32 index = SHADOW_PT_INDEX(addr, level);
		u64 *shadow_ent = ((u64 *)__va(shadow_addr)) + index;
		struct kvm_mmu_page *shadow_page;
		u64 shadow_pte;
		int metaphysical;
		gfn_t table_gfn;

		if (is_present_pte(*shadow_ent) || is_io_pte(*shadow_ent)) {
			if (level == PT_PAGE_TABLE_LEVEL)
				return shadow_ent;
			shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
			prev_shadow_ent = shadow_ent;
			continue;
		}

		if (level == PT_PAGE_TABLE_LEVEL) {

			if (walker->level == PT_DIRECTORY_LEVEL) {
				if (prev_shadow_ent)
					*prev_shadow_ent |= PT_SHADOW_PS_MARK;
				FNAME(set_pde)(vcpu, *guest_ent, shadow_ent,
					       walker->inherited_ar,
					       walker->gfn);
			} else {
				ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
				FNAME(set_pte)(vcpu, *guest_ent, shadow_ent,
					       walker->inherited_ar,
					       walker->gfn);
			}
			return shadow_ent;
		}

		if (level - 1 == PT_PAGE_TABLE_LEVEL
		    && walker->level == PT_DIRECTORY_LEVEL) {
			metaphysical = 1;
			table_gfn = (*guest_ent & PT_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
		} else {
			metaphysical = 0;
			table_gfn = walker->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
					       metaphysical, shadow_ent);
		shadow_addr = shadow_page->page_hpa;
		shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
		*shadow_ent = shadow_pte;
		prev_shadow_ent = shadow_ent;
	}
}

/*
 * The guest faulted for write.  We need to
 *
 * - check write permissions
 * - update the guest pte dirty bit
 * - update our own dirty page tracking structures
 */
static int FNAME(fix_write_pf)(struct kvm_vcpu *vcpu,
			       u64 *shadow_ent,
			       struct guest_walker *walker,
			       gva_t addr,
			       int user,
			       int *write_pt)
{
	pt_element_t *guest_ent;
	int writable_shadow;
	gfn_t gfn;
	struct kvm_mmu_page *page;

	if (is_writeble_pte(*shadow_ent))
		return !user || (*shadow_ent & PT_USER_MASK);

	writable_shadow = *shadow_ent & PT_SHADOW_WRITABLE_MASK;
	if (user) {
		/*
		 * User mode access.  Fail if it's a kernel page or a read-only
		 * page.
		 */
		if (!(*shadow_ent & PT_SHADOW_USER_MASK) || !writable_shadow)
			return 0;
		ASSERT(*shadow_ent & PT_USER_MASK);
	} else
		/*
		 * Kernel mode access.  Fail if it's a read-only page and
		 * supervisor write protection is enabled.
		 */
		if (!writable_shadow) {
			if (is_write_protection(vcpu))
				return 0;
			*shadow_ent &= ~PT_USER_MASK;
		}

	guest_ent = walker->ptep;

	if (!is_present_pte(*guest_ent)) {
		*shadow_ent = 0;
		return 0;
	}

	gfn = walker->gfn;

	if (user) {
		/*
		 * Usermode page faults won't be for page table updates.
		 */
		while ((page = kvm_mmu_lookup_page(vcpu, gfn)) != NULL) {
			pgprintk("%s: zap %lx %x\n",
				 __FUNCTION__, gfn, page->role.word);
			kvm_mmu_zap_page(vcpu, page);
		}
	} else if (kvm_mmu_lookup_page(vcpu, gfn)) {
		pgprintk("%s: found shadow page for %lx, marking ro\n",
			 __FUNCTION__, gfn);
		*guest_ent |= PT_DIRTY_MASK;
		*write_pt = 1;
		return 0;
	}
	mark_page_dirty(vcpu->kvm, gfn);
	*shadow_ent |= PT_WRITABLE_MASK;
	*guest_ent |= PT_DIRTY_MASK;
	rmap_add(vcpu, shadow_ent);

	return 1;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int pte_present = error_code & PFERR_PRESENT_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int fixed;
	int write_pt = 0;
	int r;

	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	/*
	 * Look up the shadow pte for the faulting address.
	 */
	FNAME(walk_addr)(&walker, vcpu, addr);
	shadow_pte = FNAME(fetch)(vcpu, addr, &walker);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!shadow_pte) {
		pgprintk("%s: not mapped\n", __FUNCTION__);
		inject_page_fault(vcpu, addr, error_code);
		FNAME(release_walker)(&walker);
		return 0;
	}

	pgprintk("%s: shadow pte %p %llx\n", __FUNCTION__,
		 shadow_pte, *shadow_pte);

	/*
	 * Update the shadow pte.
	 */
	if (write_fault)
		fixed = FNAME(fix_write_pf)(vcpu, shadow_pte, &walker, addr,
					    user_fault, &write_pt);
	else
		fixed = fix_read_pf(shadow_pte);

	pgprintk("%s: updated shadow pte %p %llx\n", __FUNCTION__,
		 shadow_pte, *shadow_pte);

	FNAME(release_walker)(&walker);

	/*
	 * mmio: emulate if accessible, otherwise its a guest fault.
	 */
	if (is_io_pte(*shadow_pte)) {
		if (may_access(*shadow_pte, write_fault, user_fault))
			return 1;
		pgprintk("%s: io work, no access\n", __FUNCTION__);
		inject_page_fault(vcpu, addr,
				  error_code | PFERR_PRESENT_MASK);
		kvm_mmu_audit(vcpu, "post page fault (io)");
		return 0;
	}

	/*
	 * pte not present, guest page fault.
	 */
	if (pte_present && !fixed && !write_pt) {
		inject_page_fault(vcpu, addr, error_code);
		kvm_mmu_audit(vcpu, "post page fault (guest)");
		return 0;
	}

	++kvm_stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");

	return write_pt;
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	pt_element_t guest_pte;
	gpa_t gpa;

	FNAME(walk_addr)(&walker, vcpu, vaddr);
	guest_pte = *walker.ptep;
	FNAME(release_walker)(&walker);

	if (!is_present_pte(guest_pte))
		return UNMAPPED_GVA;

	if (walker.level == PT_DIRECTORY_LEVEL) {
		ASSERT((guest_pte & PT_PAGE_SIZE_MASK));
		ASSERT(PTTYPE == 64 || is_pse(vcpu));

		gpa = (guest_pte & PT_DIR_BASE_ADDR_MASK) | (vaddr &
			(PT_LEVEL_MASK(PT_PAGE_TABLE_LEVEL) | ~PAGE_MASK));

		if (PTTYPE == 32 && is_cpuid_PSE36())
			gpa |= (guest_pte & PT32_DIR_PSE36_MASK) <<
					(32 - PT32_DIR_PSE36_SHIFT);
	} else {
		gpa = (guest_pte & PT_BASE_ADDR_MASK);
		gpa |= (vaddr & ~PAGE_MASK);
	}

	return gpa;
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef SHADOW_PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_PTE_COPY_MASK
#undef PT_NON_PTE_COPY_MASK
#undef PT_DIR_BASE_ADDR_MASK
#undef PT_MAX_FULL_LEVELS
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
	28	#define FNAME(name) paging##64_##name
	29	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	30	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	31	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	32	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	33	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	34	#define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK
cea0f0e7 AK	35	#ifdef CONFIG_X86_64
	36	#define PT_MAX_FULL_LEVELS 4
	37	#else
	38	#define PT_MAX_FULL_LEVELS 2
	39	#endif
6aa8b732 AK	40	#elif PTTYPE == 32
	41	#define pt_element_t u32
	42	#define guest_walker guest_walker32
	43	#define FNAME(name) paging##32_##name
	44	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	45	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	46	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	47	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	48	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	49	#define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK
cea0f0e7	50	#define PT_MAX_FULL_LEVELS 2
6aa8b732 AK	51	#else
	52	#error Invalid PTTYPE value
	53	#endif
	54
	55	/*
	56	* The guest_walker structure emulates the behavior of the hardware page
	57	* table walker.
	58	*/
	59	struct guest_walker {
	60	int level;
cea0f0e7	61	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
6aa8b732	62	pt_element_t *table;
ac79c978	63	pt_element_t *ptep;
6aa8b732	64	pt_element_t inherited_ar;
815af8d4	65	gfn_t gfn;
6aa8b732 AK	66	};
6aa8b732 AK	67
ac79c978 AK	68	/*
	69	* Fetch a guest pte for a guest virtual address
	70	*/
	71	static void FNAME(walk_addr)(struct guest_walker *walker,
	72	struct kvm_vcpu *vcpu, gva_t addr)
6aa8b732 AK	73	{
	74	hpa_t hpa;
	75	struct kvm_memory_slot *slot;
ac79c978	76	pt_element_t *ptep;
1b0973bd	77	pt_element_t root;
cea0f0e7	78	gfn_t table_gfn;
6aa8b732	79
cea0f0e7	80	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
6aa8b732	81	walker->level = vcpu->mmu.root_level;
1b0973bd AK	82	walker->table = NULL;
	83	root = vcpu->cr3;
	84	#if PTTYPE == 64
	85	if (!is_long_mode(vcpu)) {
	86	walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
	87	root = *walker->ptep;
	88	if (!(root & PT_PRESENT_MASK))
	89	return;
	90	--walker->level;
	91	}
	92	#endif
cea0f0e7 AK	93	table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	94	walker->table_gfn[walker->level - 1] = table_gfn;
	95	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	96	walker->level - 1, table_gfn);
	97	slot = gfn_to_memslot(vcpu->kvm, table_gfn);
1b0973bd	98	hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
6aa8b732 AK	99	walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0);
6aa8b732 AK	100
a9058ecd	101	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
6aa8b732 AK	102	(vcpu->cr3 & ~(PAGE_MASK \| CR3_FLAGS_MASK)) == 0);
6aa8b732 AK	103
6aa8b732	104	walker->inherited_ar = PT_USER_MASK \| PT_WRITABLE_MASK;
ac79c978 AK	105
	106	for (;;) {
	107	int index = PT_INDEX(addr, walker->level);
	108	hpa_t paddr;
	109
	110	ptep = &walker->table[index];
	111	ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
	112	((unsigned long)ptep & PAGE_MASK));
	113
1b0973bd AK	114	if (is_present_pte(ptep) && !(ptep & PT_ACCESSED_MASK))
1b0973bd AK	115	*ptep \|= PT_ACCESSED_MASK;
ac79c978	116
815af8d4 AK	117	if (!is_present_pte(*ptep))
	118	break;
	119
	120	if (walker->level == PT_PAGE_TABLE_LEVEL) {
	121	walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
	122	>> PAGE_SHIFT;
	123	break;
	124	}
	125
	126	if (walker->level == PT_DIRECTORY_LEVEL
	127	&& (*ptep & PT_PAGE_SIZE_MASK)
	128	&& (PTTYPE == 64 \|\| is_pse(vcpu))) {
	129	walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
	130	>> PAGE_SHIFT;
	131	walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
ac79c978	132	break;
815af8d4	133	}
ac79c978 AK	134
	135	if (walker->level != 3 \|\| is_long_mode(vcpu))
	136	walker->inherited_ar &= walker->table[index];
cea0f0e7	137	table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
ac79c978 AK	138	paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK);
	139	kunmap_atomic(walker->table, KM_USER0);
	140	walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT),
	141	KM_USER0);
	142	--walker->level;
cea0f0e7 AK	143	walker->table_gfn[walker->level - 1 ] = table_gfn;
	144	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	145	walker->level - 1, table_gfn);
ac79c978 AK	146	}
ac79c978 AK	147	walker->ptep = ptep;
374cbac0	148	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
6aa8b732 AK	149	}
	150
	151	static void FNAME(release_walker)(struct guest_walker *walker)
	152	{
1b0973bd AK	153	if (walker->table)
1b0973bd AK	154	kunmap_atomic(walker->table, KM_USER0);
6aa8b732 AK	155	}
	156
	157	static void FNAME(set_pte)(struct kvm_vcpu *vcpu, u64 guest_pte,
815af8d4	158	u64 *shadow_pte, u64 access_bits, gfn_t gfn)
6aa8b732 AK	159	{
	160	ASSERT(*shadow_pte == 0);
	161	access_bits &= guest_pte;
	162	*shadow_pte = (guest_pte & PT_PTE_COPY_MASK);
	163	set_pte_common(vcpu, shadow_pte, guest_pte & PT_BASE_ADDR_MASK,
815af8d4	164	guest_pte & PT_DIRTY_MASK, access_bits, gfn);
6aa8b732 AK	165	}
	166
	167	static void FNAME(set_pde)(struct kvm_vcpu *vcpu, u64 guest_pde,
815af8d4	168	u64 *shadow_pte, u64 access_bits, gfn_t gfn)
6aa8b732 AK	169	{
	170	gpa_t gaddr;
	171
	172	ASSERT(*shadow_pte == 0);
	173	access_bits &= guest_pde;
815af8d4	174	gaddr = (gpa_t)gfn << PAGE_SHIFT;
6aa8b732 AK	175	if (PTTYPE == 32 && is_cpuid_PSE36())
	176	gaddr \|= (guest_pde & PT32_DIR_PSE36_MASK) <<
	177	(32 - PT32_DIR_PSE36_SHIFT);
8c7bb723	178	*shadow_pte = guest_pde & PT_PTE_COPY_MASK;
6aa8b732	179	set_pte_common(vcpu, shadow_pte, gaddr,
815af8d4	180	guest_pde & PT_DIRTY_MASK, access_bits, gfn);
6aa8b732 AK	181	}
6aa8b732 AK	182
6aa8b732 AK	183	/*
	184	* Fetch a shadow pte for a specific level in the paging hierarchy.
	185	*/
	186	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
	187	struct guest_walker *walker)
	188	{
	189	hpa_t shadow_addr;
	190	int level;
	191	u64 *prev_shadow_ent = NULL;
ac79c978 AK	192	pt_element_t *guest_ent = walker->ptep;
	193
	194	if (!is_present_pte(*guest_ent))
	195	return NULL;
6aa8b732 AK	196
	197	shadow_addr = vcpu->mmu.root_hpa;
	198	level = vcpu->mmu.shadow_root_level;
aef3d3fe AK	199	if (level == PT32E_ROOT_LEVEL) {
	200	shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
	201	shadow_addr &= PT64_BASE_ADDR_MASK;
	202	--level;
	203	}
6aa8b732 AK	204
	205	for (; ; level--) {
	206	u32 index = SHADOW_PT_INDEX(addr, level);
	207	u64 shadow_ent = ((u64 )__va(shadow_addr)) + index;
25c0de2c	208	struct kvm_mmu_page *shadow_page;
8c7bb723	209	u64 shadow_pte;
cea0f0e7 AK	210	int metaphysical;
cea0f0e7 AK	211	gfn_t table_gfn;
6aa8b732 AK	212
	213	if (is_present_pte(shadow_ent) \|\| is_io_pte(shadow_ent)) {
	214	if (level == PT_PAGE_TABLE_LEVEL)
	215	return shadow_ent;
	216	shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
	217	prev_shadow_ent = shadow_ent;
	218	continue;
	219	}
	220
6aa8b732 AK	221	if (level == PT_PAGE_TABLE_LEVEL) {
	222
	223	if (walker->level == PT_DIRECTORY_LEVEL) {
	224	if (prev_shadow_ent)
	225	*prev_shadow_ent \|= PT_SHADOW_PS_MARK;
	226	FNAME(set_pde)(vcpu, *guest_ent, shadow_ent,
	227	walker->inherited_ar,
815af8d4	228	walker->gfn);
6aa8b732 AK	229	} else {
6aa8b732 AK	230	ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
815af8d4 AK	231	FNAME(set_pte)(vcpu, *guest_ent, shadow_ent,
	232	walker->inherited_ar,
	233	walker->gfn);
6aa8b732 AK	234	}
	235	return shadow_ent;
	236	}
	237
cea0f0e7 AK	238	if (level - 1 == PT_PAGE_TABLE_LEVEL
	239	&& walker->level == PT_DIRECTORY_LEVEL) {
	240	metaphysical = 1;
	241	table_gfn = (*guest_ent & PT_BASE_ADDR_MASK)
	242	>> PAGE_SHIFT;
	243	} else {
	244	metaphysical = 0;
	245	table_gfn = walker->table_gfn[level - 2];
	246	}
	247	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
	248	metaphysical, shadow_ent);
25c0de2c	249	shadow_addr = shadow_page->page_hpa;
aef3d3fe AK	250	shadow_pte = shadow_addr \| PT_PRESENT_MASK \| PT_ACCESSED_MASK
aef3d3fe AK	251	\| PT_WRITABLE_MASK \| PT_USER_MASK;
8c7bb723	252	*shadow_ent = shadow_pte;
6aa8b732 AK	253	prev_shadow_ent = shadow_ent;
	254	}
	255	}
	256
	257	/*
	258	* The guest faulted for write. We need to
	259	*
	260	* - check write permissions
	261	* - update the guest pte dirty bit
	262	* - update our own dirty page tracking structures
	263	*/
	264	static int FNAME(fix_write_pf)(struct kvm_vcpu *vcpu,
	265	u64 *shadow_ent,
	266	struct guest_walker *walker,
	267	gva_t addr,
cea0f0e7 AK	268	int user,
cea0f0e7 AK	269	int *write_pt)
6aa8b732 AK	270	{
	271	pt_element_t *guest_ent;
	272	int writable_shadow;
	273	gfn_t gfn;
14364656	274	struct kvm_mmu_page *page;
6aa8b732 AK	275
6aa8b732 AK	276	if (is_writeble_pte(*shadow_ent))
fc3dffe1	277	return !user \|\| (*shadow_ent & PT_USER_MASK);
6aa8b732 AK	278
	279	writable_shadow = *shadow_ent & PT_SHADOW_WRITABLE_MASK;
	280	if (user) {
	281	/*
	282	* User mode access. Fail if it's a kernel page or a read-only
	283	* page.
	284	*/
	285	if (!(*shadow_ent & PT_SHADOW_USER_MASK) \|\| !writable_shadow)
	286	return 0;
	287	ASSERT(*shadow_ent & PT_USER_MASK);
	288	} else
	289	/*
	290	* Kernel mode access. Fail if it's a read-only page and
	291	* supervisor write protection is enabled.
	292	*/
	293	if (!writable_shadow) {
	294	if (is_write_protection(vcpu))
	295	return 0;
	296	*shadow_ent &= ~PT_USER_MASK;
	297	}
	298
ac79c978	299	guest_ent = walker->ptep;
6aa8b732 AK	300
	301	if (!is_present_pte(*guest_ent)) {
	302	*shadow_ent = 0;
	303	return 0;
	304	}
	305
815af8d4	306	gfn = walker->gfn;
14364656 AK	307
	308	if (user) {
	309	/*
	310	* Usermode page faults won't be for page table updates.
	311	*/
	312	while ((page = kvm_mmu_lookup_page(vcpu, gfn)) != NULL) {
	313	pgprintk("%s: zap %lx %x\n",
	314	__FUNCTION__, gfn, page->role.word);
	315	kvm_mmu_zap_page(vcpu, page);
	316	}
	317	} else if (kvm_mmu_lookup_page(vcpu, gfn)) {
cea0f0e7 AK	318	pgprintk("%s: found shadow page for %lx, marking ro\n",
cea0f0e7 AK	319	__FUNCTION__, gfn);
760db773	320	*guest_ent \|= PT_DIRTY_MASK;
cea0f0e7 AK	321	*write_pt = 1;
	322	return 0;
	323	}
6aa8b732 AK	324	mark_page_dirty(vcpu->kvm, gfn);
	325	*shadow_ent \|= PT_WRITABLE_MASK;
	326	*guest_ent \|= PT_DIRTY_MASK;
714b93da	327	rmap_add(vcpu, shadow_ent);
6aa8b732 AK	328
	329	return 1;
	330	}
	331
	332	/*
	333	* Page fault handler. There are several causes for a page fault:
	334	* - there is no shadow pte for the guest pte
	335	* - write access through a shadow pte marked read only so that we can set
	336	* the dirty bit
	337	* - write access to a shadow pte marked read only so we can update the page
	338	* dirty bitmap, when userspace requests it
	339	* - mmio access; in this case we will never install a present shadow pte
	340	* - normal guest page fault due to the guest pte marked not present, not
	341	* writable, or not executable
	342	*
e2dec939 AK	343	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
e2dec939 AK	344	* a negative value on error.
6aa8b732 AK	345	*/
	346	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	347	u32 error_code)
	348	{
	349	int write_fault = error_code & PFERR_WRITE_MASK;
	350	int pte_present = error_code & PFERR_PRESENT_MASK;
	351	int user_fault = error_code & PFERR_USER_MASK;
	352	struct guest_walker walker;
	353	u64 *shadow_pte;
	354	int fixed;
cea0f0e7	355	int write_pt = 0;
e2dec939	356	int r;
6aa8b732	357
cea0f0e7	358	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
37a7d8b0	359	kvm_mmu_audit(vcpu, "pre page fault");
714b93da	360
e2dec939 AK	361	r = mmu_topup_memory_caches(vcpu);
	362	if (r)
	363	return r;
714b93da	364
6aa8b732 AK	365	/*
	366	* Look up the shadow pte for the faulting address.
	367	*/
ebeace86 AK	368	FNAME(walk_addr)(&walker, vcpu, addr);
ebeace86 AK	369	shadow_pte = FNAME(fetch)(vcpu, addr, &walker);
6aa8b732 AK	370
	371	/*
	372	* The page is not mapped by the guest. Let the guest handle it.
	373	*/
	374	if (!shadow_pte) {
cea0f0e7	375	pgprintk("%s: not mapped\n", __FUNCTION__);
6aa8b732 AK	376	inject_page_fault(vcpu, addr, error_code);
	377	FNAME(release_walker)(&walker);
	378	return 0;
	379	}
	380
cea0f0e7 AK	381	pgprintk("%s: shadow pte %p %llx\n", __FUNCTION__,
	382	shadow_pte, *shadow_pte);
	383
6aa8b732 AK	384	/*
	385	* Update the shadow pte.
	386	*/
	387	if (write_fault)
	388	fixed = FNAME(fix_write_pf)(vcpu, shadow_pte, &walker, addr,
cea0f0e7	389	user_fault, &write_pt);
6aa8b732 AK	390	else
	391	fixed = fix_read_pf(shadow_pte);
	392
cea0f0e7 AK	393	pgprintk("%s: updated shadow pte %p %llx\n", __FUNCTION__,
	394	shadow_pte, *shadow_pte);
	395
6aa8b732 AK	396	FNAME(release_walker)(&walker);
	397
	398	/*
	399	* mmio: emulate if accessible, otherwise its a guest fault.
	400	*/
	401	if (is_io_pte(*shadow_pte)) {
	402	if (may_access(*shadow_pte, write_fault, user_fault))
	403	return 1;
	404	pgprintk("%s: io work, no access\n", __FUNCTION__);
	405	inject_page_fault(vcpu, addr,
	406	error_code \| PFERR_PRESENT_MASK);
37a7d8b0	407	kvm_mmu_audit(vcpu, "post page fault (io)");
6aa8b732 AK	408	return 0;
	409	}
	410
	411	/*
	412	* pte not present, guest page fault.
	413	*/
cea0f0e7	414	if (pte_present && !fixed && !write_pt) {
6aa8b732	415	inject_page_fault(vcpu, addr, error_code);
37a7d8b0	416	kvm_mmu_audit(vcpu, "post page fault (guest)");
6aa8b732 AK	417	return 0;
	418	}
	419
	420	++kvm_stat.pf_fixed;
37a7d8b0	421	kvm_mmu_audit(vcpu, "post page fault (fixed)");
6aa8b732	422
cea0f0e7	423	return write_pt;
6aa8b732 AK	424	}
	425
	426	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
	427	{
	428	struct guest_walker walker;
	429	pt_element_t guest_pte;
	430	gpa_t gpa;
	431
ac79c978 AK	432	FNAME(walk_addr)(&walker, vcpu, vaddr);
ac79c978 AK	433	guest_pte = *walker.ptep;
6aa8b732 AK	434	FNAME(release_walker)(&walker);
	435
	436	if (!is_present_pte(guest_pte))
	437	return UNMAPPED_GVA;
	438
	439	if (walker.level == PT_DIRECTORY_LEVEL) {
	440	ASSERT((guest_pte & PT_PAGE_SIZE_MASK));
	441	ASSERT(PTTYPE == 64 \|\| is_pse(vcpu));
	442
	443	gpa = (guest_pte & PT_DIR_BASE_ADDR_MASK) \| (vaddr &
	444	(PT_LEVEL_MASK(PT_PAGE_TABLE_LEVEL) \| ~PAGE_MASK));
	445
	446	if (PTTYPE == 32 && is_cpuid_PSE36())
	447	gpa \|= (guest_pte & PT32_DIR_PSE36_MASK) <<
	448	(32 - PT32_DIR_PSE36_SHIFT);
	449	} else {
	450	gpa = (guest_pte & PT_BASE_ADDR_MASK);
	451	gpa \|= (vaddr & ~PAGE_MASK);
	452	}
	453
	454	return gpa;
	455	}
	456
	457	#undef pt_element_t
	458	#undef guest_walker
	459	#undef FNAME
	460	#undef PT_BASE_ADDR_MASK
	461	#undef PT_INDEX
	462	#undef SHADOW_PT_INDEX
	463	#undef PT_LEVEL_MASK
	464	#undef PT_PTE_COPY_MASK
	465	#undef PT_NON_PTE_COPY_MASK
	466	#undef PT_DIR_BASE_ADDR_MASK
cea0f0e7	467	#undef PT_MAX_FULL_LEVELS