[deliverable/linux.git] / drivers / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#else
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK
	#define PT_MAX_FULL_LEVELS 2
#else
	#error Invalid PTTYPE value
#endif

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t *table;
	pt_element_t *ptep;
	pt_element_t inherited_ar;
	gfn_t gfn;
	u32 error_code;
};

/*
 * Fetch a guest pte for a guest virtual address
 */
static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
			    int write_fault, int user_fault, int fetch_fault)
{
	hpa_t hpa;
	struct kvm_memory_slot *slot;
	pt_element_t *ptep;
	pt_element_t root;
	gfn_t table_gfn;

	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
	walker->level = vcpu->mmu.root_level;
	walker->table = NULL;
	root = vcpu->cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
		root = *walker->ptep;
		if (!(root & PT_PRESENT_MASK))
			goto not_present;
		--walker->level;
	}
#endif
	table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	walker->table_gfn[walker->level - 1] = table_gfn;
	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
		 walker->level - 1, table_gfn);
	slot = gfn_to_memslot(vcpu->kvm, table_gfn);
	hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
	walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0);

	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->cr3 & ~(PAGE_MASK | CR3_FLAGS_MASK)) == 0);

	walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;

	for (;;) {
		int index = PT_INDEX(addr, walker->level);
		hpa_t paddr;

		ptep = &walker->table[index];
		ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
		       ((unsigned long)ptep & PAGE_MASK));

		if (!is_present_pte(*ptep))
			goto not_present;

		if (write_fault && !is_writeble_pte(*ptep))
			if (user_fault || is_write_protection(vcpu))
				goto access_error;

		if (user_fault && !(*ptep & PT_USER_MASK))
			goto access_error;

#if PTTYPE == 64
		if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK))
			goto access_error;
#endif

		if (!(*ptep & PT_ACCESSED_MASK)) {
			mark_page_dirty(vcpu->kvm, table_gfn);
			*ptep |= PT_ACCESSED_MASK;
		}

		if (walker->level == PT_PAGE_TABLE_LEVEL) {
			walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
		    && (*ptep & PT_PAGE_SIZE_MASK)
		    && (PTTYPE == 64 || is_pse(vcpu))) {
			walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
			break;
		}

		walker->inherited_ar &= walker->table[index];
		table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
		paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK);
		kunmap_atomic(walker->table, KM_USER0);
		walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT),
					    KM_USER0);
		--walker->level;
		walker->table_gfn[walker->level - 1 ] = table_gfn;
		pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
			 walker->level - 1, table_gfn);
	}
	walker->ptep = ptep;
	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
	return 0;
}

static void FNAME(release_walker)(struct guest_walker *walker)
{
	if (walker->table)
		kunmap_atomic(walker->table, KM_USER0);
}

static void FNAME(mark_pagetable_dirty)(struct kvm *kvm,
					struct guest_walker *walker)
{
	mark_page_dirty(kvm, walker->table_gfn[walker->level - 1]);
}

static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
				  u64 *shadow_pte,
				  gpa_t gaddr,
				  pt_element_t *gpte,
				  u64 access_bits,
				  int user_fault,
				  int write_fault,
				  int *ptwrite,
				  struct guest_walker *walker,
				  gfn_t gfn)
{
	hpa_t paddr;
	int dirty = *gpte & PT_DIRTY_MASK;
	int was_rmapped = is_rmap_pte(*shadow_pte);

	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
		 " user_fault %d gfn %lx\n",
		 __FUNCTION__, *shadow_pte, (u64)*gpte, access_bits,
		 write_fault, user_fault, gfn);

	if (write_fault && !dirty) {
		*gpte |= PT_DIRTY_MASK;
		dirty = 1;
		FNAME(mark_pagetable_dirty)(vcpu->kvm, walker);
	}

	*shadow_pte |= *gpte & PT_PTE_COPY_MASK;
	*shadow_pte |= access_bits << PT_SHADOW_BITS_OFFSET;
	if (!dirty)
		access_bits &= ~PT_WRITABLE_MASK;

	paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);

	*shadow_pte |= PT_PRESENT_MASK;
	if (access_bits & PT_USER_MASK)
		*shadow_pte |= PT_USER_MASK;

	if (is_error_hpa(paddr)) {
		*shadow_pte |= gaddr;
		*shadow_pte |= PT_SHADOW_IO_MARK;
		*shadow_pte &= ~PT_PRESENT_MASK;
		return;
	}

	*shadow_pte |= paddr;

	if (!write_fault && (*shadow_pte & PT_SHADOW_USER_MASK) &&
	    !(*shadow_pte & PT_USER_MASK)) {
		/*
		 * If supervisor write protect is disabled, we shadow kernel
		 * pages as user pages so we can trap the write access.
		 */
		*shadow_pte |= PT_USER_MASK;
		*shadow_pte &= ~PT_WRITABLE_MASK;
		access_bits &= ~PT_WRITABLE_MASK;
	}

	if ((access_bits & PT_WRITABLE_MASK)
	    || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
		struct kvm_mmu_page *shadow;

		*shadow_pte |= PT_WRITABLE_MASK;
		if (user_fault) {
			mmu_unshadow(vcpu, gfn);
			goto unshadowed;
		}

		shadow = kvm_mmu_lookup_page(vcpu, gfn);
		if (shadow) {
			pgprintk("%s: found shadow page for %lx, marking ro\n",
				 __FUNCTION__, gfn);
			access_bits &= ~PT_WRITABLE_MASK;
			if (is_writeble_pte(*shadow_pte)) {
				*shadow_pte &= ~PT_WRITABLE_MASK;
				kvm_arch_ops->tlb_flush(vcpu);
			}
			if (write_fault)
				*ptwrite = 1;
		}
	}

unshadowed:

	if (access_bits & PT_WRITABLE_MASK)
		mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);

	page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
	if (!was_rmapped)
		rmap_add(vcpu, shadow_pte);
}

static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t *gpte,
			   u64 *shadow_pte, u64 access_bits,
			   int user_fault, int write_fault, int *ptwrite,
			   struct guest_walker *walker, gfn_t gfn)
{
	access_bits &= *gpte;
	FNAME(set_pte_common)(vcpu, shadow_pte, *gpte & PT_BASE_ADDR_MASK,
			      gpte, access_bits, user_fault, write_fault,
			      ptwrite, walker, gfn);
}

static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
			      u64 *spte, const void *pte, int bytes)
{
	pt_element_t gpte;

	if (bytes < sizeof(pt_element_t))
		return;
	gpte = *(const pt_element_t *)pte;
	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK))
		return;
	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
	FNAME(set_pte)(vcpu, &gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
		       0, NULL, NULL,
		       (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
}

static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t *gpde,
			   u64 *shadow_pte, u64 access_bits,
			   int user_fault, int write_fault, int *ptwrite,
			   struct guest_walker *walker, gfn_t gfn)
{
	gpa_t gaddr;

	access_bits &= *gpde;
	gaddr = (gpa_t)gfn << PAGE_SHIFT;
	if (PTTYPE == 32 && is_cpuid_PSE36())
		gaddr |= (*gpde & PT32_DIR_PSE36_MASK) <<
			(32 - PT32_DIR_PSE36_SHIFT);
	FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
			      gpde, access_bits, user_fault, write_fault,
			      ptwrite, walker, gfn);
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			 struct guest_walker *walker,
			 int user_fault, int write_fault, int *ptwrite)
{
	hpa_t shadow_addr;
	int level;
	u64 *shadow_ent;
	u64 *prev_shadow_ent = NULL;
	pt_element_t *guest_ent = walker->ptep;

	if (!is_present_pte(*guest_ent))
		return NULL;

	shadow_addr = vcpu->mmu.root_hpa;
	level = vcpu->mmu.shadow_root_level;
	if (level == PT32E_ROOT_LEVEL) {
		shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
		shadow_addr &= PT64_BASE_ADDR_MASK;
		--level;
	}

	for (; ; level--) {
		u32 index = SHADOW_PT_INDEX(addr, level);
		struct kvm_mmu_page *shadow_page;
		u64 shadow_pte;
		int metaphysical;
		gfn_t table_gfn;
		unsigned hugepage_access = 0;

		shadow_ent = ((u64 *)__va(shadow_addr)) + index;
		if (is_present_pte(*shadow_ent) || is_io_pte(*shadow_ent)) {
			if (level == PT_PAGE_TABLE_LEVEL)
				break;
			shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
			prev_shadow_ent = shadow_ent;
			continue;
		}

		if (level == PT_PAGE_TABLE_LEVEL)
			break;

		if (level - 1 == PT_PAGE_TABLE_LEVEL
		    && walker->level == PT_DIRECTORY_LEVEL) {
			metaphysical = 1;
			hugepage_access = *guest_ent;
			hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
			hugepage_access >>= PT_WRITABLE_SHIFT;
			table_gfn = (*guest_ent & PT_BASE_ADDR_MASK)
				>> PAGE_SHIFT;
		} else {
			metaphysical = 0;
			table_gfn = walker->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
					       metaphysical, hugepage_access,
					       shadow_ent);
		shadow_addr = __pa(shadow_page->spt);
		shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
		*shadow_ent = shadow_pte;
		prev_shadow_ent = shadow_ent;
	}

	if (walker->level == PT_DIRECTORY_LEVEL) {
		if (prev_shadow_ent)
			*prev_shadow_ent |= PT_SHADOW_PS_MARK;
		FNAME(set_pde)(vcpu, guest_ent, shadow_ent,
			       walker->inherited_ar, user_fault, write_fault,
			       ptwrite, walker, walker->gfn);
	} else {
		ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
		FNAME(set_pte)(vcpu, guest_ent, shadow_ent,
			       walker->inherited_ar, user_fault, write_fault,
			       ptwrite, walker, walker->gfn);
	}
	return shadow_ent;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	int fetch_fault = error_code & PFERR_FETCH_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int write_pt = 0;
	int r;

	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	/*
	 * Look up the shadow pte for the faulting address.
	 */
	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!r) {
		pgprintk("%s: guest page fault\n", __FUNCTION__);
		inject_page_fault(vcpu, addr, walker.error_code);
		FNAME(release_walker)(&walker);
		vcpu->last_pt_write_count = 0; /* reset fork detector */
		return 0;
	}

	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
				  &write_pt);
	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
		 shadow_pte, *shadow_pte, write_pt);

	FNAME(release_walker)(&walker);

	if (!write_pt)
		vcpu->last_pt_write_count = 0; /* reset fork detector */

	/*
	 * mmio: emulate if accessible, otherwise its a guest fault.
	 */
	if (is_io_pte(*shadow_pte))
		return 1;

	++vcpu->stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");

	return write_pt;
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	gpa_t gpa = UNMAPPED_GVA;
	int r;

	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);

	if (r) {
		gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
		gpa |= vaddr & ~PAGE_MASK;
	}

	FNAME(release_walker)(&walker);
	return gpa;
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef SHADOW_PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_PTE_COPY_MASK
#undef PT_NON_PTE_COPY_MASK
#undef PT_DIR_BASE_ADDR_MASK
#undef PT_MAX_FULL_LEVELS
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
	28	#define FNAME(name) paging##64_##name
	29	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	30	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	31	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	32	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	33	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	34	#define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK
cea0f0e7 AK	35	#ifdef CONFIG_X86_64
	36	#define PT_MAX_FULL_LEVELS 4
	37	#else
	38	#define PT_MAX_FULL_LEVELS 2
	39	#endif
6aa8b732 AK	40	#elif PTTYPE == 32
	41	#define pt_element_t u32
	42	#define guest_walker guest_walker32
	43	#define FNAME(name) paging##32_##name
	44	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	45	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	46	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	47	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	48	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	49	#define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK
cea0f0e7	50	#define PT_MAX_FULL_LEVELS 2
6aa8b732 AK	51	#else
	52	#error Invalid PTTYPE value
	53	#endif
	54
	55	/*
	56	* The guest_walker structure emulates the behavior of the hardware page
	57	* table walker.
	58	*/
	59	struct guest_walker {
	60	int level;
cea0f0e7	61	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
6aa8b732	62	pt_element_t *table;
ac79c978	63	pt_element_t *ptep;
6aa8b732	64	pt_element_t inherited_ar;
815af8d4	65	gfn_t gfn;
7993ba43	66	u32 error_code;
6aa8b732 AK	67	};
6aa8b732 AK	68
ac79c978 AK	69	/*
	70	* Fetch a guest pte for a guest virtual address
	71	*/
7993ba43 AK	72	static int FNAME(walk_addr)(struct guest_walker *walker,
7993ba43 AK	73	struct kvm_vcpu *vcpu, gva_t addr,
73b1087e	74	int write_fault, int user_fault, int fetch_fault)
6aa8b732 AK	75	{
	76	hpa_t hpa;
	77	struct kvm_memory_slot *slot;
ac79c978	78	pt_element_t *ptep;
1b0973bd	79	pt_element_t root;
cea0f0e7	80	gfn_t table_gfn;
6aa8b732	81
cea0f0e7	82	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
6aa8b732	83	walker->level = vcpu->mmu.root_level;
1b0973bd AK	84	walker->table = NULL;
	85	root = vcpu->cr3;
	86	#if PTTYPE == 64
	87	if (!is_long_mode(vcpu)) {
	88	walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
	89	root = *walker->ptep;
	90	if (!(root & PT_PRESENT_MASK))
7993ba43	91	goto not_present;
1b0973bd AK	92	--walker->level;
	93	}
	94	#endif
cea0f0e7 AK	95	table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	96	walker->table_gfn[walker->level - 1] = table_gfn;
	97	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	98	walker->level - 1, table_gfn);
	99	slot = gfn_to_memslot(vcpu->kvm, table_gfn);
1b0973bd	100	hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
6aa8b732 AK	101	walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0);
6aa8b732 AK	102
a9058ecd	103	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
6aa8b732 AK	104	(vcpu->cr3 & ~(PAGE_MASK \| CR3_FLAGS_MASK)) == 0);
6aa8b732 AK	105
6aa8b732	106	walker->inherited_ar = PT_USER_MASK \| PT_WRITABLE_MASK;
ac79c978 AK	107
	108	for (;;) {
	109	int index = PT_INDEX(addr, walker->level);
	110	hpa_t paddr;
	111
	112	ptep = &walker->table[index];
	113	ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
	114	((unsigned long)ptep & PAGE_MASK));
	115
815af8d4	116	if (!is_present_pte(*ptep))
7993ba43 AK	117	goto not_present;
	118
	119	if (write_fault && !is_writeble_pte(*ptep))
	120	if (user_fault \|\| is_write_protection(vcpu))
	121	goto access_error;
	122
	123	if (user_fault && !(*ptep & PT_USER_MASK))
	124	goto access_error;
	125
73b1087e AK	126	#if PTTYPE == 64
	127	if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK))
	128	goto access_error;
	129	#endif
	130
bf3f8e86 AK	131	if (!(*ptep & PT_ACCESSED_MASK)) {
	132	mark_page_dirty(vcpu->kvm, table_gfn);
	133	*ptep \|= PT_ACCESSED_MASK;
	134	}
815af8d4 AK	135
	136	if (walker->level == PT_PAGE_TABLE_LEVEL) {
	137	walker->gfn = (*ptep & PT_BASE_ADDR_MASK)
	138	>> PAGE_SHIFT;
	139	break;
	140	}
	141
	142	if (walker->level == PT_DIRECTORY_LEVEL
	143	&& (*ptep & PT_PAGE_SIZE_MASK)
	144	&& (PTTYPE == 64 \|\| is_pse(vcpu))) {
	145	walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK)
	146	>> PAGE_SHIFT;
	147	walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
ac79c978	148	break;
815af8d4	149	}
ac79c978	150
ca5aac1f	151	walker->inherited_ar &= walker->table[index];
cea0f0e7	152	table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
ac79c978 AK	153	paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK);
	154	kunmap_atomic(walker->table, KM_USER0);
	155	walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT),
	156	KM_USER0);
	157	--walker->level;
cea0f0e7 AK	158	walker->table_gfn[walker->level - 1 ] = table_gfn;
	159	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	160	walker->level - 1, table_gfn);
ac79c978 AK	161	}
ac79c978 AK	162	walker->ptep = ptep;
374cbac0	163	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep);
7993ba43 AK	164	return 1;
	165
	166	not_present:
	167	walker->error_code = 0;
	168	goto err;
	169
	170	access_error:
	171	walker->error_code = PFERR_PRESENT_MASK;
	172
	173	err:
	174	if (write_fault)
	175	walker->error_code \|= PFERR_WRITE_MASK;
	176	if (user_fault)
	177	walker->error_code \|= PFERR_USER_MASK;
73b1087e AK	178	if (fetch_fault)
73b1087e AK	179	walker->error_code \|= PFERR_FETCH_MASK;
7993ba43	180	return 0;
6aa8b732 AK	181	}
	182
	183	static void FNAME(release_walker)(struct guest_walker *walker)
	184	{
1b0973bd AK	185	if (walker->table)
1b0973bd AK	186	kunmap_atomic(walker->table, KM_USER0);
6aa8b732 AK	187	}
6aa8b732 AK	188
bf3f8e86 AK	189	static void FNAME(mark_pagetable_dirty)(struct kvm *kvm,
	190	struct guest_walker *walker)
	191	{
	192	mark_page_dirty(kvm, walker->table_gfn[walker->level - 1]);
	193	}
	194
e60d75ea AK	195	static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
	196	u64 *shadow_pte,
	197	gpa_t gaddr,
6598c8b2	198	pt_element_t *gpte,
e60d75ea	199	u64 access_bits,
97a0a01e	200	int user_fault,
63b1ad24	201	int write_fault,
97a0a01e AK	202	int *ptwrite,
97a0a01e AK	203	struct guest_walker *walker,
e60d75ea AK	204	gfn_t gfn)
	205	{
	206	hpa_t paddr;
6598c8b2	207	int dirty = *gpte & PT_DIRTY_MASK;
97a0a01e AK	208	int was_rmapped = is_rmap_pte(*shadow_pte);
	209
	210	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
	211	" user_fault %d gfn %lx\n",
	212	__FUNCTION__, shadow_pte, (u64)gpte, access_bits,
	213	write_fault, user_fault, gfn);
	214
	215	if (write_fault && !dirty) {
	216	*gpte \|= PT_DIRTY_MASK;
	217	dirty = 1;
	218	FNAME(mark_pagetable_dirty)(vcpu->kvm, walker);
	219	}
e60d75ea	220
a18de5a4	221	shadow_pte \|= gpte & PT_PTE_COPY_MASK;
e60d75ea AK	222	*shadow_pte \|= access_bits << PT_SHADOW_BITS_OFFSET;
	223	if (!dirty)
	224	access_bits &= ~PT_WRITABLE_MASK;
	225
	226	paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);
	227
97a0a01e AK	228	*shadow_pte \|= PT_PRESENT_MASK;
	229	if (access_bits & PT_USER_MASK)
	230	*shadow_pte \|= PT_USER_MASK;
e60d75ea AK	231
	232	if (is_error_hpa(paddr)) {
	233	*shadow_pte \|= gaddr;
	234	*shadow_pte \|= PT_SHADOW_IO_MARK;
	235	*shadow_pte &= ~PT_PRESENT_MASK;
	236	return;
	237	}
	238
	239	*shadow_pte \|= paddr;
	240
63b1ad24 AK	241	if (!write_fault && (*shadow_pte & PT_SHADOW_USER_MASK) &&
	242	!(*shadow_pte & PT_USER_MASK)) {
	243	/*
	244	* If supervisor write protect is disabled, we shadow kernel
	245	* pages as user pages so we can trap the write access.
	246	*/
	247	*shadow_pte \|= PT_USER_MASK;
	248	*shadow_pte &= ~PT_WRITABLE_MASK;
	249	access_bits &= ~PT_WRITABLE_MASK;
	250	}
	251
97a0a01e AK	252	if ((access_bits & PT_WRITABLE_MASK)
97a0a01e AK	253	\|\| (write_fault && !is_write_protection(vcpu) && !user_fault)) {
e60d75ea AK	254	struct kvm_mmu_page *shadow;
e60d75ea AK	255
97a0a01e AK	256	*shadow_pte \|= PT_WRITABLE_MASK;
	257	if (user_fault) {
	258	mmu_unshadow(vcpu, gfn);
	259	goto unshadowed;
	260	}
	261
e60d75ea AK	262	shadow = kvm_mmu_lookup_page(vcpu, gfn);
	263	if (shadow) {
	264	pgprintk("%s: found shadow page for %lx, marking ro\n",
	265	__FUNCTION__, gfn);
	266	access_bits &= ~PT_WRITABLE_MASK;
	267	if (is_writeble_pte(*shadow_pte)) {
97a0a01e AK	268	*shadow_pte &= ~PT_WRITABLE_MASK;
97a0a01e AK	269	kvm_arch_ops->tlb_flush(vcpu);
e60d75ea	270	}
97a0a01e AK	271	if (write_fault)
97a0a01e AK	272	*ptwrite = 1;
e60d75ea AK	273	}
	274	}
	275
97a0a01e AK	276	unshadowed:
97a0a01e AK	277
e60d75ea AK	278	if (access_bits & PT_WRITABLE_MASK)
	279	mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);
	280
	281	page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
97a0a01e AK	282	if (!was_rmapped)
97a0a01e AK	283	rmap_add(vcpu, shadow_pte);
e60d75ea AK	284	}
e60d75ea AK	285
6598c8b2	286	static void FNAME(set_pte)(struct kvm_vcpu vcpu, pt_element_t gpte,
63b1ad24	287	u64 *shadow_pte, u64 access_bits,
97a0a01e AK	288	int user_fault, int write_fault, int *ptwrite,
97a0a01e AK	289	struct guest_walker *walker, gfn_t gfn)
6aa8b732	290	{
6598c8b2	291	access_bits &= *gpte;
6598c8b2	292	FNAME(set_pte_common)(vcpu, shadow_pte, *gpte & PT_BASE_ADDR_MASK,
97a0a01e AK	293	gpte, access_bits, user_fault, write_fault,
97a0a01e AK	294	ptwrite, walker, gfn);
6aa8b732 AK	295	}
6aa8b732 AK	296
0028425f AK	297	static void FNAME(update_pte)(struct kvm_vcpu vcpu, struct kvm_mmu_page page,
	298	u64 spte, const void pte, int bytes)
	299	{
	300	pt_element_t gpte;
	301
	302	if (bytes < sizeof(pt_element_t))
	303	return;
	304	gpte = (const pt_element_t )pte;
	305	if (~gpte & (PT_PRESENT_MASK \| PT_ACCESSED_MASK))
	306	return;
	307	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
63b1ad24	308	FNAME(set_pte)(vcpu, &gpte, spte, PT_USER_MASK \| PT_WRITABLE_MASK, 0,
97a0a01e	309	0, NULL, NULL,
0028425f AK	310	(gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
	311	}
	312
6598c8b2	313	static void FNAME(set_pde)(struct kvm_vcpu vcpu, pt_element_t gpde,
97a0a01e AK	314	u64 *shadow_pte, u64 access_bits,
	315	int user_fault, int write_fault, int *ptwrite,
	316	struct guest_walker *walker, gfn_t gfn)
6aa8b732 AK	317	{
	318	gpa_t gaddr;
	319
6598c8b2	320	access_bits &= *gpde;
815af8d4	321	gaddr = (gpa_t)gfn << PAGE_SHIFT;
6aa8b732	322	if (PTTYPE == 32 && is_cpuid_PSE36())
6598c8b2	323	gaddr \|= (*gpde & PT32_DIR_PSE36_MASK) <<
6aa8b732	324	(32 - PT32_DIR_PSE36_SHIFT);
e60d75ea	325	FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
97a0a01e AK	326	gpde, access_bits, user_fault, write_fault,
97a0a01e AK	327	ptwrite, walker, gfn);
6aa8b732 AK	328	}
6aa8b732 AK	329
6aa8b732 AK	330	/*
	331	* Fetch a shadow pte for a specific level in the paging hierarchy.
	332	*/
	333	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
97a0a01e AK	334	struct guest_walker *walker,
97a0a01e AK	335	int user_fault, int write_fault, int *ptwrite)
6aa8b732 AK	336	{
	337	hpa_t shadow_addr;
	338	int level;
ef0197e8	339	u64 *shadow_ent;
6aa8b732	340	u64 *prev_shadow_ent = NULL;
ac79c978 AK	341	pt_element_t *guest_ent = walker->ptep;
	342
	343	if (!is_present_pte(*guest_ent))
	344	return NULL;
6aa8b732 AK	345
	346	shadow_addr = vcpu->mmu.root_hpa;
	347	level = vcpu->mmu.shadow_root_level;
aef3d3fe AK	348	if (level == PT32E_ROOT_LEVEL) {
	349	shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
	350	shadow_addr &= PT64_BASE_ADDR_MASK;
	351	--level;
	352	}
6aa8b732 AK	353
	354	for (; ; level--) {
	355	u32 index = SHADOW_PT_INDEX(addr, level);
25c0de2c	356	struct kvm_mmu_page *shadow_page;
8c7bb723	357	u64 shadow_pte;
cea0f0e7 AK	358	int metaphysical;
cea0f0e7 AK	359	gfn_t table_gfn;
d28c6cfb	360	unsigned hugepage_access = 0;
6aa8b732	361
ef0197e8	362	shadow_ent = ((u64 *)__va(shadow_addr)) + index;
6aa8b732 AK	363	if (is_present_pte(shadow_ent) \|\| is_io_pte(shadow_ent)) {
6aa8b732 AK	364	if (level == PT_PAGE_TABLE_LEVEL)
97a0a01e	365	break;
6aa8b732 AK	366	shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
	367	prev_shadow_ent = shadow_ent;
	368	continue;
	369	}
	370
ef0197e8 AK	371	if (level == PT_PAGE_TABLE_LEVEL)
ef0197e8 AK	372	break;
6aa8b732	373
cea0f0e7 AK	374	if (level - 1 == PT_PAGE_TABLE_LEVEL
	375	&& walker->level == PT_DIRECTORY_LEVEL) {
	376	metaphysical = 1;
d28c6cfb AK	377	hugepage_access = *guest_ent;
	378	hugepage_access &= PT_USER_MASK \| PT_WRITABLE_MASK;
	379	hugepage_access >>= PT_WRITABLE_SHIFT;
cea0f0e7 AK	380	table_gfn = (*guest_ent & PT_BASE_ADDR_MASK)
	381	>> PAGE_SHIFT;
	382	} else {
	383	metaphysical = 0;
	384	table_gfn = walker->table_gfn[level - 2];
	385	}
	386	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
d28c6cfb AK	387	metaphysical, hugepage_access,
d28c6cfb AK	388	shadow_ent);
47ad8e68	389	shadow_addr = __pa(shadow_page->spt);
aef3d3fe AK	390	shadow_pte = shadow_addr \| PT_PRESENT_MASK \| PT_ACCESSED_MASK
aef3d3fe AK	391	\| PT_WRITABLE_MASK \| PT_USER_MASK;
8c7bb723	392	*shadow_ent = shadow_pte;
6aa8b732 AK	393	prev_shadow_ent = shadow_ent;
6aa8b732 AK	394	}
ef0197e8 AK	395
	396	if (walker->level == PT_DIRECTORY_LEVEL) {
	397	if (prev_shadow_ent)
	398	*prev_shadow_ent \|= PT_SHADOW_PS_MARK;
6598c8b2	399	FNAME(set_pde)(vcpu, guest_ent, shadow_ent,
97a0a01e AK	400	walker->inherited_ar, user_fault, write_fault,
97a0a01e AK	401	ptwrite, walker, walker->gfn);
ef0197e8 AK	402	} else {
ef0197e8 AK	403	ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
6598c8b2	404	FNAME(set_pte)(vcpu, guest_ent, shadow_ent,
97a0a01e AK	405	walker->inherited_ar, user_fault, write_fault,
97a0a01e AK	406	ptwrite, walker, walker->gfn);
ef0197e8 AK	407	}
ef0197e8 AK	408	return shadow_ent;
6aa8b732 AK	409	}
6aa8b732 AK	410
6aa8b732 AK	411	/*
	412	* Page fault handler. There are several causes for a page fault:
	413	* - there is no shadow pte for the guest pte
	414	* - write access through a shadow pte marked read only so that we can set
	415	* the dirty bit
	416	* - write access to a shadow pte marked read only so we can update the page
	417	* dirty bitmap, when userspace requests it
	418	* - mmio access; in this case we will never install a present shadow pte
	419	* - normal guest page fault due to the guest pte marked not present, not
	420	* writable, or not executable
	421	*
e2dec939 AK	422	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
e2dec939 AK	423	* a negative value on error.
6aa8b732 AK	424	*/
	425	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	426	u32 error_code)
	427	{
	428	int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732	429	int user_fault = error_code & PFERR_USER_MASK;
73b1087e	430	int fetch_fault = error_code & PFERR_FETCH_MASK;
6aa8b732 AK	431	struct guest_walker walker;
6aa8b732 AK	432	u64 *shadow_pte;
cea0f0e7	433	int write_pt = 0;
e2dec939	434	int r;
6aa8b732	435
cea0f0e7	436	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
37a7d8b0	437	kvm_mmu_audit(vcpu, "pre page fault");
714b93da	438
e2dec939 AK	439	r = mmu_topup_memory_caches(vcpu);
	440	if (r)
	441	return r;
714b93da	442
6aa8b732 AK	443	/*
	444	* Look up the shadow pte for the faulting address.
	445	*/
73b1087e AK	446	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
73b1087e AK	447	fetch_fault);
6aa8b732 AK	448
	449	/*
	450	* The page is not mapped by the guest. Let the guest handle it.
	451	*/
7993ba43 AK	452	if (!r) {
	453	pgprintk("%s: guest page fault\n", __FUNCTION__);
	454	inject_page_fault(vcpu, addr, walker.error_code);
6aa8b732	455	FNAME(release_walker)(&walker);
a25f7e1f	456	vcpu->last_pt_write_count = 0; /* reset fork detector */
6aa8b732 AK	457	return 0;
	458	}
	459
97a0a01e AK	460	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
	461	&write_pt);
	462	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
	463	shadow_pte, *shadow_pte, write_pt);
cea0f0e7	464
6aa8b732 AK	465	FNAME(release_walker)(&walker);
6aa8b732 AK	466
a25f7e1f AK	467	if (!write_pt)
	468	vcpu->last_pt_write_count = 0; /* reset fork detector */
	469
6aa8b732 AK	470	/*
	471	* mmio: emulate if accessible, otherwise its a guest fault.
	472	*/
d27d4aca	473	if (is_io_pte(*shadow_pte))
7993ba43	474	return 1;
6aa8b732	475
1165f5fe	476	++vcpu->stat.pf_fixed;
37a7d8b0	477	kvm_mmu_audit(vcpu, "post page fault (fixed)");
6aa8b732	478
cea0f0e7	479	return write_pt;
6aa8b732 AK	480	}
	481
	482	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
	483	{
	484	struct guest_walker walker;
e119d117 AK	485	gpa_t gpa = UNMAPPED_GVA;
e119d117 AK	486	int r;
6aa8b732	487
e119d117	488	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
6aa8b732	489
e119d117 AK	490	if (r) {
	491	gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
	492	gpa \|= vaddr & ~PAGE_MASK;
6aa8b732 AK	493	}
6aa8b732 AK	494
e119d117	495	FNAME(release_walker)(&walker);
6aa8b732 AK	496	return gpa;
	497	}
	498
	499	#undef pt_element_t
	500	#undef guest_walker
	501	#undef FNAME
	502	#undef PT_BASE_ADDR_MASK
	503	#undef PT_INDEX
	504	#undef SHADOW_PT_INDEX
	505	#undef PT_LEVEL_MASK
	506	#undef PT_PTE_COPY_MASK
	507	#undef PT_NON_PTE_COPY_MASK
	508	#undef PT_DIR_BASE_ADDR_MASK
cea0f0e7	509	#undef PT_MAX_FULL_LEVELS