Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
22 | * so the code in this file is compiled twice, once per pte size. | |
23 | */ | |
24 | ||
25 | #if PTTYPE == 64 | |
26 | #define pt_element_t u64 | |
27 | #define guest_walker guest_walker64 | |
28 | #define FNAME(name) paging##64_##name | |
29 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
30 | #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK | |
31 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
32 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
33 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) | |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
37 | #else | |
38 | #define PT_MAX_FULL_LEVELS 2 | |
39 | #endif | |
6aa8b732 AK |
40 | #elif PTTYPE == 32 |
41 | #define pt_element_t u32 | |
42 | #define guest_walker guest_walker32 | |
43 | #define FNAME(name) paging##32_##name | |
44 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
45 | #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK | |
46 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) | |
47 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
48 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) | |
c7addb90 | 49 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 50 | #define PT_MAX_FULL_LEVELS 2 |
6aa8b732 AK |
51 | #else |
52 | #error Invalid PTTYPE value | |
53 | #endif | |
54 | ||
5fb07ddb AK |
55 | #define gpte_to_gfn FNAME(gpte_to_gfn) |
56 | #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde) | |
57 | ||
6aa8b732 AK |
58 | /* |
59 | * The guest_walker structure emulates the behavior of the hardware page | |
60 | * table walker. | |
61 | */ | |
62 | struct guest_walker { | |
63 | int level; | |
cea0f0e7 | 64 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
fe551881 | 65 | pt_element_t pte; |
6aa8b732 | 66 | pt_element_t inherited_ar; |
815af8d4 | 67 | gfn_t gfn; |
7993ba43 | 68 | u32 error_code; |
6aa8b732 AK |
69 | }; |
70 | ||
5fb07ddb AK |
71 | static gfn_t gpte_to_gfn(pt_element_t gpte) |
72 | { | |
73 | return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
74 | } | |
75 | ||
76 | static gfn_t gpte_to_gfn_pde(pt_element_t gpte) | |
77 | { | |
78 | return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
79 | } | |
80 | ||
ac79c978 AK |
81 | /* |
82 | * Fetch a guest pte for a guest virtual address | |
83 | */ | |
7993ba43 AK |
84 | static int FNAME(walk_addr)(struct guest_walker *walker, |
85 | struct kvm_vcpu *vcpu, gva_t addr, | |
73b1087e | 86 | int write_fault, int user_fault, int fetch_fault) |
6aa8b732 | 87 | { |
42bf3f0a | 88 | pt_element_t pte; |
cea0f0e7 | 89 | gfn_t table_gfn; |
42bf3f0a AK |
90 | unsigned index; |
91 | gpa_t pte_gpa; | |
6aa8b732 | 92 | |
cea0f0e7 | 93 | pgprintk("%s: addr %lx\n", __FUNCTION__, addr); |
6aa8b732 | 94 | walker->level = vcpu->mmu.root_level; |
42bf3f0a | 95 | pte = vcpu->cr3; |
1b0973bd AK |
96 | #if PTTYPE == 64 |
97 | if (!is_long_mode(vcpu)) { | |
42bf3f0a AK |
98 | pte = vcpu->pdptrs[(addr >> 30) & 3]; |
99 | if (!is_present_pte(pte)) | |
7993ba43 | 100 | goto not_present; |
1b0973bd AK |
101 | --walker->level; |
102 | } | |
103 | #endif | |
a9058ecd | 104 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
f802a307 | 105 | (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 106 | |
6aa8b732 | 107 | walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK; |
ac79c978 AK |
108 | |
109 | for (;;) { | |
42bf3f0a | 110 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 111 | |
5fb07ddb | 112 | table_gfn = gpte_to_gfn(pte); |
ec8d4eae IE |
113 | pte_gpa = table_gfn << PAGE_SHIFT; |
114 | pte_gpa += index * sizeof(pt_element_t); | |
42bf3f0a AK |
115 | walker->table_gfn[walker->level - 1] = table_gfn; |
116 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, | |
117 | walker->level - 1, table_gfn); | |
118 | ||
ec8d4eae | 119 | kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)); |
42bf3f0a AK |
120 | |
121 | if (!is_present_pte(pte)) | |
7993ba43 AK |
122 | goto not_present; |
123 | ||
42bf3f0a | 124 | if (write_fault && !is_writeble_pte(pte)) |
7993ba43 AK |
125 | if (user_fault || is_write_protection(vcpu)) |
126 | goto access_error; | |
127 | ||
42bf3f0a | 128 | if (user_fault && !(pte & PT_USER_MASK)) |
7993ba43 AK |
129 | goto access_error; |
130 | ||
73b1087e | 131 | #if PTTYPE == 64 |
42bf3f0a | 132 | if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK)) |
73b1087e AK |
133 | goto access_error; |
134 | #endif | |
135 | ||
42bf3f0a | 136 | if (!(pte & PT_ACCESSED_MASK)) { |
bf3f8e86 | 137 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 138 | pte |= PT_ACCESSED_MASK; |
ec8d4eae | 139 | kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)); |
bf3f8e86 | 140 | } |
815af8d4 AK |
141 | |
142 | if (walker->level == PT_PAGE_TABLE_LEVEL) { | |
5fb07ddb | 143 | walker->gfn = gpte_to_gfn(pte); |
815af8d4 AK |
144 | break; |
145 | } | |
146 | ||
147 | if (walker->level == PT_DIRECTORY_LEVEL | |
42bf3f0a | 148 | && (pte & PT_PAGE_SIZE_MASK) |
815af8d4 | 149 | && (PTTYPE == 64 || is_pse(vcpu))) { |
5fb07ddb | 150 | walker->gfn = gpte_to_gfn_pde(pte); |
815af8d4 | 151 | walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL); |
da928521 AK |
152 | if (PTTYPE == 32 && is_cpuid_PSE36()) |
153 | walker->gfn += pse36_gfn_delta(pte); | |
ac79c978 | 154 | break; |
815af8d4 | 155 | } |
ac79c978 | 156 | |
42bf3f0a | 157 | walker->inherited_ar &= pte; |
ac79c978 AK |
158 | --walker->level; |
159 | } | |
42bf3f0a AK |
160 | |
161 | if (write_fault && !is_dirty_pte(pte)) { | |
162 | mark_page_dirty(vcpu->kvm, table_gfn); | |
163 | pte |= PT_DIRTY_MASK; | |
ec8d4eae | 164 | kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)); |
42bf3f0a AK |
165 | kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte)); |
166 | } | |
167 | ||
168 | walker->pte = pte; | |
169 | pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)pte); | |
7993ba43 AK |
170 | return 1; |
171 | ||
172 | not_present: | |
173 | walker->error_code = 0; | |
174 | goto err; | |
175 | ||
176 | access_error: | |
177 | walker->error_code = PFERR_PRESENT_MASK; | |
178 | ||
179 | err: | |
180 | if (write_fault) | |
181 | walker->error_code |= PFERR_WRITE_MASK; | |
182 | if (user_fault) | |
183 | walker->error_code |= PFERR_USER_MASK; | |
73b1087e AK |
184 | if (fetch_fault) |
185 | walker->error_code |= PFERR_FETCH_MASK; | |
fe551881 | 186 | return 0; |
6aa8b732 AK |
187 | } |
188 | ||
e60d75ea AK |
189 | static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu, |
190 | u64 *shadow_pte, | |
191 | gpa_t gaddr, | |
fe551881 | 192 | pt_element_t gpte, |
e60d75ea | 193 | u64 access_bits, |
97a0a01e | 194 | int user_fault, |
63b1ad24 | 195 | int write_fault, |
97a0a01e AK |
196 | int *ptwrite, |
197 | struct guest_walker *walker, | |
e60d75ea AK |
198 | gfn_t gfn) |
199 | { | |
200 | hpa_t paddr; | |
fe551881 | 201 | int dirty = gpte & PT_DIRTY_MASK; |
c7addb90 AK |
202 | u64 spte; |
203 | int was_rmapped = is_rmap_pte(*shadow_pte); | |
b238f7bc | 204 | struct page *page; |
97a0a01e AK |
205 | |
206 | pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d" | |
207 | " user_fault %d gfn %lx\n", | |
c7addb90 | 208 | __FUNCTION__, *shadow_pte, (u64)gpte, access_bits, |
97a0a01e AK |
209 | write_fault, user_fault, gfn); |
210 | ||
12b7d28f AK |
211 | /* |
212 | * We don't set the accessed bit, since we sometimes want to see | |
213 | * whether the guest actually used the pte (in order to detect | |
214 | * demand paging). | |
215 | */ | |
216 | spte = PT_PRESENT_MASK | PT_DIRTY_MASK; | |
fe551881 | 217 | spte |= gpte & PT64_NX_MASK; |
e60d75ea AK |
218 | if (!dirty) |
219 | access_bits &= ~PT_WRITABLE_MASK; | |
220 | ||
4a4c9924 | 221 | paddr = gpa_to_hpa(vcpu->kvm, gaddr & PT64_BASE_ADDR_MASK); |
e60d75ea | 222 | |
b238f7bc IE |
223 | /* |
224 | * the reason paddr get mask even that it isnt pte is beacuse the | |
225 | * HPA_ERR_MASK bit might be used to signal error | |
226 | */ | |
227 | page = pfn_to_page((paddr & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT); | |
228 | ||
0d551bb6 | 229 | spte |= PT_PRESENT_MASK; |
97a0a01e | 230 | if (access_bits & PT_USER_MASK) |
0d551bb6 | 231 | spte |= PT_USER_MASK; |
e60d75ea AK |
232 | |
233 | if (is_error_hpa(paddr)) { | |
c7addb90 AK |
234 | set_shadow_pte(shadow_pte, |
235 | shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK); | |
b238f7bc | 236 | kvm_release_page_clean(page); |
e60d75ea AK |
237 | return; |
238 | } | |
239 | ||
0d551bb6 | 240 | spte |= paddr; |
e60d75ea | 241 | |
97a0a01e AK |
242 | if ((access_bits & PT_WRITABLE_MASK) |
243 | || (write_fault && !is_write_protection(vcpu) && !user_fault)) { | |
e60d75ea AK |
244 | struct kvm_mmu_page *shadow; |
245 | ||
0d551bb6 | 246 | spte |= PT_WRITABLE_MASK; |
97a0a01e | 247 | if (user_fault) { |
f67a46f4 | 248 | mmu_unshadow(vcpu->kvm, gfn); |
97a0a01e AK |
249 | goto unshadowed; |
250 | } | |
251 | ||
f67a46f4 | 252 | shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn); |
e60d75ea AK |
253 | if (shadow) { |
254 | pgprintk("%s: found shadow page for %lx, marking ro\n", | |
255 | __FUNCTION__, gfn); | |
256 | access_bits &= ~PT_WRITABLE_MASK; | |
0d551bb6 AK |
257 | if (is_writeble_pte(spte)) { |
258 | spte &= ~PT_WRITABLE_MASK; | |
cbdd1bea | 259 | kvm_x86_ops->tlb_flush(vcpu); |
e60d75ea | 260 | } |
97a0a01e AK |
261 | if (write_fault) |
262 | *ptwrite = 1; | |
e60d75ea AK |
263 | } |
264 | } | |
265 | ||
97a0a01e AK |
266 | unshadowed: |
267 | ||
e60d75ea AK |
268 | if (access_bits & PT_WRITABLE_MASK) |
269 | mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT); | |
270 | ||
c7addb90 | 271 | pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte); |
e663ee64 | 272 | set_shadow_pte(shadow_pte, spte); |
e60d75ea | 273 | page_header_update_slot(vcpu->kvm, shadow_pte, gaddr); |
8a7ae055 | 274 | if (!was_rmapped) { |
290fc38d IE |
275 | rmap_add(vcpu, shadow_pte, (gaddr & PT64_BASE_ADDR_MASK) |
276 | >> PAGE_SHIFT); | |
b238f7bc | 277 | if (!is_rmap_pte(*shadow_pte)) |
b4231d61 | 278 | kvm_release_page_clean(page); |
8a7ae055 IE |
279 | } |
280 | else | |
b238f7bc | 281 | kvm_release_page_clean(page); |
12b7d28f AK |
282 | if (!ptwrite || !*ptwrite) |
283 | vcpu->last_pte_updated = shadow_pte; | |
e60d75ea AK |
284 | } |
285 | ||
fe551881 | 286 | static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte, |
63b1ad24 | 287 | u64 *shadow_pte, u64 access_bits, |
97a0a01e AK |
288 | int user_fault, int write_fault, int *ptwrite, |
289 | struct guest_walker *walker, gfn_t gfn) | |
6aa8b732 | 290 | { |
fe551881 SL |
291 | access_bits &= gpte; |
292 | FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK, | |
97a0a01e AK |
293 | gpte, access_bits, user_fault, write_fault, |
294 | ptwrite, walker, gfn); | |
6aa8b732 AK |
295 | } |
296 | ||
0028425f | 297 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page, |
c7addb90 AK |
298 | u64 *spte, const void *pte, int bytes, |
299 | int offset_in_pte) | |
0028425f AK |
300 | { |
301 | pt_element_t gpte; | |
302 | ||
0028425f | 303 | gpte = *(const pt_element_t *)pte; |
c7addb90 AK |
304 | if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) { |
305 | if (!offset_in_pte && !is_present_pte(gpte)) | |
306 | set_shadow_pte(spte, shadow_notrap_nonpresent_pte); | |
307 | return; | |
308 | } | |
309 | if (bytes < sizeof(pt_element_t)) | |
0028425f AK |
310 | return; |
311 | pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte); | |
fe551881 | 312 | FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0, |
5fb07ddb | 313 | 0, NULL, NULL, gpte_to_gfn(gpte)); |
0028425f AK |
314 | } |
315 | ||
fe551881 | 316 | static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde, |
97a0a01e AK |
317 | u64 *shadow_pte, u64 access_bits, |
318 | int user_fault, int write_fault, int *ptwrite, | |
319 | struct guest_walker *walker, gfn_t gfn) | |
6aa8b732 AK |
320 | { |
321 | gpa_t gaddr; | |
322 | ||
fe551881 | 323 | access_bits &= gpde; |
815af8d4 | 324 | gaddr = (gpa_t)gfn << PAGE_SHIFT; |
e60d75ea | 325 | FNAME(set_pte_common)(vcpu, shadow_pte, gaddr, |
97a0a01e AK |
326 | gpde, access_bits, user_fault, write_fault, |
327 | ptwrite, walker, gfn); | |
6aa8b732 AK |
328 | } |
329 | ||
6aa8b732 AK |
330 | /* |
331 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
332 | */ | |
333 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, | |
97a0a01e AK |
334 | struct guest_walker *walker, |
335 | int user_fault, int write_fault, int *ptwrite) | |
6aa8b732 AK |
336 | { |
337 | hpa_t shadow_addr; | |
338 | int level; | |
ef0197e8 | 339 | u64 *shadow_ent; |
6aa8b732 | 340 | u64 *prev_shadow_ent = NULL; |
ac79c978 | 341 | |
fe551881 | 342 | if (!is_present_pte(walker->pte)) |
ac79c978 | 343 | return NULL; |
6aa8b732 AK |
344 | |
345 | shadow_addr = vcpu->mmu.root_hpa; | |
346 | level = vcpu->mmu.shadow_root_level; | |
aef3d3fe AK |
347 | if (level == PT32E_ROOT_LEVEL) { |
348 | shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3]; | |
349 | shadow_addr &= PT64_BASE_ADDR_MASK; | |
350 | --level; | |
351 | } | |
6aa8b732 AK |
352 | |
353 | for (; ; level--) { | |
354 | u32 index = SHADOW_PT_INDEX(addr, level); | |
25c0de2c | 355 | struct kvm_mmu_page *shadow_page; |
8c7bb723 | 356 | u64 shadow_pte; |
cea0f0e7 AK |
357 | int metaphysical; |
358 | gfn_t table_gfn; | |
d28c6cfb | 359 | unsigned hugepage_access = 0; |
6aa8b732 | 360 | |
ef0197e8 | 361 | shadow_ent = ((u64 *)__va(shadow_addr)) + index; |
c7addb90 | 362 | if (is_shadow_present_pte(*shadow_ent)) { |
6aa8b732 | 363 | if (level == PT_PAGE_TABLE_LEVEL) |
97a0a01e | 364 | break; |
6aa8b732 AK |
365 | shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK; |
366 | prev_shadow_ent = shadow_ent; | |
367 | continue; | |
368 | } | |
369 | ||
ef0197e8 AK |
370 | if (level == PT_PAGE_TABLE_LEVEL) |
371 | break; | |
6aa8b732 | 372 | |
cea0f0e7 AK |
373 | if (level - 1 == PT_PAGE_TABLE_LEVEL |
374 | && walker->level == PT_DIRECTORY_LEVEL) { | |
375 | metaphysical = 1; | |
fe551881 | 376 | hugepage_access = walker->pte; |
d28c6cfb | 377 | hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK; |
cc70e737 AK |
378 | if (!is_dirty_pte(walker->pte)) |
379 | hugepage_access &= ~PT_WRITABLE_MASK; | |
c22e3514 | 380 | hugepage_access >>= PT_WRITABLE_SHIFT; |
fe551881 | 381 | if (walker->pte & PT64_NX_MASK) |
d55e2cb2 | 382 | hugepage_access |= (1 << 2); |
5fb07ddb | 383 | table_gfn = gpte_to_gfn(walker->pte); |
cea0f0e7 AK |
384 | } else { |
385 | metaphysical = 0; | |
386 | table_gfn = walker->table_gfn[level - 2]; | |
387 | } | |
388 | shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1, | |
d28c6cfb AK |
389 | metaphysical, hugepage_access, |
390 | shadow_ent); | |
47ad8e68 | 391 | shadow_addr = __pa(shadow_page->spt); |
aef3d3fe AK |
392 | shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK |
393 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
8c7bb723 | 394 | *shadow_ent = shadow_pte; |
6aa8b732 AK |
395 | prev_shadow_ent = shadow_ent; |
396 | } | |
ef0197e8 AK |
397 | |
398 | if (walker->level == PT_DIRECTORY_LEVEL) { | |
fe551881 | 399 | FNAME(set_pde)(vcpu, walker->pte, shadow_ent, |
97a0a01e AK |
400 | walker->inherited_ar, user_fault, write_fault, |
401 | ptwrite, walker, walker->gfn); | |
ef0197e8 AK |
402 | } else { |
403 | ASSERT(walker->level == PT_PAGE_TABLE_LEVEL); | |
fe551881 | 404 | FNAME(set_pte)(vcpu, walker->pte, shadow_ent, |
97a0a01e AK |
405 | walker->inherited_ar, user_fault, write_fault, |
406 | ptwrite, walker, walker->gfn); | |
ef0197e8 AK |
407 | } |
408 | return shadow_ent; | |
6aa8b732 AK |
409 | } |
410 | ||
6aa8b732 AK |
411 | /* |
412 | * Page fault handler. There are several causes for a page fault: | |
413 | * - there is no shadow pte for the guest pte | |
414 | * - write access through a shadow pte marked read only so that we can set | |
415 | * the dirty bit | |
416 | * - write access to a shadow pte marked read only so we can update the page | |
417 | * dirty bitmap, when userspace requests it | |
418 | * - mmio access; in this case we will never install a present shadow pte | |
419 | * - normal guest page fault due to the guest pte marked not present, not | |
420 | * writable, or not executable | |
421 | * | |
e2dec939 AK |
422 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
423 | * a negative value on error. | |
6aa8b732 AK |
424 | */ |
425 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
426 | u32 error_code) | |
427 | { | |
428 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 | 429 | int user_fault = error_code & PFERR_USER_MASK; |
73b1087e | 430 | int fetch_fault = error_code & PFERR_FETCH_MASK; |
6aa8b732 AK |
431 | struct guest_walker walker; |
432 | u64 *shadow_pte; | |
cea0f0e7 | 433 | int write_pt = 0; |
e2dec939 | 434 | int r; |
6aa8b732 | 435 | |
cea0f0e7 | 436 | pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code); |
37a7d8b0 | 437 | kvm_mmu_audit(vcpu, "pre page fault"); |
714b93da | 438 | |
e2dec939 AK |
439 | r = mmu_topup_memory_caches(vcpu); |
440 | if (r) | |
441 | return r; | |
714b93da | 442 | |
6aa8b732 AK |
443 | /* |
444 | * Look up the shadow pte for the faulting address. | |
445 | */ | |
73b1087e AK |
446 | r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault, |
447 | fetch_fault); | |
6aa8b732 AK |
448 | |
449 | /* | |
450 | * The page is not mapped by the guest. Let the guest handle it. | |
451 | */ | |
7993ba43 AK |
452 | if (!r) { |
453 | pgprintk("%s: guest page fault\n", __FUNCTION__); | |
454 | inject_page_fault(vcpu, addr, walker.error_code); | |
a25f7e1f | 455 | vcpu->last_pt_write_count = 0; /* reset fork detector */ |
6aa8b732 AK |
456 | return 0; |
457 | } | |
458 | ||
97a0a01e AK |
459 | shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
460 | &write_pt); | |
461 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__, | |
462 | shadow_pte, *shadow_pte, write_pt); | |
cea0f0e7 | 463 | |
a25f7e1f AK |
464 | if (!write_pt) |
465 | vcpu->last_pt_write_count = 0; /* reset fork detector */ | |
466 | ||
6aa8b732 AK |
467 | /* |
468 | * mmio: emulate if accessible, otherwise its a guest fault. | |
469 | */ | |
d27d4aca | 470 | if (is_io_pte(*shadow_pte)) |
7993ba43 | 471 | return 1; |
6aa8b732 | 472 | |
1165f5fe | 473 | ++vcpu->stat.pf_fixed; |
37a7d8b0 | 474 | kvm_mmu_audit(vcpu, "post page fault (fixed)"); |
6aa8b732 | 475 | |
cea0f0e7 | 476 | return write_pt; |
6aa8b732 AK |
477 | } |
478 | ||
479 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr) | |
480 | { | |
481 | struct guest_walker walker; | |
e119d117 AK |
482 | gpa_t gpa = UNMAPPED_GVA; |
483 | int r; | |
6aa8b732 | 484 | |
e119d117 | 485 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0); |
6aa8b732 | 486 | |
e119d117 AK |
487 | if (r) { |
488 | gpa = (gpa_t)walker.gfn << PAGE_SHIFT; | |
489 | gpa |= vaddr & ~PAGE_MASK; | |
6aa8b732 AK |
490 | } |
491 | ||
492 | return gpa; | |
493 | } | |
494 | ||
c7addb90 AK |
495 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
496 | struct kvm_mmu_page *sp) | |
497 | { | |
e5a4c8ca | 498 | int i, offset = 0; |
c7addb90 | 499 | pt_element_t *gpt; |
8a7ae055 | 500 | struct page *page; |
c7addb90 | 501 | |
e5a4c8ca AK |
502 | if (sp->role.metaphysical |
503 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { | |
c7addb90 AK |
504 | nonpaging_prefetch_page(vcpu, sp); |
505 | return; | |
506 | } | |
507 | ||
e5a4c8ca AK |
508 | if (PTTYPE == 32) |
509 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
8a7ae055 IE |
510 | page = gfn_to_page(vcpu->kvm, sp->gfn); |
511 | gpt = kmap_atomic(page, KM_USER0); | |
c7addb90 | 512 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
e5a4c8ca | 513 | if (is_present_pte(gpt[offset + i])) |
c7addb90 AK |
514 | sp->spt[i] = shadow_trap_nonpresent_pte; |
515 | else | |
516 | sp->spt[i] = shadow_notrap_nonpresent_pte; | |
517 | kunmap_atomic(gpt, KM_USER0); | |
b4231d61 | 518 | kvm_release_page_clean(page); |
c7addb90 AK |
519 | } |
520 | ||
6aa8b732 AK |
521 | #undef pt_element_t |
522 | #undef guest_walker | |
523 | #undef FNAME | |
524 | #undef PT_BASE_ADDR_MASK | |
525 | #undef PT_INDEX | |
526 | #undef SHADOW_PT_INDEX | |
527 | #undef PT_LEVEL_MASK | |
6aa8b732 | 528 | #undef PT_DIR_BASE_ADDR_MASK |
c7addb90 | 529 | #undef PT_LEVEL_BITS |
cea0f0e7 | 530 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb AK |
531 | #undef gpte_to_gfn |
532 | #undef gpte_to_gfn_pde |