Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
22 | * so the code in this file is compiled twice, once per pte size. | |
23 | */ | |
24 | ||
25 | #if PTTYPE == 64 | |
26 | #define pt_element_t u64 | |
27 | #define guest_walker guest_walker64 | |
28 | #define FNAME(name) paging##64_##name | |
29 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
30 | #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK | |
31 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
32 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
33 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) | |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
37 | #else | |
38 | #define PT_MAX_FULL_LEVELS 2 | |
39 | #endif | |
6aa8b732 AK |
40 | #elif PTTYPE == 32 |
41 | #define pt_element_t u32 | |
42 | #define guest_walker guest_walker32 | |
43 | #define FNAME(name) paging##32_##name | |
44 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
45 | #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK | |
46 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) | |
47 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
48 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) | |
c7addb90 | 49 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 50 | #define PT_MAX_FULL_LEVELS 2 |
6aa8b732 AK |
51 | #else |
52 | #error Invalid PTTYPE value | |
53 | #endif | |
54 | ||
55 | /* | |
56 | * The guest_walker structure emulates the behavior of the hardware page | |
57 | * table walker. | |
58 | */ | |
59 | struct guest_walker { | |
60 | int level; | |
cea0f0e7 | 61 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
6aa8b732 | 62 | pt_element_t *table; |
fe551881 | 63 | pt_element_t pte; |
ac79c978 | 64 | pt_element_t *ptep; |
fe551881 SL |
65 | struct page *page; |
66 | int index; | |
6aa8b732 | 67 | pt_element_t inherited_ar; |
815af8d4 | 68 | gfn_t gfn; |
7993ba43 | 69 | u32 error_code; |
6aa8b732 AK |
70 | }; |
71 | ||
ac79c978 AK |
72 | /* |
73 | * Fetch a guest pte for a guest virtual address | |
74 | */ | |
7993ba43 AK |
75 | static int FNAME(walk_addr)(struct guest_walker *walker, |
76 | struct kvm_vcpu *vcpu, gva_t addr, | |
73b1087e | 77 | int write_fault, int user_fault, int fetch_fault) |
6aa8b732 AK |
78 | { |
79 | hpa_t hpa; | |
80 | struct kvm_memory_slot *slot; | |
ac79c978 | 81 | pt_element_t *ptep; |
1b0973bd | 82 | pt_element_t root; |
cea0f0e7 | 83 | gfn_t table_gfn; |
6aa8b732 | 84 | |
cea0f0e7 | 85 | pgprintk("%s: addr %lx\n", __FUNCTION__, addr); |
6aa8b732 | 86 | walker->level = vcpu->mmu.root_level; |
1b0973bd | 87 | walker->table = NULL; |
fe551881 SL |
88 | walker->page = NULL; |
89 | walker->ptep = NULL; | |
1b0973bd AK |
90 | root = vcpu->cr3; |
91 | #if PTTYPE == 64 | |
92 | if (!is_long_mode(vcpu)) { | |
93 | walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3]; | |
94 | root = *walker->ptep; | |
fe551881 | 95 | walker->pte = root; |
1b0973bd | 96 | if (!(root & PT_PRESENT_MASK)) |
7993ba43 | 97 | goto not_present; |
1b0973bd AK |
98 | --walker->level; |
99 | } | |
100 | #endif | |
cea0f0e7 AK |
101 | table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
102 | walker->table_gfn[walker->level - 1] = table_gfn; | |
103 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, | |
104 | walker->level - 1, table_gfn); | |
105 | slot = gfn_to_memslot(vcpu->kvm, table_gfn); | |
4a4c9924 | 106 | hpa = safe_gpa_to_hpa(vcpu->kvm, root & PT64_BASE_ADDR_MASK); |
fe551881 SL |
107 | walker->page = pfn_to_page(hpa >> PAGE_SHIFT); |
108 | walker->table = kmap_atomic(walker->page, KM_USER0); | |
6aa8b732 | 109 | |
a9058ecd | 110 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
f802a307 | 111 | (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 112 | |
6aa8b732 | 113 | walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK; |
ac79c978 AK |
114 | |
115 | for (;;) { | |
116 | int index = PT_INDEX(addr, walker->level); | |
117 | hpa_t paddr; | |
118 | ||
119 | ptep = &walker->table[index]; | |
fe551881 | 120 | walker->index = index; |
ac79c978 AK |
121 | ASSERT(((unsigned long)walker->table & PAGE_MASK) == |
122 | ((unsigned long)ptep & PAGE_MASK)); | |
123 | ||
815af8d4 | 124 | if (!is_present_pte(*ptep)) |
7993ba43 AK |
125 | goto not_present; |
126 | ||
127 | if (write_fault && !is_writeble_pte(*ptep)) | |
128 | if (user_fault || is_write_protection(vcpu)) | |
129 | goto access_error; | |
130 | ||
131 | if (user_fault && !(*ptep & PT_USER_MASK)) | |
132 | goto access_error; | |
133 | ||
73b1087e AK |
134 | #if PTTYPE == 64 |
135 | if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK)) | |
136 | goto access_error; | |
137 | #endif | |
138 | ||
bf3f8e86 AK |
139 | if (!(*ptep & PT_ACCESSED_MASK)) { |
140 | mark_page_dirty(vcpu->kvm, table_gfn); | |
141 | *ptep |= PT_ACCESSED_MASK; | |
142 | } | |
815af8d4 AK |
143 | |
144 | if (walker->level == PT_PAGE_TABLE_LEVEL) { | |
145 | walker->gfn = (*ptep & PT_BASE_ADDR_MASK) | |
146 | >> PAGE_SHIFT; | |
e3c5e7ec AK |
147 | if (write_fault && !is_dirty_pte(*ptep)) { |
148 | mark_page_dirty(vcpu->kvm, table_gfn); | |
149 | *ptep |= PT_DIRTY_MASK; | |
150 | } | |
815af8d4 AK |
151 | break; |
152 | } | |
153 | ||
154 | if (walker->level == PT_DIRECTORY_LEVEL | |
155 | && (*ptep & PT_PAGE_SIZE_MASK) | |
156 | && (PTTYPE == 64 || is_pse(vcpu))) { | |
157 | walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK) | |
158 | >> PAGE_SHIFT; | |
159 | walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL); | |
e3c5e7ec AK |
160 | if (write_fault && !is_dirty_pte(*ptep)) { |
161 | mark_page_dirty(vcpu->kvm, table_gfn); | |
162 | *ptep |= PT_DIRTY_MASK; | |
163 | } | |
ac79c978 | 164 | break; |
815af8d4 | 165 | } |
ac79c978 | 166 | |
ca5aac1f | 167 | walker->inherited_ar &= walker->table[index]; |
cea0f0e7 | 168 | table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT; |
ac79c978 | 169 | kunmap_atomic(walker->table, KM_USER0); |
4a4c9924 | 170 | paddr = safe_gpa_to_hpa(vcpu->kvm, table_gfn << PAGE_SHIFT); |
fe551881 SL |
171 | walker->page = pfn_to_page(paddr >> PAGE_SHIFT); |
172 | walker->table = kmap_atomic(walker->page, KM_USER0); | |
ac79c978 | 173 | --walker->level; |
d77c26fc | 174 | walker->table_gfn[walker->level - 1] = table_gfn; |
cea0f0e7 AK |
175 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, |
176 | walker->level - 1, table_gfn); | |
ac79c978 | 177 | } |
fe551881 SL |
178 | walker->pte = *ptep; |
179 | if (walker->page) | |
180 | walker->ptep = NULL; | |
181 | if (walker->table) | |
182 | kunmap_atomic(walker->table, KM_USER0); | |
374cbac0 | 183 | pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep); |
7993ba43 AK |
184 | return 1; |
185 | ||
186 | not_present: | |
187 | walker->error_code = 0; | |
188 | goto err; | |
189 | ||
190 | access_error: | |
191 | walker->error_code = PFERR_PRESENT_MASK; | |
192 | ||
193 | err: | |
194 | if (write_fault) | |
195 | walker->error_code |= PFERR_WRITE_MASK; | |
196 | if (user_fault) | |
197 | walker->error_code |= PFERR_USER_MASK; | |
73b1087e AK |
198 | if (fetch_fault) |
199 | walker->error_code |= PFERR_FETCH_MASK; | |
1b0973bd AK |
200 | if (walker->table) |
201 | kunmap_atomic(walker->table, KM_USER0); | |
fe551881 | 202 | return 0; |
6aa8b732 AK |
203 | } |
204 | ||
e60d75ea AK |
205 | static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu, |
206 | u64 *shadow_pte, | |
207 | gpa_t gaddr, | |
fe551881 | 208 | pt_element_t gpte, |
e60d75ea | 209 | u64 access_bits, |
97a0a01e | 210 | int user_fault, |
63b1ad24 | 211 | int write_fault, |
97a0a01e AK |
212 | int *ptwrite, |
213 | struct guest_walker *walker, | |
e60d75ea AK |
214 | gfn_t gfn) |
215 | { | |
216 | hpa_t paddr; | |
fe551881 | 217 | int dirty = gpte & PT_DIRTY_MASK; |
c7addb90 AK |
218 | u64 spte; |
219 | int was_rmapped = is_rmap_pte(*shadow_pte); | |
97a0a01e AK |
220 | |
221 | pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d" | |
222 | " user_fault %d gfn %lx\n", | |
c7addb90 | 223 | __FUNCTION__, *shadow_pte, (u64)gpte, access_bits, |
97a0a01e AK |
224 | write_fault, user_fault, gfn); |
225 | ||
12b7d28f AK |
226 | /* |
227 | * We don't set the accessed bit, since we sometimes want to see | |
228 | * whether the guest actually used the pte (in order to detect | |
229 | * demand paging). | |
230 | */ | |
231 | spte = PT_PRESENT_MASK | PT_DIRTY_MASK; | |
fe551881 | 232 | spte |= gpte & PT64_NX_MASK; |
e60d75ea AK |
233 | if (!dirty) |
234 | access_bits &= ~PT_WRITABLE_MASK; | |
235 | ||
4a4c9924 | 236 | paddr = gpa_to_hpa(vcpu->kvm, gaddr & PT64_BASE_ADDR_MASK); |
e60d75ea | 237 | |
0d551bb6 | 238 | spte |= PT_PRESENT_MASK; |
97a0a01e | 239 | if (access_bits & PT_USER_MASK) |
0d551bb6 | 240 | spte |= PT_USER_MASK; |
e60d75ea AK |
241 | |
242 | if (is_error_hpa(paddr)) { | |
c7addb90 AK |
243 | set_shadow_pte(shadow_pte, |
244 | shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK); | |
e60d75ea AK |
245 | return; |
246 | } | |
247 | ||
0d551bb6 | 248 | spte |= paddr; |
e60d75ea | 249 | |
97a0a01e AK |
250 | if ((access_bits & PT_WRITABLE_MASK) |
251 | || (write_fault && !is_write_protection(vcpu) && !user_fault)) { | |
e60d75ea AK |
252 | struct kvm_mmu_page *shadow; |
253 | ||
0d551bb6 | 254 | spte |= PT_WRITABLE_MASK; |
97a0a01e | 255 | if (user_fault) { |
f67a46f4 | 256 | mmu_unshadow(vcpu->kvm, gfn); |
97a0a01e AK |
257 | goto unshadowed; |
258 | } | |
259 | ||
f67a46f4 | 260 | shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn); |
e60d75ea AK |
261 | if (shadow) { |
262 | pgprintk("%s: found shadow page for %lx, marking ro\n", | |
263 | __FUNCTION__, gfn); | |
264 | access_bits &= ~PT_WRITABLE_MASK; | |
0d551bb6 AK |
265 | if (is_writeble_pte(spte)) { |
266 | spte &= ~PT_WRITABLE_MASK; | |
cbdd1bea | 267 | kvm_x86_ops->tlb_flush(vcpu); |
e60d75ea | 268 | } |
97a0a01e AK |
269 | if (write_fault) |
270 | *ptwrite = 1; | |
e60d75ea AK |
271 | } |
272 | } | |
273 | ||
97a0a01e AK |
274 | unshadowed: |
275 | ||
e60d75ea AK |
276 | if (access_bits & PT_WRITABLE_MASK) |
277 | mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT); | |
278 | ||
c7addb90 | 279 | pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte); |
e663ee64 | 280 | set_shadow_pte(shadow_pte, spte); |
e60d75ea | 281 | page_header_update_slot(vcpu->kvm, shadow_pte, gaddr); |
97a0a01e | 282 | if (!was_rmapped) |
290fc38d IE |
283 | rmap_add(vcpu, shadow_pte, (gaddr & PT64_BASE_ADDR_MASK) |
284 | >> PAGE_SHIFT); | |
12b7d28f AK |
285 | if (!ptwrite || !*ptwrite) |
286 | vcpu->last_pte_updated = shadow_pte; | |
e60d75ea AK |
287 | } |
288 | ||
fe551881 | 289 | static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte, |
63b1ad24 | 290 | u64 *shadow_pte, u64 access_bits, |
97a0a01e AK |
291 | int user_fault, int write_fault, int *ptwrite, |
292 | struct guest_walker *walker, gfn_t gfn) | |
6aa8b732 | 293 | { |
fe551881 SL |
294 | access_bits &= gpte; |
295 | FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK, | |
97a0a01e AK |
296 | gpte, access_bits, user_fault, write_fault, |
297 | ptwrite, walker, gfn); | |
6aa8b732 AK |
298 | } |
299 | ||
0028425f | 300 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page, |
c7addb90 AK |
301 | u64 *spte, const void *pte, int bytes, |
302 | int offset_in_pte) | |
0028425f AK |
303 | { |
304 | pt_element_t gpte; | |
305 | ||
0028425f | 306 | gpte = *(const pt_element_t *)pte; |
c7addb90 AK |
307 | if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) { |
308 | if (!offset_in_pte && !is_present_pte(gpte)) | |
309 | set_shadow_pte(spte, shadow_notrap_nonpresent_pte); | |
310 | return; | |
311 | } | |
312 | if (bytes < sizeof(pt_element_t)) | |
0028425f AK |
313 | return; |
314 | pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte); | |
fe551881 | 315 | FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0, |
97a0a01e | 316 | 0, NULL, NULL, |
0028425f AK |
317 | (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT); |
318 | } | |
319 | ||
fe551881 | 320 | static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde, |
97a0a01e AK |
321 | u64 *shadow_pte, u64 access_bits, |
322 | int user_fault, int write_fault, int *ptwrite, | |
323 | struct guest_walker *walker, gfn_t gfn) | |
6aa8b732 AK |
324 | { |
325 | gpa_t gaddr; | |
326 | ||
fe551881 | 327 | access_bits &= gpde; |
815af8d4 | 328 | gaddr = (gpa_t)gfn << PAGE_SHIFT; |
6aa8b732 | 329 | if (PTTYPE == 32 && is_cpuid_PSE36()) |
fe551881 | 330 | gaddr |= (gpde & PT32_DIR_PSE36_MASK) << |
6aa8b732 | 331 | (32 - PT32_DIR_PSE36_SHIFT); |
e60d75ea | 332 | FNAME(set_pte_common)(vcpu, shadow_pte, gaddr, |
97a0a01e AK |
333 | gpde, access_bits, user_fault, write_fault, |
334 | ptwrite, walker, gfn); | |
6aa8b732 AK |
335 | } |
336 | ||
6aa8b732 AK |
337 | /* |
338 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
339 | */ | |
340 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, | |
97a0a01e AK |
341 | struct guest_walker *walker, |
342 | int user_fault, int write_fault, int *ptwrite) | |
6aa8b732 AK |
343 | { |
344 | hpa_t shadow_addr; | |
345 | int level; | |
ef0197e8 | 346 | u64 *shadow_ent; |
6aa8b732 | 347 | u64 *prev_shadow_ent = NULL; |
ac79c978 | 348 | |
fe551881 | 349 | if (!is_present_pte(walker->pte)) |
ac79c978 | 350 | return NULL; |
6aa8b732 AK |
351 | |
352 | shadow_addr = vcpu->mmu.root_hpa; | |
353 | level = vcpu->mmu.shadow_root_level; | |
aef3d3fe AK |
354 | if (level == PT32E_ROOT_LEVEL) { |
355 | shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3]; | |
356 | shadow_addr &= PT64_BASE_ADDR_MASK; | |
357 | --level; | |
358 | } | |
6aa8b732 AK |
359 | |
360 | for (; ; level--) { | |
361 | u32 index = SHADOW_PT_INDEX(addr, level); | |
25c0de2c | 362 | struct kvm_mmu_page *shadow_page; |
8c7bb723 | 363 | u64 shadow_pte; |
cea0f0e7 AK |
364 | int metaphysical; |
365 | gfn_t table_gfn; | |
d28c6cfb | 366 | unsigned hugepage_access = 0; |
6aa8b732 | 367 | |
ef0197e8 | 368 | shadow_ent = ((u64 *)__va(shadow_addr)) + index; |
c7addb90 | 369 | if (is_shadow_present_pte(*shadow_ent)) { |
6aa8b732 | 370 | if (level == PT_PAGE_TABLE_LEVEL) |
97a0a01e | 371 | break; |
6aa8b732 AK |
372 | shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK; |
373 | prev_shadow_ent = shadow_ent; | |
374 | continue; | |
375 | } | |
376 | ||
ef0197e8 AK |
377 | if (level == PT_PAGE_TABLE_LEVEL) |
378 | break; | |
6aa8b732 | 379 | |
cea0f0e7 AK |
380 | if (level - 1 == PT_PAGE_TABLE_LEVEL |
381 | && walker->level == PT_DIRECTORY_LEVEL) { | |
382 | metaphysical = 1; | |
fe551881 | 383 | hugepage_access = walker->pte; |
d28c6cfb | 384 | hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK; |
fe551881 | 385 | if (walker->pte & PT64_NX_MASK) |
d55e2cb2 | 386 | hugepage_access |= (1 << 2); |
d28c6cfb | 387 | hugepage_access >>= PT_WRITABLE_SHIFT; |
fe551881 | 388 | table_gfn = (walker->pte & PT_BASE_ADDR_MASK) |
cea0f0e7 AK |
389 | >> PAGE_SHIFT; |
390 | } else { | |
391 | metaphysical = 0; | |
392 | table_gfn = walker->table_gfn[level - 2]; | |
393 | } | |
394 | shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1, | |
d28c6cfb AK |
395 | metaphysical, hugepage_access, |
396 | shadow_ent); | |
47ad8e68 | 397 | shadow_addr = __pa(shadow_page->spt); |
aef3d3fe AK |
398 | shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK |
399 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
8c7bb723 | 400 | *shadow_ent = shadow_pte; |
6aa8b732 AK |
401 | prev_shadow_ent = shadow_ent; |
402 | } | |
ef0197e8 AK |
403 | |
404 | if (walker->level == PT_DIRECTORY_LEVEL) { | |
fe551881 | 405 | FNAME(set_pde)(vcpu, walker->pte, shadow_ent, |
97a0a01e AK |
406 | walker->inherited_ar, user_fault, write_fault, |
407 | ptwrite, walker, walker->gfn); | |
ef0197e8 AK |
408 | } else { |
409 | ASSERT(walker->level == PT_PAGE_TABLE_LEVEL); | |
fe551881 | 410 | FNAME(set_pte)(vcpu, walker->pte, shadow_ent, |
97a0a01e AK |
411 | walker->inherited_ar, user_fault, write_fault, |
412 | ptwrite, walker, walker->gfn); | |
ef0197e8 AK |
413 | } |
414 | return shadow_ent; | |
6aa8b732 AK |
415 | } |
416 | ||
6aa8b732 AK |
417 | /* |
418 | * Page fault handler. There are several causes for a page fault: | |
419 | * - there is no shadow pte for the guest pte | |
420 | * - write access through a shadow pte marked read only so that we can set | |
421 | * the dirty bit | |
422 | * - write access to a shadow pte marked read only so we can update the page | |
423 | * dirty bitmap, when userspace requests it | |
424 | * - mmio access; in this case we will never install a present shadow pte | |
425 | * - normal guest page fault due to the guest pte marked not present, not | |
426 | * writable, or not executable | |
427 | * | |
e2dec939 AK |
428 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
429 | * a negative value on error. | |
6aa8b732 AK |
430 | */ |
431 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
432 | u32 error_code) | |
433 | { | |
434 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 | 435 | int user_fault = error_code & PFERR_USER_MASK; |
73b1087e | 436 | int fetch_fault = error_code & PFERR_FETCH_MASK; |
6aa8b732 AK |
437 | struct guest_walker walker; |
438 | u64 *shadow_pte; | |
cea0f0e7 | 439 | int write_pt = 0; |
e2dec939 | 440 | int r; |
6aa8b732 | 441 | |
cea0f0e7 | 442 | pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code); |
37a7d8b0 | 443 | kvm_mmu_audit(vcpu, "pre page fault"); |
714b93da | 444 | |
e2dec939 AK |
445 | r = mmu_topup_memory_caches(vcpu); |
446 | if (r) | |
447 | return r; | |
714b93da | 448 | |
6aa8b732 AK |
449 | /* |
450 | * Look up the shadow pte for the faulting address. | |
451 | */ | |
73b1087e AK |
452 | r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault, |
453 | fetch_fault); | |
6aa8b732 AK |
454 | |
455 | /* | |
456 | * The page is not mapped by the guest. Let the guest handle it. | |
457 | */ | |
7993ba43 AK |
458 | if (!r) { |
459 | pgprintk("%s: guest page fault\n", __FUNCTION__); | |
460 | inject_page_fault(vcpu, addr, walker.error_code); | |
a25f7e1f | 461 | vcpu->last_pt_write_count = 0; /* reset fork detector */ |
6aa8b732 AK |
462 | return 0; |
463 | } | |
464 | ||
97a0a01e AK |
465 | shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
466 | &write_pt); | |
467 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__, | |
468 | shadow_pte, *shadow_pte, write_pt); | |
cea0f0e7 | 469 | |
a25f7e1f AK |
470 | if (!write_pt) |
471 | vcpu->last_pt_write_count = 0; /* reset fork detector */ | |
472 | ||
6aa8b732 AK |
473 | /* |
474 | * mmio: emulate if accessible, otherwise its a guest fault. | |
475 | */ | |
d27d4aca | 476 | if (is_io_pte(*shadow_pte)) |
7993ba43 | 477 | return 1; |
6aa8b732 | 478 | |
1165f5fe | 479 | ++vcpu->stat.pf_fixed; |
37a7d8b0 | 480 | kvm_mmu_audit(vcpu, "post page fault (fixed)"); |
6aa8b732 | 481 | |
cea0f0e7 | 482 | return write_pt; |
6aa8b732 AK |
483 | } |
484 | ||
485 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr) | |
486 | { | |
487 | struct guest_walker walker; | |
e119d117 AK |
488 | gpa_t gpa = UNMAPPED_GVA; |
489 | int r; | |
6aa8b732 | 490 | |
e119d117 | 491 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0); |
6aa8b732 | 492 | |
e119d117 AK |
493 | if (r) { |
494 | gpa = (gpa_t)walker.gfn << PAGE_SHIFT; | |
495 | gpa |= vaddr & ~PAGE_MASK; | |
6aa8b732 AK |
496 | } |
497 | ||
498 | return gpa; | |
499 | } | |
500 | ||
c7addb90 AK |
501 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
502 | struct kvm_mmu_page *sp) | |
503 | { | |
504 | int i; | |
505 | pt_element_t *gpt; | |
506 | ||
507 | if (sp->role.metaphysical || PTTYPE == 32) { | |
508 | nonpaging_prefetch_page(vcpu, sp); | |
509 | return; | |
510 | } | |
511 | ||
512 | gpt = kmap_atomic(gfn_to_page(vcpu->kvm, sp->gfn), KM_USER0); | |
513 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
514 | if (is_present_pte(gpt[i])) | |
515 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
516 | else | |
517 | sp->spt[i] = shadow_notrap_nonpresent_pte; | |
518 | kunmap_atomic(gpt, KM_USER0); | |
519 | } | |
520 | ||
6aa8b732 AK |
521 | #undef pt_element_t |
522 | #undef guest_walker | |
523 | #undef FNAME | |
524 | #undef PT_BASE_ADDR_MASK | |
525 | #undef PT_INDEX | |
526 | #undef SHADOW_PT_INDEX | |
527 | #undef PT_LEVEL_MASK | |
6aa8b732 | 528 | #undef PT_DIR_BASE_ADDR_MASK |
c7addb90 | 529 | #undef PT_LEVEL_BITS |
cea0f0e7 | 530 | #undef PT_MAX_FULL_LEVELS |