Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
16 | ||
e495606d AK |
17 | #include "kvm_svm.h" |
18 | #include "x86_emulate.h" | |
85f455f7 | 19 | #include "irq.h" |
e495606d | 20 | |
6aa8b732 | 21 | #include <linux/module.h> |
9d8f549d | 22 | #include <linux/kernel.h> |
6aa8b732 AK |
23 | #include <linux/vmalloc.h> |
24 | #include <linux/highmem.h> | |
e8edc6e0 | 25 | #include <linux/sched.h> |
6aa8b732 | 26 | |
e495606d | 27 | #include <asm/desc.h> |
6aa8b732 AK |
28 | |
29 | MODULE_AUTHOR("Qumranet"); | |
30 | MODULE_LICENSE("GPL"); | |
31 | ||
32 | #define IOPM_ALLOC_ORDER 2 | |
33 | #define MSRPM_ALLOC_ORDER 1 | |
34 | ||
35 | #define DB_VECTOR 1 | |
36 | #define UD_VECTOR 6 | |
37 | #define GP_VECTOR 13 | |
38 | ||
39 | #define DR7_GD_MASK (1 << 13) | |
40 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
41 | |
42 | #define SEG_TYPE_LDT 2 | |
43 | #define SEG_TYPE_BUSY_TSS16 3 | |
44 | ||
45 | #define KVM_EFER_LMA (1 << 10) | |
46 | #define KVM_EFER_LME (1 << 8) | |
47 | ||
80b7706e JR |
48 | #define SVM_FEATURE_NPT (1 << 0) |
49 | #define SVM_FEATURE_LBRV (1 << 1) | |
50 | #define SVM_DEATURE_SVML (1 << 2) | |
51 | ||
04d2cc77 AK |
52 | static void kvm_reput_irq(struct vcpu_svm *svm); |
53 | ||
a2fa3e9f GH |
54 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
55 | { | |
fb3f0f51 | 56 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
57 | } |
58 | ||
6aa8b732 AK |
59 | unsigned long iopm_base; |
60 | unsigned long msrpm_base; | |
61 | ||
62 | struct kvm_ldttss_desc { | |
63 | u16 limit0; | |
64 | u16 base0; | |
65 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
66 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
67 | u32 base3; | |
68 | u32 zero1; | |
69 | } __attribute__((packed)); | |
70 | ||
71 | struct svm_cpu_data { | |
72 | int cpu; | |
73 | ||
5008fdf5 AK |
74 | u64 asid_generation; |
75 | u32 max_asid; | |
76 | u32 next_asid; | |
6aa8b732 AK |
77 | struct kvm_ldttss_desc *tss_desc; |
78 | ||
79 | struct page *save_area; | |
80 | }; | |
81 | ||
82 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 83 | static uint32_t svm_features; |
6aa8b732 AK |
84 | |
85 | struct svm_init_data { | |
86 | int cpu; | |
87 | int r; | |
88 | }; | |
89 | ||
90 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
91 | ||
9d8f549d | 92 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
93 | #define MSRS_RANGE_SIZE 2048 |
94 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
95 | ||
96 | #define MAX_INST_SIZE 15 | |
97 | ||
80b7706e JR |
98 | static inline u32 svm_has(u32 feat) |
99 | { | |
100 | return svm_features & feat; | |
101 | } | |
102 | ||
6aa8b732 AK |
103 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
104 | { | |
105 | int word_index = __ffs(vcpu->irq_summary); | |
106 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
107 | int irq = word_index * BITS_PER_LONG + bit_index; | |
108 | ||
109 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
110 | if (!vcpu->irq_pending[word_index]) | |
111 | clear_bit(word_index, &vcpu->irq_summary); | |
112 | return irq; | |
113 | } | |
114 | ||
115 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
116 | { | |
117 | set_bit(irq, vcpu->irq_pending); | |
118 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
119 | } | |
120 | ||
121 | static inline void clgi(void) | |
122 | { | |
123 | asm volatile (SVM_CLGI); | |
124 | } | |
125 | ||
126 | static inline void stgi(void) | |
127 | { | |
128 | asm volatile (SVM_STGI); | |
129 | } | |
130 | ||
131 | static inline void invlpga(unsigned long addr, u32 asid) | |
132 | { | |
133 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
134 | } | |
135 | ||
136 | static inline unsigned long kvm_read_cr2(void) | |
137 | { | |
138 | unsigned long cr2; | |
139 | ||
140 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
141 | return cr2; | |
142 | } | |
143 | ||
144 | static inline void kvm_write_cr2(unsigned long val) | |
145 | { | |
146 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
147 | } | |
148 | ||
149 | static inline unsigned long read_dr6(void) | |
150 | { | |
151 | unsigned long dr6; | |
152 | ||
153 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
154 | return dr6; | |
155 | } | |
156 | ||
157 | static inline void write_dr6(unsigned long val) | |
158 | { | |
159 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
160 | } | |
161 | ||
162 | static inline unsigned long read_dr7(void) | |
163 | { | |
164 | unsigned long dr7; | |
165 | ||
166 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
167 | return dr7; | |
168 | } | |
169 | ||
170 | static inline void write_dr7(unsigned long val) | |
171 | { | |
172 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
173 | } | |
174 | ||
6aa8b732 AK |
175 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
176 | { | |
a2fa3e9f | 177 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
178 | } |
179 | ||
180 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
181 | { | |
182 | force_new_asid(vcpu); | |
183 | } | |
184 | ||
185 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
186 | { | |
187 | if (!(efer & KVM_EFER_LMA)) | |
188 | efer &= ~KVM_EFER_LME; | |
189 | ||
a2fa3e9f | 190 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
6aa8b732 AK |
191 | vcpu->shadow_efer = efer; |
192 | } | |
193 | ||
194 | static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code) | |
195 | { | |
a2fa3e9f GH |
196 | struct vcpu_svm *svm = to_svm(vcpu); |
197 | ||
198 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
6aa8b732 AK |
199 | SVM_EVTINJ_VALID_ERR | |
200 | SVM_EVTINJ_TYPE_EXEPT | | |
201 | GP_VECTOR; | |
a2fa3e9f | 202 | svm->vmcb->control.event_inj_err = error_code; |
6aa8b732 AK |
203 | } |
204 | ||
205 | static void inject_ud(struct kvm_vcpu *vcpu) | |
206 | { | |
a2fa3e9f | 207 | to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID | |
6aa8b732 AK |
208 | SVM_EVTINJ_TYPE_EXEPT | |
209 | UD_VECTOR; | |
210 | } | |
211 | ||
6aa8b732 AK |
212 | static int is_page_fault(uint32_t info) |
213 | { | |
214 | info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
215 | return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT); | |
216 | } | |
217 | ||
218 | static int is_external_interrupt(u32 info) | |
219 | { | |
220 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
221 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
222 | } | |
223 | ||
224 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
225 | { | |
a2fa3e9f GH |
226 | struct vcpu_svm *svm = to_svm(vcpu); |
227 | ||
228 | if (!svm->next_rip) { | |
6aa8b732 AK |
229 | printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__); |
230 | return; | |
231 | } | |
3077c451 | 232 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) { |
6aa8b732 AK |
233 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
234 | __FUNCTION__, | |
a2fa3e9f GH |
235 | svm->vmcb->save.rip, |
236 | svm->next_rip); | |
6aa8b732 AK |
237 | } |
238 | ||
a2fa3e9f GH |
239 | vcpu->rip = svm->vmcb->save.rip = svm->next_rip; |
240 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
c1150d8c DL |
241 | |
242 | vcpu->interrupt_window_open = 1; | |
6aa8b732 AK |
243 | } |
244 | ||
245 | static int has_svm(void) | |
246 | { | |
247 | uint32_t eax, ebx, ecx, edx; | |
248 | ||
1e885461 | 249 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
250 | printk(KERN_INFO "has_svm: not amd\n"); |
251 | return 0; | |
252 | } | |
253 | ||
254 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
255 | if (eax < SVM_CPUID_FUNC) { | |
256 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
257 | return 0; | |
258 | } | |
259 | ||
260 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
261 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
262 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
263 | return 0; | |
264 | } | |
265 | return 1; | |
266 | } | |
267 | ||
268 | static void svm_hardware_disable(void *garbage) | |
269 | { | |
270 | struct svm_cpu_data *svm_data | |
271 | = per_cpu(svm_data, raw_smp_processor_id()); | |
272 | ||
273 | if (svm_data) { | |
274 | uint64_t efer; | |
275 | ||
276 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
277 | rdmsrl(MSR_EFER, efer); | |
278 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 279 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
280 | __free_page(svm_data->save_area); |
281 | kfree(svm_data); | |
282 | } | |
283 | } | |
284 | ||
285 | static void svm_hardware_enable(void *garbage) | |
286 | { | |
287 | ||
288 | struct svm_cpu_data *svm_data; | |
289 | uint64_t efer; | |
05b3e0c2 | 290 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
291 | struct desc_ptr gdt_descr; |
292 | #else | |
293 | struct Xgt_desc_struct gdt_descr; | |
294 | #endif | |
295 | struct desc_struct *gdt; | |
296 | int me = raw_smp_processor_id(); | |
297 | ||
298 | if (!has_svm()) { | |
299 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
300 | return; | |
301 | } | |
302 | svm_data = per_cpu(svm_data, me); | |
303 | ||
304 | if (!svm_data) { | |
305 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
306 | me); | |
307 | return; | |
308 | } | |
309 | ||
310 | svm_data->asid_generation = 1; | |
311 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
312 | svm_data->next_asid = svm_data->max_asid + 1; | |
80b7706e | 313 | svm_features = cpuid_edx(SVM_CPUID_FUNC); |
6aa8b732 AK |
314 | |
315 | asm volatile ( "sgdt %0" : "=m"(gdt_descr) ); | |
316 | gdt = (struct desc_struct *)gdt_descr.address; | |
317 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
318 | ||
319 | rdmsrl(MSR_EFER, efer); | |
320 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
321 | ||
322 | wrmsrl(MSR_VM_HSAVE_PA, | |
323 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
324 | } | |
325 | ||
326 | static int svm_cpu_init(int cpu) | |
327 | { | |
328 | struct svm_cpu_data *svm_data; | |
329 | int r; | |
330 | ||
331 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
332 | if (!svm_data) | |
333 | return -ENOMEM; | |
334 | svm_data->cpu = cpu; | |
335 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
336 | r = -ENOMEM; | |
337 | if (!svm_data->save_area) | |
338 | goto err_1; | |
339 | ||
340 | per_cpu(svm_data, cpu) = svm_data; | |
341 | ||
342 | return 0; | |
343 | ||
344 | err_1: | |
345 | kfree(svm_data); | |
346 | return r; | |
347 | ||
348 | } | |
349 | ||
bfc733a7 RR |
350 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
351 | int read, int write) | |
6aa8b732 AK |
352 | { |
353 | int i; | |
354 | ||
355 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
356 | if (msr >= msrpm_ranges[i] && | |
357 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
358 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
359 | msrpm_ranges[i]) * 2; | |
360 | ||
361 | u32 *base = msrpm + (msr_offset / 32); | |
362 | u32 msr_shift = msr_offset % 32; | |
363 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
364 | *base = (*base & ~(0x3 << msr_shift)) | | |
365 | (mask << msr_shift); | |
bfc733a7 | 366 | return; |
6aa8b732 AK |
367 | } |
368 | } | |
bfc733a7 | 369 | BUG(); |
6aa8b732 AK |
370 | } |
371 | ||
372 | static __init int svm_hardware_setup(void) | |
373 | { | |
374 | int cpu; | |
375 | struct page *iopm_pages; | |
376 | struct page *msrpm_pages; | |
c8681339 | 377 | void *iopm_va, *msrpm_va; |
6aa8b732 AK |
378 | int r; |
379 | ||
6aa8b732 AK |
380 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
381 | ||
382 | if (!iopm_pages) | |
383 | return -ENOMEM; | |
c8681339 AL |
384 | |
385 | iopm_va = page_address(iopm_pages); | |
386 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
387 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
388 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
389 | ||
390 | ||
391 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
392 | ||
393 | r = -ENOMEM; | |
394 | if (!msrpm_pages) | |
395 | goto err_1; | |
396 | ||
397 | msrpm_va = page_address(msrpm_pages); | |
398 | memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
399 | msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT; | |
400 | ||
05b3e0c2 | 401 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
402 | set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1); |
403 | set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1); | |
404 | set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1); | |
6aa8b732 AK |
405 | set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1); |
406 | set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1); | |
407 | set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1); | |
408 | #endif | |
0e859cac | 409 | set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1); |
6aa8b732 AK |
410 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1); |
411 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1); | |
412 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1); | |
413 | ||
414 | for_each_online_cpu(cpu) { | |
415 | r = svm_cpu_init(cpu); | |
416 | if (r) | |
417 | goto err_2; | |
418 | } | |
419 | return 0; | |
420 | ||
421 | err_2: | |
422 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
423 | msrpm_base = 0; | |
424 | err_1: | |
425 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
426 | iopm_base = 0; | |
427 | return r; | |
428 | } | |
429 | ||
430 | static __exit void svm_hardware_unsetup(void) | |
431 | { | |
432 | __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER); | |
433 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
434 | iopm_base = msrpm_base = 0; | |
435 | } | |
436 | ||
437 | static void init_seg(struct vmcb_seg *seg) | |
438 | { | |
439 | seg->selector = 0; | |
440 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
441 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
442 | seg->limit = 0xffff; | |
443 | seg->base = 0; | |
444 | } | |
445 | ||
446 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
447 | { | |
448 | seg->selector = 0; | |
449 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
450 | seg->limit = 0xffff; | |
451 | seg->base = 0; | |
452 | } | |
453 | ||
6aa8b732 AK |
454 | static void init_vmcb(struct vmcb *vmcb) |
455 | { | |
456 | struct vmcb_control_area *control = &vmcb->control; | |
457 | struct vmcb_save_area *save = &vmcb->save; | |
6aa8b732 AK |
458 | |
459 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
460 | INTERCEPT_CR3_MASK | | |
461 | INTERCEPT_CR4_MASK; | |
462 | ||
463 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
464 | INTERCEPT_CR3_MASK | | |
465 | INTERCEPT_CR4_MASK; | |
466 | ||
467 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
468 | INTERCEPT_DR1_MASK | | |
469 | INTERCEPT_DR2_MASK | | |
470 | INTERCEPT_DR3_MASK; | |
471 | ||
472 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
473 | INTERCEPT_DR1_MASK | | |
474 | INTERCEPT_DR2_MASK | | |
475 | INTERCEPT_DR3_MASK | | |
476 | INTERCEPT_DR5_MASK | | |
477 | INTERCEPT_DR7_MASK; | |
478 | ||
479 | control->intercept_exceptions = 1 << PF_VECTOR; | |
480 | ||
481 | ||
482 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
483 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 484 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
485 | /* |
486 | * selective cr0 intercept bug? | |
487 | * 0: 0f 22 d8 mov %eax,%cr3 | |
488 | * 3: 0f 20 c0 mov %cr0,%eax | |
489 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
490 | * b: 0f 22 c0 mov %eax,%cr0 | |
491 | * set cr3 ->interception | |
492 | * get cr0 ->interception | |
493 | * set cr0 -> no interception | |
494 | */ | |
495 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
496 | (1ULL << INTERCEPT_CPUID) | | |
497 | (1ULL << INTERCEPT_HLT) | | |
6aa8b732 AK |
498 | (1ULL << INTERCEPT_INVLPGA) | |
499 | (1ULL << INTERCEPT_IOIO_PROT) | | |
500 | (1ULL << INTERCEPT_MSR_PROT) | | |
501 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 502 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
503 | (1ULL << INTERCEPT_VMRUN) | |
504 | (1ULL << INTERCEPT_VMMCALL) | | |
505 | (1ULL << INTERCEPT_VMLOAD) | | |
506 | (1ULL << INTERCEPT_VMSAVE) | | |
507 | (1ULL << INTERCEPT_STGI) | | |
508 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 JR |
509 | (1ULL << INTERCEPT_SKINIT) | |
510 | (1ULL << INTERCEPT_MONITOR) | | |
511 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
512 | |
513 | control->iopm_base_pa = iopm_base; | |
514 | control->msrpm_base_pa = msrpm_base; | |
0cc5064d | 515 | control->tsc_offset = 0; |
6aa8b732 AK |
516 | control->int_ctl = V_INTR_MASKING_MASK; |
517 | ||
518 | init_seg(&save->es); | |
519 | init_seg(&save->ss); | |
520 | init_seg(&save->ds); | |
521 | init_seg(&save->fs); | |
522 | init_seg(&save->gs); | |
523 | ||
524 | save->cs.selector = 0xf000; | |
525 | /* Executable/Readable Code Segment */ | |
526 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
527 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
528 | save->cs.limit = 0xffff; | |
d92899a0 AK |
529 | /* |
530 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
531 | * be consistent with it. | |
532 | * | |
533 | * Replace when we have real mode working for vmx. | |
534 | */ | |
535 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
536 | |
537 | save->gdtr.limit = 0xffff; | |
538 | save->idtr.limit = 0xffff; | |
539 | ||
540 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
541 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
542 | ||
543 | save->efer = MSR_EFER_SVME_MASK; | |
544 | ||
545 | save->dr6 = 0xffff0ff0; | |
546 | save->dr7 = 0x400; | |
547 | save->rflags = 2; | |
548 | save->rip = 0x0000fff0; | |
549 | ||
550 | /* | |
551 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
552 | * cache by default. the orderly way is to enable cache in bios. | |
553 | */ | |
707d92fa | 554 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 555 | save->cr4 = X86_CR4_PAE; |
6aa8b732 AK |
556 | /* rdx = ?? */ |
557 | } | |
558 | ||
04d2cc77 AK |
559 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu) |
560 | { | |
561 | struct vcpu_svm *svm = to_svm(vcpu); | |
562 | ||
563 | init_vmcb(svm->vmcb); | |
70433389 AK |
564 | |
565 | if (vcpu->vcpu_id != 0) { | |
566 | svm->vmcb->save.rip = 0; | |
567 | svm->vmcb->save.cs.base = svm->vcpu.sipi_vector << 12; | |
568 | svm->vmcb->save.cs.selector = svm->vcpu.sipi_vector << 8; | |
569 | } | |
04d2cc77 AK |
570 | } |
571 | ||
fb3f0f51 | 572 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 573 | { |
a2fa3e9f | 574 | struct vcpu_svm *svm; |
6aa8b732 | 575 | struct page *page; |
fb3f0f51 | 576 | int err; |
6aa8b732 | 577 | |
c16f862d | 578 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
579 | if (!svm) { |
580 | err = -ENOMEM; | |
581 | goto out; | |
582 | } | |
583 | ||
584 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
585 | if (err) | |
586 | goto free_svm; | |
587 | ||
97222cc8 ED |
588 | if (irqchip_in_kernel(kvm)) { |
589 | err = kvm_create_lapic(&svm->vcpu); | |
590 | if (err < 0) | |
591 | goto free_svm; | |
592 | } | |
593 | ||
6aa8b732 | 594 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
595 | if (!page) { |
596 | err = -ENOMEM; | |
597 | goto uninit; | |
598 | } | |
6aa8b732 | 599 | |
a2fa3e9f GH |
600 | svm->vmcb = page_address(page); |
601 | clear_page(svm->vmcb); | |
602 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
603 | svm->asid_generation = 0; | |
604 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
605 | init_vmcb(svm->vmcb); | |
606 | ||
fb3f0f51 RR |
607 | fx_init(&svm->vcpu); |
608 | svm->vcpu.fpu_active = 1; | |
609 | svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; | |
610 | if (svm->vcpu.vcpu_id == 0) | |
611 | svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP; | |
6aa8b732 | 612 | |
fb3f0f51 | 613 | return &svm->vcpu; |
36241b8c | 614 | |
fb3f0f51 RR |
615 | uninit: |
616 | kvm_vcpu_uninit(&svm->vcpu); | |
617 | free_svm: | |
a4770347 | 618 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
619 | out: |
620 | return ERR_PTR(err); | |
6aa8b732 AK |
621 | } |
622 | ||
623 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
624 | { | |
a2fa3e9f GH |
625 | struct vcpu_svm *svm = to_svm(vcpu); |
626 | ||
fb3f0f51 RR |
627 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
628 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 629 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
630 | } |
631 | ||
15ad7146 | 632 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 633 | { |
a2fa3e9f | 634 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 635 | int i; |
0cc5064d | 636 | |
0cc5064d AK |
637 | if (unlikely(cpu != vcpu->cpu)) { |
638 | u64 tsc_this, delta; | |
639 | ||
640 | /* | |
641 | * Make sure that the guest sees a monotonically | |
642 | * increasing TSC. | |
643 | */ | |
644 | rdtscll(tsc_this); | |
645 | delta = vcpu->host_tsc - tsc_this; | |
a2fa3e9f | 646 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 647 | vcpu->cpu = cpu; |
a3d7f85f | 648 | kvm_migrate_apic_timer(vcpu); |
0cc5064d | 649 | } |
94dfbdb3 AL |
650 | |
651 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 652 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
653 | } |
654 | ||
655 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
656 | { | |
a2fa3e9f | 657 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
658 | int i; |
659 | ||
660 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 661 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 662 | |
0cc5064d | 663 | rdtscll(vcpu->host_tsc); |
6aa8b732 AK |
664 | } |
665 | ||
774c47f1 AK |
666 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
667 | { | |
668 | } | |
669 | ||
6aa8b732 AK |
670 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
671 | { | |
a2fa3e9f GH |
672 | struct vcpu_svm *svm = to_svm(vcpu); |
673 | ||
674 | vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
675 | vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
676 | vcpu->rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
677 | } |
678 | ||
679 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
680 | { | |
a2fa3e9f GH |
681 | struct vcpu_svm *svm = to_svm(vcpu); |
682 | svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX]; | |
683 | svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP]; | |
684 | svm->vmcb->save.rip = vcpu->rip; | |
6aa8b732 AK |
685 | } |
686 | ||
687 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
688 | { | |
a2fa3e9f | 689 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
690 | } |
691 | ||
692 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
693 | { | |
a2fa3e9f | 694 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
695 | } |
696 | ||
697 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
698 | { | |
a2fa3e9f | 699 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
700 | |
701 | switch (seg) { | |
702 | case VCPU_SREG_CS: return &save->cs; | |
703 | case VCPU_SREG_DS: return &save->ds; | |
704 | case VCPU_SREG_ES: return &save->es; | |
705 | case VCPU_SREG_FS: return &save->fs; | |
706 | case VCPU_SREG_GS: return &save->gs; | |
707 | case VCPU_SREG_SS: return &save->ss; | |
708 | case VCPU_SREG_TR: return &save->tr; | |
709 | case VCPU_SREG_LDTR: return &save->ldtr; | |
710 | } | |
711 | BUG(); | |
8b6d44c7 | 712 | return NULL; |
6aa8b732 AK |
713 | } |
714 | ||
715 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
716 | { | |
717 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
718 | ||
719 | return s->base; | |
720 | } | |
721 | ||
722 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
723 | struct kvm_segment *var, int seg) | |
724 | { | |
725 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
726 | ||
727 | var->base = s->base; | |
728 | var->limit = s->limit; | |
729 | var->selector = s->selector; | |
730 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
731 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
732 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
733 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
734 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
735 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
736 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
737 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
738 | var->unusable = !var->present; | |
739 | } | |
740 | ||
6aa8b732 AK |
741 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
742 | { | |
a2fa3e9f GH |
743 | struct vcpu_svm *svm = to_svm(vcpu); |
744 | ||
745 | dt->limit = svm->vmcb->save.idtr.limit; | |
746 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
747 | } |
748 | ||
749 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
750 | { | |
a2fa3e9f GH |
751 | struct vcpu_svm *svm = to_svm(vcpu); |
752 | ||
753 | svm->vmcb->save.idtr.limit = dt->limit; | |
754 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
755 | } |
756 | ||
757 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
758 | { | |
a2fa3e9f GH |
759 | struct vcpu_svm *svm = to_svm(vcpu); |
760 | ||
761 | dt->limit = svm->vmcb->save.gdtr.limit; | |
762 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
763 | } |
764 | ||
765 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
766 | { | |
a2fa3e9f GH |
767 | struct vcpu_svm *svm = to_svm(vcpu); |
768 | ||
769 | svm->vmcb->save.gdtr.limit = dt->limit; | |
770 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
771 | } |
772 | ||
25c4c276 | 773 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
774 | { |
775 | } | |
776 | ||
6aa8b732 AK |
777 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
778 | { | |
a2fa3e9f GH |
779 | struct vcpu_svm *svm = to_svm(vcpu); |
780 | ||
05b3e0c2 | 781 | #ifdef CONFIG_X86_64 |
6aa8b732 | 782 | if (vcpu->shadow_efer & KVM_EFER_LME) { |
707d92fa | 783 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
6aa8b732 | 784 | vcpu->shadow_efer |= KVM_EFER_LMA; |
a2fa3e9f | 785 | svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME; |
6aa8b732 AK |
786 | } |
787 | ||
707d92fa | 788 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) { |
6aa8b732 | 789 | vcpu->shadow_efer &= ~KVM_EFER_LMA; |
a2fa3e9f | 790 | svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME); |
6aa8b732 AK |
791 | } |
792 | } | |
793 | #endif | |
707d92fa | 794 | if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 795 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
796 | vcpu->fpu_active = 1; |
797 | } | |
798 | ||
6aa8b732 | 799 | vcpu->cr0 = cr0; |
707d92fa RR |
800 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
801 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 802 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
803 | } |
804 | ||
805 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
806 | { | |
807 | vcpu->cr4 = cr4; | |
a2fa3e9f | 808 | to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE; |
6aa8b732 AK |
809 | } |
810 | ||
811 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
812 | struct kvm_segment *var, int seg) | |
813 | { | |
a2fa3e9f | 814 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
815 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
816 | ||
817 | s->base = var->base; | |
818 | s->limit = var->limit; | |
819 | s->selector = var->selector; | |
820 | if (var->unusable) | |
821 | s->attrib = 0; | |
822 | else { | |
823 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
824 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
825 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
826 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
827 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
828 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
829 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
830 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
831 | } | |
832 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
833 | svm->vmcb->save.cpl |
834 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
835 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
836 | ||
837 | } | |
838 | ||
839 | /* FIXME: | |
840 | ||
a2fa3e9f GH |
841 | svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK; |
842 | svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
6aa8b732 AK |
843 | |
844 | */ | |
845 | ||
846 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
847 | { | |
848 | return -EOPNOTSUPP; | |
849 | } | |
850 | ||
2a8067f1 ED |
851 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
852 | { | |
853 | struct vcpu_svm *svm = to_svm(vcpu); | |
854 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
855 | ||
856 | if (is_external_interrupt(exit_int_info)) | |
857 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
858 | return -1; | |
859 | } | |
860 | ||
6aa8b732 AK |
861 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
862 | { | |
94dfbdb3 | 863 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 864 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 865 | #endif |
6aa8b732 AK |
866 | } |
867 | ||
868 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
869 | { | |
94dfbdb3 | 870 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 871 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 872 | #endif |
6aa8b732 AK |
873 | } |
874 | ||
e756fc62 | 875 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
876 | { |
877 | if (svm_data->next_asid > svm_data->max_asid) { | |
878 | ++svm_data->asid_generation; | |
879 | svm_data->next_asid = 1; | |
a2fa3e9f | 880 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
881 | } |
882 | ||
e756fc62 | 883 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
884 | svm->asid_generation = svm_data->asid_generation; |
885 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
886 | } |
887 | ||
6aa8b732 AK |
888 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
889 | { | |
a2fa3e9f | 890 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
891 | } |
892 | ||
893 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
894 | int *exception) | |
895 | { | |
a2fa3e9f GH |
896 | struct vcpu_svm *svm = to_svm(vcpu); |
897 | ||
6aa8b732 AK |
898 | *exception = 0; |
899 | ||
a2fa3e9f GH |
900 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
901 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
902 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
903 | *exception = DB_VECTOR; |
904 | return; | |
905 | } | |
906 | ||
907 | switch (dr) { | |
908 | case 0 ... 3: | |
a2fa3e9f | 909 | svm->db_regs[dr] = value; |
6aa8b732 AK |
910 | return; |
911 | case 4 ... 5: | |
66aee91a | 912 | if (vcpu->cr4 & X86_CR4_DE) { |
6aa8b732 AK |
913 | *exception = UD_VECTOR; |
914 | return; | |
915 | } | |
916 | case 7: { | |
917 | if (value & ~((1ULL << 32) - 1)) { | |
918 | *exception = GP_VECTOR; | |
919 | return; | |
920 | } | |
a2fa3e9f | 921 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
922 | return; |
923 | } | |
924 | default: | |
925 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
926 | __FUNCTION__, dr); | |
927 | *exception = UD_VECTOR; | |
928 | return; | |
929 | } | |
930 | } | |
931 | ||
e756fc62 | 932 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 933 | { |
a2fa3e9f | 934 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 935 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
936 | u64 fault_address; |
937 | u32 error_code; | |
938 | enum emulation_result er; | |
e2dec939 | 939 | int r; |
6aa8b732 | 940 | |
85f455f7 ED |
941 | if (!irqchip_in_kernel(kvm) && |
942 | is_external_interrupt(exit_int_info)) | |
e756fc62 | 943 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 944 | |
e756fc62 | 945 | mutex_lock(&kvm->lock); |
6aa8b732 | 946 | |
a2fa3e9f GH |
947 | fault_address = svm->vmcb->control.exit_info_2; |
948 | error_code = svm->vmcb->control.exit_info_1; | |
e756fc62 | 949 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
e2dec939 | 950 | if (r < 0) { |
e756fc62 | 951 | mutex_unlock(&kvm->lock); |
e2dec939 AK |
952 | return r; |
953 | } | |
954 | if (!r) { | |
e756fc62 | 955 | mutex_unlock(&kvm->lock); |
6aa8b732 AK |
956 | return 1; |
957 | } | |
e756fc62 RR |
958 | er = emulate_instruction(&svm->vcpu, kvm_run, fault_address, |
959 | error_code); | |
960 | mutex_unlock(&kvm->lock); | |
6aa8b732 AK |
961 | |
962 | switch (er) { | |
963 | case EMULATE_DONE: | |
964 | return 1; | |
965 | case EMULATE_DO_MMIO: | |
e756fc62 | 966 | ++svm->vcpu.stat.mmio_exits; |
6aa8b732 AK |
967 | return 0; |
968 | case EMULATE_FAIL: | |
054b1369 | 969 | kvm_report_emulation_failure(&svm->vcpu, "pagetable"); |
6aa8b732 AK |
970 | break; |
971 | default: | |
972 | BUG(); | |
973 | } | |
974 | ||
975 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
976 | return 0; | |
977 | } | |
978 | ||
e756fc62 | 979 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 980 | { |
a2fa3e9f | 981 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
e756fc62 | 982 | if (!(svm->vcpu.cr0 & X86_CR0_TS)) |
a2fa3e9f | 983 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 984 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
985 | |
986 | return 1; | |
7807fa6c AL |
987 | } |
988 | ||
e756fc62 | 989 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
990 | { |
991 | /* | |
992 | * VMCB is undefined after a SHUTDOWN intercept | |
993 | * so reinitialize it. | |
994 | */ | |
a2fa3e9f GH |
995 | clear_page(svm->vmcb); |
996 | init_vmcb(svm->vmcb); | |
46fe4ddd JR |
997 | |
998 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
999 | return 0; | |
1000 | } | |
1001 | ||
e756fc62 | 1002 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1003 | { |
a2fa3e9f | 1004 | u32 io_info = svm->vmcb->control.exit_info_1; //address size bug? |
039576c0 AK |
1005 | int size, down, in, string, rep; |
1006 | unsigned port; | |
6aa8b732 | 1007 | |
e756fc62 | 1008 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1009 | |
a2fa3e9f | 1010 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1011 | |
e70669ab LV |
1012 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1013 | ||
1014 | if (string) { | |
1015 | if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO) | |
1016 | return 0; | |
1017 | return 1; | |
1018 | } | |
1019 | ||
039576c0 AK |
1020 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1021 | port = io_info >> 16; | |
1022 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1023 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1024 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1025 | |
3090dd73 | 1026 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1027 | } |
1028 | ||
e756fc62 | 1029 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1030 | { |
1031 | return 1; | |
1032 | } | |
1033 | ||
e756fc62 | 1034 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1035 | { |
a2fa3e9f | 1036 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1037 | skip_emulated_instruction(&svm->vcpu); |
1038 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1039 | } |
1040 | ||
e756fc62 | 1041 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1042 | { |
a2fa3e9f | 1043 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 RR |
1044 | skip_emulated_instruction(&svm->vcpu); |
1045 | return kvm_hypercall(&svm->vcpu, kvm_run); | |
02e235bc AK |
1046 | } |
1047 | ||
e756fc62 RR |
1048 | static int invalid_op_interception(struct vcpu_svm *svm, |
1049 | struct kvm_run *kvm_run) | |
6aa8b732 | 1050 | { |
e756fc62 | 1051 | inject_ud(&svm->vcpu); |
6aa8b732 AK |
1052 | return 1; |
1053 | } | |
1054 | ||
e756fc62 RR |
1055 | static int task_switch_interception(struct vcpu_svm *svm, |
1056 | struct kvm_run *kvm_run) | |
6aa8b732 | 1057 | { |
f0242478 | 1058 | pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__); |
6aa8b732 AK |
1059 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
1060 | return 0; | |
1061 | } | |
1062 | ||
e756fc62 | 1063 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1064 | { |
a2fa3e9f | 1065 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1066 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1067 | return 1; |
6aa8b732 AK |
1068 | } |
1069 | ||
e756fc62 RR |
1070 | static int emulate_on_interception(struct vcpu_svm *svm, |
1071 | struct kvm_run *kvm_run) | |
6aa8b732 | 1072 | { |
e756fc62 | 1073 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0) != EMULATE_DONE) |
f0242478 | 1074 | pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__); |
6aa8b732 AK |
1075 | return 1; |
1076 | } | |
1077 | ||
1078 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) | |
1079 | { | |
a2fa3e9f GH |
1080 | struct vcpu_svm *svm = to_svm(vcpu); |
1081 | ||
6aa8b732 | 1082 | switch (ecx) { |
6aa8b732 AK |
1083 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1084 | u64 tsc; | |
1085 | ||
1086 | rdtscll(tsc); | |
a2fa3e9f | 1087 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1088 | break; |
1089 | } | |
0e859cac | 1090 | case MSR_K6_STAR: |
a2fa3e9f | 1091 | *data = svm->vmcb->save.star; |
6aa8b732 | 1092 | break; |
0e859cac | 1093 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1094 | case MSR_LSTAR: |
a2fa3e9f | 1095 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1096 | break; |
1097 | case MSR_CSTAR: | |
a2fa3e9f | 1098 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1099 | break; |
1100 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1101 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1102 | break; |
1103 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1104 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1105 | break; |
1106 | #endif | |
1107 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1108 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1109 | break; |
1110 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1111 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1112 | break; |
1113 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1114 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 AK |
1115 | break; |
1116 | default: | |
3bab1f5d | 1117 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1118 | } |
1119 | return 0; | |
1120 | } | |
1121 | ||
e756fc62 | 1122 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1123 | { |
e756fc62 | 1124 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1125 | u64 data; |
1126 | ||
e756fc62 RR |
1127 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
1128 | svm_inject_gp(&svm->vcpu, 0); | |
6aa8b732 | 1129 | else { |
a2fa3e9f | 1130 | svm->vmcb->save.rax = data & 0xffffffff; |
e756fc62 | 1131 | svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1132 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1133 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1134 | } |
1135 | return 1; | |
1136 | } | |
1137 | ||
1138 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1139 | { | |
a2fa3e9f GH |
1140 | struct vcpu_svm *svm = to_svm(vcpu); |
1141 | ||
6aa8b732 | 1142 | switch (ecx) { |
6aa8b732 AK |
1143 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1144 | u64 tsc; | |
1145 | ||
1146 | rdtscll(tsc); | |
a2fa3e9f | 1147 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1148 | break; |
1149 | } | |
0e859cac | 1150 | case MSR_K6_STAR: |
a2fa3e9f | 1151 | svm->vmcb->save.star = data; |
6aa8b732 | 1152 | break; |
49b14f24 | 1153 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1154 | case MSR_LSTAR: |
a2fa3e9f | 1155 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1156 | break; |
1157 | case MSR_CSTAR: | |
a2fa3e9f | 1158 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1159 | break; |
1160 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1161 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1162 | break; |
1163 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1164 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1165 | break; |
1166 | #endif | |
1167 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1168 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1169 | break; |
1170 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1171 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1172 | break; |
1173 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1174 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 AK |
1175 | break; |
1176 | default: | |
3bab1f5d | 1177 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1178 | } |
1179 | return 0; | |
1180 | } | |
1181 | ||
e756fc62 | 1182 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1183 | { |
e756fc62 | 1184 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1185 | u64 data = (svm->vmcb->save.rax & -1u) |
e756fc62 | 1186 | | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1187 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 RR |
1188 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
1189 | svm_inject_gp(&svm->vcpu, 0); | |
6aa8b732 | 1190 | else |
e756fc62 | 1191 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1192 | return 1; |
1193 | } | |
1194 | ||
e756fc62 | 1195 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1196 | { |
e756fc62 RR |
1197 | if (svm->vmcb->control.exit_info_1) |
1198 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1199 | else |
e756fc62 | 1200 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1201 | } |
1202 | ||
e756fc62 | 1203 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1204 | struct kvm_run *kvm_run) |
1205 | { | |
85f455f7 ED |
1206 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1207 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1208 | /* |
1209 | * If the user space waits to inject interrupts, exit as soon as | |
1210 | * possible | |
1211 | */ | |
1212 | if (kvm_run->request_interrupt_window && | |
e756fc62 RR |
1213 | !svm->vcpu.irq_summary) { |
1214 | ++svm->vcpu.stat.irq_window_exits; | |
c1150d8c DL |
1215 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | return 1; | |
1220 | } | |
1221 | ||
e756fc62 | 1222 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1223 | struct kvm_run *kvm_run) = { |
1224 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1225 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1226 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
1227 | /* for now: */ | |
1228 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1229 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1230 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1231 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
1232 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1233 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1234 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1235 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1236 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1237 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1238 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1239 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1240 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
1241 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, | |
7807fa6c | 1242 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1243 | [SVM_EXIT_INTR] = nop_on_interception, |
1244 | [SVM_EXIT_NMI] = nop_on_interception, | |
1245 | [SVM_EXIT_SMI] = nop_on_interception, | |
1246 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1247 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1248 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1249 | [SVM_EXIT_CPUID] = cpuid_interception, | |
1250 | [SVM_EXIT_HLT] = halt_interception, | |
1251 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1252 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1253 | [SVM_EXIT_IOIO] = io_interception, | |
1254 | [SVM_EXIT_MSR] = msr_interception, | |
1255 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1256 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1257 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1258 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1259 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1260 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1261 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1262 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1263 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
916ce236 JR |
1264 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1265 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
6aa8b732 AK |
1266 | }; |
1267 | ||
1268 | ||
04d2cc77 | 1269 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1270 | { |
04d2cc77 | 1271 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1272 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1273 | |
04d2cc77 AK |
1274 | kvm_reput_irq(svm); |
1275 | ||
1276 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1277 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1278 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1279 | = svm->vmcb->control.exit_code; | |
1280 | return 0; | |
1281 | } | |
1282 | ||
a2fa3e9f | 1283 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
6aa8b732 AK |
1284 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR) |
1285 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " | |
1286 | "exit_code 0x%x\n", | |
a2fa3e9f | 1287 | __FUNCTION__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1288 | exit_code); |
1289 | ||
9d8f549d | 1290 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
6aa8b732 AK |
1291 | || svm_exit_handlers[exit_code] == 0) { |
1292 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
364b625b | 1293 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1294 | return 0; |
1295 | } | |
1296 | ||
e756fc62 | 1297 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1298 | } |
1299 | ||
1300 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1301 | { | |
1302 | int cpu = raw_smp_processor_id(); | |
1303 | ||
1304 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1305 | svm_data->tss_desc->type = 9; //available 32/64-bit TSS | |
1306 | load_TR_desc(); | |
1307 | } | |
1308 | ||
e756fc62 | 1309 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1310 | { |
1311 | int cpu = raw_smp_processor_id(); | |
1312 | ||
1313 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1314 | ||
a2fa3e9f | 1315 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1316 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1317 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1318 | new_asid(svm, svm_data); |
6aa8b732 AK |
1319 | } |
1320 | ||
1321 | ||
85f455f7 | 1322 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1323 | { |
1324 | struct vmcb_control_area *control; | |
1325 | ||
e756fc62 | 1326 | control = &svm->vmcb->control; |
85f455f7 | 1327 | control->int_vector = irq; |
6aa8b732 AK |
1328 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1329 | control->int_ctl |= V_IRQ_MASK | | |
1330 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1331 | } | |
1332 | ||
2a8067f1 ED |
1333 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1334 | { | |
1335 | struct vcpu_svm *svm = to_svm(vcpu); | |
1336 | ||
1337 | svm_inject_irq(svm, irq); | |
1338 | } | |
1339 | ||
04d2cc77 | 1340 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1341 | { |
04d2cc77 | 1342 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1343 | struct vmcb *vmcb = svm->vmcb; |
1344 | int intr_vector = -1; | |
1345 | ||
1b9778da | 1346 | kvm_inject_pending_timer_irqs(vcpu); |
85f455f7 ED |
1347 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && |
1348 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1349 | intr_vector = vmcb->control.exit_int_info & | |
1350 | SVM_EVTINJ_VEC_MASK; | |
1351 | vmcb->control.exit_int_info = 0; | |
1352 | svm_inject_irq(svm, intr_vector); | |
1353 | return; | |
1354 | } | |
1355 | ||
1356 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
1357 | return; | |
1358 | ||
1b9778da | 1359 | if (!kvm_cpu_has_interrupt(vcpu)) |
85f455f7 ED |
1360 | return; |
1361 | ||
1362 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1363 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1364 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1365 | /* unable to deliver irq, set pending irq */ | |
1366 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1367 | svm_inject_irq(svm, 0x0); | |
1368 | return; | |
1369 | } | |
1370 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1371 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1372 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1373 | kvm_timer_intr_post(vcpu, intr_vector); |
85f455f7 ED |
1374 | } |
1375 | ||
1376 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1377 | { | |
e756fc62 | 1378 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1379 | |
7017fc3d ED |
1380 | if ((control->int_ctl & V_IRQ_MASK) |
1381 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1382 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1383 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1384 | } |
c1150d8c | 1385 | |
e756fc62 | 1386 | svm->vcpu.interrupt_window_open = |
c1150d8c DL |
1387 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1388 | } | |
1389 | ||
85f455f7 ED |
1390 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1391 | { | |
1392 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
1393 | int word_index = __ffs(vcpu->irq_summary); | |
1394 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
1395 | int irq = word_index * BITS_PER_LONG + bit_index; | |
1396 | ||
1397 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
1398 | if (!vcpu->irq_pending[word_index]) | |
1399 | clear_bit(word_index, &vcpu->irq_summary); | |
1400 | svm_inject_irq(svm, irq); | |
1401 | } | |
1402 | ||
04d2cc77 | 1403 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1404 | struct kvm_run *kvm_run) |
1405 | { | |
04d2cc77 | 1406 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1407 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1408 | |
e756fc62 | 1409 | svm->vcpu.interrupt_window_open = |
c1150d8c | 1410 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1411 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1412 | |
e756fc62 | 1413 | if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary) |
c1150d8c DL |
1414 | /* |
1415 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1416 | */ | |
85f455f7 | 1417 | svm_do_inject_vector(svm); |
c1150d8c DL |
1418 | |
1419 | /* | |
1420 | * Interrupts blocked. Wait for unblock. | |
1421 | */ | |
e756fc62 RR |
1422 | if (!svm->vcpu.interrupt_window_open && |
1423 | (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) { | |
c1150d8c DL |
1424 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
1425 | } else | |
1426 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); | |
1427 | } | |
1428 | ||
6aa8b732 AK |
1429 | static void save_db_regs(unsigned long *db_regs) |
1430 | { | |
5aff458e AK |
1431 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1432 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1433 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1434 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1435 | } |
1436 | ||
1437 | static void load_db_regs(unsigned long *db_regs) | |
1438 | { | |
5aff458e AK |
1439 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1440 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1441 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1442 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1443 | } |
1444 | ||
d9e368d6 AK |
1445 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1446 | { | |
1447 | force_new_asid(vcpu); | |
1448 | } | |
1449 | ||
04d2cc77 AK |
1450 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1451 | { | |
1452 | } | |
1453 | ||
1454 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
6aa8b732 | 1455 | { |
a2fa3e9f | 1456 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1457 | u16 fs_selector; |
1458 | u16 gs_selector; | |
1459 | u16 ldt_selector; | |
d9e368d6 | 1460 | |
e756fc62 | 1461 | pre_svm_run(svm); |
6aa8b732 AK |
1462 | |
1463 | save_host_msrs(vcpu); | |
1464 | fs_selector = read_fs(); | |
1465 | gs_selector = read_gs(); | |
1466 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1467 | svm->host_cr2 = kvm_read_cr2(); |
1468 | svm->host_dr6 = read_dr6(); | |
1469 | svm->host_dr7 = read_dr7(); | |
1470 | svm->vmcb->save.cr2 = vcpu->cr2; | |
6aa8b732 | 1471 | |
a2fa3e9f | 1472 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1473 | write_dr7(0); |
a2fa3e9f GH |
1474 | save_db_regs(svm->host_db_regs); |
1475 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1476 | } |
36241b8c | 1477 | |
04d2cc77 AK |
1478 | clgi(); |
1479 | ||
1480 | local_irq_enable(); | |
36241b8c | 1481 | |
6aa8b732 | 1482 | asm volatile ( |
05b3e0c2 | 1483 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1484 | "push %%rbx; push %%rcx; push %%rdx;" |
1485 | "push %%rsi; push %%rdi; push %%rbp;" | |
1486 | "push %%r8; push %%r9; push %%r10; push %%r11;" | |
1487 | "push %%r12; push %%r13; push %%r14; push %%r15;" | |
1488 | #else | |
1489 | "push %%ebx; push %%ecx; push %%edx;" | |
1490 | "push %%esi; push %%edi; push %%ebp;" | |
1491 | #endif | |
1492 | ||
05b3e0c2 | 1493 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1494 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1495 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1496 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1497 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1498 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1499 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1500 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1501 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1502 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1503 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1504 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1505 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1506 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1507 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1508 | #else |
fb3f0f51 RR |
1509 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1510 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1511 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1512 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1513 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1514 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1515 | #endif |
1516 | ||
05b3e0c2 | 1517 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1518 | /* Enter guest mode */ |
1519 | "push %%rax \n\t" | |
fb3f0f51 | 1520 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1521 | SVM_VMLOAD "\n\t" |
1522 | SVM_VMRUN "\n\t" | |
1523 | SVM_VMSAVE "\n\t" | |
1524 | "pop %%rax \n\t" | |
1525 | #else | |
1526 | /* Enter guest mode */ | |
1527 | "push %%eax \n\t" | |
fb3f0f51 | 1528 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1529 | SVM_VMLOAD "\n\t" |
1530 | SVM_VMRUN "\n\t" | |
1531 | SVM_VMSAVE "\n\t" | |
1532 | "pop %%eax \n\t" | |
1533 | #endif | |
1534 | ||
1535 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1536 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1537 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1538 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1539 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1540 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1541 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1542 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1543 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1544 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1545 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1546 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1547 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1548 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1549 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1550 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 AK |
1551 | |
1552 | "pop %%r15; pop %%r14; pop %%r13; pop %%r12;" | |
1553 | "pop %%r11; pop %%r10; pop %%r9; pop %%r8;" | |
1554 | "pop %%rbp; pop %%rdi; pop %%rsi;" | |
1555 | "pop %%rdx; pop %%rcx; pop %%rbx; \n\t" | |
1556 | #else | |
fb3f0f51 RR |
1557 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1558 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1559 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1560 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1561 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1562 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 AK |
1563 | |
1564 | "pop %%ebp; pop %%edi; pop %%esi;" | |
1565 | "pop %%edx; pop %%ecx; pop %%ebx; \n\t" | |
1566 | #endif | |
1567 | : | |
fb3f0f51 | 1568 | : [svm]"a"(svm), |
6aa8b732 | 1569 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
fb3f0f51 RR |
1570 | [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])), |
1571 | [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])), | |
1572 | [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])), | |
1573 | [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])), | |
1574 | [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])), | |
1575 | [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1576 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1577 | ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])), |
1578 | [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])), | |
1579 | [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])), | |
1580 | [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])), | |
1581 | [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])), | |
1582 | [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])), | |
1583 | [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])), | |
1584 | [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15])) | |
6aa8b732 AK |
1585 | #endif |
1586 | : "cc", "memory" ); | |
1587 | ||
04d2cc77 | 1588 | local_irq_disable(); |
d9e368d6 | 1589 | |
04d2cc77 | 1590 | stgi(); |
36241b8c | 1591 | |
a2fa3e9f GH |
1592 | if ((svm->vmcb->save.dr7 & 0xff)) |
1593 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1594 | |
a2fa3e9f | 1595 | vcpu->cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1596 | |
a2fa3e9f GH |
1597 | write_dr6(svm->host_dr6); |
1598 | write_dr7(svm->host_dr7); | |
1599 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1600 | |
1601 | load_fs(fs_selector); | |
1602 | load_gs(gs_selector); | |
1603 | load_ldt(ldt_selector); | |
1604 | load_host_msrs(vcpu); | |
1605 | ||
1606 | reload_tss(vcpu); | |
1607 | ||
a2fa3e9f | 1608 | svm->next_rip = 0; |
6aa8b732 AK |
1609 | } |
1610 | ||
6aa8b732 AK |
1611 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1612 | { | |
a2fa3e9f GH |
1613 | struct vcpu_svm *svm = to_svm(vcpu); |
1614 | ||
1615 | svm->vmcb->save.cr3 = root; | |
6aa8b732 | 1616 | force_new_asid(vcpu); |
7807fa6c AL |
1617 | |
1618 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1619 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1620 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1621 | vcpu->fpu_active = 0; |
1622 | } | |
6aa8b732 AK |
1623 | } |
1624 | ||
1625 | static void svm_inject_page_fault(struct kvm_vcpu *vcpu, | |
1626 | unsigned long addr, | |
1627 | uint32_t err_code) | |
1628 | { | |
a2fa3e9f GH |
1629 | struct vcpu_svm *svm = to_svm(vcpu); |
1630 | uint32_t exit_int_info = svm->vmcb->control.exit_int_info; | |
6aa8b732 | 1631 | |
1165f5fe | 1632 | ++vcpu->stat.pf_guest; |
6aa8b732 AK |
1633 | |
1634 | if (is_page_fault(exit_int_info)) { | |
1635 | ||
a2fa3e9f GH |
1636 | svm->vmcb->control.event_inj_err = 0; |
1637 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1638 | SVM_EVTINJ_VALID_ERR | | |
1639 | SVM_EVTINJ_TYPE_EXEPT | | |
1640 | DF_VECTOR; | |
6aa8b732 AK |
1641 | return; |
1642 | } | |
1643 | vcpu->cr2 = addr; | |
a2fa3e9f GH |
1644 | svm->vmcb->save.cr2 = addr; |
1645 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1646 | SVM_EVTINJ_VALID_ERR | | |
1647 | SVM_EVTINJ_TYPE_EXEPT | | |
1648 | PF_VECTOR; | |
1649 | svm->vmcb->control.event_inj_err = err_code; | |
6aa8b732 AK |
1650 | } |
1651 | ||
1652 | ||
1653 | static int is_disabled(void) | |
1654 | { | |
6031a61c JR |
1655 | u64 vm_cr; |
1656 | ||
1657 | rdmsrl(MSR_VM_CR, vm_cr); | |
1658 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1659 | return 1; | |
1660 | ||
6aa8b732 AK |
1661 | return 0; |
1662 | } | |
1663 | ||
102d8325 IM |
1664 | static void |
1665 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1666 | { | |
1667 | /* | |
1668 | * Patch in the VMMCALL instruction: | |
1669 | */ | |
1670 | hypercall[0] = 0x0f; | |
1671 | hypercall[1] = 0x01; | |
1672 | hypercall[2] = 0xd9; | |
1673 | hypercall[3] = 0xc3; | |
1674 | } | |
1675 | ||
002c7f7c YS |
1676 | static void svm_check_processor_compat(void *rtn) |
1677 | { | |
1678 | *(int *)rtn = 0; | |
1679 | } | |
1680 | ||
cbdd1bea | 1681 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1682 | .cpu_has_kvm_support = has_svm, |
1683 | .disabled_by_bios = is_disabled, | |
1684 | .hardware_setup = svm_hardware_setup, | |
1685 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1686 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1687 | .hardware_enable = svm_hardware_enable, |
1688 | .hardware_disable = svm_hardware_disable, | |
1689 | ||
1690 | .vcpu_create = svm_create_vcpu, | |
1691 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1692 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1693 | |
04d2cc77 | 1694 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1695 | .vcpu_load = svm_vcpu_load, |
1696 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1697 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1698 | |
1699 | .set_guest_debug = svm_guest_debug, | |
1700 | .get_msr = svm_get_msr, | |
1701 | .set_msr = svm_set_msr, | |
1702 | .get_segment_base = svm_get_segment_base, | |
1703 | .get_segment = svm_get_segment, | |
1704 | .set_segment = svm_set_segment, | |
1747fb71 | 1705 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1706 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1707 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1708 | .set_cr3 = svm_set_cr3, |
1709 | .set_cr4 = svm_set_cr4, | |
1710 | .set_efer = svm_set_efer, | |
1711 | .get_idt = svm_get_idt, | |
1712 | .set_idt = svm_set_idt, | |
1713 | .get_gdt = svm_get_gdt, | |
1714 | .set_gdt = svm_set_gdt, | |
1715 | .get_dr = svm_get_dr, | |
1716 | .set_dr = svm_set_dr, | |
1717 | .cache_regs = svm_cache_regs, | |
1718 | .decache_regs = svm_decache_regs, | |
1719 | .get_rflags = svm_get_rflags, | |
1720 | .set_rflags = svm_set_rflags, | |
1721 | ||
6aa8b732 AK |
1722 | .tlb_flush = svm_flush_tlb, |
1723 | .inject_page_fault = svm_inject_page_fault, | |
1724 | ||
1725 | .inject_gp = svm_inject_gp, | |
1726 | ||
1727 | .run = svm_vcpu_run, | |
04d2cc77 | 1728 | .handle_exit = handle_exit, |
6aa8b732 | 1729 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1730 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1731 | .get_irq = svm_get_irq, |
1732 | .set_irq = svm_set_irq, | |
04d2cc77 AK |
1733 | .inject_pending_irq = svm_intr_assist, |
1734 | .inject_pending_vectors = do_interrupt_requests, | |
6aa8b732 AK |
1735 | }; |
1736 | ||
1737 | static int __init svm_init(void) | |
1738 | { | |
cbdd1bea | 1739 | return kvm_init_x86(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 1740 | THIS_MODULE); |
6aa8b732 AK |
1741 | } |
1742 | ||
1743 | static void __exit svm_exit(void) | |
1744 | { | |
cbdd1bea | 1745 | kvm_exit_x86(); |
6aa8b732 AK |
1746 | } |
1747 | ||
1748 | module_init(svm_init) | |
1749 | module_exit(svm_exit) |