Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
16 | ||
e495606d AK |
17 | #include "kvm_svm.h" |
18 | #include "x86_emulate.h" | |
19 | ||
6aa8b732 | 20 | #include <linux/module.h> |
9d8f549d | 21 | #include <linux/kernel.h> |
6aa8b732 AK |
22 | #include <linux/vmalloc.h> |
23 | #include <linux/highmem.h> | |
07031e14 | 24 | #include <linux/profile.h> |
e8edc6e0 | 25 | #include <linux/sched.h> |
6aa8b732 | 26 | |
e495606d | 27 | #include <asm/desc.h> |
6aa8b732 AK |
28 | |
29 | MODULE_AUTHOR("Qumranet"); | |
30 | MODULE_LICENSE("GPL"); | |
31 | ||
32 | #define IOPM_ALLOC_ORDER 2 | |
33 | #define MSRPM_ALLOC_ORDER 1 | |
34 | ||
35 | #define DB_VECTOR 1 | |
36 | #define UD_VECTOR 6 | |
37 | #define GP_VECTOR 13 | |
38 | ||
39 | #define DR7_GD_MASK (1 << 13) | |
40 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
41 | |
42 | #define SEG_TYPE_LDT 2 | |
43 | #define SEG_TYPE_BUSY_TSS16 3 | |
44 | ||
45 | #define KVM_EFER_LMA (1 << 10) | |
46 | #define KVM_EFER_LME (1 << 8) | |
47 | ||
80b7706e JR |
48 | #define SVM_FEATURE_NPT (1 << 0) |
49 | #define SVM_FEATURE_LBRV (1 << 1) | |
50 | #define SVM_DEATURE_SVML (1 << 2) | |
51 | ||
a2fa3e9f GH |
52 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
53 | { | |
fb3f0f51 | 54 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
55 | } |
56 | ||
6aa8b732 AK |
57 | unsigned long iopm_base; |
58 | unsigned long msrpm_base; | |
59 | ||
60 | struct kvm_ldttss_desc { | |
61 | u16 limit0; | |
62 | u16 base0; | |
63 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
64 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
65 | u32 base3; | |
66 | u32 zero1; | |
67 | } __attribute__((packed)); | |
68 | ||
69 | struct svm_cpu_data { | |
70 | int cpu; | |
71 | ||
5008fdf5 AK |
72 | u64 asid_generation; |
73 | u32 max_asid; | |
74 | u32 next_asid; | |
6aa8b732 AK |
75 | struct kvm_ldttss_desc *tss_desc; |
76 | ||
77 | struct page *save_area; | |
78 | }; | |
79 | ||
80 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 81 | static uint32_t svm_features; |
6aa8b732 AK |
82 | |
83 | struct svm_init_data { | |
84 | int cpu; | |
85 | int r; | |
86 | }; | |
87 | ||
88 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
89 | ||
9d8f549d | 90 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
91 | #define MSRS_RANGE_SIZE 2048 |
92 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
93 | ||
94 | #define MAX_INST_SIZE 15 | |
95 | ||
80b7706e JR |
96 | static inline u32 svm_has(u32 feat) |
97 | { | |
98 | return svm_features & feat; | |
99 | } | |
100 | ||
e756fc62 | 101 | static unsigned get_addr_size(struct vcpu_svm *svm) |
6aa8b732 | 102 | { |
e756fc62 | 103 | struct vmcb_save_area *sa = &svm->vmcb->save; |
6aa8b732 AK |
104 | u16 cs_attrib; |
105 | ||
707d92fa | 106 | if (!(sa->cr0 & X86_CR0_PE) || (sa->rflags & X86_EFLAGS_VM)) |
6aa8b732 AK |
107 | return 2; |
108 | ||
109 | cs_attrib = sa->cs.attrib; | |
110 | ||
111 | return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 : | |
112 | (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2; | |
113 | } | |
114 | ||
115 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) | |
116 | { | |
117 | int word_index = __ffs(vcpu->irq_summary); | |
118 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
119 | int irq = word_index * BITS_PER_LONG + bit_index; | |
120 | ||
121 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
122 | if (!vcpu->irq_pending[word_index]) | |
123 | clear_bit(word_index, &vcpu->irq_summary); | |
124 | return irq; | |
125 | } | |
126 | ||
127 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
128 | { | |
129 | set_bit(irq, vcpu->irq_pending); | |
130 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
131 | } | |
132 | ||
133 | static inline void clgi(void) | |
134 | { | |
135 | asm volatile (SVM_CLGI); | |
136 | } | |
137 | ||
138 | static inline void stgi(void) | |
139 | { | |
140 | asm volatile (SVM_STGI); | |
141 | } | |
142 | ||
143 | static inline void invlpga(unsigned long addr, u32 asid) | |
144 | { | |
145 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
146 | } | |
147 | ||
148 | static inline unsigned long kvm_read_cr2(void) | |
149 | { | |
150 | unsigned long cr2; | |
151 | ||
152 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
153 | return cr2; | |
154 | } | |
155 | ||
156 | static inline void kvm_write_cr2(unsigned long val) | |
157 | { | |
158 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
159 | } | |
160 | ||
161 | static inline unsigned long read_dr6(void) | |
162 | { | |
163 | unsigned long dr6; | |
164 | ||
165 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
166 | return dr6; | |
167 | } | |
168 | ||
169 | static inline void write_dr6(unsigned long val) | |
170 | { | |
171 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
172 | } | |
173 | ||
174 | static inline unsigned long read_dr7(void) | |
175 | { | |
176 | unsigned long dr7; | |
177 | ||
178 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
179 | return dr7; | |
180 | } | |
181 | ||
182 | static inline void write_dr7(unsigned long val) | |
183 | { | |
184 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
185 | } | |
186 | ||
6aa8b732 AK |
187 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
188 | { | |
a2fa3e9f | 189 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
190 | } |
191 | ||
192 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
193 | { | |
194 | force_new_asid(vcpu); | |
195 | } | |
196 | ||
197 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
198 | { | |
199 | if (!(efer & KVM_EFER_LMA)) | |
200 | efer &= ~KVM_EFER_LME; | |
201 | ||
a2fa3e9f | 202 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
6aa8b732 AK |
203 | vcpu->shadow_efer = efer; |
204 | } | |
205 | ||
206 | static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code) | |
207 | { | |
a2fa3e9f GH |
208 | struct vcpu_svm *svm = to_svm(vcpu); |
209 | ||
210 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
6aa8b732 AK |
211 | SVM_EVTINJ_VALID_ERR | |
212 | SVM_EVTINJ_TYPE_EXEPT | | |
213 | GP_VECTOR; | |
a2fa3e9f | 214 | svm->vmcb->control.event_inj_err = error_code; |
6aa8b732 AK |
215 | } |
216 | ||
217 | static void inject_ud(struct kvm_vcpu *vcpu) | |
218 | { | |
a2fa3e9f | 219 | to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID | |
6aa8b732 AK |
220 | SVM_EVTINJ_TYPE_EXEPT | |
221 | UD_VECTOR; | |
222 | } | |
223 | ||
6aa8b732 AK |
224 | static int is_page_fault(uint32_t info) |
225 | { | |
226 | info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
227 | return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT); | |
228 | } | |
229 | ||
230 | static int is_external_interrupt(u32 info) | |
231 | { | |
232 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
233 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
234 | } | |
235 | ||
236 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
237 | { | |
a2fa3e9f GH |
238 | struct vcpu_svm *svm = to_svm(vcpu); |
239 | ||
240 | if (!svm->next_rip) { | |
6aa8b732 AK |
241 | printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__); |
242 | return; | |
243 | } | |
3077c451 | 244 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) { |
6aa8b732 AK |
245 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
246 | __FUNCTION__, | |
a2fa3e9f GH |
247 | svm->vmcb->save.rip, |
248 | svm->next_rip); | |
6aa8b732 AK |
249 | } |
250 | ||
a2fa3e9f GH |
251 | vcpu->rip = svm->vmcb->save.rip = svm->next_rip; |
252 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
c1150d8c DL |
253 | |
254 | vcpu->interrupt_window_open = 1; | |
6aa8b732 AK |
255 | } |
256 | ||
257 | static int has_svm(void) | |
258 | { | |
259 | uint32_t eax, ebx, ecx, edx; | |
260 | ||
1e885461 | 261 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
262 | printk(KERN_INFO "has_svm: not amd\n"); |
263 | return 0; | |
264 | } | |
265 | ||
266 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
267 | if (eax < SVM_CPUID_FUNC) { | |
268 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
269 | return 0; | |
270 | } | |
271 | ||
272 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
273 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
274 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
275 | return 0; | |
276 | } | |
277 | return 1; | |
278 | } | |
279 | ||
280 | static void svm_hardware_disable(void *garbage) | |
281 | { | |
282 | struct svm_cpu_data *svm_data | |
283 | = per_cpu(svm_data, raw_smp_processor_id()); | |
284 | ||
285 | if (svm_data) { | |
286 | uint64_t efer; | |
287 | ||
288 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
289 | rdmsrl(MSR_EFER, efer); | |
290 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 291 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
292 | __free_page(svm_data->save_area); |
293 | kfree(svm_data); | |
294 | } | |
295 | } | |
296 | ||
297 | static void svm_hardware_enable(void *garbage) | |
298 | { | |
299 | ||
300 | struct svm_cpu_data *svm_data; | |
301 | uint64_t efer; | |
05b3e0c2 | 302 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
303 | struct desc_ptr gdt_descr; |
304 | #else | |
305 | struct Xgt_desc_struct gdt_descr; | |
306 | #endif | |
307 | struct desc_struct *gdt; | |
308 | int me = raw_smp_processor_id(); | |
309 | ||
310 | if (!has_svm()) { | |
311 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
312 | return; | |
313 | } | |
314 | svm_data = per_cpu(svm_data, me); | |
315 | ||
316 | if (!svm_data) { | |
317 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
318 | me); | |
319 | return; | |
320 | } | |
321 | ||
322 | svm_data->asid_generation = 1; | |
323 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
324 | svm_data->next_asid = svm_data->max_asid + 1; | |
80b7706e | 325 | svm_features = cpuid_edx(SVM_CPUID_FUNC); |
6aa8b732 AK |
326 | |
327 | asm volatile ( "sgdt %0" : "=m"(gdt_descr) ); | |
328 | gdt = (struct desc_struct *)gdt_descr.address; | |
329 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
330 | ||
331 | rdmsrl(MSR_EFER, efer); | |
332 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
333 | ||
334 | wrmsrl(MSR_VM_HSAVE_PA, | |
335 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
336 | } | |
337 | ||
338 | static int svm_cpu_init(int cpu) | |
339 | { | |
340 | struct svm_cpu_data *svm_data; | |
341 | int r; | |
342 | ||
343 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
344 | if (!svm_data) | |
345 | return -ENOMEM; | |
346 | svm_data->cpu = cpu; | |
347 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
348 | r = -ENOMEM; | |
349 | if (!svm_data->save_area) | |
350 | goto err_1; | |
351 | ||
352 | per_cpu(svm_data, cpu) = svm_data; | |
353 | ||
354 | return 0; | |
355 | ||
356 | err_1: | |
357 | kfree(svm_data); | |
358 | return r; | |
359 | ||
360 | } | |
361 | ||
bfc733a7 RR |
362 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
363 | int read, int write) | |
6aa8b732 AK |
364 | { |
365 | int i; | |
366 | ||
367 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
368 | if (msr >= msrpm_ranges[i] && | |
369 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
370 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
371 | msrpm_ranges[i]) * 2; | |
372 | ||
373 | u32 *base = msrpm + (msr_offset / 32); | |
374 | u32 msr_shift = msr_offset % 32; | |
375 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
376 | *base = (*base & ~(0x3 << msr_shift)) | | |
377 | (mask << msr_shift); | |
bfc733a7 | 378 | return; |
6aa8b732 AK |
379 | } |
380 | } | |
bfc733a7 | 381 | BUG(); |
6aa8b732 AK |
382 | } |
383 | ||
384 | static __init int svm_hardware_setup(void) | |
385 | { | |
386 | int cpu; | |
387 | struct page *iopm_pages; | |
388 | struct page *msrpm_pages; | |
c8681339 | 389 | void *iopm_va, *msrpm_va; |
6aa8b732 AK |
390 | int r; |
391 | ||
873a7c42 | 392 | kvm_emulator_want_group7_invlpg(); |
6aa8b732 AK |
393 | |
394 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); | |
395 | ||
396 | if (!iopm_pages) | |
397 | return -ENOMEM; | |
c8681339 AL |
398 | |
399 | iopm_va = page_address(iopm_pages); | |
400 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
401 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
402 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
403 | ||
404 | ||
405 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
406 | ||
407 | r = -ENOMEM; | |
408 | if (!msrpm_pages) | |
409 | goto err_1; | |
410 | ||
411 | msrpm_va = page_address(msrpm_pages); | |
412 | memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
413 | msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT; | |
414 | ||
05b3e0c2 | 415 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
416 | set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1); |
417 | set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1); | |
418 | set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1); | |
6aa8b732 AK |
419 | set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1); |
420 | set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1); | |
421 | set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1); | |
422 | #endif | |
0e859cac | 423 | set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1); |
6aa8b732 AK |
424 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1); |
425 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1); | |
426 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1); | |
427 | ||
428 | for_each_online_cpu(cpu) { | |
429 | r = svm_cpu_init(cpu); | |
430 | if (r) | |
431 | goto err_2; | |
432 | } | |
433 | return 0; | |
434 | ||
435 | err_2: | |
436 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
437 | msrpm_base = 0; | |
438 | err_1: | |
439 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
440 | iopm_base = 0; | |
441 | return r; | |
442 | } | |
443 | ||
444 | static __exit void svm_hardware_unsetup(void) | |
445 | { | |
446 | __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER); | |
447 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
448 | iopm_base = msrpm_base = 0; | |
449 | } | |
450 | ||
451 | static void init_seg(struct vmcb_seg *seg) | |
452 | { | |
453 | seg->selector = 0; | |
454 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
455 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
456 | seg->limit = 0xffff; | |
457 | seg->base = 0; | |
458 | } | |
459 | ||
460 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
461 | { | |
462 | seg->selector = 0; | |
463 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
464 | seg->limit = 0xffff; | |
465 | seg->base = 0; | |
466 | } | |
467 | ||
6aa8b732 AK |
468 | static void init_vmcb(struct vmcb *vmcb) |
469 | { | |
470 | struct vmcb_control_area *control = &vmcb->control; | |
471 | struct vmcb_save_area *save = &vmcb->save; | |
6aa8b732 AK |
472 | |
473 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
474 | INTERCEPT_CR3_MASK | | |
475 | INTERCEPT_CR4_MASK; | |
476 | ||
477 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
478 | INTERCEPT_CR3_MASK | | |
479 | INTERCEPT_CR4_MASK; | |
480 | ||
481 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
482 | INTERCEPT_DR1_MASK | | |
483 | INTERCEPT_DR2_MASK | | |
484 | INTERCEPT_DR3_MASK; | |
485 | ||
486 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
487 | INTERCEPT_DR1_MASK | | |
488 | INTERCEPT_DR2_MASK | | |
489 | INTERCEPT_DR3_MASK | | |
490 | INTERCEPT_DR5_MASK | | |
491 | INTERCEPT_DR7_MASK; | |
492 | ||
493 | control->intercept_exceptions = 1 << PF_VECTOR; | |
494 | ||
495 | ||
496 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
497 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 498 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
499 | /* |
500 | * selective cr0 intercept bug? | |
501 | * 0: 0f 22 d8 mov %eax,%cr3 | |
502 | * 3: 0f 20 c0 mov %cr0,%eax | |
503 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
504 | * b: 0f 22 c0 mov %eax,%cr0 | |
505 | * set cr3 ->interception | |
506 | * get cr0 ->interception | |
507 | * set cr0 -> no interception | |
508 | */ | |
509 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
510 | (1ULL << INTERCEPT_CPUID) | | |
511 | (1ULL << INTERCEPT_HLT) | | |
6aa8b732 AK |
512 | (1ULL << INTERCEPT_INVLPGA) | |
513 | (1ULL << INTERCEPT_IOIO_PROT) | | |
514 | (1ULL << INTERCEPT_MSR_PROT) | | |
515 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 516 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
517 | (1ULL << INTERCEPT_VMRUN) | |
518 | (1ULL << INTERCEPT_VMMCALL) | | |
519 | (1ULL << INTERCEPT_VMLOAD) | | |
520 | (1ULL << INTERCEPT_VMSAVE) | | |
521 | (1ULL << INTERCEPT_STGI) | | |
522 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 JR |
523 | (1ULL << INTERCEPT_SKINIT) | |
524 | (1ULL << INTERCEPT_MONITOR) | | |
525 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
526 | |
527 | control->iopm_base_pa = iopm_base; | |
528 | control->msrpm_base_pa = msrpm_base; | |
0cc5064d | 529 | control->tsc_offset = 0; |
6aa8b732 AK |
530 | control->int_ctl = V_INTR_MASKING_MASK; |
531 | ||
532 | init_seg(&save->es); | |
533 | init_seg(&save->ss); | |
534 | init_seg(&save->ds); | |
535 | init_seg(&save->fs); | |
536 | init_seg(&save->gs); | |
537 | ||
538 | save->cs.selector = 0xf000; | |
539 | /* Executable/Readable Code Segment */ | |
540 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
541 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
542 | save->cs.limit = 0xffff; | |
d92899a0 AK |
543 | /* |
544 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
545 | * be consistent with it. | |
546 | * | |
547 | * Replace when we have real mode working for vmx. | |
548 | */ | |
549 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
550 | |
551 | save->gdtr.limit = 0xffff; | |
552 | save->idtr.limit = 0xffff; | |
553 | ||
554 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
555 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
556 | ||
557 | save->efer = MSR_EFER_SVME_MASK; | |
558 | ||
559 | save->dr6 = 0xffff0ff0; | |
560 | save->dr7 = 0x400; | |
561 | save->rflags = 2; | |
562 | save->rip = 0x0000fff0; | |
563 | ||
564 | /* | |
565 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
566 | * cache by default. the orderly way is to enable cache in bios. | |
567 | */ | |
707d92fa | 568 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 569 | save->cr4 = X86_CR4_PAE; |
6aa8b732 AK |
570 | /* rdx = ?? */ |
571 | } | |
572 | ||
fb3f0f51 | 573 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 574 | { |
a2fa3e9f | 575 | struct vcpu_svm *svm; |
6aa8b732 | 576 | struct page *page; |
fb3f0f51 | 577 | int err; |
6aa8b732 | 578 | |
c16f862d | 579 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
580 | if (!svm) { |
581 | err = -ENOMEM; | |
582 | goto out; | |
583 | } | |
584 | ||
585 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
586 | if (err) | |
587 | goto free_svm; | |
588 | ||
6aa8b732 | 589 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
590 | if (!page) { |
591 | err = -ENOMEM; | |
592 | goto uninit; | |
593 | } | |
6aa8b732 | 594 | |
a2fa3e9f GH |
595 | svm->vmcb = page_address(page); |
596 | clear_page(svm->vmcb); | |
597 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
598 | svm->asid_generation = 0; | |
599 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
600 | init_vmcb(svm->vmcb); | |
601 | ||
fb3f0f51 RR |
602 | fx_init(&svm->vcpu); |
603 | svm->vcpu.fpu_active = 1; | |
604 | svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; | |
605 | if (svm->vcpu.vcpu_id == 0) | |
606 | svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP; | |
6aa8b732 | 607 | |
fb3f0f51 | 608 | return &svm->vcpu; |
36241b8c | 609 | |
fb3f0f51 RR |
610 | uninit: |
611 | kvm_vcpu_uninit(&svm->vcpu); | |
612 | free_svm: | |
a4770347 | 613 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
614 | out: |
615 | return ERR_PTR(err); | |
6aa8b732 AK |
616 | } |
617 | ||
618 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
619 | { | |
a2fa3e9f GH |
620 | struct vcpu_svm *svm = to_svm(vcpu); |
621 | ||
fb3f0f51 RR |
622 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
623 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 624 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
625 | } |
626 | ||
15ad7146 | 627 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 628 | { |
a2fa3e9f | 629 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 630 | int i; |
0cc5064d | 631 | |
0cc5064d AK |
632 | if (unlikely(cpu != vcpu->cpu)) { |
633 | u64 tsc_this, delta; | |
634 | ||
635 | /* | |
636 | * Make sure that the guest sees a monotonically | |
637 | * increasing TSC. | |
638 | */ | |
639 | rdtscll(tsc_this); | |
640 | delta = vcpu->host_tsc - tsc_this; | |
a2fa3e9f | 641 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d AK |
642 | vcpu->cpu = cpu; |
643 | } | |
94dfbdb3 AL |
644 | |
645 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 646 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
647 | } |
648 | ||
649 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
650 | { | |
a2fa3e9f | 651 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
652 | int i; |
653 | ||
654 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 655 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 656 | |
0cc5064d | 657 | rdtscll(vcpu->host_tsc); |
6aa8b732 AK |
658 | } |
659 | ||
774c47f1 AK |
660 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
661 | { | |
662 | } | |
663 | ||
6aa8b732 AK |
664 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
665 | { | |
a2fa3e9f GH |
666 | struct vcpu_svm *svm = to_svm(vcpu); |
667 | ||
668 | vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
669 | vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
670 | vcpu->rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
671 | } |
672 | ||
673 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
674 | { | |
a2fa3e9f GH |
675 | struct vcpu_svm *svm = to_svm(vcpu); |
676 | svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX]; | |
677 | svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP]; | |
678 | svm->vmcb->save.rip = vcpu->rip; | |
6aa8b732 AK |
679 | } |
680 | ||
681 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
682 | { | |
a2fa3e9f | 683 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
684 | } |
685 | ||
686 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
687 | { | |
a2fa3e9f | 688 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
689 | } |
690 | ||
691 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
692 | { | |
a2fa3e9f | 693 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
694 | |
695 | switch (seg) { | |
696 | case VCPU_SREG_CS: return &save->cs; | |
697 | case VCPU_SREG_DS: return &save->ds; | |
698 | case VCPU_SREG_ES: return &save->es; | |
699 | case VCPU_SREG_FS: return &save->fs; | |
700 | case VCPU_SREG_GS: return &save->gs; | |
701 | case VCPU_SREG_SS: return &save->ss; | |
702 | case VCPU_SREG_TR: return &save->tr; | |
703 | case VCPU_SREG_LDTR: return &save->ldtr; | |
704 | } | |
705 | BUG(); | |
8b6d44c7 | 706 | return NULL; |
6aa8b732 AK |
707 | } |
708 | ||
709 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
710 | { | |
711 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
712 | ||
713 | return s->base; | |
714 | } | |
715 | ||
716 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
717 | struct kvm_segment *var, int seg) | |
718 | { | |
719 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
720 | ||
721 | var->base = s->base; | |
722 | var->limit = s->limit; | |
723 | var->selector = s->selector; | |
724 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
725 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
726 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
727 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
728 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
729 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
730 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
731 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
732 | var->unusable = !var->present; | |
733 | } | |
734 | ||
735 | static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
736 | { | |
737 | struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS); | |
738 | ||
739 | *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
740 | *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
741 | } | |
742 | ||
743 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
744 | { | |
a2fa3e9f GH |
745 | struct vcpu_svm *svm = to_svm(vcpu); |
746 | ||
747 | dt->limit = svm->vmcb->save.idtr.limit; | |
748 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
749 | } |
750 | ||
751 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
752 | { | |
a2fa3e9f GH |
753 | struct vcpu_svm *svm = to_svm(vcpu); |
754 | ||
755 | svm->vmcb->save.idtr.limit = dt->limit; | |
756 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
757 | } |
758 | ||
759 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
760 | { | |
a2fa3e9f GH |
761 | struct vcpu_svm *svm = to_svm(vcpu); |
762 | ||
763 | dt->limit = svm->vmcb->save.gdtr.limit; | |
764 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
765 | } |
766 | ||
767 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
768 | { | |
a2fa3e9f GH |
769 | struct vcpu_svm *svm = to_svm(vcpu); |
770 | ||
771 | svm->vmcb->save.gdtr.limit = dt->limit; | |
772 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
773 | } |
774 | ||
25c4c276 | 775 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
776 | { |
777 | } | |
778 | ||
6aa8b732 AK |
779 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
780 | { | |
a2fa3e9f GH |
781 | struct vcpu_svm *svm = to_svm(vcpu); |
782 | ||
05b3e0c2 | 783 | #ifdef CONFIG_X86_64 |
6aa8b732 | 784 | if (vcpu->shadow_efer & KVM_EFER_LME) { |
707d92fa | 785 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
6aa8b732 | 786 | vcpu->shadow_efer |= KVM_EFER_LMA; |
a2fa3e9f | 787 | svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME; |
6aa8b732 AK |
788 | } |
789 | ||
707d92fa | 790 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) { |
6aa8b732 | 791 | vcpu->shadow_efer &= ~KVM_EFER_LMA; |
a2fa3e9f | 792 | svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME); |
6aa8b732 AK |
793 | } |
794 | } | |
795 | #endif | |
707d92fa | 796 | if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 797 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
798 | vcpu->fpu_active = 1; |
799 | } | |
800 | ||
6aa8b732 | 801 | vcpu->cr0 = cr0; |
707d92fa RR |
802 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
803 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 804 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
805 | } |
806 | ||
807 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
808 | { | |
809 | vcpu->cr4 = cr4; | |
a2fa3e9f | 810 | to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE; |
6aa8b732 AK |
811 | } |
812 | ||
813 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
814 | struct kvm_segment *var, int seg) | |
815 | { | |
a2fa3e9f | 816 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
817 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
818 | ||
819 | s->base = var->base; | |
820 | s->limit = var->limit; | |
821 | s->selector = var->selector; | |
822 | if (var->unusable) | |
823 | s->attrib = 0; | |
824 | else { | |
825 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
826 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
827 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
828 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
829 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
830 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
831 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
832 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
833 | } | |
834 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
835 | svm->vmcb->save.cpl |
836 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
837 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
838 | ||
839 | } | |
840 | ||
841 | /* FIXME: | |
842 | ||
a2fa3e9f GH |
843 | svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK; |
844 | svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
6aa8b732 AK |
845 | |
846 | */ | |
847 | ||
848 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
849 | { | |
850 | return -EOPNOTSUPP; | |
851 | } | |
852 | ||
853 | static void load_host_msrs(struct kvm_vcpu *vcpu) | |
854 | { | |
94dfbdb3 | 855 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 856 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 857 | #endif |
6aa8b732 AK |
858 | } |
859 | ||
860 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
861 | { | |
94dfbdb3 | 862 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 863 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 864 | #endif |
6aa8b732 AK |
865 | } |
866 | ||
e756fc62 | 867 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
868 | { |
869 | if (svm_data->next_asid > svm_data->max_asid) { | |
870 | ++svm_data->asid_generation; | |
871 | svm_data->next_asid = 1; | |
a2fa3e9f | 872 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
873 | } |
874 | ||
e756fc62 | 875 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
876 | svm->asid_generation = svm_data->asid_generation; |
877 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
878 | } |
879 | ||
880 | static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
881 | { | |
a2fa3e9f | 882 | invlpga(address, to_svm(vcpu)->vmcb->control.asid); // is needed? |
6aa8b732 AK |
883 | } |
884 | ||
885 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) | |
886 | { | |
a2fa3e9f | 887 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
888 | } |
889 | ||
890 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
891 | int *exception) | |
892 | { | |
a2fa3e9f GH |
893 | struct vcpu_svm *svm = to_svm(vcpu); |
894 | ||
6aa8b732 AK |
895 | *exception = 0; |
896 | ||
a2fa3e9f GH |
897 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
898 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
899 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
900 | *exception = DB_VECTOR; |
901 | return; | |
902 | } | |
903 | ||
904 | switch (dr) { | |
905 | case 0 ... 3: | |
a2fa3e9f | 906 | svm->db_regs[dr] = value; |
6aa8b732 AK |
907 | return; |
908 | case 4 ... 5: | |
66aee91a | 909 | if (vcpu->cr4 & X86_CR4_DE) { |
6aa8b732 AK |
910 | *exception = UD_VECTOR; |
911 | return; | |
912 | } | |
913 | case 7: { | |
914 | if (value & ~((1ULL << 32) - 1)) { | |
915 | *exception = GP_VECTOR; | |
916 | return; | |
917 | } | |
a2fa3e9f | 918 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
919 | return; |
920 | } | |
921 | default: | |
922 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
923 | __FUNCTION__, dr); | |
924 | *exception = UD_VECTOR; | |
925 | return; | |
926 | } | |
927 | } | |
928 | ||
e756fc62 | 929 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 930 | { |
a2fa3e9f | 931 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 932 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
933 | u64 fault_address; |
934 | u32 error_code; | |
935 | enum emulation_result er; | |
e2dec939 | 936 | int r; |
6aa8b732 AK |
937 | |
938 | if (is_external_interrupt(exit_int_info)) | |
e756fc62 | 939 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 940 | |
e756fc62 | 941 | mutex_lock(&kvm->lock); |
6aa8b732 | 942 | |
a2fa3e9f GH |
943 | fault_address = svm->vmcb->control.exit_info_2; |
944 | error_code = svm->vmcb->control.exit_info_1; | |
e756fc62 | 945 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
e2dec939 | 946 | if (r < 0) { |
e756fc62 | 947 | mutex_unlock(&kvm->lock); |
e2dec939 AK |
948 | return r; |
949 | } | |
950 | if (!r) { | |
e756fc62 | 951 | mutex_unlock(&kvm->lock); |
6aa8b732 AK |
952 | return 1; |
953 | } | |
e756fc62 RR |
954 | er = emulate_instruction(&svm->vcpu, kvm_run, fault_address, |
955 | error_code); | |
956 | mutex_unlock(&kvm->lock); | |
6aa8b732 AK |
957 | |
958 | switch (er) { | |
959 | case EMULATE_DONE: | |
960 | return 1; | |
961 | case EMULATE_DO_MMIO: | |
e756fc62 | 962 | ++svm->vcpu.stat.mmio_exits; |
6aa8b732 AK |
963 | return 0; |
964 | case EMULATE_FAIL: | |
e756fc62 | 965 | vcpu_printf(&svm->vcpu, "%s: emulate fail\n", __FUNCTION__); |
6aa8b732 AK |
966 | break; |
967 | default: | |
968 | BUG(); | |
969 | } | |
970 | ||
971 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
972 | return 0; | |
973 | } | |
974 | ||
e756fc62 | 975 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 976 | { |
a2fa3e9f | 977 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
e756fc62 | 978 | if (!(svm->vcpu.cr0 & X86_CR0_TS)) |
a2fa3e9f | 979 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 980 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
981 | |
982 | return 1; | |
7807fa6c AL |
983 | } |
984 | ||
e756fc62 | 985 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
986 | { |
987 | /* | |
988 | * VMCB is undefined after a SHUTDOWN intercept | |
989 | * so reinitialize it. | |
990 | */ | |
a2fa3e9f GH |
991 | clear_page(svm->vmcb); |
992 | init_vmcb(svm->vmcb); | |
46fe4ddd JR |
993 | |
994 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
995 | return 0; | |
996 | } | |
997 | ||
e756fc62 | 998 | static int io_get_override(struct vcpu_svm *svm, |
6aa8b732 AK |
999 | struct vmcb_seg **seg, |
1000 | int *addr_override) | |
1001 | { | |
1002 | u8 inst[MAX_INST_SIZE]; | |
1003 | unsigned ins_length; | |
1004 | gva_t rip; | |
1005 | int i; | |
1006 | ||
a2fa3e9f GH |
1007 | rip = svm->vmcb->save.rip; |
1008 | ins_length = svm->next_rip - rip; | |
1009 | rip += svm->vmcb->save.cs.base; | |
6aa8b732 AK |
1010 | |
1011 | if (ins_length > MAX_INST_SIZE) | |
1012 | printk(KERN_DEBUG | |
1013 | "%s: inst length err, cs base 0x%llx rip 0x%llx " | |
1014 | "next rip 0x%llx ins_length %u\n", | |
1015 | __FUNCTION__, | |
a2fa3e9f GH |
1016 | svm->vmcb->save.cs.base, |
1017 | svm->vmcb->save.rip, | |
1018 | svm->vmcb->control.exit_info_2, | |
6aa8b732 AK |
1019 | ins_length); |
1020 | ||
e7d5d76c LV |
1021 | if (emulator_read_std(rip, inst, ins_length, &svm->vcpu) |
1022 | != X86EMUL_CONTINUE) | |
6aa8b732 AK |
1023 | /* #PF */ |
1024 | return 0; | |
1025 | ||
1026 | *addr_override = 0; | |
8b6d44c7 | 1027 | *seg = NULL; |
6aa8b732 AK |
1028 | for (i = 0; i < ins_length; i++) |
1029 | switch (inst[i]) { | |
1030 | case 0xf0: | |
1031 | case 0xf2: | |
1032 | case 0xf3: | |
1033 | case 0x66: | |
1034 | continue; | |
1035 | case 0x67: | |
1036 | *addr_override = 1; | |
1037 | continue; | |
1038 | case 0x2e: | |
a2fa3e9f | 1039 | *seg = &svm->vmcb->save.cs; |
6aa8b732 AK |
1040 | continue; |
1041 | case 0x36: | |
a2fa3e9f | 1042 | *seg = &svm->vmcb->save.ss; |
6aa8b732 AK |
1043 | continue; |
1044 | case 0x3e: | |
a2fa3e9f | 1045 | *seg = &svm->vmcb->save.ds; |
6aa8b732 AK |
1046 | continue; |
1047 | case 0x26: | |
a2fa3e9f | 1048 | *seg = &svm->vmcb->save.es; |
6aa8b732 AK |
1049 | continue; |
1050 | case 0x64: | |
a2fa3e9f | 1051 | *seg = &svm->vmcb->save.fs; |
6aa8b732 AK |
1052 | continue; |
1053 | case 0x65: | |
a2fa3e9f | 1054 | *seg = &svm->vmcb->save.gs; |
6aa8b732 AK |
1055 | continue; |
1056 | default: | |
1057 | return 1; | |
1058 | } | |
1059 | printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__); | |
1060 | return 0; | |
1061 | } | |
1062 | ||
0e5017d4 | 1063 | static unsigned long io_address(struct vcpu_svm *svm, int ins, gva_t *address) |
6aa8b732 AK |
1064 | { |
1065 | unsigned long addr_mask; | |
1066 | unsigned long *reg; | |
1067 | struct vmcb_seg *seg; | |
1068 | int addr_override; | |
a2fa3e9f | 1069 | struct vmcb_save_area *save_area = &svm->vmcb->save; |
6aa8b732 | 1070 | u16 cs_attrib = save_area->cs.attrib; |
e756fc62 | 1071 | unsigned addr_size = get_addr_size(svm); |
6aa8b732 | 1072 | |
e756fc62 | 1073 | if (!io_get_override(svm, &seg, &addr_override)) |
6aa8b732 AK |
1074 | return 0; |
1075 | ||
1076 | if (addr_override) | |
1077 | addr_size = (addr_size == 2) ? 4: (addr_size >> 1); | |
1078 | ||
1079 | if (ins) { | |
e756fc62 | 1080 | reg = &svm->vcpu.regs[VCPU_REGS_RDI]; |
a2fa3e9f | 1081 | seg = &svm->vmcb->save.es; |
6aa8b732 | 1082 | } else { |
e756fc62 | 1083 | reg = &svm->vcpu.regs[VCPU_REGS_RSI]; |
a2fa3e9f | 1084 | seg = (seg) ? seg : &svm->vmcb->save.ds; |
6aa8b732 AK |
1085 | } |
1086 | ||
1087 | addr_mask = ~0ULL >> (64 - (addr_size * 8)); | |
1088 | ||
1089 | if ((cs_attrib & SVM_SELECTOR_L_MASK) && | |
a2fa3e9f | 1090 | !(svm->vmcb->save.rflags & X86_EFLAGS_VM)) { |
6aa8b732 AK |
1091 | *address = (*reg & addr_mask); |
1092 | return addr_mask; | |
1093 | } | |
1094 | ||
1095 | if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) { | |
e756fc62 | 1096 | svm_inject_gp(&svm->vcpu, 0); |
6aa8b732 AK |
1097 | return 0; |
1098 | } | |
1099 | ||
1100 | *address = (*reg & addr_mask) + seg->base; | |
1101 | return addr_mask; | |
1102 | } | |
1103 | ||
e756fc62 | 1104 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1105 | { |
a2fa3e9f | 1106 | u32 io_info = svm->vmcb->control.exit_info_1; //address size bug? |
039576c0 AK |
1107 | int size, down, in, string, rep; |
1108 | unsigned port; | |
1109 | unsigned long count; | |
1110 | gva_t address = 0; | |
6aa8b732 | 1111 | |
e756fc62 | 1112 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1113 | |
a2fa3e9f | 1114 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1115 | |
039576c0 AK |
1116 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1117 | port = io_info >> 16; | |
1118 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
1119 | string = (io_info & SVM_IOIO_STR_MASK) != 0; | |
1120 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; | |
1121 | count = 1; | |
a2fa3e9f | 1122 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1123 | |
039576c0 | 1124 | if (string) { |
6aa8b732 AK |
1125 | unsigned addr_mask; |
1126 | ||
0e5017d4 | 1127 | addr_mask = io_address(svm, in, &address); |
6aa8b732 | 1128 | if (!addr_mask) { |
d27d4aca AK |
1129 | printk(KERN_DEBUG "%s: get io address failed\n", |
1130 | __FUNCTION__); | |
6aa8b732 AK |
1131 | return 1; |
1132 | } | |
1133 | ||
039576c0 | 1134 | if (rep) |
e756fc62 | 1135 | count = svm->vcpu.regs[VCPU_REGS_RCX] & addr_mask; |
039576c0 | 1136 | } |
e756fc62 RR |
1137 | return kvm_setup_pio(&svm->vcpu, kvm_run, in, size, count, string, |
1138 | down, address, rep, port); | |
6aa8b732 AK |
1139 | } |
1140 | ||
e756fc62 | 1141 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1142 | { |
1143 | return 1; | |
1144 | } | |
1145 | ||
e756fc62 | 1146 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1147 | { |
a2fa3e9f | 1148 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1149 | skip_emulated_instruction(&svm->vcpu); |
1150 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1151 | } |
1152 | ||
e756fc62 | 1153 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1154 | { |
a2fa3e9f | 1155 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 RR |
1156 | skip_emulated_instruction(&svm->vcpu); |
1157 | return kvm_hypercall(&svm->vcpu, kvm_run); | |
02e235bc AK |
1158 | } |
1159 | ||
e756fc62 RR |
1160 | static int invalid_op_interception(struct vcpu_svm *svm, |
1161 | struct kvm_run *kvm_run) | |
6aa8b732 | 1162 | { |
e756fc62 | 1163 | inject_ud(&svm->vcpu); |
6aa8b732 AK |
1164 | return 1; |
1165 | } | |
1166 | ||
e756fc62 RR |
1167 | static int task_switch_interception(struct vcpu_svm *svm, |
1168 | struct kvm_run *kvm_run) | |
6aa8b732 | 1169 | { |
f0242478 | 1170 | pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__); |
6aa8b732 AK |
1171 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
1172 | return 0; | |
1173 | } | |
1174 | ||
e756fc62 | 1175 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1176 | { |
a2fa3e9f | 1177 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1178 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1179 | return 1; |
6aa8b732 AK |
1180 | } |
1181 | ||
e756fc62 RR |
1182 | static int emulate_on_interception(struct vcpu_svm *svm, |
1183 | struct kvm_run *kvm_run) | |
6aa8b732 | 1184 | { |
e756fc62 | 1185 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0) != EMULATE_DONE) |
f0242478 | 1186 | pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__); |
6aa8b732 AK |
1187 | return 1; |
1188 | } | |
1189 | ||
1190 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) | |
1191 | { | |
a2fa3e9f GH |
1192 | struct vcpu_svm *svm = to_svm(vcpu); |
1193 | ||
6aa8b732 | 1194 | switch (ecx) { |
6aa8b732 AK |
1195 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1196 | u64 tsc; | |
1197 | ||
1198 | rdtscll(tsc); | |
a2fa3e9f | 1199 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1200 | break; |
1201 | } | |
0e859cac | 1202 | case MSR_K6_STAR: |
a2fa3e9f | 1203 | *data = svm->vmcb->save.star; |
6aa8b732 | 1204 | break; |
0e859cac | 1205 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1206 | case MSR_LSTAR: |
a2fa3e9f | 1207 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1208 | break; |
1209 | case MSR_CSTAR: | |
a2fa3e9f | 1210 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1211 | break; |
1212 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1213 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1214 | break; |
1215 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1216 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1217 | break; |
1218 | #endif | |
1219 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1220 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1221 | break; |
1222 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1223 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1224 | break; |
1225 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1226 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 AK |
1227 | break; |
1228 | default: | |
3bab1f5d | 1229 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1230 | } |
1231 | return 0; | |
1232 | } | |
1233 | ||
e756fc62 | 1234 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1235 | { |
e756fc62 | 1236 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1237 | u64 data; |
1238 | ||
e756fc62 RR |
1239 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
1240 | svm_inject_gp(&svm->vcpu, 0); | |
6aa8b732 | 1241 | else { |
a2fa3e9f | 1242 | svm->vmcb->save.rax = data & 0xffffffff; |
e756fc62 | 1243 | svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1244 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1245 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1246 | } |
1247 | return 1; | |
1248 | } | |
1249 | ||
1250 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1251 | { | |
a2fa3e9f GH |
1252 | struct vcpu_svm *svm = to_svm(vcpu); |
1253 | ||
6aa8b732 | 1254 | switch (ecx) { |
6aa8b732 AK |
1255 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1256 | u64 tsc; | |
1257 | ||
1258 | rdtscll(tsc); | |
a2fa3e9f | 1259 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1260 | break; |
1261 | } | |
0e859cac | 1262 | case MSR_K6_STAR: |
a2fa3e9f | 1263 | svm->vmcb->save.star = data; |
6aa8b732 | 1264 | break; |
49b14f24 | 1265 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1266 | case MSR_LSTAR: |
a2fa3e9f | 1267 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1268 | break; |
1269 | case MSR_CSTAR: | |
a2fa3e9f | 1270 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1271 | break; |
1272 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1273 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1274 | break; |
1275 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1276 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1277 | break; |
1278 | #endif | |
1279 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1280 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1281 | break; |
1282 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1283 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1284 | break; |
1285 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1286 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 AK |
1287 | break; |
1288 | default: | |
3bab1f5d | 1289 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1290 | } |
1291 | return 0; | |
1292 | } | |
1293 | ||
e756fc62 | 1294 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1295 | { |
e756fc62 | 1296 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1297 | u64 data = (svm->vmcb->save.rax & -1u) |
e756fc62 | 1298 | | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1299 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 RR |
1300 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
1301 | svm_inject_gp(&svm->vcpu, 0); | |
6aa8b732 | 1302 | else |
e756fc62 | 1303 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1304 | return 1; |
1305 | } | |
1306 | ||
e756fc62 | 1307 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1308 | { |
e756fc62 RR |
1309 | if (svm->vmcb->control.exit_info_1) |
1310 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1311 | else |
e756fc62 | 1312 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1313 | } |
1314 | ||
e756fc62 | 1315 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1316 | struct kvm_run *kvm_run) |
1317 | { | |
1318 | /* | |
1319 | * If the user space waits to inject interrupts, exit as soon as | |
1320 | * possible | |
1321 | */ | |
1322 | if (kvm_run->request_interrupt_window && | |
e756fc62 RR |
1323 | !svm->vcpu.irq_summary) { |
1324 | ++svm->vcpu.stat.irq_window_exits; | |
c1150d8c DL |
1325 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | return 1; | |
1330 | } | |
1331 | ||
e756fc62 | 1332 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1333 | struct kvm_run *kvm_run) = { |
1334 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1335 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1336 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
1337 | /* for now: */ | |
1338 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1339 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1340 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1341 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
1342 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1343 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1344 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1345 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1346 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1347 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1348 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1349 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1350 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
1351 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, | |
7807fa6c | 1352 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1353 | [SVM_EXIT_INTR] = nop_on_interception, |
1354 | [SVM_EXIT_NMI] = nop_on_interception, | |
1355 | [SVM_EXIT_SMI] = nop_on_interception, | |
1356 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1357 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1358 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1359 | [SVM_EXIT_CPUID] = cpuid_interception, | |
1360 | [SVM_EXIT_HLT] = halt_interception, | |
1361 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1362 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1363 | [SVM_EXIT_IOIO] = io_interception, | |
1364 | [SVM_EXIT_MSR] = msr_interception, | |
1365 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1366 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1367 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1368 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1369 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1370 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1371 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1372 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1373 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
916ce236 JR |
1374 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1375 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
6aa8b732 AK |
1376 | }; |
1377 | ||
1378 | ||
e756fc62 | 1379 | static int handle_exit(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1380 | { |
a2fa3e9f | 1381 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1382 | |
a2fa3e9f | 1383 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
6aa8b732 AK |
1384 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR) |
1385 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " | |
1386 | "exit_code 0x%x\n", | |
a2fa3e9f | 1387 | __FUNCTION__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1388 | exit_code); |
1389 | ||
9d8f549d | 1390 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
6aa8b732 AK |
1391 | || svm_exit_handlers[exit_code] == 0) { |
1392 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
364b625b | 1393 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1394 | return 0; |
1395 | } | |
1396 | ||
e756fc62 | 1397 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1398 | } |
1399 | ||
1400 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1401 | { | |
1402 | int cpu = raw_smp_processor_id(); | |
1403 | ||
1404 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1405 | svm_data->tss_desc->type = 9; //available 32/64-bit TSS | |
1406 | load_TR_desc(); | |
1407 | } | |
1408 | ||
e756fc62 | 1409 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1410 | { |
1411 | int cpu = raw_smp_processor_id(); | |
1412 | ||
1413 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1414 | ||
a2fa3e9f | 1415 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1416 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1417 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1418 | new_asid(svm, svm_data); |
6aa8b732 AK |
1419 | } |
1420 | ||
1421 | ||
0e5017d4 | 1422 | static inline void inject_irq(struct vcpu_svm *svm) |
6aa8b732 AK |
1423 | { |
1424 | struct vmcb_control_area *control; | |
1425 | ||
e756fc62 RR |
1426 | control = &svm->vmcb->control; |
1427 | control->int_vector = pop_irq(&svm->vcpu); | |
6aa8b732 AK |
1428 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1429 | control->int_ctl |= V_IRQ_MASK | | |
1430 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1431 | } | |
1432 | ||
0e5017d4 | 1433 | static void reput_irq(struct vcpu_svm *svm) |
6aa8b732 | 1434 | { |
e756fc62 | 1435 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 AK |
1436 | |
1437 | if (control->int_ctl & V_IRQ_MASK) { | |
1438 | control->int_ctl &= ~V_IRQ_MASK; | |
e756fc62 | 1439 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1440 | } |
c1150d8c | 1441 | |
e756fc62 | 1442 | svm->vcpu.interrupt_window_open = |
c1150d8c DL |
1443 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1444 | } | |
1445 | ||
e756fc62 | 1446 | static void do_interrupt_requests(struct vcpu_svm *svm, |
c1150d8c DL |
1447 | struct kvm_run *kvm_run) |
1448 | { | |
a2fa3e9f | 1449 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1450 | |
e756fc62 | 1451 | svm->vcpu.interrupt_window_open = |
c1150d8c | 1452 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1453 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1454 | |
e756fc62 | 1455 | if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary) |
c1150d8c DL |
1456 | /* |
1457 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1458 | */ | |
0e5017d4 | 1459 | inject_irq(svm); |
c1150d8c DL |
1460 | |
1461 | /* | |
1462 | * Interrupts blocked. Wait for unblock. | |
1463 | */ | |
e756fc62 RR |
1464 | if (!svm->vcpu.interrupt_window_open && |
1465 | (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) { | |
c1150d8c DL |
1466 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
1467 | } else | |
1468 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); | |
1469 | } | |
1470 | ||
e756fc62 | 1471 | static void post_kvm_run_save(struct vcpu_svm *svm, |
c1150d8c DL |
1472 | struct kvm_run *kvm_run) |
1473 | { | |
e756fc62 RR |
1474 | kvm_run->ready_for_interrupt_injection |
1475 | = (svm->vcpu.interrupt_window_open && | |
1476 | svm->vcpu.irq_summary == 0); | |
a2fa3e9f | 1477 | kvm_run->if_flag = (svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0; |
e756fc62 RR |
1478 | kvm_run->cr8 = svm->vcpu.cr8; |
1479 | kvm_run->apic_base = svm->vcpu.apic_base; | |
c1150d8c DL |
1480 | } |
1481 | ||
1482 | /* | |
1483 | * Check if userspace requested an interrupt window, and that the | |
1484 | * interrupt window is open. | |
1485 | * | |
1486 | * No need to exit to userspace if we already have an interrupt queued. | |
1487 | */ | |
e756fc62 | 1488 | static int dm_request_for_irq_injection(struct vcpu_svm *svm, |
c1150d8c DL |
1489 | struct kvm_run *kvm_run) |
1490 | { | |
e756fc62 | 1491 | return (!svm->vcpu.irq_summary && |
c1150d8c | 1492 | kvm_run->request_interrupt_window && |
e756fc62 RR |
1493 | svm->vcpu.interrupt_window_open && |
1494 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); | |
6aa8b732 AK |
1495 | } |
1496 | ||
1497 | static void save_db_regs(unsigned long *db_regs) | |
1498 | { | |
5aff458e AK |
1499 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1500 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1501 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1502 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1503 | } |
1504 | ||
1505 | static void load_db_regs(unsigned long *db_regs) | |
1506 | { | |
5aff458e AK |
1507 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1508 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1509 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1510 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1511 | } |
1512 | ||
d9e368d6 AK |
1513 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1514 | { | |
1515 | force_new_asid(vcpu); | |
1516 | } | |
1517 | ||
6aa8b732 AK |
1518 | static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1519 | { | |
a2fa3e9f | 1520 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1521 | u16 fs_selector; |
1522 | u16 gs_selector; | |
1523 | u16 ldt_selector; | |
e2dec939 | 1524 | int r; |
6aa8b732 AK |
1525 | |
1526 | again: | |
17c3ba9d AK |
1527 | r = kvm_mmu_reload(vcpu); |
1528 | if (unlikely(r)) | |
1529 | return r; | |
1530 | ||
cccf748b | 1531 | if (!vcpu->mmio_read_completed) |
e756fc62 | 1532 | do_interrupt_requests(svm, kvm_run); |
6aa8b732 AK |
1533 | |
1534 | clgi(); | |
1535 | ||
d9e368d6 AK |
1536 | vcpu->guest_mode = 1; |
1537 | if (vcpu->requests) | |
1538 | if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests)) | |
1539 | svm_flush_tlb(vcpu); | |
1540 | ||
e756fc62 | 1541 | pre_svm_run(svm); |
6aa8b732 AK |
1542 | |
1543 | save_host_msrs(vcpu); | |
1544 | fs_selector = read_fs(); | |
1545 | gs_selector = read_gs(); | |
1546 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1547 | svm->host_cr2 = kvm_read_cr2(); |
1548 | svm->host_dr6 = read_dr6(); | |
1549 | svm->host_dr7 = read_dr7(); | |
1550 | svm->vmcb->save.cr2 = vcpu->cr2; | |
6aa8b732 | 1551 | |
a2fa3e9f | 1552 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1553 | write_dr7(0); |
a2fa3e9f GH |
1554 | save_db_regs(svm->host_db_regs); |
1555 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1556 | } |
36241b8c | 1557 | |
7807fa6c | 1558 | if (vcpu->fpu_active) { |
b114b080 RR |
1559 | fx_save(&vcpu->host_fx_image); |
1560 | fx_restore(&vcpu->guest_fx_image); | |
7807fa6c | 1561 | } |
36241b8c | 1562 | |
6aa8b732 | 1563 | asm volatile ( |
05b3e0c2 | 1564 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1565 | "push %%rbx; push %%rcx; push %%rdx;" |
1566 | "push %%rsi; push %%rdi; push %%rbp;" | |
1567 | "push %%r8; push %%r9; push %%r10; push %%r11;" | |
1568 | "push %%r12; push %%r13; push %%r14; push %%r15;" | |
1569 | #else | |
1570 | "push %%ebx; push %%ecx; push %%edx;" | |
1571 | "push %%esi; push %%edi; push %%ebp;" | |
1572 | #endif | |
1573 | ||
05b3e0c2 | 1574 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1575 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1576 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1577 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1578 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1579 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1580 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1581 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1582 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1583 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1584 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1585 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1586 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1587 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1588 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1589 | #else |
fb3f0f51 RR |
1590 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1591 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1592 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1593 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1594 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1595 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1596 | #endif |
1597 | ||
05b3e0c2 | 1598 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1599 | /* Enter guest mode */ |
1600 | "push %%rax \n\t" | |
fb3f0f51 | 1601 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1602 | SVM_VMLOAD "\n\t" |
1603 | SVM_VMRUN "\n\t" | |
1604 | SVM_VMSAVE "\n\t" | |
1605 | "pop %%rax \n\t" | |
1606 | #else | |
1607 | /* Enter guest mode */ | |
1608 | "push %%eax \n\t" | |
fb3f0f51 | 1609 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1610 | SVM_VMLOAD "\n\t" |
1611 | SVM_VMRUN "\n\t" | |
1612 | SVM_VMSAVE "\n\t" | |
1613 | "pop %%eax \n\t" | |
1614 | #endif | |
1615 | ||
1616 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1617 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1618 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1619 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1620 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1621 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1622 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1623 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1624 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1625 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1626 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1627 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1628 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1629 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1630 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1631 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 AK |
1632 | |
1633 | "pop %%r15; pop %%r14; pop %%r13; pop %%r12;" | |
1634 | "pop %%r11; pop %%r10; pop %%r9; pop %%r8;" | |
1635 | "pop %%rbp; pop %%rdi; pop %%rsi;" | |
1636 | "pop %%rdx; pop %%rcx; pop %%rbx; \n\t" | |
1637 | #else | |
fb3f0f51 RR |
1638 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1639 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1640 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1641 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1642 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1643 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 AK |
1644 | |
1645 | "pop %%ebp; pop %%edi; pop %%esi;" | |
1646 | "pop %%edx; pop %%ecx; pop %%ebx; \n\t" | |
1647 | #endif | |
1648 | : | |
fb3f0f51 | 1649 | : [svm]"a"(svm), |
6aa8b732 | 1650 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
fb3f0f51 RR |
1651 | [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])), |
1652 | [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])), | |
1653 | [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])), | |
1654 | [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])), | |
1655 | [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])), | |
1656 | [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1657 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1658 | ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])), |
1659 | [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])), | |
1660 | [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])), | |
1661 | [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])), | |
1662 | [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])), | |
1663 | [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])), | |
1664 | [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])), | |
1665 | [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15])) | |
6aa8b732 AK |
1666 | #endif |
1667 | : "cc", "memory" ); | |
1668 | ||
d9e368d6 AK |
1669 | vcpu->guest_mode = 0; |
1670 | ||
7807fa6c | 1671 | if (vcpu->fpu_active) { |
b114b080 RR |
1672 | fx_save(&vcpu->guest_fx_image); |
1673 | fx_restore(&vcpu->host_fx_image); | |
7807fa6c | 1674 | } |
36241b8c | 1675 | |
a2fa3e9f GH |
1676 | if ((svm->vmcb->save.dr7 & 0xff)) |
1677 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1678 | |
a2fa3e9f | 1679 | vcpu->cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1680 | |
a2fa3e9f GH |
1681 | write_dr6(svm->host_dr6); |
1682 | write_dr7(svm->host_dr7); | |
1683 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1684 | |
1685 | load_fs(fs_selector); | |
1686 | load_gs(gs_selector); | |
1687 | load_ldt(ldt_selector); | |
1688 | load_host_msrs(vcpu); | |
1689 | ||
1690 | reload_tss(vcpu); | |
1691 | ||
07031e14 IM |
1692 | /* |
1693 | * Profile KVM exit RIPs: | |
1694 | */ | |
1695 | if (unlikely(prof_on == KVM_PROFILING)) | |
1696 | profile_hit(KVM_PROFILING, | |
a2fa3e9f | 1697 | (void *)(unsigned long)svm->vmcb->save.rip); |
07031e14 | 1698 | |
6aa8b732 AK |
1699 | stgi(); |
1700 | ||
0e5017d4 | 1701 | reput_irq(svm); |
6aa8b732 | 1702 | |
a2fa3e9f | 1703 | svm->next_rip = 0; |
6aa8b732 | 1704 | |
a2fa3e9f | 1705 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
8eb7d334 AK |
1706 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
1707 | kvm_run->fail_entry.hardware_entry_failure_reason | |
a2fa3e9f | 1708 | = svm->vmcb->control.exit_code; |
e756fc62 | 1709 | post_kvm_run_save(svm, kvm_run); |
6aa8b732 AK |
1710 | return 0; |
1711 | } | |
1712 | ||
e756fc62 | 1713 | r = handle_exit(svm, kvm_run); |
e2dec939 | 1714 | if (r > 0) { |
6aa8b732 | 1715 | if (signal_pending(current)) { |
1165f5fe | 1716 | ++vcpu->stat.signal_exits; |
e756fc62 | 1717 | post_kvm_run_save(svm, kvm_run); |
1b19f3e6 | 1718 | kvm_run->exit_reason = KVM_EXIT_INTR; |
c1150d8c DL |
1719 | return -EINTR; |
1720 | } | |
1721 | ||
e756fc62 | 1722 | if (dm_request_for_irq_injection(svm, kvm_run)) { |
1165f5fe | 1723 | ++vcpu->stat.request_irq_exits; |
e756fc62 | 1724 | post_kvm_run_save(svm, kvm_run); |
1b19f3e6 | 1725 | kvm_run->exit_reason = KVM_EXIT_INTR; |
6aa8b732 AK |
1726 | return -EINTR; |
1727 | } | |
1728 | kvm_resched(vcpu); | |
1729 | goto again; | |
1730 | } | |
e756fc62 | 1731 | post_kvm_run_save(svm, kvm_run); |
e2dec939 | 1732 | return r; |
6aa8b732 AK |
1733 | } |
1734 | ||
6aa8b732 AK |
1735 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1736 | { | |
a2fa3e9f GH |
1737 | struct vcpu_svm *svm = to_svm(vcpu); |
1738 | ||
1739 | svm->vmcb->save.cr3 = root; | |
6aa8b732 | 1740 | force_new_asid(vcpu); |
7807fa6c AL |
1741 | |
1742 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1743 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1744 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1745 | vcpu->fpu_active = 0; |
1746 | } | |
6aa8b732 AK |
1747 | } |
1748 | ||
1749 | static void svm_inject_page_fault(struct kvm_vcpu *vcpu, | |
1750 | unsigned long addr, | |
1751 | uint32_t err_code) | |
1752 | { | |
a2fa3e9f GH |
1753 | struct vcpu_svm *svm = to_svm(vcpu); |
1754 | uint32_t exit_int_info = svm->vmcb->control.exit_int_info; | |
6aa8b732 | 1755 | |
1165f5fe | 1756 | ++vcpu->stat.pf_guest; |
6aa8b732 AK |
1757 | |
1758 | if (is_page_fault(exit_int_info)) { | |
1759 | ||
a2fa3e9f GH |
1760 | svm->vmcb->control.event_inj_err = 0; |
1761 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1762 | SVM_EVTINJ_VALID_ERR | | |
1763 | SVM_EVTINJ_TYPE_EXEPT | | |
1764 | DF_VECTOR; | |
6aa8b732 AK |
1765 | return; |
1766 | } | |
1767 | vcpu->cr2 = addr; | |
a2fa3e9f GH |
1768 | svm->vmcb->save.cr2 = addr; |
1769 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1770 | SVM_EVTINJ_VALID_ERR | | |
1771 | SVM_EVTINJ_TYPE_EXEPT | | |
1772 | PF_VECTOR; | |
1773 | svm->vmcb->control.event_inj_err = err_code; | |
6aa8b732 AK |
1774 | } |
1775 | ||
1776 | ||
1777 | static int is_disabled(void) | |
1778 | { | |
6031a61c JR |
1779 | u64 vm_cr; |
1780 | ||
1781 | rdmsrl(MSR_VM_CR, vm_cr); | |
1782 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1783 | return 1; | |
1784 | ||
6aa8b732 AK |
1785 | return 0; |
1786 | } | |
1787 | ||
102d8325 IM |
1788 | static void |
1789 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1790 | { | |
1791 | /* | |
1792 | * Patch in the VMMCALL instruction: | |
1793 | */ | |
1794 | hypercall[0] = 0x0f; | |
1795 | hypercall[1] = 0x01; | |
1796 | hypercall[2] = 0xd9; | |
1797 | hypercall[3] = 0xc3; | |
1798 | } | |
1799 | ||
002c7f7c YS |
1800 | static void svm_check_processor_compat(void *rtn) |
1801 | { | |
1802 | *(int *)rtn = 0; | |
1803 | } | |
1804 | ||
6aa8b732 AK |
1805 | static struct kvm_arch_ops svm_arch_ops = { |
1806 | .cpu_has_kvm_support = has_svm, | |
1807 | .disabled_by_bios = is_disabled, | |
1808 | .hardware_setup = svm_hardware_setup, | |
1809 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1810 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1811 | .hardware_enable = svm_hardware_enable, |
1812 | .hardware_disable = svm_hardware_disable, | |
1813 | ||
1814 | .vcpu_create = svm_create_vcpu, | |
1815 | .vcpu_free = svm_free_vcpu, | |
1816 | ||
1817 | .vcpu_load = svm_vcpu_load, | |
1818 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1819 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1820 | |
1821 | .set_guest_debug = svm_guest_debug, | |
1822 | .get_msr = svm_get_msr, | |
1823 | .set_msr = svm_set_msr, | |
1824 | .get_segment_base = svm_get_segment_base, | |
1825 | .get_segment = svm_get_segment, | |
1826 | .set_segment = svm_set_segment, | |
6aa8b732 | 1827 | .get_cs_db_l_bits = svm_get_cs_db_l_bits, |
25c4c276 | 1828 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1829 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1830 | .set_cr3 = svm_set_cr3, |
1831 | .set_cr4 = svm_set_cr4, | |
1832 | .set_efer = svm_set_efer, | |
1833 | .get_idt = svm_get_idt, | |
1834 | .set_idt = svm_set_idt, | |
1835 | .get_gdt = svm_get_gdt, | |
1836 | .set_gdt = svm_set_gdt, | |
1837 | .get_dr = svm_get_dr, | |
1838 | .set_dr = svm_set_dr, | |
1839 | .cache_regs = svm_cache_regs, | |
1840 | .decache_regs = svm_decache_regs, | |
1841 | .get_rflags = svm_get_rflags, | |
1842 | .set_rflags = svm_set_rflags, | |
1843 | ||
1844 | .invlpg = svm_invlpg, | |
1845 | .tlb_flush = svm_flush_tlb, | |
1846 | .inject_page_fault = svm_inject_page_fault, | |
1847 | ||
1848 | .inject_gp = svm_inject_gp, | |
1849 | ||
1850 | .run = svm_vcpu_run, | |
1851 | .skip_emulated_instruction = skip_emulated_instruction, | |
102d8325 | 1852 | .patch_hypercall = svm_patch_hypercall, |
6aa8b732 AK |
1853 | }; |
1854 | ||
1855 | static int __init svm_init(void) | |
1856 | { | |
c16f862d RR |
1857 | return kvm_init_arch(&svm_arch_ops, sizeof(struct vcpu_svm), |
1858 | THIS_MODULE); | |
6aa8b732 AK |
1859 | } |
1860 | ||
1861 | static void __exit svm_exit(void) | |
1862 | { | |
1863 | kvm_exit_arch(); | |
1864 | } | |
1865 | ||
1866 | module_init(svm_init) | |
1867 | module_exit(svm_exit) |