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KVM: x86 emulator: Extract the common code of SrcReg and DstReg
[deliverable/linux.git] / drivers / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732
AK		 27#else
28#include "kvm.h"
34c16eec 29#include "x86.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
32#include "x86_emulate.h"
33#include <linux/module.h>
34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
50#define DstMask (3<<1)
51/* Source operand type. */
52#define SrcNone (0<<3) /* No source operand. */
53#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
54#define SrcReg (1<<3) /* Register operand. */
55#define SrcMem (2<<3) /* Memory operand. */
56#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
57#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
58#define SrcImm (5<<3) /* Immediate operand. */
59#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
60#define SrcMask (7<<3)
61/* Generic ModRM decode. */
62#define ModRM (1<<6)
63/* Destination is only written; never read. */
64#define Mov (1<<7)
038e51de 65#define BitOp (1<<8)
c7e75a3d 66#define MemAbs (1<<9) /* Memory operand is absolute displacement */
6aa8b732 67
c7e75a3d 68static u16 opcode_table[256] = {
6aa8b732
AK		 69 /* 0x00 - 0x07 */
70 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
71 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
72 0, 0, 0, 0,
73 /* 0x08 - 0x0F */
74 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
75 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
76 0, 0, 0, 0,
77 /* 0x10 - 0x17 */
78 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
79 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
80 0, 0, 0, 0,
81 /* 0x18 - 0x1F */
82 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
83 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
84 0, 0, 0, 0,
85 /* 0x20 - 0x27 */
86 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
87 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 88 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 89 /* 0x28 - 0x2F */
90 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
91 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
92 0, 0, 0, 0,
93 /* 0x30 - 0x37 */
94 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
95 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
96 0, 0, 0, 0,
97 /* 0x38 - 0x3F */
98 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
99 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
100 0, 0, 0, 0,
d77a2507
NK		 101 /* 0x40 - 0x47 */
102 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
103 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
104 /* 0x48 - 0x4F */
105 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
106 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7f0aaee0 107 /* 0x50 - 0x57 */
7e778161
NK		 108 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
109 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7f0aaee0
NK		 110 /* 0x58 - 0x5F */
111 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
112 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7d316911 113 /* 0x60 - 0x67 */
6aa8b732 114 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 115 0, 0, 0, 0,
116 /* 0x68 - 0x6F */
117 0, 0, ImplicitOps|Mov, 0,
e70669ab
LV		 118 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
119 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 120 /* 0x70 - 0x77 */
121 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
122 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
123 /* 0x78 - 0x7F */
124 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
125 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 126 /* 0x80 - 0x87 */
127 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
128 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
129 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
130 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
131 /* 0x88 - 0x8F */
132 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
133 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
7e0b54b1 134 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov,
6aa8b732 135 /* 0x90 - 0x9F */
535eabcf 136 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0,
6aa8b732 137 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 138 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
139 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
6aa8b732
AK		 140 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
141 ByteOp | ImplicitOps, ImplicitOps,
142 /* 0xA8 - 0xAF */
143 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
144 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
145 ByteOp | ImplicitOps, ImplicitOps,
146 /* 0xB0 - 0xBF */
147 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
148 /* 0xC0 - 0xC7 */
d9413cd7
NK		 149 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
150 0, ImplicitOps, 0, 0,
151 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 152 /* 0xC8 - 0xCF */
153 0, 0, 0, 0, 0, 0, 0, 0,
154 /* 0xD0 - 0xD7 */
155 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
156 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
157 0, 0, 0, 0,
158 /* 0xD8 - 0xDF */
159 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 160 /* 0xE0 - 0xE7 */
161 0, 0, 0, 0, 0, 0, 0, 0,
162 /* 0xE8 - 0xEF */
f6eed391 163 ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0,
6aa8b732
AK		 164 /* 0xF0 - 0xF7 */
165 0, 0, 0, 0,
b284be57 166 ImplicitOps, ImplicitOps,
72d6e5a0 167 ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
6aa8b732 168 /* 0xF8 - 0xFF */
b284be57 169 ImplicitOps, 0, ImplicitOps, ImplicitOps,
6aa8b732
AK		 170 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
171};
172
038e51de 173static u16 twobyte_table[256] = {
6aa8b732
AK		 174 /* 0x00 - 0x0F */
175 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 176 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 177 /* 0x10 - 0x1F */
178 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
179 /* 0x20 - 0x2F */
180 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
181 0, 0, 0, 0, 0, 0, 0, 0,
182 /* 0x30 - 0x3F */
35f3f286 183 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 184 /* 0x40 - 0x47 */
185 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
186 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
187 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
188 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
189 /* 0x48 - 0x4F */
190 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
191 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
192 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
193 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
194 /* 0x50 - 0x5F */
195 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
196 /* 0x60 - 0x6F */
197 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
198 /* 0x70 - 0x7F */
199 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
200 /* 0x80 - 0x8F */
bbe9abbd
NK		 201 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
202 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
203 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
204 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 205 /* 0x90 - 0x9F */
206 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
207 /* 0xA0 - 0xA7 */
038e51de 208 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 209 /* 0xA8 - 0xAF */
038e51de 210 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 211 /* 0xB0 - 0xB7 */
212 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 213 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 214 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
215 DstReg | SrcMem16 | ModRM | Mov,
216 /* 0xB8 - 0xBF */
038e51de 217 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 218 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
219 DstReg | SrcMem16 | ModRM | Mov,
220 /* 0xC0 - 0xCF */
a012e65a
SY		 221 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
222 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 223 /* 0xD0 - 0xDF */
224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
225 /* 0xE0 - 0xEF */
226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
227 /* 0xF0 - 0xFF */
228 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
229};
230
6aa8b732
AK		 231/* EFLAGS bit definitions. */
232#define EFLG_OF (1<<11)
233#define EFLG_DF (1<<10)
234#define EFLG_SF (1<<7)
235#define EFLG_ZF (1<<6)
236#define EFLG_AF (1<<4)
237#define EFLG_PF (1<<2)
238#define EFLG_CF (1<<0)
239
240/*
241 * Instruction emulation:
242 * Most instructions are emulated directly via a fragment of inline assembly
243 * code. This allows us to save/restore EFLAGS and thus very easily pick up
244 * any modified flags.
245 */
246
05b3e0c2 247#if defined(CONFIG_X86_64)
6aa8b732
AK		 248#define _LO32 "k" /* force 32-bit operand */
249#define _STK "%%rsp" /* stack pointer */
250#elif defined(__i386__)
251#define _LO32 "" /* force 32-bit operand */
252#define _STK "%%esp" /* stack pointer */
253#endif
254
255/*
256 * These EFLAGS bits are restored from saved value during emulation, and
257 * any changes are written back to the saved value after emulation.
258 */
259#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
260
261/* Before executing instruction: restore necessary bits in EFLAGS. */
262#define _PRE_EFLAGS(_sav, _msk, _tmp) \
263 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \
264 "push %"_sav"; " \
265 "movl %"_msk",%"_LO32 _tmp"; " \
266 "andl %"_LO32 _tmp",("_STK"); " \
267 "pushf; " \
268 "notl %"_LO32 _tmp"; " \
269 "andl %"_LO32 _tmp",("_STK"); " \
270 "pop %"_tmp"; " \
271 "orl %"_LO32 _tmp",("_STK"); " \
272 "popf; " \
273 /* _sav &= ~msk; */ \
274 "movl %"_msk",%"_LO32 _tmp"; " \
275 "notl %"_LO32 _tmp"; " \
276 "andl %"_LO32 _tmp",%"_sav"; "
277
278/* After executing instruction: write-back necessary bits in EFLAGS. */
279#define _POST_EFLAGS(_sav, _msk, _tmp) \
280 /* _sav |= EFLAGS & _msk; */ \
281 "pushf; " \
282 "pop %"_tmp"; " \
283 "andl %"_msk",%"_LO32 _tmp"; " \
284 "orl %"_LO32 _tmp",%"_sav"; "
285
286/* Raw emulation: instruction has two explicit operands. */
287#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
288 do { \
289 unsigned long _tmp; \
290 \
291 switch ((_dst).bytes) { \
292 case 2: \
293 __asm__ __volatile__ ( \
d77c26fc 294 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 295 _op"w %"_wx"3,%1; " \
d77c26fc 296 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 297 : "=m" (_eflags), "=m" ((_dst).val), \
298 "=&r" (_tmp) \
d77c26fc 299 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 300 break; \
301 case 4: \
302 __asm__ __volatile__ ( \
d77c26fc 303 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 304 _op"l %"_lx"3,%1; " \
d77c26fc 305 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 306 : "=m" (_eflags), "=m" ((_dst).val), \
307 "=&r" (_tmp) \
d77c26fc 308 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 309 break; \
310 case 8: \
311 __emulate_2op_8byte(_op, _src, _dst, \
312 _eflags, _qx, _qy); \
313 break; \
314 } \
315 } while (0)
316
317#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
318 do { \
319 unsigned long _tmp; \
d77c26fc 320 switch ((_dst).bytes) { \
6aa8b732
AK		 321 case 1: \
322 __asm__ __volatile__ ( \
d77c26fc 323 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 324 _op"b %"_bx"3,%1; " \
d77c26fc 325 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 326 : "=m" (_eflags), "=m" ((_dst).val), \
327 "=&r" (_tmp) \
d77c26fc 328 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 329 break; \
330 default: \
331 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
332 _wx, _wy, _lx, _ly, _qx, _qy); \
333 break; \
334 } \
335 } while (0)
336
337/* Source operand is byte-sized and may be restricted to just %cl. */
338#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
339 __emulate_2op(_op, _src, _dst, _eflags, \
340 "b", "c", "b", "c", "b", "c", "b", "c")
341
342/* Source operand is byte, word, long or quad sized. */
343#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
344 __emulate_2op(_op, _src, _dst, _eflags, \
345 "b", "q", "w", "r", _LO32, "r", "", "r")
346
347/* Source operand is word, long or quad sized. */
348#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
349 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
350 "w", "r", _LO32, "r", "", "r")
351
352/* Instruction has only one explicit operand (no source operand). */
353#define emulate_1op(_op, _dst, _eflags) \
354 do { \
355 unsigned long _tmp; \
356 \
d77c26fc 357 switch ((_dst).bytes) { \
6aa8b732
AK		 358 case 1: \
359 __asm__ __volatile__ ( \
d77c26fc 360 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 361 _op"b %1; " \
d77c26fc 362 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 363 : "=m" (_eflags), "=m" ((_dst).val), \
364 "=&r" (_tmp) \
d77c26fc 365 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 366 break; \
367 case 2: \
368 __asm__ __volatile__ ( \
d77c26fc 369 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 370 _op"w %1; " \
d77c26fc 371 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 372 : "=m" (_eflags), "=m" ((_dst).val), \
373 "=&r" (_tmp) \
d77c26fc 374 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 375 break; \
376 case 4: \
377 __asm__ __volatile__ ( \
d77c26fc 378 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 379 _op"l %1; " \
d77c26fc 380 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 381 : "=m" (_eflags), "=m" ((_dst).val), \
382 "=&r" (_tmp) \
d77c26fc 383 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 384 break; \
385 case 8: \
386 __emulate_1op_8byte(_op, _dst, _eflags); \
387 break; \
388 } \
389 } while (0)
390
391/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 392#if defined(CONFIG_X86_64)
6aa8b732
AK		 393#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
394 do { \
395 __asm__ __volatile__ ( \
d77c26fc 396 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 397 _op"q %"_qx"3,%1; " \
d77c26fc 398 _POST_EFLAGS("0", "4", "2") \
6aa8b732 399 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 400 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 401 } while (0)
402
403#define __emulate_1op_8byte(_op, _dst, _eflags) \
404 do { \
405 __asm__ __volatile__ ( \
d77c26fc 406 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 407 _op"q %1; " \
d77c26fc 408 _POST_EFLAGS("0", "3", "2") \
6aa8b732 409 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 410 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 411 } while (0)
412
413#elif defined(__i386__)
414#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
415#define __emulate_1op_8byte(_op, _dst, _eflags)
416#endif /* __i386__ */
417
418/* Fetch next part of the instruction being emulated. */
419#define insn_fetch(_type, _size, _eip) \
420({ unsigned long _x; \
421 rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x, \
d77c26fc
MD		 422 (_size), ctxt->vcpu); \
423 if (rc != 0) \
6aa8b732
AK		 424 goto done; \
425 (_eip) += (_size); \
426 (_type)_x; \
427})
428
429/* Access/update address held in a register, based on addressing mode. */
e70669ab 430#define address_mask(reg) \
e4e03ded
LV		 431 ((c->ad_bytes == sizeof(unsigned long)) ? \
432 (reg) : ((reg) & ((1UL << (c->ad_bytes << 3)) - 1)))
6aa8b732 433#define register_address(base, reg) \
e70669ab 434 ((base) + address_mask(reg))
6aa8b732
AK		 435#define register_address_increment(reg, inc) \
436 do { \
437 /* signed type ensures sign extension to long */ \
438 int _inc = (inc); \
e4e03ded 439 if (c->ad_bytes == sizeof(unsigned long)) \
6aa8b732
AK		 440 (reg) += _inc; \
441 else \
e4e03ded
LV		 442 (reg) = ((reg) & \
443 ~((1UL << (c->ad_bytes << 3)) - 1)) | \
444 (((reg) + _inc) & \
445 ((1UL << (c->ad_bytes << 3)) - 1)); \
6aa8b732
AK		 446 } while (0)
447
098c937b
NK		 448#define JMP_REL(rel) \
449 do { \
e4e03ded 450 register_address_increment(c->eip, rel); \
098c937b
NK		 451 } while (0)
452
1e3c5cb0
RR		 453/*
454 * Given the 'reg' portion of a ModRM byte, and a register block, return a
455 * pointer into the block that addresses the relevant register.
456 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
457 */
458static void *decode_register(u8 modrm_reg, unsigned long *regs,
459 int highbyte_regs)
6aa8b732
AK		 460{
461 void *p;
462
463 p = &regs[modrm_reg];
464 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
465 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
466 return p;
467}
468
469static int read_descriptor(struct x86_emulate_ctxt *ctxt,
470 struct x86_emulate_ops *ops,
471 void *ptr,
472 u16 *size, unsigned long *address, int op_bytes)
473{
474 int rc;
475
476 if (op_bytes == 2)
477 op_bytes = 3;
478 *address = 0;
cebff02b
LV		 479 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
480 ctxt->vcpu);
6aa8b732
AK		 481 if (rc)
482 return rc;
cebff02b
LV		 483 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
484 ctxt->vcpu);
6aa8b732
AK		 485 return rc;
486}
487
bbe9abbd
NK		 488static int test_cc(unsigned int condition, unsigned int flags)
489{
490 int rc = 0;
491
492 switch ((condition & 15) >> 1) {
493 case 0: /* o */
494 rc |= (flags & EFLG_OF);
495 break;
496 case 1: /* b/c/nae */
497 rc |= (flags & EFLG_CF);
498 break;
499 case 2: /* z/e */
500 rc |= (flags & EFLG_ZF);
501 break;
502 case 3: /* be/na */
503 rc |= (flags & (EFLG_CF|EFLG_ZF));
504 break;
505 case 4: /* s */
506 rc |= (flags & EFLG_SF);
507 break;
508 case 5: /* p/pe */
509 rc |= (flags & EFLG_PF);
510 break;
511 case 7: /* le/ng */
512 rc |= (flags & EFLG_ZF);
513 /* fall through */
514 case 6: /* l/nge */
515 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
516 break;
517 }
518
519 /* Odd condition identifiers (lsb == 1) have inverted sense. */
520 return (!!rc ^ (condition & 1));
521}
522
3c118e24
AK		 523static void decode_register_operand(struct operand *op,
524 struct decode_cache *c,
525 int highbyte_regs,
526 int inhibit_bytereg)
527{
528 op->type = OP_REG;
529 if ((c->d & ByteOp) && !inhibit_bytereg) {
530 op->ptr = decode_register(c->modrm_reg, c->regs, highbyte_regs);
531 op->val = *(u8 *)op->ptr;
532 op->bytes = 1;
533 } else {
534 op->ptr = decode_register(c->modrm_reg, c->regs, 0);
535 op->bytes = c->op_bytes;
536 switch (op->bytes) {
537 case 2:
538 op->val = *(u16 *)op->ptr;
539 break;
540 case 4:
541 op->val = *(u32 *)op->ptr;
542 break;
543 case 8:
544 op->val = *(u64 *) op->ptr;
545 break;
546 }
547 }
548 op->orig_val = op->val;
549}
550
6aa8b732 551int
8b4caf66 552x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 553{
e4e03ded
LV		 554 struct decode_cache *c = &ctxt->decode;
555 u8 sib, rex_prefix = 0;
6aa8b732 556 int rc = 0;
6aa8b732 557 int mode = ctxt->mode;
e4e03ded 558 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
6aa8b732
AK		 559
560 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 561
e4e03ded
LV		 562 memset(c, 0, sizeof(struct decode_cache));
563 c->eip = ctxt->vcpu->rip;
564 memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs);
6aa8b732
AK		 565
566 switch (mode) {
567 case X86EMUL_MODE_REAL:
568 case X86EMUL_MODE_PROT16:
e4e03ded 569 c->op_bytes = c->ad_bytes = 2;
6aa8b732
AK		 570 break;
571 case X86EMUL_MODE_PROT32:
e4e03ded 572 c->op_bytes = c->ad_bytes = 4;
6aa8b732 573 break;
05b3e0c2 574#ifdef CONFIG_X86_64
6aa8b732 575 case X86EMUL_MODE_PROT64:
e4e03ded
LV		 576 c->op_bytes = 4;
577 c->ad_bytes = 8;
6aa8b732
AK		 578 break;
579#endif
580 default:
581 return -1;
582 }
583
584 /* Legacy prefixes. */
b4c6abfe 585 for (;;) {
e4e03ded 586 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 587 case 0x66: /* operand-size override */
e4e03ded 588 c->op_bytes ^= 6; /* switch between 2/4 bytes */
6aa8b732
AK		 589 break;
590 case 0x67: /* address-size override */
591 if (mode == X86EMUL_MODE_PROT64)
e4e03ded
LV		 592 /* switch between 4/8 bytes */
593 c->ad_bytes ^= 12;
6aa8b732 594 else
e4e03ded
LV		 595 /* switch between 2/4 bytes */
596 c->ad_bytes ^= 6;
6aa8b732
AK		 597 break;
598 case 0x2e: /* CS override */
e4e03ded 599 c->override_base = &ctxt->cs_base;
6aa8b732
AK		 600 break;
601 case 0x3e: /* DS override */
e4e03ded 602 c->override_base = &ctxt->ds_base;
6aa8b732
AK		 603 break;
604 case 0x26: /* ES override */
e4e03ded 605 c->override_base = &ctxt->es_base;
6aa8b732
AK		 606 break;
607 case 0x64: /* FS override */
e4e03ded 608 c->override_base = &ctxt->fs_base;
6aa8b732
AK		 609 break;
610 case 0x65: /* GS override */
e4e03ded 611 c->override_base = &ctxt->gs_base;
6aa8b732
AK		 612 break;
613 case 0x36: /* SS override */
e4e03ded 614 c->override_base = &ctxt->ss_base;
6aa8b732 615 break;
b4c6abfe
LV		 616 case 0x40 ... 0x4f: /* REX */
617 if (mode != X86EMUL_MODE_PROT64)
618 goto done_prefixes;
619 rex_prefix = c->b;
620 continue;
6aa8b732 621 case 0xf0: /* LOCK */
e4e03ded 622 c->lock_prefix = 1;
6aa8b732 623 break;
ae6200ba 624 case 0xf2: /* REPNE/REPNZ */
6aa8b732 625 case 0xf3: /* REP/REPE/REPZ */
e4e03ded 626 c->rep_prefix = 1;
6aa8b732 627 break;
6aa8b732
AK		 628 default:
629 goto done_prefixes;
630 }
b4c6abfe
LV		 631
632 /* Any legacy prefix after a REX prefix nullifies its effect. */
633
634 rex_prefix = 0;
6aa8b732
AK		 635 }
636
637done_prefixes:
638
639 /* REX prefix. */
b4c6abfe
LV		 640 if (rex_prefix) {
641 if (rex_prefix & 8)
e4e03ded 642 c->op_bytes = 8; /* REX.W */
b4c6abfe
LV		 643 c->modrm_reg = (rex_prefix & 4) << 1; /* REX.R */
644 index_reg = (rex_prefix & 2) << 2; /* REX.X */
645 c->modrm_rm = base_reg = (rex_prefix & 1) << 3; /* REG.B */
6aa8b732
AK		 646 }
647
648 /* Opcode byte(s). */
e4e03ded
LV		 649 c->d = opcode_table[c->b];
650 if (c->d == 0) {
6aa8b732 651 /* Two-byte opcode? */
e4e03ded
LV		 652 if (c->b == 0x0f) {
653 c->twobyte = 1;
654 c->b = insn_fetch(u8, 1, c->eip);
655 c->d = twobyte_table[c->b];
6aa8b732
AK		 656 }
657
658 /* Unrecognised? */
8b4caf66
LV		 659 if (c->d == 0) {
660 DPRINTF("Cannot emulate %02x\n", c->b);
661 return -1;
662 }
6aa8b732
AK		 663 }
664
665 /* ModRM and SIB bytes. */
e4e03ded
LV		 666 if (c->d & ModRM) {
667 c->modrm = insn_fetch(u8, 1, c->eip);
668 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
669 c->modrm_reg |= (c->modrm & 0x38) >> 3;
670 c->modrm_rm |= (c->modrm & 0x07);
671 c->modrm_ea = 0;
672 c->use_modrm_ea = 1;
673
674 if (c->modrm_mod == 3) {
675 c->modrm_val = *(unsigned long *)
676 decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
6aa8b732
AK		 677 goto modrm_done;
678 }
679
e4e03ded
LV		 680 if (c->ad_bytes == 2) {
681 unsigned bx = c->regs[VCPU_REGS_RBX];
682 unsigned bp = c->regs[VCPU_REGS_RBP];
683 unsigned si = c->regs[VCPU_REGS_RSI];
684 unsigned di = c->regs[VCPU_REGS_RDI];
6aa8b732
AK		 685
686 /* 16-bit ModR/M decode. */
e4e03ded 687 switch (c->modrm_mod) {
6aa8b732 688 case 0:
e4e03ded
LV		 689 if (c->modrm_rm == 6)
690 c->modrm_ea +=
691 insn_fetch(u16, 2, c->eip);
6aa8b732
AK		 692 break;
693 case 1:
e4e03ded 694 c->modrm_ea += insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 695 break;
696 case 2:
e4e03ded 697 c->modrm_ea += insn_fetch(u16, 2, c->eip);
6aa8b732
AK		 698 break;
699 }
e4e03ded 700 switch (c->modrm_rm) {
6aa8b732 701 case 0:
e4e03ded 702 c->modrm_ea += bx + si;
6aa8b732
AK		 703 break;
704 case 1:
e4e03ded 705 c->modrm_ea += bx + di;
6aa8b732
AK		 706 break;
707 case 2:
e4e03ded 708 c->modrm_ea += bp + si;
6aa8b732
AK		 709 break;
710 case 3:
e4e03ded 711 c->modrm_ea += bp + di;
6aa8b732
AK		 712 break;
713 case 4:
e4e03ded 714 c->modrm_ea += si;
6aa8b732
AK		 715 break;
716 case 5:
e4e03ded 717 c->modrm_ea += di;
6aa8b732
AK		 718 break;
719 case 6:
e4e03ded
LV		 720 if (c->modrm_mod != 0)
721 c->modrm_ea += bp;
6aa8b732
AK		 722 break;
723 case 7:
e4e03ded 724 c->modrm_ea += bx;
6aa8b732
AK		 725 break;
726 }
e4e03ded
LV		 727 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
728 (c->modrm_rm == 6 && c->modrm_mod != 0))
729 if (!c->override_base)
730 c->override_base = &ctxt->ss_base;
731 c->modrm_ea = (u16)c->modrm_ea;
6aa8b732
AK		 732 } else {
733 /* 32/64-bit ModR/M decode. */
e4e03ded 734 switch (c->modrm_rm) {
6aa8b732
AK		 735 case 4:
736 case 12:
e4e03ded 737 sib = insn_fetch(u8, 1, c->eip);
6aa8b732
AK		 738 index_reg |= (sib >> 3) & 7;
739 base_reg |= sib & 7;
740 scale = sib >> 6;
741
742 switch (base_reg) {
743 case 5:
e4e03ded
LV		 744 if (c->modrm_mod != 0)
745 c->modrm_ea +=
746 c->regs[base_reg];
6aa8b732 747 else
e4e03ded
LV		 748 c->modrm_ea +=
749 insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 750 break;
751 default:
e4e03ded 752 c->modrm_ea += c->regs[base_reg];
6aa8b732
AK		 753 }
754 switch (index_reg) {
755 case 4:
756 break;
757 default:
e4e03ded
LV		 758 c->modrm_ea +=
759 c->regs[index_reg] << scale;
6aa8b732
AK		 760
761 }
762 break;
763 case 5:
e4e03ded
LV		 764 if (c->modrm_mod != 0)
765 c->modrm_ea += c->regs[c->modrm_rm];
6aa8b732
AK		 766 else if (mode == X86EMUL_MODE_PROT64)
767 rip_relative = 1;
768 break;
769 default:
e4e03ded 770 c->modrm_ea += c->regs[c->modrm_rm];
6aa8b732
AK		 771 break;
772 }
e4e03ded 773 switch (c->modrm_mod) {
6aa8b732 774 case 0:
e4e03ded
LV		 775 if (c->modrm_rm == 5)
776 c->modrm_ea +=
777 insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 778 break;
779 case 1:
e4e03ded 780 c->modrm_ea += insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 781 break;
782 case 2:
e4e03ded 783 c->modrm_ea += insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 784 break;
785 }
786 }
6aa8b732 787 if (rip_relative) {
e4e03ded
LV		 788 c->modrm_ea += c->eip;
789 switch (c->d & SrcMask) {
6aa8b732 790 case SrcImmByte:
e4e03ded 791 c->modrm_ea += 1;
6aa8b732
AK		 792 break;
793 case SrcImm:
e4e03ded
LV		 794 if (c->d & ByteOp)
795 c->modrm_ea += 1;
6aa8b732 796 else
e4e03ded
LV		 797 if (c->op_bytes == 8)
798 c->modrm_ea += 4;
6aa8b732 799 else
e4e03ded 800 c->modrm_ea += c->op_bytes;
6aa8b732
AK		 801 }
802 }
d77c26fc 803modrm_done:
6aa8b732 804 ;
c7e75a3d
AK		 805 } else if (c->d & MemAbs) {
806 switch (c->ad_bytes) {
807 case 2:
808 c->modrm_ea = insn_fetch(u16, 2, c->eip);
809 break;
810 case 4:
811 c->modrm_ea = insn_fetch(u32, 4, c->eip);
812 break;
813 case 8:
814 c->modrm_ea = insn_fetch(u64, 8, c->eip);
815 break;
816 }
817
6aa8b732
AK		 818 }
819
c7e75a3d
AK		 820 if (!c->override_base)
821 c->override_base = &ctxt->ds_base;
822 if (mode == X86EMUL_MODE_PROT64 &&
823 c->override_base != &ctxt->fs_base &&
824 c->override_base != &ctxt->gs_base)
825 c->override_base = NULL;
826
827 if (c->override_base)
828 c->modrm_ea += *c->override_base;
829
830 if (c->ad_bytes != 8)
831 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 832 /*
833 * Decode and fetch the source operand: register, memory
834 * or immediate.
835 */
e4e03ded 836 switch (c->d & SrcMask) {
6aa8b732
AK		 837 case SrcNone:
838 break;
839 case SrcReg:
3c118e24 840 decode_register_operand(&c->src, c, rex_prefix == 0, 0);
6aa8b732
AK		 841 break;
842 case SrcMem16:
e4e03ded 843 c->src.bytes = 2;
6aa8b732
AK		 844 goto srcmem_common;
845 case SrcMem32:
e4e03ded 846 c->src.bytes = 4;
6aa8b732
AK		 847 goto srcmem_common;
848 case SrcMem:
e4e03ded
LV		 849 c->src.bytes = (c->d & ByteOp) ? 1 :
850 c->op_bytes;
b85b9ee9 851 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 852 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 853 break;
d77c26fc 854 srcmem_common:
4e62417b
AJ		 855 /*
856 * For instructions with a ModR/M byte, switch to register
857 * access if Mod = 3.
858 */
e4e03ded
LV		 859 if ((c->d & ModRM) && c->modrm_mod == 3) {
860 c->src.type = OP_REG;
4e62417b
AJ		 861 break;
862 }
e4e03ded 863 c->src.type = OP_MEM;
6aa8b732
AK		 864 break;
865 case SrcImm:
e4e03ded
LV		 866 c->src.type = OP_IMM;
867 c->src.ptr = (unsigned long *)c->eip;
868 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
869 if (c->src.bytes == 8)
870 c->src.bytes = 4;
6aa8b732 871 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 872 switch (c->src.bytes) {
6aa8b732 873 case 1:
e4e03ded 874 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 875 break;
876 case 2:
e4e03ded 877 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 878 break;
879 case 4:
e4e03ded 880 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 881 break;
882 }
883 break;
884 case SrcImmByte:
e4e03ded
LV		 885 c->src.type = OP_IMM;
886 c->src.ptr = (unsigned long *)c->eip;
887 c->src.bytes = 1;
888 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 889 break;
890 }
891
038e51de 892 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 893 switch (c->d & DstMask) {
038e51de
AK		 894 case ImplicitOps:
895 /* Special instructions do their own operand decoding. */
8b4caf66 896 return 0;
038e51de 897 case DstReg:
3c118e24
AK		 898 decode_register_operand(&c->dst, c, rex_prefix == 0,
899 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 900 break;
901 case DstMem:
e4e03ded
LV		 902 if ((c->d & ModRM) && c->modrm_mod == 3) {
903 c->dst.type = OP_REG;
4e62417b
AJ		 904 break;
905 }
8b4caf66
LV		 906 c->dst.type = OP_MEM;
907 break;
908 }
909
910done:
911 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
912}
913
8cdbd2c9
LV		 914static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
915{
916 struct decode_cache *c = &ctxt->decode;
917
918 c->dst.type = OP_MEM;
919 c->dst.bytes = c->op_bytes;
920 c->dst.val = c->src.val;
921 register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes);
922 c->dst.ptr = (void *) register_address(ctxt->ss_base,
923 c->regs[VCPU_REGS_RSP]);
924}
925
926static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
927 struct x86_emulate_ops *ops)
928{
929 struct decode_cache *c = &ctxt->decode;
930 int rc;
931
932 /* 64-bit mode: POP always pops a 64-bit operand. */
933
934 if (ctxt->mode == X86EMUL_MODE_PROT64)
935 c->dst.bytes = 8;
936
937 rc = ops->read_std(register_address(ctxt->ss_base,
938 c->regs[VCPU_REGS_RSP]),
939 &c->dst.val, c->dst.bytes, ctxt->vcpu);
940 if (rc != 0)
941 return rc;
942
943 register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes);
944
945 return 0;
946}
947
05f086f8 948static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 949{
05f086f8 950 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 951 switch (c->modrm_reg) {
952 case 0: /* rol */
05f086f8 953 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 954 break;
955 case 1: /* ror */
05f086f8 956 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 957 break;
958 case 2: /* rcl */
05f086f8 959 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 960 break;
961 case 3: /* rcr */
05f086f8 962 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 963 break;
964 case 4: /* sal/shl */
965 case 6: /* sal/shl */
05f086f8 966 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 967 break;
968 case 5: /* shr */
05f086f8 969 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 970 break;
971 case 7: /* sar */
05f086f8 972 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 973 break;
974 }
975}
976
977static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 978 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 979{
980 struct decode_cache *c = &ctxt->decode;
981 int rc = 0;
982
983 switch (c->modrm_reg) {
984 case 0 ... 1: /* test */
985 /*
986 * Special case in Grp3: test has an immediate
987 * source operand.
988 */
989 c->src.type = OP_IMM;
990 c->src.ptr = (unsigned long *)c->eip;
991 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
992 if (c->src.bytes == 8)
993 c->src.bytes = 4;
994 switch (c->src.bytes) {
995 case 1:
996 c->src.val = insn_fetch(s8, 1, c->eip);
997 break;
998 case 2:
999 c->src.val = insn_fetch(s16, 2, c->eip);
1000 break;
1001 case 4:
1002 c->src.val = insn_fetch(s32, 4, c->eip);
1003 break;
1004 }
05f086f8 1005 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1006 break;
1007 case 2: /* not */
1008 c->dst.val = ~c->dst.val;
1009 break;
1010 case 3: /* neg */
05f086f8 1011 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1012 break;
1013 default:
1014 DPRINTF("Cannot emulate %02x\n", c->b);
1015 rc = X86EMUL_UNHANDLEABLE;
1016 break;
1017 }
1018done:
1019 return rc;
1020}
1021
1022static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1023 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1024{
1025 struct decode_cache *c = &ctxt->decode;
1026 int rc;
1027
1028 switch (c->modrm_reg) {
1029 case 0: /* inc */
05f086f8 1030 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1031 break;
1032 case 1: /* dec */
05f086f8 1033 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1034 break;
1035 case 4: /* jmp abs */
1036 if (c->b == 0xff)
1037 c->eip = c->dst.val;
1038 else {
1039 DPRINTF("Cannot emulate %02x\n", c->b);
1040 return X86EMUL_UNHANDLEABLE;
1041 }
1042 break;
1043 case 6: /* push */
1044
1045 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1046
1047 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1048 c->dst.bytes = 8;
1049 rc = ops->read_std((unsigned long)c->dst.ptr,
1050 &c->dst.val, 8, ctxt->vcpu);
1051 if (rc != 0)
1052 return rc;
1053 }
1054 register_address_increment(c->regs[VCPU_REGS_RSP],
1055 -c->dst.bytes);
1056 rc = ops->write_emulated(register_address(ctxt->ss_base,
1057 c->regs[VCPU_REGS_RSP]), &c->dst.val,
1058 c->dst.bytes, ctxt->vcpu);
1059 if (rc != 0)
1060 return rc;
a01af5ec 1061 c->dst.type = OP_NONE;
8cdbd2c9
LV		 1062 break;
1063 default:
1064 DPRINTF("Cannot emulate %02x\n", c->b);
1065 return X86EMUL_UNHANDLEABLE;
1066 }
1067 return 0;
1068}
1069
1070static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1071 struct x86_emulate_ops *ops,
8cdbd2c9
LV		 1072 unsigned long cr2)
1073{
1074 struct decode_cache *c = &ctxt->decode;
1075 u64 old, new;
1076 int rc;
1077
1078 rc = ops->read_emulated(cr2, &old, 8, ctxt->vcpu);
1079 if (rc != 0)
1080 return rc;
1081
1082 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1083 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1084
1085 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1086 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1087 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1088
1089 } else {
1090 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1091 (u32) c->regs[VCPU_REGS_RBX];
1092
1093 rc = ops->cmpxchg_emulated(cr2, &old, &new, 8, ctxt->vcpu);
1094 if (rc != 0)
1095 return rc;
05f086f8 1096 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1097 }
1098 return 0;
1099}
1100
1101static inline int writeback(struct x86_emulate_ctxt *ctxt,
1102 struct x86_emulate_ops *ops)
1103{
1104 int rc;
1105 struct decode_cache *c = &ctxt->decode;
1106
1107 switch (c->dst.type) {
1108 case OP_REG:
1109 /* The 4-byte case *is* correct:
1110 * in 64-bit mode we zero-extend.
1111 */
1112 switch (c->dst.bytes) {
1113 case 1:
1114 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1115 break;
1116 case 2:
1117 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1118 break;
1119 case 4:
1120 *c->dst.ptr = (u32)c->dst.val;
1121 break; /* 64b: zero-ext */
1122 case 8:
1123 *c->dst.ptr = c->dst.val;
1124 break;
1125 }
1126 break;
1127 case OP_MEM:
1128 if (c->lock_prefix)
1129 rc = ops->cmpxchg_emulated(
1130 (unsigned long)c->dst.ptr,
1131 &c->dst.orig_val,
1132 &c->dst.val,
1133 c->dst.bytes,
1134 ctxt->vcpu);
1135 else
1136 rc = ops->write_emulated(
1137 (unsigned long)c->dst.ptr,
1138 &c->dst.val,
1139 c->dst.bytes,
1140 ctxt->vcpu);
1141 if (rc != 0)
1142 return rc;
a01af5ec
LV		 1143 break;
1144 case OP_NONE:
1145 /* no writeback */
1146 break;
8cdbd2c9
LV		 1147 default:
1148 break;
1149 }
1150 return 0;
1151}
1152
8b4caf66 1153int
1be3aa47 1154x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66
LV		 1155{
1156 unsigned long cr2 = ctxt->cr2;
8b4caf66 1157 u64 msr_data;
3427318f 1158 unsigned long saved_eip = 0;
8b4caf66 1159 struct decode_cache *c = &ctxt->decode;
1be3aa47 1160 int rc = 0;
8b4caf66 1161
3427318f
LV		 1162 /* Shadow copy of register state. Committed on successful emulation.
1163 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1164 * modify them.
1165 */
1166
1167 memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs);
1168 saved_eip = c->eip;
1169
c7e75a3d 1170 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
8b4caf66
LV		 1171 cr2 = c->modrm_ea;
1172
1173 if (c->src.type == OP_MEM) {
1174 c->src.ptr = (unsigned long *)cr2;
1175 c->src.val = 0;
d77c26fc
MD		 1176 rc = ops->read_emulated((unsigned long)c->src.ptr,
1177 &c->src.val,
1178 c->src.bytes,
1179 ctxt->vcpu);
1180 if (rc != 0)
8b4caf66
LV		 1181 goto done;
1182 c->src.orig_val = c->src.val;
1183 }
1184
1185 if ((c->d & DstMask) == ImplicitOps)
1186 goto special_insn;
1187
1188
1189 if (c->dst.type == OP_MEM) {
1190 c->dst.ptr = (unsigned long *)cr2;
1191 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1192 c->dst.val = 0;
e4e03ded
LV		 1193 if (c->d & BitOp) {
1194 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1195
e4e03ded
LV		 1196 c->dst.ptr = (void *)c->dst.ptr +
1197 (c->src.val & mask) / 8;
038e51de 1198 }
e4e03ded
LV		 1199 if (!(c->d & Mov) &&
1200 /* optimisation - avoid slow emulated read */
1201 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1202 &c->dst.val,
1203 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1204 goto done;
038e51de 1205 }
e4e03ded 1206 c->dst.orig_val = c->dst.val;
038e51de 1207
e4e03ded 1208 if (c->twobyte)
6aa8b732
AK		 1209 goto twobyte_insn;
1210
e4e03ded 1211 switch (c->b) {
6aa8b732
AK		 1212 case 0x00 ... 0x05:
1213 add: /* add */
05f086f8 1214 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1215 break;
1216 case 0x08 ... 0x0d:
1217 or: /* or */
05f086f8 1218 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1219 break;
1220 case 0x10 ... 0x15:
1221 adc: /* adc */
05f086f8 1222 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1223 break;
1224 case 0x18 ... 0x1d:
1225 sbb: /* sbb */
05f086f8 1226 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1227 break;
19eb938e 1228 case 0x20 ... 0x23:
6aa8b732 1229 and: /* and */
05f086f8 1230 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1231 break;
19eb938e 1232 case 0x24: /* and al imm8 */
e4e03ded
LV		 1233 c->dst.type = OP_REG;
1234 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1235 c->dst.val = *(u8 *)c->dst.ptr;
1236 c->dst.bytes = 1;
1237 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1238 goto and;
1239 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1240 c->dst.type = OP_REG;
1241 c->dst.bytes = c->op_bytes;
1242 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1243 if (c->op_bytes == 2)
1244 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1245 else
e4e03ded
LV		 1246 c->dst.val = *(u32 *)c->dst.ptr;
1247 c->dst.orig_val = c->dst.val;
19eb938e 1248 goto and;
6aa8b732
AK		 1249 case 0x28 ... 0x2d:
1250 sub: /* sub */
05f086f8 1251 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1252 break;
1253 case 0x30 ... 0x35:
1254 xor: /* xor */
05f086f8 1255 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1256 break;
1257 case 0x38 ... 0x3d:
1258 cmp: /* cmp */
05f086f8 1259 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1260 break;
1261 case 0x63: /* movsxd */
8b4caf66 1262 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1263 goto cannot_emulate;
e4e03ded 1264 c->dst.val = (s32) c->src.val;
6aa8b732
AK		 1265 break;
1266 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1267 switch (c->modrm_reg) {
6aa8b732
AK		 1268 case 0:
1269 goto add;
1270 case 1:
1271 goto or;
1272 case 2:
1273 goto adc;
1274 case 3:
1275 goto sbb;
1276 case 4:
1277 goto and;
1278 case 5:
1279 goto sub;
1280 case 6:
1281 goto xor;
1282 case 7:
1283 goto cmp;
1284 }
1285 break;
1286 case 0x84 ... 0x85:
05f086f8 1287 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1288 break;
1289 case 0x86 ... 0x87: /* xchg */
1290 /* Write back the register source. */
e4e03ded 1291 switch (c->dst.bytes) {
6aa8b732 1292 case 1:
e4e03ded 1293 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1294 break;
1295 case 2:
e4e03ded 1296 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1297 break;
1298 case 4:
e4e03ded 1299 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1300 break; /* 64b reg: zero-extend */
1301 case 8:
e4e03ded 1302 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1303 break;
1304 }
1305 /*
1306 * Write back the memory destination with implicit LOCK
1307 * prefix.
1308 */
e4e03ded
LV		 1309 c->dst.val = c->src.val;
1310 c->lock_prefix = 1;
6aa8b732 1311 break;
6aa8b732 1312 case 0x88 ... 0x8b: /* mov */
7de75248 1313 goto mov;
7e0b54b1 1314 case 0x8d: /* lea r16/r32, m */
e4e03ded 1315 c->dst.val = c->modrm_val;
7e0b54b1 1316 break;
6aa8b732 1317 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1318 rc = emulate_grp1a(ctxt, ops);
1319 if (rc != 0)
6aa8b732 1320 goto done;
6aa8b732 1321 break;
7de75248 1322 case 0xa0 ... 0xa1: /* mov */
e4e03ded
LV		 1323 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1324 c->dst.val = c->src.val;
7de75248
NK		 1325 break;
1326 case 0xa2 ... 0xa3: /* mov */
e4e03ded 1327 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
7de75248 1328 break;
6aa8b732 1329 case 0xc0 ... 0xc1:
05f086f8 1330 emulate_grp2(ctxt);
6aa8b732 1331 break;
7de75248
NK		 1332 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1333 mov:
e4e03ded 1334 c->dst.val = c->src.val;
7de75248 1335 break;
6aa8b732 1336 case 0xd0 ... 0xd1: /* Grp2 */
e4e03ded 1337 c->src.val = 1;
05f086f8 1338 emulate_grp2(ctxt);
8cdbd2c9 1339 break;
6aa8b732 1340 case 0xd2 ... 0xd3: /* Grp2 */
e4e03ded 1341 c->src.val = c->regs[VCPU_REGS_RCX];
05f086f8 1342 emulate_grp2(ctxt);
8cdbd2c9 1343 break;
6aa8b732 1344 case 0xf6 ... 0xf7: /* Grp3 */
05f086f8 1345 rc = emulate_grp3(ctxt, ops);
8cdbd2c9
LV		 1346 if (rc != 0)
1347 goto done;
6aa8b732
AK		 1348 break;
1349 case 0xfe ... 0xff: /* Grp4/Grp5 */
a01af5ec 1350 rc = emulate_grp45(ctxt, ops);
8cdbd2c9
LV		 1351 if (rc != 0)
1352 goto done;
6aa8b732
AK		 1353 break;
1354 }
1355
1356writeback:
a01af5ec
LV		 1357 rc = writeback(ctxt, ops);
1358 if (rc != 0)
1359 goto done;
6aa8b732
AK		 1360
1361 /* Commit shadow register state. */
e4e03ded 1362 memcpy(ctxt->vcpu->regs, c->regs, sizeof c->regs);
e4e03ded 1363 ctxt->vcpu->rip = c->eip;
6aa8b732
AK		 1364
1365done:
3427318f
LV		 1366 if (rc == X86EMUL_UNHANDLEABLE) {
1367 c->eip = saved_eip;
1368 return -1;
1369 }
1370 return 0;
6aa8b732
AK		 1371
1372special_insn:
e4e03ded 1373 if (c->twobyte)
6aa8b732 1374 goto twobyte_special_insn;
e4e03ded 1375 switch (c->b) {
d77a2507
NK		 1376 case 0x40 ... 0x47: /* inc r16/r32 */
1377 c->dst.bytes = c->op_bytes;
1378 c->dst.ptr = (unsigned long *)&c->regs[c->b & 0x7];
1379 c->dst.val = *c->dst.ptr;
1380 emulate_1op("inc", c->dst, ctxt->eflags);
1381 break;
1382 case 0x48 ... 0x4f: /* dec r16/r32 */
1383 c->dst.bytes = c->op_bytes;
1384 c->dst.ptr = (unsigned long *)&c->regs[c->b & 0x7];
1385 c->dst.val = *c->dst.ptr;
1386 emulate_1op("dec", c->dst, ctxt->eflags);
1387 break;
7e778161 1388 case 0x50 ... 0x57: /* push reg */
e4e03ded
LV		 1389 if (c->op_bytes == 2)
1390 c->src.val = (u16) c->regs[c->b & 0x7];
7e778161 1391 else
e4e03ded
LV		 1392 c->src.val = (u32) c->regs[c->b & 0x7];
1393 c->dst.type = OP_MEM;
1394 c->dst.bytes = c->op_bytes;
1395 c->dst.val = c->src.val;
1396 register_address_increment(c->regs[VCPU_REGS_RSP],
1397 -c->op_bytes);
1398 c->dst.ptr = (void *) register_address(
1399 ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
7e778161 1400 break;
7de75248 1401 case 0x58 ... 0x5f: /* pop reg */
8cdbd2c9 1402 c->dst.ptr = (unsigned long *)&c->regs[c->b & 0x7];
7de75248
NK		 1403 pop_instruction:
1404 if ((rc = ops->read_std(register_address(ctxt->ss_base,
e4e03ded
LV		 1405 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1406 c->op_bytes, ctxt->vcpu)) != 0)
7de75248
NK		 1407 goto done;
1408
e4e03ded
LV		 1409 register_address_increment(c->regs[VCPU_REGS_RSP],
1410 c->op_bytes);
a01af5ec 1411 c->dst.type = OP_NONE; /* Disable writeback. */
7de75248 1412 break;
1e35d3c4 1413 case 0x6a: /* push imm8 */
e4e03ded
LV		 1414 c->src.val = 0L;
1415 c->src.val = insn_fetch(s8, 1, c->eip);
8cdbd2c9 1416 emulate_push(ctxt);
1e35d3c4 1417 break;
e70669ab
LV		 1418 case 0x6c: /* insb */
1419 case 0x6d: /* insw/insd */
3090dd73 1420 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e4e03ded
LV		 1421 1,
1422 (c->d & ByteOp) ? 1 : c->op_bytes,
1423 c->rep_prefix ?
1424 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
05f086f8 1425 (ctxt->eflags & EFLG_DF),
e70669ab 1426 register_address(ctxt->es_base,
e4e03ded
LV		 1427 c->regs[VCPU_REGS_RDI]),
1428 c->rep_prefix,
3427318f
LV		 1429 c->regs[VCPU_REGS_RDX]) == 0) {
1430 c->eip = saved_eip;
e70669ab 1431 return -1;
3427318f 1432 }
e70669ab
LV		 1433 return 0;
1434 case 0x6e: /* outsb */
1435 case 0x6f: /* outsw/outsd */
3090dd73 1436 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e4e03ded
LV		 1437 0,
1438 (c->d & ByteOp) ? 1 : c->op_bytes,
1439 c->rep_prefix ?
1440 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
05f086f8 1441 (ctxt->eflags & EFLG_DF),
e4e03ded
LV		 1442 register_address(c->override_base ?
1443 *c->override_base :
1444 ctxt->ds_base,
1445 c->regs[VCPU_REGS_RSI]),
1446 c->rep_prefix,
3427318f
LV		 1447 c->regs[VCPU_REGS_RDX]) == 0) {
1448 c->eip = saved_eip;
e70669ab 1449 return -1;
3427318f 1450 }
e70669ab 1451 return 0;
55bebde4 1452 case 0x70 ... 0x7f: /* jcc (short) */ {
e4e03ded 1453 int rel = insn_fetch(s8, 1, c->eip);
55bebde4 1454
05f086f8 1455 if (test_cc(c->b, ctxt->eflags))
55bebde4
NK		 1456 JMP_REL(rel);
1457 break;
1458 }
fd2a7608 1459 case 0x9c: /* pushf */
05f086f8 1460 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1461 emulate_push(ctxt);
1462 break;
535eabcf 1463 case 0x9d: /* popf */
05f086f8 1464 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1465 goto pop_instruction;
7de75248 1466 case 0xc3: /* ret */
e4e03ded 1467 c->dst.ptr = &c->eip;
7de75248
NK		 1468 goto pop_instruction;
1469 case 0xf4: /* hlt */
1470 ctxt->vcpu->halt_request = 1;
1471 goto done;
b284be57
NK		 1472 case 0xf5: /* cmc */
1473 /* complement carry flag from eflags reg */
1474 ctxt->eflags ^= EFLG_CF;
1475 c->dst.type = OP_NONE; /* Disable writeback. */
1476 break;
1477 case 0xf8: /* clc */
1478 ctxt->eflags &= ~EFLG_CF;
1479 c->dst.type = OP_NONE; /* Disable writeback. */
1480 break;
1481 case 0xfa: /* cli */
1482 ctxt->eflags &= ~X86_EFLAGS_IF;
1483 c->dst.type = OP_NONE; /* Disable writeback. */
1484 break;
1485 case 0xfb: /* sti */
1486 ctxt->eflags |= X86_EFLAGS_IF;
1487 c->dst.type = OP_NONE; /* Disable writeback. */
1488 break;
e70669ab 1489 }
e4e03ded
LV		 1490 if (c->rep_prefix) {
1491 if (c->regs[VCPU_REGS_RCX] == 0) {
1492 ctxt->vcpu->rip = c->eip;
6aa8b732
AK		 1493 goto done;
1494 }
e4e03ded
LV		 1495 c->regs[VCPU_REGS_RCX]--;
1496 c->eip = ctxt->vcpu->rip;
6aa8b732 1497 }
e4e03ded 1498 switch (c->b) {
6aa8b732 1499 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1500 c->dst.type = OP_MEM;
1501 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1502 c->dst.ptr = (unsigned long *)register_address(
1503 ctxt->es_base,
1504 c->regs[VCPU_REGS_RDI]);
6aa8b732 1505 if ((rc = ops->read_emulated(register_address(
e4e03ded
LV		 1506 c->override_base ? *c->override_base :
1507 ctxt->ds_base,
1508 c->regs[VCPU_REGS_RSI]),
1509 &c->dst.val,
1510 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1511 goto done;
e4e03ded 1512 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1513 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded
LV		 1514 : c->dst.bytes);
1515 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1516 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1517 : c->dst.bytes);
6aa8b732
AK		 1518 break;
1519 case 0xa6 ... 0xa7: /* cmps */
1520 DPRINTF("Urk! I don't handle CMPS.\n");
1521 goto cannot_emulate;
1522 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1523 c->dst.type = OP_MEM;
1524 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1525 c->dst.ptr = (unsigned long *)cr2;
1526 c->dst.val = c->regs[VCPU_REGS_RAX];
1527 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1528 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1529 : c->dst.bytes);
6aa8b732
AK		 1530 break;
1531 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1532 c->dst.type = OP_REG;
1533 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1534 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1535 if ((rc = ops->read_emulated(cr2, &c->dst.val,
1536 c->dst.bytes,
cebff02b 1537 ctxt->vcpu)) != 0)
6aa8b732 1538 goto done;
e4e03ded 1539 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1540 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1541 : c->dst.bytes);
6aa8b732
AK		 1542 break;
1543 case 0xae ... 0xaf: /* scas */
1544 DPRINTF("Urk! I don't handle SCAS.\n");
1545 goto cannot_emulate;
1a52e051
NK		 1546 case 0xe8: /* call (near) */ {
1547 long int rel;
e4e03ded 1548 switch (c->op_bytes) {
1a52e051 1549 case 2:
e4e03ded 1550 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1551 break;
1552 case 4:
e4e03ded 1553 rel = insn_fetch(s32, 4, c->eip);
1a52e051
NK		 1554 break;
1555 case 8:
e4e03ded 1556 rel = insn_fetch(s64, 8, c->eip);
1a52e051
NK		 1557 break;
1558 default:
1559 DPRINTF("Call: Invalid op_bytes\n");
1560 goto cannot_emulate;
1561 }
e4e03ded 1562 c->src.val = (unsigned long) c->eip;
1a52e051 1563 JMP_REL(rel);
e4e03ded 1564 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1565 emulate_push(ctxt);
1566 break;
1a52e051
NK		 1567 }
1568 case 0xe9: /* jmp rel */
1569 case 0xeb: /* jmp rel short */
e4e03ded 1570 JMP_REL(c->src.val);
a01af5ec 1571 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051
NK		 1572 break;
1573
7f0aaee0 1574
6aa8b732
AK		 1575 }
1576 goto writeback;
1577
1578twobyte_insn:
e4e03ded 1579 switch (c->b) {
6aa8b732 1580 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1581 switch (c->modrm_reg) {
6aa8b732
AK		 1582 u16 size;
1583 unsigned long address;
1584
aca7f966 1585 case 0: /* vmcall */
e4e03ded 1586 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1587 goto cannot_emulate;
1588
7aa81cc0
AL		 1589 rc = kvm_fix_hypercall(ctxt->vcpu);
1590 if (rc)
1591 goto done;
1592
1593 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1594 break;
6aa8b732 1595 case 2: /* lgdt */
e4e03ded
LV		 1596 rc = read_descriptor(ctxt, ops, c->src.ptr,
1597 &size, &address, c->op_bytes);
6aa8b732
AK		 1598 if (rc)
1599 goto done;
1600 realmode_lgdt(ctxt->vcpu, size, address);
1601 break;
aca7f966 1602 case 3: /* lidt/vmmcall */
e4e03ded 1603 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1604 rc = kvm_fix_hypercall(ctxt->vcpu);
1605 if (rc)
1606 goto done;
1607 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1608 } else {
e4e03ded 1609 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1610 &size, &address,
e4e03ded 1611 c->op_bytes);
aca7f966
AL		 1612 if (rc)
1613 goto done;
1614 realmode_lidt(ctxt->vcpu, size, address);
1615 }
6aa8b732
AK		 1616 break;
1617 case 4: /* smsw */
e4e03ded 1618 if (c->modrm_mod != 3)
6aa8b732 1619 goto cannot_emulate;
e4e03ded 1620 *(u16 *)&c->regs[c->modrm_rm]
6aa8b732
AK		 1621 = realmode_get_cr(ctxt->vcpu, 0);
1622 break;
1623 case 6: /* lmsw */
e4e03ded 1624 if (c->modrm_mod != 3)
6aa8b732 1625 goto cannot_emulate;
05f086f8
LV		 1626 realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val,
1627 &ctxt->eflags);
6aa8b732
AK		 1628 break;
1629 case 7: /* invlpg*/
1630 emulate_invlpg(ctxt->vcpu, cr2);
1631 break;
1632 default:
1633 goto cannot_emulate;
1634 }
a01af5ec
LV		 1635 /* Disable writeback. */
1636 c->dst.type = OP_NONE;
6aa8b732
AK		 1637 break;
1638 case 0x21: /* mov from dr to reg */
e4e03ded 1639 if (c->modrm_mod != 3)
6aa8b732 1640 goto cannot_emulate;
8cdbd2c9 1641 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1642 if (rc)
1643 goto cannot_emulate;
1644 c->dst.type = OP_NONE; /* no writeback */
6aa8b732
AK		 1645 break;
1646 case 0x23: /* mov from reg to dr */
e4e03ded 1647 if (c->modrm_mod != 3)
6aa8b732 1648 goto cannot_emulate;
e4e03ded
LV		 1649 rc = emulator_set_dr(ctxt, c->modrm_reg,
1650 c->regs[c->modrm_rm]);
a01af5ec
LV		 1651 if (rc)
1652 goto cannot_emulate;
1653 c->dst.type = OP_NONE; /* no writeback */
6aa8b732
AK		 1654 break;
1655 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1656 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1657 if (!test_cc(c->b, ctxt->eflags))
1658 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1659 break;
7de75248
NK		 1660 case 0xa3:
1661 bt: /* bt */
e4f8e039 1662 c->dst.type = OP_NONE;
e4e03ded
LV		 1663 /* only subword offset */
1664 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1665 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1666 break;
1667 case 0xab:
1668 bts: /* bts */
e4e03ded
LV		 1669 /* only subword offset */
1670 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1671 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1672 break;
6aa8b732
AK		 1673 case 0xb0 ... 0xb1: /* cmpxchg */
1674 /*
1675 * Save real source value, then compare EAX against
1676 * destination.
1677 */
e4e03ded
LV		 1678 c->src.orig_val = c->src.val;
1679 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1680 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1681 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1682 /* Success: write back to memory. */
e4e03ded 1683 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1684 } else {
1685 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1686 c->dst.type = OP_REG;
1687 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1688 }
1689 break;
6aa8b732
AK		 1690 case 0xb3:
1691 btr: /* btr */
e4e03ded
LV		 1692 /* only subword offset */
1693 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1694 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1695 break;
6aa8b732 1696 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1697 c->dst.bytes = c->op_bytes;
1698 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1699 : (u16) c->src.val;
6aa8b732 1700 break;
6aa8b732 1701 case 0xba: /* Grp8 */
e4e03ded 1702 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1703 case 0:
1704 goto bt;
1705 case 1:
1706 goto bts;
1707 case 2:
1708 goto btr;
1709 case 3:
1710 goto btc;
1711 }
1712 break;
7de75248
NK		 1713 case 0xbb:
1714 btc: /* btc */
e4e03ded
LV		 1715 /* only subword offset */
1716 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1717 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 1718 break;
6aa8b732 1719 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 1720 c->dst.bytes = c->op_bytes;
1721 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1722 (s16) c->src.val;
6aa8b732 1723 break;
a012e65a 1724 case 0xc3: /* movnti */
e4e03ded
LV		 1725 c->dst.bytes = c->op_bytes;
1726 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1727 (u64) c->src.val;
a012e65a 1728 break;
6aa8b732
AK		 1729 }
1730 goto writeback;
1731
1732twobyte_special_insn:
e4e03ded 1733 switch (c->b) {
7de75248
NK		 1734 case 0x06:
1735 emulate_clts(ctxt->vcpu);
1736 break;
651a3e29
AK		 1737 case 0x08: /* invd */
1738 break;
687fdbfe
AK		 1739 case 0x09: /* wbinvd */
1740 break;
6aa8b732
AK		 1741 case 0x0d: /* GrpP (prefetch) */
1742 case 0x18: /* Grp16 (prefetch/nop) */
1743 break;
6aa8b732 1744 case 0x20: /* mov cr, reg */
e4e03ded 1745 if (c->modrm_mod != 3)
6aa8b732 1746 goto cannot_emulate;
e4e03ded
LV		 1747 c->regs[c->modrm_rm] =
1748 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
6aa8b732
AK		 1749 break;
1750 case 0x22: /* mov reg, cr */
e4e03ded 1751 if (c->modrm_mod != 3)
6aa8b732 1752 goto cannot_emulate;
e4e03ded 1753 realmode_set_cr(ctxt->vcpu,
05f086f8 1754 c->modrm_reg, c->modrm_val, &ctxt->eflags);
6aa8b732 1755 break;
35f3f286
AK		 1756 case 0x30:
1757 /* wrmsr */
e4e03ded
LV		 1758 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1759 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1760 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
35f3f286 1761 if (rc) {
cbdd1bea 1762 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
e4e03ded 1763 c->eip = ctxt->vcpu->rip;
35f3f286
AK		 1764 }
1765 rc = X86EMUL_CONTINUE;
1766 break;
1767 case 0x32:
1768 /* rdmsr */
8cdbd2c9 1769 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
35f3f286 1770 if (rc) {
cbdd1bea 1771 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
e4e03ded 1772 c->eip = ctxt->vcpu->rip;
35f3f286 1773 } else {
e4e03ded
LV		 1774 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1775 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
35f3f286
AK		 1776 }
1777 rc = X86EMUL_CONTINUE;
1778 break;
bbe9abbd
NK		 1779 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1780 long int rel;
1781
e4e03ded 1782 switch (c->op_bytes) {
bbe9abbd 1783 case 2:
e4e03ded 1784 rel = insn_fetch(s16, 2, c->eip);
bbe9abbd
NK		 1785 break;
1786 case 4:
e4e03ded 1787 rel = insn_fetch(s32, 4, c->eip);
bbe9abbd
NK		 1788 break;
1789 case 8:
e4e03ded 1790 rel = insn_fetch(s64, 8, c->eip);
bbe9abbd
NK		 1791 break;
1792 default:
1793 DPRINTF("jnz: Invalid op_bytes\n");
1794 goto cannot_emulate;
1795 }
05f086f8 1796 if (test_cc(c->b, ctxt->eflags))
bbe9abbd
NK		 1797 JMP_REL(rel);
1798 break;
1799 }
6aa8b732 1800 case 0xc7: /* Grp9 (cmpxchg8b) */
05f086f8 1801 rc = emulate_grp9(ctxt, ops, cr2);
8cdbd2c9
LV		 1802 if (rc != 0)
1803 goto done;
1804 break;
6aa8b732 1805 }
a01af5ec
LV		 1806 /* Disable writeback. */
1807 c->dst.type = OP_NONE;
6aa8b732
AK		 1808 goto writeback;
1809
1810cannot_emulate:
e4e03ded 1811 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 1812 c->eip = saved_eip;
6aa8b732
AK		 1813 return -1;
1814}
Linux kernel - Deliverables
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