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KVM: Use generalized exception queue for injecting #UD
[deliverable/linux.git] / drivers / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732
AK		 27#else
28#include "kvm.h"
34c16eec 29#include "x86.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
32#include "x86_emulate.h"
33#include <linux/module.h>
34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
50#define DstMask (3<<1)
51/* Source operand type. */
52#define SrcNone (0<<3) /* No source operand. */
53#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
54#define SrcReg (1<<3) /* Register operand. */
55#define SrcMem (2<<3) /* Memory operand. */
56#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
57#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
58#define SrcImm (5<<3) /* Immediate operand. */
59#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
60#define SrcMask (7<<3)
61/* Generic ModRM decode. */
62#define ModRM (1<<6)
63/* Destination is only written; never read. */
64#define Mov (1<<7)
038e51de 65#define BitOp (1<<8)
c7e75a3d 66#define MemAbs (1<<9) /* Memory operand is absolute displacement */
b9fa9d6b 67#define String (1<<10) /* String instruction (rep capable) */
6aa8b732 68
c7e75a3d 69static u16 opcode_table[256] = {
6aa8b732
AK		 70 /* 0x00 - 0x07 */
71 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
72 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
73 0, 0, 0, 0,
74 /* 0x08 - 0x0F */
75 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
76 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
77 0, 0, 0, 0,
78 /* 0x10 - 0x17 */
79 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
80 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
81 0, 0, 0, 0,
82 /* 0x18 - 0x1F */
83 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
84 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
85 0, 0, 0, 0,
86 /* 0x20 - 0x27 */
87 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
88 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 89 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 90 /* 0x28 - 0x2F */
91 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
92 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
93 0, 0, 0, 0,
94 /* 0x30 - 0x37 */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
97 0, 0, 0, 0,
98 /* 0x38 - 0x3F */
99 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
100 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
101 0, 0, 0, 0,
d77a2507 102 /* 0x40 - 0x47 */
33615aa9 103 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 104 /* 0x48 - 0x4F */
33615aa9 105 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 106 /* 0x50 - 0x57 */
33615aa9 107 SrcReg, SrcReg, SrcReg, SrcReg, SrcReg, SrcReg, SrcReg, SrcReg,
7f0aaee0 108 /* 0x58 - 0x5F */
33615aa9 109 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7d316911 110 /* 0x60 - 0x67 */
6aa8b732 111 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 112 0, 0, 0, 0,
113 /* 0x68 - 0x6F */
114 0, 0, ImplicitOps|Mov, 0,
e70669ab
LV		 115 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
116 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 117 /* 0x70 - 0x77 */
118 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
119 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
120 /* 0x78 - 0x7F */
121 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
122 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 123 /* 0x80 - 0x87 */
124 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
125 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
126 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
127 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
128 /* 0x88 - 0x8F */
129 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
130 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
7e0b54b1 131 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov,
6aa8b732 132 /* 0x90 - 0x9F */
535eabcf 133 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0,
6aa8b732 134 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 135 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
136 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 137 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
138 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 139 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 140 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
141 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
142 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732
AK		 143 /* 0xB0 - 0xBF */
144 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
145 /* 0xC0 - 0xC7 */
d9413cd7
NK		 146 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
147 0, ImplicitOps, 0, 0,
148 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 149 /* 0xC8 - 0xCF */
150 0, 0, 0, 0, 0, 0, 0, 0,
151 /* 0xD0 - 0xD7 */
152 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
153 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
154 0, 0, 0, 0,
155 /* 0xD8 - 0xDF */
156 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 157 /* 0xE0 - 0xE7 */
158 0, 0, 0, 0, 0, 0, 0, 0,
159 /* 0xE8 - 0xEF */
f6eed391 160 ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0,
6aa8b732
AK		 161 /* 0xF0 - 0xF7 */
162 0, 0, 0, 0,
b284be57 163 ImplicitOps, ImplicitOps,
72d6e5a0 164 ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
6aa8b732 165 /* 0xF8 - 0xFF */
b284be57 166 ImplicitOps, 0, ImplicitOps, ImplicitOps,
6aa8b732
AK		 167 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
168};
169
038e51de 170static u16 twobyte_table[256] = {
6aa8b732
AK		 171 /* 0x00 - 0x0F */
172 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 173 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 174 /* 0x10 - 0x1F */
175 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
176 /* 0x20 - 0x2F */
177 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
178 0, 0, 0, 0, 0, 0, 0, 0,
179 /* 0x30 - 0x3F */
35f3f286 180 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 181 /* 0x40 - 0x47 */
182 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
183 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
184 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
185 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
186 /* 0x48 - 0x4F */
187 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
188 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
189 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
190 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
191 /* 0x50 - 0x5F */
192 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
193 /* 0x60 - 0x6F */
194 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
195 /* 0x70 - 0x7F */
196 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
197 /* 0x80 - 0x8F */
bbe9abbd
NK		 198 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
199 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
200 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
201 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 202 /* 0x90 - 0x9F */
203 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
204 /* 0xA0 - 0xA7 */
038e51de 205 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 206 /* 0xA8 - 0xAF */
038e51de 207 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 208 /* 0xB0 - 0xB7 */
209 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 210 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 211 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
212 DstReg | SrcMem16 | ModRM | Mov,
213 /* 0xB8 - 0xBF */
038e51de 214 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 215 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
216 DstReg | SrcMem16 | ModRM | Mov,
217 /* 0xC0 - 0xCF */
a012e65a
SY		 218 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
219 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 220 /* 0xD0 - 0xDF */
221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
222 /* 0xE0 - 0xEF */
223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
224 /* 0xF0 - 0xFF */
225 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
226};
227
6aa8b732
AK		 228/* EFLAGS bit definitions. */
229#define EFLG_OF (1<<11)
230#define EFLG_DF (1<<10)
231#define EFLG_SF (1<<7)
232#define EFLG_ZF (1<<6)
233#define EFLG_AF (1<<4)
234#define EFLG_PF (1<<2)
235#define EFLG_CF (1<<0)
236
237/*
238 * Instruction emulation:
239 * Most instructions are emulated directly via a fragment of inline assembly
240 * code. This allows us to save/restore EFLAGS and thus very easily pick up
241 * any modified flags.
242 */
243
05b3e0c2 244#if defined(CONFIG_X86_64)
6aa8b732
AK		 245#define _LO32 "k" /* force 32-bit operand */
246#define _STK "%%rsp" /* stack pointer */
247#elif defined(__i386__)
248#define _LO32 "" /* force 32-bit operand */
249#define _STK "%%esp" /* stack pointer */
250#endif
251
252/*
253 * These EFLAGS bits are restored from saved value during emulation, and
254 * any changes are written back to the saved value after emulation.
255 */
256#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
257
258/* Before executing instruction: restore necessary bits in EFLAGS. */
259#define _PRE_EFLAGS(_sav, _msk, _tmp) \
260 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \
261 "push %"_sav"; " \
262 "movl %"_msk",%"_LO32 _tmp"; " \
263 "andl %"_LO32 _tmp",("_STK"); " \
264 "pushf; " \
265 "notl %"_LO32 _tmp"; " \
266 "andl %"_LO32 _tmp",("_STK"); " \
267 "pop %"_tmp"; " \
268 "orl %"_LO32 _tmp",("_STK"); " \
269 "popf; " \
270 /* _sav &= ~msk; */ \
271 "movl %"_msk",%"_LO32 _tmp"; " \
272 "notl %"_LO32 _tmp"; " \
273 "andl %"_LO32 _tmp",%"_sav"; "
274
275/* After executing instruction: write-back necessary bits in EFLAGS. */
276#define _POST_EFLAGS(_sav, _msk, _tmp) \
277 /* _sav |= EFLAGS & _msk; */ \
278 "pushf; " \
279 "pop %"_tmp"; " \
280 "andl %"_msk",%"_LO32 _tmp"; " \
281 "orl %"_LO32 _tmp",%"_sav"; "
282
283/* Raw emulation: instruction has two explicit operands. */
284#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
285 do { \
286 unsigned long _tmp; \
287 \
288 switch ((_dst).bytes) { \
289 case 2: \
290 __asm__ __volatile__ ( \
d77c26fc 291 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 292 _op"w %"_wx"3,%1; " \
d77c26fc 293 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 294 : "=m" (_eflags), "=m" ((_dst).val), \
295 "=&r" (_tmp) \
d77c26fc 296 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 297 break; \
298 case 4: \
299 __asm__ __volatile__ ( \
d77c26fc 300 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 301 _op"l %"_lx"3,%1; " \
d77c26fc 302 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 303 : "=m" (_eflags), "=m" ((_dst).val), \
304 "=&r" (_tmp) \
d77c26fc 305 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 306 break; \
307 case 8: \
308 __emulate_2op_8byte(_op, _src, _dst, \
309 _eflags, _qx, _qy); \
310 break; \
311 } \
312 } while (0)
313
314#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
315 do { \
316 unsigned long _tmp; \
d77c26fc 317 switch ((_dst).bytes) { \
6aa8b732
AK		 318 case 1: \
319 __asm__ __volatile__ ( \
d77c26fc 320 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 321 _op"b %"_bx"3,%1; " \
d77c26fc 322 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 323 : "=m" (_eflags), "=m" ((_dst).val), \
324 "=&r" (_tmp) \
d77c26fc 325 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 326 break; \
327 default: \
328 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
329 _wx, _wy, _lx, _ly, _qx, _qy); \
330 break; \
331 } \
332 } while (0)
333
334/* Source operand is byte-sized and may be restricted to just %cl. */
335#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
336 __emulate_2op(_op, _src, _dst, _eflags, \
337 "b", "c", "b", "c", "b", "c", "b", "c")
338
339/* Source operand is byte, word, long or quad sized. */
340#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
341 __emulate_2op(_op, _src, _dst, _eflags, \
342 "b", "q", "w", "r", _LO32, "r", "", "r")
343
344/* Source operand is word, long or quad sized. */
345#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
346 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
347 "w", "r", _LO32, "r", "", "r")
348
349/* Instruction has only one explicit operand (no source operand). */
350#define emulate_1op(_op, _dst, _eflags) \
351 do { \
352 unsigned long _tmp; \
353 \
d77c26fc 354 switch ((_dst).bytes) { \
6aa8b732
AK		 355 case 1: \
356 __asm__ __volatile__ ( \
d77c26fc 357 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 358 _op"b %1; " \
d77c26fc 359 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 360 : "=m" (_eflags), "=m" ((_dst).val), \
361 "=&r" (_tmp) \
d77c26fc 362 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 363 break; \
364 case 2: \
365 __asm__ __volatile__ ( \
d77c26fc 366 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 367 _op"w %1; " \
d77c26fc 368 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 369 : "=m" (_eflags), "=m" ((_dst).val), \
370 "=&r" (_tmp) \
d77c26fc 371 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 372 break; \
373 case 4: \
374 __asm__ __volatile__ ( \
d77c26fc 375 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 376 _op"l %1; " \
d77c26fc 377 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 378 : "=m" (_eflags), "=m" ((_dst).val), \
379 "=&r" (_tmp) \
d77c26fc 380 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 381 break; \
382 case 8: \
383 __emulate_1op_8byte(_op, _dst, _eflags); \
384 break; \
385 } \
386 } while (0)
387
388/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 389#if defined(CONFIG_X86_64)
6aa8b732
AK		 390#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
391 do { \
392 __asm__ __volatile__ ( \
d77c26fc 393 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 394 _op"q %"_qx"3,%1; " \
d77c26fc 395 _POST_EFLAGS("0", "4", "2") \
6aa8b732 396 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 397 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 398 } while (0)
399
400#define __emulate_1op_8byte(_op, _dst, _eflags) \
401 do { \
402 __asm__ __volatile__ ( \
d77c26fc 403 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 404 _op"q %1; " \
d77c26fc 405 _POST_EFLAGS("0", "3", "2") \
6aa8b732 406 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 407 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 408 } while (0)
409
410#elif defined(__i386__)
411#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
412#define __emulate_1op_8byte(_op, _dst, _eflags)
413#endif /* __i386__ */
414
415/* Fetch next part of the instruction being emulated. */
416#define insn_fetch(_type, _size, _eip) \
417({ unsigned long _x; \
62266869 418 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 419 if (rc != 0) \
6aa8b732
AK		 420 goto done; \
421 (_eip) += (_size); \
422 (_type)_x; \
423})
424
425/* Access/update address held in a register, based on addressing mode. */
e70669ab 426#define address_mask(reg) \
e4e03ded
LV		 427 ((c->ad_bytes == sizeof(unsigned long)) ? \
428 (reg) : ((reg) & ((1UL << (c->ad_bytes << 3)) - 1)))
6aa8b732 429#define register_address(base, reg) \
e70669ab 430 ((base) + address_mask(reg))
6aa8b732
AK		 431#define register_address_increment(reg, inc) \
432 do { \
433 /* signed type ensures sign extension to long */ \
434 int _inc = (inc); \
e4e03ded 435 if (c->ad_bytes == sizeof(unsigned long)) \
6aa8b732
AK		 436 (reg) += _inc; \
437 else \
e4e03ded
LV		 438 (reg) = ((reg) & \
439 ~((1UL << (c->ad_bytes << 3)) - 1)) | \
440 (((reg) + _inc) & \
441 ((1UL << (c->ad_bytes << 3)) - 1)); \
6aa8b732
AK		 442 } while (0)
443
098c937b
NK		 444#define JMP_REL(rel) \
445 do { \
e4e03ded 446 register_address_increment(c->eip, rel); \
098c937b
NK		 447 } while (0)
448
62266869
AK		 449static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
450 struct x86_emulate_ops *ops,
451 unsigned long linear, u8 *dest)
452{
453 struct fetch_cache *fc = &ctxt->decode.fetch;
454 int rc;
455 int size;
456
457 if (linear < fc->start || linear >= fc->end) {
458 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
459 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
460 if (rc)
461 return rc;
462 fc->start = linear;
463 fc->end = linear + size;
464 }
465 *dest = fc->data[linear - fc->start];
466 return 0;
467}
468
469static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
470 struct x86_emulate_ops *ops,
471 unsigned long eip, void *dest, unsigned size)
472{
473 int rc = 0;
474
475 eip += ctxt->cs_base;
476 while (size--) {
477 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
478 if (rc)
479 return rc;
480 }
481 return 0;
482}
483
1e3c5cb0
RR		 484/*
485 * Given the 'reg' portion of a ModRM byte, and a register block, return a
486 * pointer into the block that addresses the relevant register.
487 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
488 */
489static void *decode_register(u8 modrm_reg, unsigned long *regs,
490 int highbyte_regs)
6aa8b732
AK		 491{
492 void *p;
493
494 p = &regs[modrm_reg];
495 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
496 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
497 return p;
498}
499
500static int read_descriptor(struct x86_emulate_ctxt *ctxt,
501 struct x86_emulate_ops *ops,
502 void *ptr,
503 u16 *size, unsigned long *address, int op_bytes)
504{
505 int rc;
506
507 if (op_bytes == 2)
508 op_bytes = 3;
509 *address = 0;
cebff02b
LV		 510 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
511 ctxt->vcpu);
6aa8b732
AK		 512 if (rc)
513 return rc;
cebff02b
LV		 514 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
515 ctxt->vcpu);
6aa8b732
AK		 516 return rc;
517}
518
bbe9abbd
NK		 519static int test_cc(unsigned int condition, unsigned int flags)
520{
521 int rc = 0;
522
523 switch ((condition & 15) >> 1) {
524 case 0: /* o */
525 rc |= (flags & EFLG_OF);
526 break;
527 case 1: /* b/c/nae */
528 rc |= (flags & EFLG_CF);
529 break;
530 case 2: /* z/e */
531 rc |= (flags & EFLG_ZF);
532 break;
533 case 3: /* be/na */
534 rc |= (flags & (EFLG_CF|EFLG_ZF));
535 break;
536 case 4: /* s */
537 rc |= (flags & EFLG_SF);
538 break;
539 case 5: /* p/pe */
540 rc |= (flags & EFLG_PF);
541 break;
542 case 7: /* le/ng */
543 rc |= (flags & EFLG_ZF);
544 /* fall through */
545 case 6: /* l/nge */
546 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
547 break;
548 }
549
550 /* Odd condition identifiers (lsb == 1) have inverted sense. */
551 return (!!rc ^ (condition & 1));
552}
553
3c118e24
AK		 554static void decode_register_operand(struct operand *op,
555 struct decode_cache *c,
3c118e24
AK		 556 int inhibit_bytereg)
557{
33615aa9 558 unsigned reg = c->modrm_reg;
9f1ef3f8 559 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 560
561 if (!(c->d & ModRM))
562 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 563 op->type = OP_REG;
564 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 565 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 566 op->val = *(u8 *)op->ptr;
567 op->bytes = 1;
568 } else {
33615aa9 569 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 570 op->bytes = c->op_bytes;
571 switch (op->bytes) {
572 case 2:
573 op->val = *(u16 *)op->ptr;
574 break;
575 case 4:
576 op->val = *(u32 *)op->ptr;
577 break;
578 case 8:
579 op->val = *(u64 *) op->ptr;
580 break;
581 }
582 }
583 op->orig_val = op->val;
584}
585
1c73ef66
AK		 586static int decode_modrm(struct x86_emulate_ctxt *ctxt,
587 struct x86_emulate_ops *ops)
588{
589 struct decode_cache *c = &ctxt->decode;
590 u8 sib;
591 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
592 int rc = 0;
593
594 if (c->rex_prefix) {
595 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
596 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
597 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
598 }
599
600 c->modrm = insn_fetch(u8, 1, c->eip);
601 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
602 c->modrm_reg |= (c->modrm & 0x38) >> 3;
603 c->modrm_rm |= (c->modrm & 0x07);
604 c->modrm_ea = 0;
605 c->use_modrm_ea = 1;
606
607 if (c->modrm_mod == 3) {
608 c->modrm_val = *(unsigned long *)
609 decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
610 return rc;
611 }
612
613 if (c->ad_bytes == 2) {
614 unsigned bx = c->regs[VCPU_REGS_RBX];
615 unsigned bp = c->regs[VCPU_REGS_RBP];
616 unsigned si = c->regs[VCPU_REGS_RSI];
617 unsigned di = c->regs[VCPU_REGS_RDI];
618
619 /* 16-bit ModR/M decode. */
620 switch (c->modrm_mod) {
621 case 0:
622 if (c->modrm_rm == 6)
623 c->modrm_ea += insn_fetch(u16, 2, c->eip);
624 break;
625 case 1:
626 c->modrm_ea += insn_fetch(s8, 1, c->eip);
627 break;
628 case 2:
629 c->modrm_ea += insn_fetch(u16, 2, c->eip);
630 break;
631 }
632 switch (c->modrm_rm) {
633 case 0:
634 c->modrm_ea += bx + si;
635 break;
636 case 1:
637 c->modrm_ea += bx + di;
638 break;
639 case 2:
640 c->modrm_ea += bp + si;
641 break;
642 case 3:
643 c->modrm_ea += bp + di;
644 break;
645 case 4:
646 c->modrm_ea += si;
647 break;
648 case 5:
649 c->modrm_ea += di;
650 break;
651 case 6:
652 if (c->modrm_mod != 0)
653 c->modrm_ea += bp;
654 break;
655 case 7:
656 c->modrm_ea += bx;
657 break;
658 }
659 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
660 (c->modrm_rm == 6 && c->modrm_mod != 0))
661 if (!c->override_base)
662 c->override_base = &ctxt->ss_base;
663 c->modrm_ea = (u16)c->modrm_ea;
664 } else {
665 /* 32/64-bit ModR/M decode. */
666 switch (c->modrm_rm) {
667 case 4:
668 case 12:
669 sib = insn_fetch(u8, 1, c->eip);
670 index_reg |= (sib >> 3) & 7;
671 base_reg |= sib & 7;
672 scale = sib >> 6;
673
674 switch (base_reg) {
675 case 5:
676 if (c->modrm_mod != 0)
677 c->modrm_ea += c->regs[base_reg];
678 else
679 c->modrm_ea +=
680 insn_fetch(s32, 4, c->eip);
681 break;
682 default:
683 c->modrm_ea += c->regs[base_reg];
684 }
685 switch (index_reg) {
686 case 4:
687 break;
688 default:
689 c->modrm_ea += c->regs[index_reg] << scale;
690 }
691 break;
692 case 5:
693 if (c->modrm_mod != 0)
694 c->modrm_ea += c->regs[c->modrm_rm];
695 else if (ctxt->mode == X86EMUL_MODE_PROT64)
696 rip_relative = 1;
697 break;
698 default:
699 c->modrm_ea += c->regs[c->modrm_rm];
700 break;
701 }
702 switch (c->modrm_mod) {
703 case 0:
704 if (c->modrm_rm == 5)
705 c->modrm_ea += insn_fetch(s32, 4, c->eip);
706 break;
707 case 1:
708 c->modrm_ea += insn_fetch(s8, 1, c->eip);
709 break;
710 case 2:
711 c->modrm_ea += insn_fetch(s32, 4, c->eip);
712 break;
713 }
714 }
715 if (rip_relative) {
716 c->modrm_ea += c->eip;
717 switch (c->d & SrcMask) {
718 case SrcImmByte:
719 c->modrm_ea += 1;
720 break;
721 case SrcImm:
722 if (c->d & ByteOp)
723 c->modrm_ea += 1;
724 else
725 if (c->op_bytes == 8)
726 c->modrm_ea += 4;
727 else
728 c->modrm_ea += c->op_bytes;
729 }
730 }
731done:
732 return rc;
733}
734
735static int decode_abs(struct x86_emulate_ctxt *ctxt,
736 struct x86_emulate_ops *ops)
737{
738 struct decode_cache *c = &ctxt->decode;
739 int rc = 0;
740
741 switch (c->ad_bytes) {
742 case 2:
743 c->modrm_ea = insn_fetch(u16, 2, c->eip);
744 break;
745 case 4:
746 c->modrm_ea = insn_fetch(u32, 4, c->eip);
747 break;
748 case 8:
749 c->modrm_ea = insn_fetch(u64, 8, c->eip);
750 break;
751 }
752done:
753 return rc;
754}
755
6aa8b732 756int
8b4caf66 757x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 758{
e4e03ded 759 struct decode_cache *c = &ctxt->decode;
6aa8b732 760 int rc = 0;
6aa8b732 761 int mode = ctxt->mode;
f21b8bf4 762 int def_op_bytes, def_ad_bytes;
6aa8b732
AK		 763
764 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 765
e4e03ded
LV		 766 memset(c, 0, sizeof(struct decode_cache));
767 c->eip = ctxt->vcpu->rip;
768 memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs);
6aa8b732
AK		 769
770 switch (mode) {
771 case X86EMUL_MODE_REAL:
772 case X86EMUL_MODE_PROT16:
f21b8bf4 773 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 774 break;
775 case X86EMUL_MODE_PROT32:
f21b8bf4 776 def_op_bytes = def_ad_bytes = 4;
6aa8b732 777 break;
05b3e0c2 778#ifdef CONFIG_X86_64
6aa8b732 779 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 780 def_op_bytes = 4;
781 def_ad_bytes = 8;
6aa8b732
AK		 782 break;
783#endif
784 default:
785 return -1;
786 }
787
f21b8bf4
AK		 788 c->op_bytes = def_op_bytes;
789 c->ad_bytes = def_ad_bytes;
790
6aa8b732 791 /* Legacy prefixes. */
b4c6abfe 792 for (;;) {
e4e03ded 793 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 794 case 0x66: /* operand-size override */
f21b8bf4
AK		 795 /* switch between 2/4 bytes */
796 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 797 break;
798 case 0x67: /* address-size override */
799 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 800 /* switch between 4/8 bytes */
f21b8bf4 801 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 802 else
e4e03ded 803 /* switch between 2/4 bytes */
f21b8bf4 804 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732
AK		 805 break;
806 case 0x2e: /* CS override */
e4e03ded 807 c->override_base = &ctxt->cs_base;
6aa8b732
AK		 808 break;
809 case 0x3e: /* DS override */
e4e03ded 810 c->override_base = &ctxt->ds_base;
6aa8b732
AK		 811 break;
812 case 0x26: /* ES override */
e4e03ded 813 c->override_base = &ctxt->es_base;
6aa8b732
AK		 814 break;
815 case 0x64: /* FS override */
e4e03ded 816 c->override_base = &ctxt->fs_base;
6aa8b732
AK		 817 break;
818 case 0x65: /* GS override */
e4e03ded 819 c->override_base = &ctxt->gs_base;
6aa8b732
AK		 820 break;
821 case 0x36: /* SS override */
e4e03ded 822 c->override_base = &ctxt->ss_base;
6aa8b732 823 break;
b4c6abfe
LV		 824 case 0x40 ... 0x4f: /* REX */
825 if (mode != X86EMUL_MODE_PROT64)
826 goto done_prefixes;
33615aa9 827 c->rex_prefix = c->b;
b4c6abfe 828 continue;
6aa8b732 829 case 0xf0: /* LOCK */
e4e03ded 830 c->lock_prefix = 1;
6aa8b732 831 break;
ae6200ba 832 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 833 c->rep_prefix = REPNE_PREFIX;
834 break;
6aa8b732 835 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 836 c->rep_prefix = REPE_PREFIX;
6aa8b732 837 break;
6aa8b732
AK		 838 default:
839 goto done_prefixes;
840 }
b4c6abfe
LV		 841
842 /* Any legacy prefix after a REX prefix nullifies its effect. */
843
33615aa9 844 c->rex_prefix = 0;
6aa8b732
AK		 845 }
846
847done_prefixes:
848
849 /* REX prefix. */
1c73ef66 850 if (c->rex_prefix)
33615aa9 851 if (c->rex_prefix & 8)
e4e03ded 852 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 853
854 /* Opcode byte(s). */
e4e03ded
LV		 855 c->d = opcode_table[c->b];
856 if (c->d == 0) {
6aa8b732 857 /* Two-byte opcode? */
e4e03ded
LV		 858 if (c->b == 0x0f) {
859 c->twobyte = 1;
860 c->b = insn_fetch(u8, 1, c->eip);
861 c->d = twobyte_table[c->b];
6aa8b732
AK		 862 }
863
864 /* Unrecognised? */
8b4caf66
LV		 865 if (c->d == 0) {
866 DPRINTF("Cannot emulate %02x\n", c->b);
867 return -1;
868 }
6aa8b732
AK		 869 }
870
871 /* ModRM and SIB bytes. */
1c73ef66
AK		 872 if (c->d & ModRM)
873 rc = decode_modrm(ctxt, ops);
874 else if (c->d & MemAbs)
875 rc = decode_abs(ctxt, ops);
876 if (rc)
877 goto done;
6aa8b732 878
c7e75a3d
AK		 879 if (!c->override_base)
880 c->override_base = &ctxt->ds_base;
881 if (mode == X86EMUL_MODE_PROT64 &&
882 c->override_base != &ctxt->fs_base &&
883 c->override_base != &ctxt->gs_base)
884 c->override_base = NULL;
885
886 if (c->override_base)
887 c->modrm_ea += *c->override_base;
888
889 if (c->ad_bytes != 8)
890 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 891 /*
892 * Decode and fetch the source operand: register, memory
893 * or immediate.
894 */
e4e03ded 895 switch (c->d & SrcMask) {
6aa8b732
AK		 896 case SrcNone:
897 break;
898 case SrcReg:
9f1ef3f8 899 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 900 break;
901 case SrcMem16:
e4e03ded 902 c->src.bytes = 2;
6aa8b732
AK		 903 goto srcmem_common;
904 case SrcMem32:
e4e03ded 905 c->src.bytes = 4;
6aa8b732
AK		 906 goto srcmem_common;
907 case SrcMem:
e4e03ded
LV		 908 c->src.bytes = (c->d & ByteOp) ? 1 :
909 c->op_bytes;
b85b9ee9 910 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 911 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 912 break;
d77c26fc 913 srcmem_common:
4e62417b
AJ		 914 /*
915 * For instructions with a ModR/M byte, switch to register
916 * access if Mod = 3.
917 */
e4e03ded
LV		 918 if ((c->d & ModRM) && c->modrm_mod == 3) {
919 c->src.type = OP_REG;
4e62417b
AJ		 920 break;
921 }
e4e03ded 922 c->src.type = OP_MEM;
6aa8b732
AK		 923 break;
924 case SrcImm:
e4e03ded
LV		 925 c->src.type = OP_IMM;
926 c->src.ptr = (unsigned long *)c->eip;
927 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
928 if (c->src.bytes == 8)
929 c->src.bytes = 4;
6aa8b732 930 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 931 switch (c->src.bytes) {
6aa8b732 932 case 1:
e4e03ded 933 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 934 break;
935 case 2:
e4e03ded 936 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 937 break;
938 case 4:
e4e03ded 939 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 940 break;
941 }
942 break;
943 case SrcImmByte:
e4e03ded
LV		 944 c->src.type = OP_IMM;
945 c->src.ptr = (unsigned long *)c->eip;
946 c->src.bytes = 1;
947 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 948 break;
949 }
950
038e51de 951 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 952 switch (c->d & DstMask) {
038e51de
AK		 953 case ImplicitOps:
954 /* Special instructions do their own operand decoding. */
8b4caf66 955 return 0;
038e51de 956 case DstReg:
9f1ef3f8 957 decode_register_operand(&c->dst, c,
3c118e24 958 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 959 break;
960 case DstMem:
e4e03ded
LV		 961 if ((c->d & ModRM) && c->modrm_mod == 3) {
962 c->dst.type = OP_REG;
4e62417b
AJ		 963 break;
964 }
8b4caf66
LV		 965 c->dst.type = OP_MEM;
966 break;
967 }
968
969done:
970 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
971}
972
8cdbd2c9
LV		 973static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
974{
975 struct decode_cache *c = &ctxt->decode;
976
977 c->dst.type = OP_MEM;
978 c->dst.bytes = c->op_bytes;
979 c->dst.val = c->src.val;
980 register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes);
981 c->dst.ptr = (void *) register_address(ctxt->ss_base,
982 c->regs[VCPU_REGS_RSP]);
983}
984
985static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
986 struct x86_emulate_ops *ops)
987{
988 struct decode_cache *c = &ctxt->decode;
989 int rc;
990
991 /* 64-bit mode: POP always pops a 64-bit operand. */
992
993 if (ctxt->mode == X86EMUL_MODE_PROT64)
994 c->dst.bytes = 8;
995
996 rc = ops->read_std(register_address(ctxt->ss_base,
997 c->regs[VCPU_REGS_RSP]),
998 &c->dst.val, c->dst.bytes, ctxt->vcpu);
999 if (rc != 0)
1000 return rc;
1001
1002 register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes);
1003
1004 return 0;
1005}
1006
05f086f8 1007static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1008{
05f086f8 1009 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1010 switch (c->modrm_reg) {
1011 case 0: /* rol */
05f086f8 1012 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1013 break;
1014 case 1: /* ror */
05f086f8 1015 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1016 break;
1017 case 2: /* rcl */
05f086f8 1018 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1019 break;
1020 case 3: /* rcr */
05f086f8 1021 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1022 break;
1023 case 4: /* sal/shl */
1024 case 6: /* sal/shl */
05f086f8 1025 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1026 break;
1027 case 5: /* shr */
05f086f8 1028 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1029 break;
1030 case 7: /* sar */
05f086f8 1031 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1032 break;
1033 }
1034}
1035
1036static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1037 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1038{
1039 struct decode_cache *c = &ctxt->decode;
1040 int rc = 0;
1041
1042 switch (c->modrm_reg) {
1043 case 0 ... 1: /* test */
1044 /*
1045 * Special case in Grp3: test has an immediate
1046 * source operand.
1047 */
1048 c->src.type = OP_IMM;
1049 c->src.ptr = (unsigned long *)c->eip;
1050 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1051 if (c->src.bytes == 8)
1052 c->src.bytes = 4;
1053 switch (c->src.bytes) {
1054 case 1:
1055 c->src.val = insn_fetch(s8, 1, c->eip);
1056 break;
1057 case 2:
1058 c->src.val = insn_fetch(s16, 2, c->eip);
1059 break;
1060 case 4:
1061 c->src.val = insn_fetch(s32, 4, c->eip);
1062 break;
1063 }
05f086f8 1064 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1065 break;
1066 case 2: /* not */
1067 c->dst.val = ~c->dst.val;
1068 break;
1069 case 3: /* neg */
05f086f8 1070 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1071 break;
1072 default:
1073 DPRINTF("Cannot emulate %02x\n", c->b);
1074 rc = X86EMUL_UNHANDLEABLE;
1075 break;
1076 }
1077done:
1078 return rc;
1079}
1080
1081static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1082 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1083{
1084 struct decode_cache *c = &ctxt->decode;
1085 int rc;
1086
1087 switch (c->modrm_reg) {
1088 case 0: /* inc */
05f086f8 1089 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1090 break;
1091 case 1: /* dec */
05f086f8 1092 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1093 break;
1094 case 4: /* jmp abs */
1095 if (c->b == 0xff)
1096 c->eip = c->dst.val;
1097 else {
1098 DPRINTF("Cannot emulate %02x\n", c->b);
1099 return X86EMUL_UNHANDLEABLE;
1100 }
1101 break;
1102 case 6: /* push */
1103
1104 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1105
1106 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1107 c->dst.bytes = 8;
1108 rc = ops->read_std((unsigned long)c->dst.ptr,
1109 &c->dst.val, 8, ctxt->vcpu);
1110 if (rc != 0)
1111 return rc;
1112 }
1113 register_address_increment(c->regs[VCPU_REGS_RSP],
1114 -c->dst.bytes);
1115 rc = ops->write_emulated(register_address(ctxt->ss_base,
1116 c->regs[VCPU_REGS_RSP]), &c->dst.val,
1117 c->dst.bytes, ctxt->vcpu);
1118 if (rc != 0)
1119 return rc;
a01af5ec 1120 c->dst.type = OP_NONE;
8cdbd2c9
LV		 1121 break;
1122 default:
1123 DPRINTF("Cannot emulate %02x\n", c->b);
1124 return X86EMUL_UNHANDLEABLE;
1125 }
1126 return 0;
1127}
1128
1129static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1130 struct x86_emulate_ops *ops,
e8d8d7fe 1131 unsigned long memop)
8cdbd2c9
LV		 1132{
1133 struct decode_cache *c = &ctxt->decode;
1134 u64 old, new;
1135 int rc;
1136
e8d8d7fe 1137 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1138 if (rc != 0)
1139 return rc;
1140
1141 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1142 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1143
1144 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1145 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1146 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1147
1148 } else {
1149 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1150 (u32) c->regs[VCPU_REGS_RBX];
1151
e8d8d7fe 1152 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1153 if (rc != 0)
1154 return rc;
05f086f8 1155 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1156 }
1157 return 0;
1158}
1159
1160static inline int writeback(struct x86_emulate_ctxt *ctxt,
1161 struct x86_emulate_ops *ops)
1162{
1163 int rc;
1164 struct decode_cache *c = &ctxt->decode;
1165
1166 switch (c->dst.type) {
1167 case OP_REG:
1168 /* The 4-byte case *is* correct:
1169 * in 64-bit mode we zero-extend.
1170 */
1171 switch (c->dst.bytes) {
1172 case 1:
1173 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1174 break;
1175 case 2:
1176 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1177 break;
1178 case 4:
1179 *c->dst.ptr = (u32)c->dst.val;
1180 break; /* 64b: zero-ext */
1181 case 8:
1182 *c->dst.ptr = c->dst.val;
1183 break;
1184 }
1185 break;
1186 case OP_MEM:
1187 if (c->lock_prefix)
1188 rc = ops->cmpxchg_emulated(
1189 (unsigned long)c->dst.ptr,
1190 &c->dst.orig_val,
1191 &c->dst.val,
1192 c->dst.bytes,
1193 ctxt->vcpu);
1194 else
1195 rc = ops->write_emulated(
1196 (unsigned long)c->dst.ptr,
1197 &c->dst.val,
1198 c->dst.bytes,
1199 ctxt->vcpu);
1200 if (rc != 0)
1201 return rc;
a01af5ec
LV		 1202 break;
1203 case OP_NONE:
1204 /* no writeback */
1205 break;
8cdbd2c9
LV		 1206 default:
1207 break;
1208 }
1209 return 0;
1210}
1211
8b4caf66 1212int
1be3aa47 1213x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1214{
e8d8d7fe 1215 unsigned long memop = 0;
8b4caf66 1216 u64 msr_data;
3427318f 1217 unsigned long saved_eip = 0;
8b4caf66 1218 struct decode_cache *c = &ctxt->decode;
1be3aa47 1219 int rc = 0;
8b4caf66 1220
3427318f
LV		 1221 /* Shadow copy of register state. Committed on successful emulation.
1222 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1223 * modify them.
1224 */
1225
1226 memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs);
1227 saved_eip = c->eip;
1228
c7e75a3d 1229 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1230 memop = c->modrm_ea;
8b4caf66 1231
b9fa9d6b
AK		 1232 if (c->rep_prefix && (c->d & String)) {
1233 /* All REP prefixes have the same first termination condition */
1234 if (c->regs[VCPU_REGS_RCX] == 0) {
1235 ctxt->vcpu->rip = c->eip;
1236 goto done;
1237 }
1238 /* The second termination condition only applies for REPE
1239 * and REPNE. Test if the repeat string operation prefix is
1240 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1241 * corresponding termination condition according to:
1242 * - if REPE/REPZ and ZF = 0 then done
1243 * - if REPNE/REPNZ and ZF = 1 then done
1244 */
1245 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1246 (c->b == 0xae) || (c->b == 0xaf)) {
1247 if ((c->rep_prefix == REPE_PREFIX) &&
1248 ((ctxt->eflags & EFLG_ZF) == 0)) {
1249 ctxt->vcpu->rip = c->eip;
1250 goto done;
1251 }
1252 if ((c->rep_prefix == REPNE_PREFIX) &&
1253 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
1254 ctxt->vcpu->rip = c->eip;
1255 goto done;
1256 }
1257 }
1258 c->regs[VCPU_REGS_RCX]--;
1259 c->eip = ctxt->vcpu->rip;
1260 }
1261
8b4caf66 1262 if (c->src.type == OP_MEM) {
e8d8d7fe 1263 c->src.ptr = (unsigned long *)memop;
8b4caf66 1264 c->src.val = 0;
d77c26fc
MD		 1265 rc = ops->read_emulated((unsigned long)c->src.ptr,
1266 &c->src.val,
1267 c->src.bytes,
1268 ctxt->vcpu);
1269 if (rc != 0)
8b4caf66
LV		 1270 goto done;
1271 c->src.orig_val = c->src.val;
1272 }
1273
1274 if ((c->d & DstMask) == ImplicitOps)
1275 goto special_insn;
1276
1277
1278 if (c->dst.type == OP_MEM) {
e8d8d7fe 1279 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1280 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1281 c->dst.val = 0;
e4e03ded
LV		 1282 if (c->d & BitOp) {
1283 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1284
e4e03ded
LV		 1285 c->dst.ptr = (void *)c->dst.ptr +
1286 (c->src.val & mask) / 8;
038e51de 1287 }
e4e03ded
LV		 1288 if (!(c->d & Mov) &&
1289 /* optimisation - avoid slow emulated read */
1290 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1291 &c->dst.val,
1292 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1293 goto done;
038e51de 1294 }
e4e03ded 1295 c->dst.orig_val = c->dst.val;
038e51de 1296
018a98db
AK		 1297special_insn:
1298
e4e03ded 1299 if (c->twobyte)
6aa8b732
AK		 1300 goto twobyte_insn;
1301
e4e03ded 1302 switch (c->b) {
6aa8b732
AK		 1303 case 0x00 ... 0x05:
1304 add: /* add */
05f086f8 1305 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1306 break;
1307 case 0x08 ... 0x0d:
1308 or: /* or */
05f086f8 1309 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1310 break;
1311 case 0x10 ... 0x15:
1312 adc: /* adc */
05f086f8 1313 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1314 break;
1315 case 0x18 ... 0x1d:
1316 sbb: /* sbb */
05f086f8 1317 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1318 break;
19eb938e 1319 case 0x20 ... 0x23:
6aa8b732 1320 and: /* and */
05f086f8 1321 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1322 break;
19eb938e 1323 case 0x24: /* and al imm8 */
e4e03ded
LV		 1324 c->dst.type = OP_REG;
1325 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1326 c->dst.val = *(u8 *)c->dst.ptr;
1327 c->dst.bytes = 1;
1328 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1329 goto and;
1330 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1331 c->dst.type = OP_REG;
1332 c->dst.bytes = c->op_bytes;
1333 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1334 if (c->op_bytes == 2)
1335 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1336 else
e4e03ded
LV		 1337 c->dst.val = *(u32 *)c->dst.ptr;
1338 c->dst.orig_val = c->dst.val;
19eb938e 1339 goto and;
6aa8b732
AK		 1340 case 0x28 ... 0x2d:
1341 sub: /* sub */
05f086f8 1342 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1343 break;
1344 case 0x30 ... 0x35:
1345 xor: /* xor */
05f086f8 1346 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1347 break;
1348 case 0x38 ... 0x3d:
1349 cmp: /* cmp */
05f086f8 1350 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1351 break;
33615aa9
AK		 1352 case 0x40 ... 0x47: /* inc r16/r32 */
1353 emulate_1op("inc", c->dst, ctxt->eflags);
1354 break;
1355 case 0x48 ... 0x4f: /* dec r16/r32 */
1356 emulate_1op("dec", c->dst, ctxt->eflags);
1357 break;
1358 case 0x50 ... 0x57: /* push reg */
1359 c->dst.type = OP_MEM;
1360 c->dst.bytes = c->op_bytes;
1361 c->dst.val = c->src.val;
1362 register_address_increment(c->regs[VCPU_REGS_RSP],
1363 -c->op_bytes);
1364 c->dst.ptr = (void *) register_address(
1365 ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
1366 break;
1367 case 0x58 ... 0x5f: /* pop reg */
1368 pop_instruction:
1369 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1370 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1371 c->op_bytes, ctxt->vcpu)) != 0)
1372 goto done;
1373
1374 register_address_increment(c->regs[VCPU_REGS_RSP],
1375 c->op_bytes);
1376 c->dst.type = OP_NONE; /* Disable writeback. */
1377 break;
6aa8b732 1378 case 0x63: /* movsxd */
8b4caf66 1379 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1380 goto cannot_emulate;
e4e03ded 1381 c->dst.val = (s32) c->src.val;
6aa8b732 1382 break;
018a98db
AK		 1383 case 0x6a: /* push imm8 */
1384 c->src.val = 0L;
1385 c->src.val = insn_fetch(s8, 1, c->eip);
1386 emulate_push(ctxt);
1387 break;
1388 case 0x6c: /* insb */
1389 case 0x6d: /* insw/insd */
1390 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1391 1,
1392 (c->d & ByteOp) ? 1 : c->op_bytes,
1393 c->rep_prefix ?
1394 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1395 (ctxt->eflags & EFLG_DF),
1396 register_address(ctxt->es_base,
1397 c->regs[VCPU_REGS_RDI]),
1398 c->rep_prefix,
1399 c->regs[VCPU_REGS_RDX]) == 0) {
1400 c->eip = saved_eip;
1401 return -1;
1402 }
1403 return 0;
1404 case 0x6e: /* outsb */
1405 case 0x6f: /* outsw/outsd */
1406 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1407 0,
1408 (c->d & ByteOp) ? 1 : c->op_bytes,
1409 c->rep_prefix ?
1410 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1411 (ctxt->eflags & EFLG_DF),
1412 register_address(c->override_base ?
1413 *c->override_base :
1414 ctxt->ds_base,
1415 c->regs[VCPU_REGS_RSI]),
1416 c->rep_prefix,
1417 c->regs[VCPU_REGS_RDX]) == 0) {
1418 c->eip = saved_eip;
1419 return -1;
1420 }
1421 return 0;
1422 case 0x70 ... 0x7f: /* jcc (short) */ {
1423 int rel = insn_fetch(s8, 1, c->eip);
1424
1425 if (test_cc(c->b, ctxt->eflags))
1426 JMP_REL(rel);
1427 break;
1428 }
6aa8b732 1429 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1430 switch (c->modrm_reg) {
6aa8b732
AK		 1431 case 0:
1432 goto add;
1433 case 1:
1434 goto or;
1435 case 2:
1436 goto adc;
1437 case 3:
1438 goto sbb;
1439 case 4:
1440 goto and;
1441 case 5:
1442 goto sub;
1443 case 6:
1444 goto xor;
1445 case 7:
1446 goto cmp;
1447 }
1448 break;
1449 case 0x84 ... 0x85:
05f086f8 1450 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1451 break;
1452 case 0x86 ... 0x87: /* xchg */
1453 /* Write back the register source. */
e4e03ded 1454 switch (c->dst.bytes) {
6aa8b732 1455 case 1:
e4e03ded 1456 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1457 break;
1458 case 2:
e4e03ded 1459 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1460 break;
1461 case 4:
e4e03ded 1462 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1463 break; /* 64b reg: zero-extend */
1464 case 8:
e4e03ded 1465 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1466 break;
1467 }
1468 /*
1469 * Write back the memory destination with implicit LOCK
1470 * prefix.
1471 */
e4e03ded
LV		 1472 c->dst.val = c->src.val;
1473 c->lock_prefix = 1;
6aa8b732 1474 break;
6aa8b732 1475 case 0x88 ... 0x8b: /* mov */
7de75248 1476 goto mov;
7e0b54b1 1477 case 0x8d: /* lea r16/r32, m */
e4e03ded 1478 c->dst.val = c->modrm_val;
7e0b54b1 1479 break;
6aa8b732 1480 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1481 rc = emulate_grp1a(ctxt, ops);
1482 if (rc != 0)
6aa8b732 1483 goto done;
6aa8b732 1484 break;
fd2a7608 1485 case 0x9c: /* pushf */
05f086f8 1486 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1487 emulate_push(ctxt);
1488 break;
535eabcf 1489 case 0x9d: /* popf */
05f086f8 1490 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1491 goto pop_instruction;
018a98db
AK		 1492 case 0xa0 ... 0xa1: /* mov */
1493 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1494 c->dst.val = c->src.val;
1495 break;
1496 case 0xa2 ... 0xa3: /* mov */
1497 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1498 break;
6aa8b732 1499 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1500 c->dst.type = OP_MEM;
1501 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1502 c->dst.ptr = (unsigned long *)register_address(
1503 ctxt->es_base,
1504 c->regs[VCPU_REGS_RDI]);
6aa8b732 1505 if ((rc = ops->read_emulated(register_address(
e4e03ded
LV		 1506 c->override_base ? *c->override_base :
1507 ctxt->ds_base,
1508 c->regs[VCPU_REGS_RSI]),
1509 &c->dst.val,
1510 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1511 goto done;
e4e03ded 1512 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1513 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded
LV		 1514 : c->dst.bytes);
1515 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1516 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1517 : c->dst.bytes);
6aa8b732
AK		 1518 break;
1519 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1520 c->src.type = OP_NONE; /* Disable writeback. */
1521 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1522 c->src.ptr = (unsigned long *)register_address(
1523 c->override_base ? *c->override_base :
1524 ctxt->ds_base,
1525 c->regs[VCPU_REGS_RSI]);
1526 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1527 &c->src.val,
1528 c->src.bytes,
1529 ctxt->vcpu)) != 0)
1530 goto done;
1531
1532 c->dst.type = OP_NONE; /* Disable writeback. */
1533 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1534 c->dst.ptr = (unsigned long *)register_address(
1535 ctxt->es_base,
1536 c->regs[VCPU_REGS_RDI]);
1537 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1538 &c->dst.val,
1539 c->dst.bytes,
1540 ctxt->vcpu)) != 0)
1541 goto done;
1542
1543 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1544
1545 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1546
1547 register_address_increment(c->regs[VCPU_REGS_RSI],
1548 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1549 : c->src.bytes);
1550 register_address_increment(c->regs[VCPU_REGS_RDI],
1551 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1552 : c->dst.bytes);
1553
1554 break;
6aa8b732 1555 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1556 c->dst.type = OP_MEM;
1557 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
a7e6c88a
SY		 1558 c->dst.ptr = (unsigned long *)register_address(
1559 ctxt->es_base,
1560 c->regs[VCPU_REGS_RDI]);
e4e03ded
LV		 1561 c->dst.val = c->regs[VCPU_REGS_RAX];
1562 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1563 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1564 : c->dst.bytes);
6aa8b732
AK		 1565 break;
1566 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1567 c->dst.type = OP_REG;
1568 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1569 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
a7e6c88a
SY		 1570 if ((rc = ops->read_emulated(register_address(
1571 c->override_base ? *c->override_base :
1572 ctxt->ds_base,
1573 c->regs[VCPU_REGS_RSI]),
1574 &c->dst.val,
1575 c->dst.bytes,
1576 ctxt->vcpu)) != 0)
6aa8b732 1577 goto done;
e4e03ded 1578 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1579 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1580 : c->dst.bytes);
6aa8b732
AK		 1581 break;
1582 case 0xae ... 0xaf: /* scas */
1583 DPRINTF("Urk! I don't handle SCAS.\n");
1584 goto cannot_emulate;
018a98db
AK		 1585 case 0xc0 ... 0xc1:
1586 emulate_grp2(ctxt);
1587 break;
111de5d6
AK		 1588 case 0xc3: /* ret */
1589 c->dst.ptr = &c->eip;
1590 goto pop_instruction;
018a98db
AK		 1591 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1592 mov:
1593 c->dst.val = c->src.val;
1594 break;
1595 case 0xd0 ... 0xd1: /* Grp2 */
1596 c->src.val = 1;
1597 emulate_grp2(ctxt);
1598 break;
1599 case 0xd2 ... 0xd3: /* Grp2 */
1600 c->src.val = c->regs[VCPU_REGS_RCX];
1601 emulate_grp2(ctxt);
1602 break;
1a52e051
NK		 1603 case 0xe8: /* call (near) */ {
1604 long int rel;
e4e03ded 1605 switch (c->op_bytes) {
1a52e051 1606 case 2:
e4e03ded 1607 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1608 break;
1609 case 4:
e4e03ded 1610 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1611 break;
1a52e051
NK		 1612 default:
1613 DPRINTF("Call: Invalid op_bytes\n");
1614 goto cannot_emulate;
1615 }
e4e03ded 1616 c->src.val = (unsigned long) c->eip;
1a52e051 1617 JMP_REL(rel);
e4e03ded 1618 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1619 emulate_push(ctxt);
1620 break;
1a52e051
NK		 1621 }
1622 case 0xe9: /* jmp rel */
1623 case 0xeb: /* jmp rel short */
e4e03ded 1624 JMP_REL(c->src.val);
a01af5ec 1625 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1626 break;
111de5d6
AK		 1627 case 0xf4: /* hlt */
1628 ctxt->vcpu->halt_request = 1;
1629 goto done;
1630 case 0xf5: /* cmc */
1631 /* complement carry flag from eflags reg */
1632 ctxt->eflags ^= EFLG_CF;
1633 c->dst.type = OP_NONE; /* Disable writeback. */
1634 break;
018a98db
AK		 1635 case 0xf6 ... 0xf7: /* Grp3 */
1636 rc = emulate_grp3(ctxt, ops);
1637 if (rc != 0)
1638 goto done;
1639 break;
111de5d6
AK		 1640 case 0xf8: /* clc */
1641 ctxt->eflags &= ~EFLG_CF;
1642 c->dst.type = OP_NONE; /* Disable writeback. */
1643 break;
1644 case 0xfa: /* cli */
1645 ctxt->eflags &= ~X86_EFLAGS_IF;
1646 c->dst.type = OP_NONE; /* Disable writeback. */
1647 break;
1648 case 0xfb: /* sti */
1649 ctxt->eflags |= X86_EFLAGS_IF;
1650 c->dst.type = OP_NONE; /* Disable writeback. */
1651 break;
018a98db
AK		 1652 case 0xfe ... 0xff: /* Grp4/Grp5 */
1653 rc = emulate_grp45(ctxt, ops);
1654 if (rc != 0)
1655 goto done;
1656 break;
6aa8b732 1657 }
018a98db
AK		 1658
1659writeback:
1660 rc = writeback(ctxt, ops);
1661 if (rc != 0)
1662 goto done;
1663
1664 /* Commit shadow register state. */
1665 memcpy(ctxt->vcpu->regs, c->regs, sizeof c->regs);
1666 ctxt->vcpu->rip = c->eip;
1667
1668done:
1669 if (rc == X86EMUL_UNHANDLEABLE) {
1670 c->eip = saved_eip;
1671 return -1;
1672 }
1673 return 0;
6aa8b732
AK		 1674
1675twobyte_insn:
e4e03ded 1676 switch (c->b) {
6aa8b732 1677 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1678 switch (c->modrm_reg) {
6aa8b732
AK		 1679 u16 size;
1680 unsigned long address;
1681
aca7f966 1682 case 0: /* vmcall */
e4e03ded 1683 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1684 goto cannot_emulate;
1685
7aa81cc0
AL		 1686 rc = kvm_fix_hypercall(ctxt->vcpu);
1687 if (rc)
1688 goto done;
1689
1690 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1691 break;
6aa8b732 1692 case 2: /* lgdt */
e4e03ded
LV		 1693 rc = read_descriptor(ctxt, ops, c->src.ptr,
1694 &size, &address, c->op_bytes);
6aa8b732
AK		 1695 if (rc)
1696 goto done;
1697 realmode_lgdt(ctxt->vcpu, size, address);
1698 break;
aca7f966 1699 case 3: /* lidt/vmmcall */
e4e03ded 1700 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1701 rc = kvm_fix_hypercall(ctxt->vcpu);
1702 if (rc)
1703 goto done;
1704 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1705 } else {
e4e03ded 1706 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1707 &size, &address,
e4e03ded 1708 c->op_bytes);
aca7f966
AL		 1709 if (rc)
1710 goto done;
1711 realmode_lidt(ctxt->vcpu, size, address);
1712 }
6aa8b732
AK		 1713 break;
1714 case 4: /* smsw */
e4e03ded 1715 if (c->modrm_mod != 3)
6aa8b732 1716 goto cannot_emulate;
e4e03ded 1717 *(u16 *)&c->regs[c->modrm_rm]
6aa8b732
AK		 1718 = realmode_get_cr(ctxt->vcpu, 0);
1719 break;
1720 case 6: /* lmsw */
e4e03ded 1721 if (c->modrm_mod != 3)
6aa8b732 1722 goto cannot_emulate;
05f086f8
LV		 1723 realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val,
1724 &ctxt->eflags);
6aa8b732
AK		 1725 break;
1726 case 7: /* invlpg*/
e8d8d7fe 1727 emulate_invlpg(ctxt->vcpu, memop);
6aa8b732
AK		 1728 break;
1729 default:
1730 goto cannot_emulate;
1731 }
a01af5ec
LV		 1732 /* Disable writeback. */
1733 c->dst.type = OP_NONE;
6aa8b732 1734 break;
018a98db
AK		 1735 case 0x06:
1736 emulate_clts(ctxt->vcpu);
1737 c->dst.type = OP_NONE;
1738 break;
1739 case 0x08: /* invd */
1740 case 0x09: /* wbinvd */
1741 case 0x0d: /* GrpP (prefetch) */
1742 case 0x18: /* Grp16 (prefetch/nop) */
1743 c->dst.type = OP_NONE;
1744 break;
1745 case 0x20: /* mov cr, reg */
1746 if (c->modrm_mod != 3)
1747 goto cannot_emulate;
1748 c->regs[c->modrm_rm] =
1749 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1750 c->dst.type = OP_NONE; /* no writeback */
1751 break;
6aa8b732 1752 case 0x21: /* mov from dr to reg */
e4e03ded 1753 if (c->modrm_mod != 3)
6aa8b732 1754 goto cannot_emulate;
8cdbd2c9 1755 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1756 if (rc)
1757 goto cannot_emulate;
1758 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1759 break;
018a98db
AK		 1760 case 0x22: /* mov reg, cr */
1761 if (c->modrm_mod != 3)
1762 goto cannot_emulate;
1763 realmode_set_cr(ctxt->vcpu,
1764 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1765 c->dst.type = OP_NONE;
1766 break;
6aa8b732 1767 case 0x23: /* mov from reg to dr */
e4e03ded 1768 if (c->modrm_mod != 3)
6aa8b732 1769 goto cannot_emulate;
e4e03ded
LV		 1770 rc = emulator_set_dr(ctxt, c->modrm_reg,
1771 c->regs[c->modrm_rm]);
a01af5ec
LV		 1772 if (rc)
1773 goto cannot_emulate;
1774 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1775 break;
018a98db
AK		 1776 case 0x30:
1777 /* wrmsr */
1778 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1779 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1780 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1781 if (rc) {
c1a5d4f9 1782 kvm_inject_gp(ctxt->vcpu, 0);
018a98db
AK		 1783 c->eip = ctxt->vcpu->rip;
1784 }
1785 rc = X86EMUL_CONTINUE;
1786 c->dst.type = OP_NONE;
1787 break;
1788 case 0x32:
1789 /* rdmsr */
1790 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1791 if (rc) {
c1a5d4f9 1792 kvm_inject_gp(ctxt->vcpu, 0);
018a98db
AK		 1793 c->eip = ctxt->vcpu->rip;
1794 } else {
1795 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1796 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1797 }
1798 rc = X86EMUL_CONTINUE;
1799 c->dst.type = OP_NONE;
1800 break;
6aa8b732 1801 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1802 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1803 if (!test_cc(c->b, ctxt->eflags))
1804 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1805 break;
018a98db
AK		 1806 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1807 long int rel;
1808
1809 switch (c->op_bytes) {
1810 case 2:
1811 rel = insn_fetch(s16, 2, c->eip);
1812 break;
1813 case 4:
1814 rel = insn_fetch(s32, 4, c->eip);
1815 break;
1816 case 8:
1817 rel = insn_fetch(s64, 8, c->eip);
1818 break;
1819 default:
1820 DPRINTF("jnz: Invalid op_bytes\n");
1821 goto cannot_emulate;
1822 }
1823 if (test_cc(c->b, ctxt->eflags))
1824 JMP_REL(rel);
1825 c->dst.type = OP_NONE;
1826 break;
1827 }
7de75248
NK		 1828 case 0xa3:
1829 bt: /* bt */
e4f8e039 1830 c->dst.type = OP_NONE;
e4e03ded
LV		 1831 /* only subword offset */
1832 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1833 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1834 break;
1835 case 0xab:
1836 bts: /* bts */
e4e03ded
LV		 1837 /* only subword offset */
1838 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1839 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1840 break;
6aa8b732
AK		 1841 case 0xb0 ... 0xb1: /* cmpxchg */
1842 /*
1843 * Save real source value, then compare EAX against
1844 * destination.
1845 */
e4e03ded
LV		 1846 c->src.orig_val = c->src.val;
1847 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1848 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1849 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1850 /* Success: write back to memory. */
e4e03ded 1851 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1852 } else {
1853 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1854 c->dst.type = OP_REG;
1855 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1856 }
1857 break;
6aa8b732
AK		 1858 case 0xb3:
1859 btr: /* btr */
e4e03ded
LV		 1860 /* only subword offset */
1861 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1862 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1863 break;
6aa8b732 1864 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1865 c->dst.bytes = c->op_bytes;
1866 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1867 : (u16) c->src.val;
6aa8b732 1868 break;
6aa8b732 1869 case 0xba: /* Grp8 */
e4e03ded 1870 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1871 case 0:
1872 goto bt;
1873 case 1:
1874 goto bts;
1875 case 2:
1876 goto btr;
1877 case 3:
1878 goto btc;
1879 }
1880 break;
7de75248
NK		 1881 case 0xbb:
1882 btc: /* btc */
e4e03ded
LV		 1883 /* only subword offset */
1884 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1885 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 1886 break;
6aa8b732 1887 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 1888 c->dst.bytes = c->op_bytes;
1889 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1890 (s16) c->src.val;
6aa8b732 1891 break;
a012e65a 1892 case 0xc3: /* movnti */
e4e03ded
LV		 1893 c->dst.bytes = c->op_bytes;
1894 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1895 (u64) c->src.val;
a012e65a 1896 break;
6aa8b732 1897 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 1898 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 1899 if (rc != 0)
1900 goto done;
018a98db 1901 c->dst.type = OP_NONE;
8cdbd2c9 1902 break;
6aa8b732
AK		 1903 }
1904 goto writeback;
1905
1906cannot_emulate:
e4e03ded 1907 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 1908 c->eip = saved_eip;
6aa8b732
AK		 1909 return -1;
1910}
Linux kernel - Deliverables
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