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KVM: VMX: Reset mmu context when entering real mode
[deliverable/linux.git] / drivers / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
26#define DPRINTF(_f, _a ...) printf( _f , ## _a )
27#else
28#include "kvm.h"
29#define DPRINTF(x...) do {} while (0)
30#endif
31#include "x86_emulate.h"
32#include <linux/module.h>
33
34/*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43/* Operand sizes: 8-bit operands or specified/overridden size. */
44#define ByteOp (1<<0) /* 8-bit operands. */
45/* Destination operand type. */
46#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47#define DstReg (2<<1) /* Register operand. */
48#define DstMem (3<<1) /* Memory operand. */
49#define DstMask (3<<1)
50/* Source operand type. */
51#define SrcNone (0<<3) /* No source operand. */
52#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53#define SrcReg (1<<3) /* Register operand. */
54#define SrcMem (2<<3) /* Memory operand. */
55#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57#define SrcImm (5<<3) /* Immediate operand. */
58#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59#define SrcMask (7<<3)
60/* Generic ModRM decode. */
61#define ModRM (1<<6)
62/* Destination is only written; never read. */
63#define Mov (1<<7)
038e51de 64#define BitOp (1<<8)
6aa8b732
AK		 65
66static u8 opcode_table[256] = {
67 /* 0x00 - 0x07 */
68 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
69 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
70 0, 0, 0, 0,
71 /* 0x08 - 0x0F */
72 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
73 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
74 0, 0, 0, 0,
75 /* 0x10 - 0x17 */
76 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
77 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
78 0, 0, 0, 0,
79 /* 0x18 - 0x1F */
80 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
81 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
82 0, 0, 0, 0,
83 /* 0x20 - 0x27 */
84 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
85 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 86 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 87 /* 0x28 - 0x2F */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 0, 0, 0, 0,
91 /* 0x30 - 0x37 */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x38 - 0x3F */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 0, 0, 0, 0,
99 /* 0x40 - 0x4F */
100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7f0aaee0 101 /* 0x50 - 0x57 */
7e778161
NK		 102 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
103 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7f0aaee0
NK		 104 /* 0x58 - 0x5F */
105 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
106 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7d316911 107 /* 0x60 - 0x67 */
6aa8b732 108 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 109 0, 0, 0, 0,
110 /* 0x68 - 0x6F */
111 0, 0, ImplicitOps|Mov, 0,
e70669ab
LV		 112 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
113 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 114 /* 0x70 - 0x77 */
115 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
116 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
117 /* 0x78 - 0x7F */
118 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
119 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 120 /* 0x80 - 0x87 */
121 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
122 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
123 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
124 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
125 /* 0x88 - 0x8F */
126 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
127 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
7e0b54b1 128 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov,
6aa8b732 129 /* 0x90 - 0x9F */
535eabcf 130 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0,
6aa8b732
AK		 131 /* 0xA0 - 0xA7 */
132 ByteOp | DstReg | SrcMem | Mov, DstReg | SrcMem | Mov,
133 ByteOp | DstMem | SrcReg | Mov, DstMem | SrcReg | Mov,
134 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
135 ByteOp | ImplicitOps, ImplicitOps,
136 /* 0xA8 - 0xAF */
137 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
138 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
139 ByteOp | ImplicitOps, ImplicitOps,
140 /* 0xB0 - 0xBF */
141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
142 /* 0xC0 - 0xC7 */
d9413cd7
NK		 143 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
144 0, ImplicitOps, 0, 0,
145 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 146 /* 0xC8 - 0xCF */
147 0, 0, 0, 0, 0, 0, 0, 0,
148 /* 0xD0 - 0xD7 */
149 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
150 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
151 0, 0, 0, 0,
152 /* 0xD8 - 0xDF */
153 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 154 /* 0xE0 - 0xE7 */
155 0, 0, 0, 0, 0, 0, 0, 0,
156 /* 0xE8 - 0xEF */
f6eed391 157 ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0,
6aa8b732
AK		 158 /* 0xF0 - 0xF7 */
159 0, 0, 0, 0,
72d6e5a0
AK		 160 ImplicitOps, 0,
161 ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
6aa8b732
AK		 162 /* 0xF8 - 0xFF */
163 0, 0, 0, 0,
164 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
165};
166
038e51de 167static u16 twobyte_table[256] = {
6aa8b732
AK		 168 /* 0x00 - 0x0F */
169 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
687fdbfe 170 0, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 171 /* 0x10 - 0x1F */
172 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
173 /* 0x20 - 0x2F */
174 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
175 0, 0, 0, 0, 0, 0, 0, 0,
176 /* 0x30 - 0x3F */
35f3f286 177 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 178 /* 0x40 - 0x47 */
179 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
180 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
181 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
182 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
183 /* 0x48 - 0x4F */
184 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
185 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
186 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
187 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
188 /* 0x50 - 0x5F */
189 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
190 /* 0x60 - 0x6F */
191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
192 /* 0x70 - 0x7F */
193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
194 /* 0x80 - 0x8F */
bbe9abbd
NK		 195 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
196 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
197 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
198 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 199 /* 0x90 - 0x9F */
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
201 /* 0xA0 - 0xA7 */
038e51de 202 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 203 /* 0xA8 - 0xAF */
038e51de 204 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 205 /* 0xB0 - 0xB7 */
206 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 207 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 208 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
209 DstReg | SrcMem16 | ModRM | Mov,
210 /* 0xB8 - 0xBF */
038e51de 211 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 212 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem16 | ModRM | Mov,
214 /* 0xC0 - 0xCF */
215 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, 0,
216 /* 0xD0 - 0xDF */
217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
218 /* 0xE0 - 0xEF */
219 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
220 /* 0xF0 - 0xFF */
221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
222};
223
6aa8b732
AK		 224/* Type, address-of, and value of an instruction's operand. */
225struct operand {
226 enum { OP_REG, OP_MEM, OP_IMM } type;
227 unsigned int bytes;
228 unsigned long val, orig_val, *ptr;
229};
230
231/* EFLAGS bit definitions. */
232#define EFLG_OF (1<<11)
233#define EFLG_DF (1<<10)
234#define EFLG_SF (1<<7)
235#define EFLG_ZF (1<<6)
236#define EFLG_AF (1<<4)
237#define EFLG_PF (1<<2)
238#define EFLG_CF (1<<0)
239
240/*
241 * Instruction emulation:
242 * Most instructions are emulated directly via a fragment of inline assembly
243 * code. This allows us to save/restore EFLAGS and thus very easily pick up
244 * any modified flags.
245 */
246
05b3e0c2 247#if defined(CONFIG_X86_64)
6aa8b732
AK		 248#define _LO32 "k" /* force 32-bit operand */
249#define _STK "%%rsp" /* stack pointer */
250#elif defined(__i386__)
251#define _LO32 "" /* force 32-bit operand */
252#define _STK "%%esp" /* stack pointer */
253#endif
254
255/*
256 * These EFLAGS bits are restored from saved value during emulation, and
257 * any changes are written back to the saved value after emulation.
258 */
259#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
260
261/* Before executing instruction: restore necessary bits in EFLAGS. */
262#define _PRE_EFLAGS(_sav, _msk, _tmp) \
263 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \
264 "push %"_sav"; " \
265 "movl %"_msk",%"_LO32 _tmp"; " \
266 "andl %"_LO32 _tmp",("_STK"); " \
267 "pushf; " \
268 "notl %"_LO32 _tmp"; " \
269 "andl %"_LO32 _tmp",("_STK"); " \
270 "pop %"_tmp"; " \
271 "orl %"_LO32 _tmp",("_STK"); " \
272 "popf; " \
273 /* _sav &= ~msk; */ \
274 "movl %"_msk",%"_LO32 _tmp"; " \
275 "notl %"_LO32 _tmp"; " \
276 "andl %"_LO32 _tmp",%"_sav"; "
277
278/* After executing instruction: write-back necessary bits in EFLAGS. */
279#define _POST_EFLAGS(_sav, _msk, _tmp) \
280 /* _sav |= EFLAGS & _msk; */ \
281 "pushf; " \
282 "pop %"_tmp"; " \
283 "andl %"_msk",%"_LO32 _tmp"; " \
284 "orl %"_LO32 _tmp",%"_sav"; "
285
286/* Raw emulation: instruction has two explicit operands. */
287#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
288 do { \
289 unsigned long _tmp; \
290 \
291 switch ((_dst).bytes) { \
292 case 2: \
293 __asm__ __volatile__ ( \
294 _PRE_EFLAGS("0","4","2") \
295 _op"w %"_wx"3,%1; " \
296 _POST_EFLAGS("0","4","2") \
297 : "=m" (_eflags), "=m" ((_dst).val), \
298 "=&r" (_tmp) \
299 : _wy ((_src).val), "i" (EFLAGS_MASK) ); \
300 break; \
301 case 4: \
302 __asm__ __volatile__ ( \
303 _PRE_EFLAGS("0","4","2") \
304 _op"l %"_lx"3,%1; " \
305 _POST_EFLAGS("0","4","2") \
306 : "=m" (_eflags), "=m" ((_dst).val), \
307 "=&r" (_tmp) \
308 : _ly ((_src).val), "i" (EFLAGS_MASK) ); \
309 break; \
310 case 8: \
311 __emulate_2op_8byte(_op, _src, _dst, \
312 _eflags, _qx, _qy); \
313 break; \
314 } \
315 } while (0)
316
317#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
318 do { \
319 unsigned long _tmp; \
320 switch ( (_dst).bytes ) \
321 { \
322 case 1: \
323 __asm__ __volatile__ ( \
324 _PRE_EFLAGS("0","4","2") \
325 _op"b %"_bx"3,%1; " \
326 _POST_EFLAGS("0","4","2") \
327 : "=m" (_eflags), "=m" ((_dst).val), \
328 "=&r" (_tmp) \
329 : _by ((_src).val), "i" (EFLAGS_MASK) ); \
330 break; \
331 default: \
332 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
333 _wx, _wy, _lx, _ly, _qx, _qy); \
334 break; \
335 } \
336 } while (0)
337
338/* Source operand is byte-sized and may be restricted to just %cl. */
339#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
340 __emulate_2op(_op, _src, _dst, _eflags, \
341 "b", "c", "b", "c", "b", "c", "b", "c")
342
343/* Source operand is byte, word, long or quad sized. */
344#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
345 __emulate_2op(_op, _src, _dst, _eflags, \
346 "b", "q", "w", "r", _LO32, "r", "", "r")
347
348/* Source operand is word, long or quad sized. */
349#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
350 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
351 "w", "r", _LO32, "r", "", "r")
352
353/* Instruction has only one explicit operand (no source operand). */
354#define emulate_1op(_op, _dst, _eflags) \
355 do { \
356 unsigned long _tmp; \
357 \
358 switch ( (_dst).bytes ) \
359 { \
360 case 1: \
361 __asm__ __volatile__ ( \
362 _PRE_EFLAGS("0","3","2") \
363 _op"b %1; " \
364 _POST_EFLAGS("0","3","2") \
365 : "=m" (_eflags), "=m" ((_dst).val), \
366 "=&r" (_tmp) \
367 : "i" (EFLAGS_MASK) ); \
368 break; \
369 case 2: \
370 __asm__ __volatile__ ( \
371 _PRE_EFLAGS("0","3","2") \
372 _op"w %1; " \
373 _POST_EFLAGS("0","3","2") \
374 : "=m" (_eflags), "=m" ((_dst).val), \
375 "=&r" (_tmp) \
376 : "i" (EFLAGS_MASK) ); \
377 break; \
378 case 4: \
379 __asm__ __volatile__ ( \
380 _PRE_EFLAGS("0","3","2") \
381 _op"l %1; " \
382 _POST_EFLAGS("0","3","2") \
383 : "=m" (_eflags), "=m" ((_dst).val), \
384 "=&r" (_tmp) \
385 : "i" (EFLAGS_MASK) ); \
386 break; \
387 case 8: \
388 __emulate_1op_8byte(_op, _dst, _eflags); \
389 break; \
390 } \
391 } while (0)
392
393/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 394#if defined(CONFIG_X86_64)
6aa8b732
AK		 395#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
396 do { \
397 __asm__ __volatile__ ( \
398 _PRE_EFLAGS("0","4","2") \
399 _op"q %"_qx"3,%1; " \
400 _POST_EFLAGS("0","4","2") \
401 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
402 : _qy ((_src).val), "i" (EFLAGS_MASK) ); \
403 } while (0)
404
405#define __emulate_1op_8byte(_op, _dst, _eflags) \
406 do { \
407 __asm__ __volatile__ ( \
408 _PRE_EFLAGS("0","3","2") \
409 _op"q %1; " \
410 _POST_EFLAGS("0","3","2") \
411 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
412 : "i" (EFLAGS_MASK) ); \
413 } while (0)
414
415#elif defined(__i386__)
416#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
417#define __emulate_1op_8byte(_op, _dst, _eflags)
418#endif /* __i386__ */
419
420/* Fetch next part of the instruction being emulated. */
421#define insn_fetch(_type, _size, _eip) \
422({ unsigned long _x; \
423 rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x, \
cebff02b 424 (_size), ctxt->vcpu); \
6aa8b732
AK		 425 if ( rc != 0 ) \
426 goto done; \
427 (_eip) += (_size); \
428 (_type)_x; \
429})
430
431/* Access/update address held in a register, based on addressing mode. */
e70669ab
LV		 432#define address_mask(reg) \
433 ((ad_bytes == sizeof(unsigned long)) ? \
434 (reg) : ((reg) & ((1UL << (ad_bytes << 3)) - 1)))
6aa8b732 435#define register_address(base, reg) \
e70669ab 436 ((base) + address_mask(reg))
6aa8b732
AK		 437#define register_address_increment(reg, inc) \
438 do { \
439 /* signed type ensures sign extension to long */ \
440 int _inc = (inc); \
441 if ( ad_bytes == sizeof(unsigned long) ) \
442 (reg) += _inc; \
443 else \
444 (reg) = ((reg) & ~((1UL << (ad_bytes << 3)) - 1)) | \
445 (((reg) + _inc) & ((1UL << (ad_bytes << 3)) - 1)); \
446 } while (0)
447
098c937b
NK		 448#define JMP_REL(rel) \
449 do { \
450 _eip += (int)(rel); \
451 _eip = ((op_bytes == 2) ? (uint16_t)_eip : (uint32_t)_eip); \
452 } while (0)
453
1e3c5cb0
RR		 454/*
455 * Given the 'reg' portion of a ModRM byte, and a register block, return a
456 * pointer into the block that addresses the relevant register.
457 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
458 */
459static void *decode_register(u8 modrm_reg, unsigned long *regs,
460 int highbyte_regs)
6aa8b732
AK		 461{
462 void *p;
463
464 p = &regs[modrm_reg];
465 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
466 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
467 return p;
468}
469
470static int read_descriptor(struct x86_emulate_ctxt *ctxt,
471 struct x86_emulate_ops *ops,
472 void *ptr,
473 u16 *size, unsigned long *address, int op_bytes)
474{
475 int rc;
476
477 if (op_bytes == 2)
478 op_bytes = 3;
479 *address = 0;
cebff02b
LV		 480 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
481 ctxt->vcpu);
6aa8b732
AK		 482 if (rc)
483 return rc;
cebff02b
LV		 484 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
485 ctxt->vcpu);
6aa8b732
AK		 486 return rc;
487}
488
bbe9abbd
NK		 489static int test_cc(unsigned int condition, unsigned int flags)
490{
491 int rc = 0;
492
493 switch ((condition & 15) >> 1) {
494 case 0: /* o */
495 rc |= (flags & EFLG_OF);
496 break;
497 case 1: /* b/c/nae */
498 rc |= (flags & EFLG_CF);
499 break;
500 case 2: /* z/e */
501 rc |= (flags & EFLG_ZF);
502 break;
503 case 3: /* be/na */
504 rc |= (flags & (EFLG_CF|EFLG_ZF));
505 break;
506 case 4: /* s */
507 rc |= (flags & EFLG_SF);
508 break;
509 case 5: /* p/pe */
510 rc |= (flags & EFLG_PF);
511 break;
512 case 7: /* le/ng */
513 rc |= (flags & EFLG_ZF);
514 /* fall through */
515 case 6: /* l/nge */
516 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
517 break;
518 }
519
520 /* Odd condition identifiers (lsb == 1) have inverted sense. */
521 return (!!rc ^ (condition & 1));
522}
523
6aa8b732
AK		 524int
525x86_emulate_memop(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
526{
038e51de
AK		 527 unsigned d;
528 u8 b, sib, twobyte = 0, rex_prefix = 0;
6aa8b732
AK		 529 u8 modrm, modrm_mod = 0, modrm_reg = 0, modrm_rm = 0;
530 unsigned long *override_base = NULL;
531 unsigned int op_bytes, ad_bytes, lock_prefix = 0, rep_prefix = 0, i;
532 int rc = 0;
533 struct operand src, dst;
534 unsigned long cr2 = ctxt->cr2;
535 int mode = ctxt->mode;
536 unsigned long modrm_ea;
537 int use_modrm_ea, index_reg = 0, base_reg = 0, scale, rip_relative = 0;
02c03a32 538 int no_wb = 0;
35f3f286 539 u64 msr_data;
6aa8b732
AK		 540
541 /* Shadow copy of register state. Committed on successful emulation. */
542 unsigned long _regs[NR_VCPU_REGS];
543 unsigned long _eip = ctxt->vcpu->rip, _eflags = ctxt->eflags;
544 unsigned long modrm_val = 0;
545
546 memcpy(_regs, ctxt->vcpu->regs, sizeof _regs);
547
548 switch (mode) {
549 case X86EMUL_MODE_REAL:
550 case X86EMUL_MODE_PROT16:
551 op_bytes = ad_bytes = 2;
552 break;
553 case X86EMUL_MODE_PROT32:
554 op_bytes = ad_bytes = 4;
555 break;
05b3e0c2 556#ifdef CONFIG_X86_64
6aa8b732
AK		 557 case X86EMUL_MODE_PROT64:
558 op_bytes = 4;
559 ad_bytes = 8;
560 break;
561#endif
562 default:
563 return -1;
564 }
565
566 /* Legacy prefixes. */
567 for (i = 0; i < 8; i++) {
568 switch (b = insn_fetch(u8, 1, _eip)) {
569 case 0x66: /* operand-size override */
570 op_bytes ^= 6; /* switch between 2/4 bytes */
571 break;
572 case 0x67: /* address-size override */
573 if (mode == X86EMUL_MODE_PROT64)
574 ad_bytes ^= 12; /* switch between 4/8 bytes */
575 else
576 ad_bytes ^= 6; /* switch between 2/4 bytes */
577 break;
578 case 0x2e: /* CS override */
579 override_base = &ctxt->cs_base;
580 break;
581 case 0x3e: /* DS override */
582 override_base = &ctxt->ds_base;
583 break;
584 case 0x26: /* ES override */
585 override_base = &ctxt->es_base;
586 break;
587 case 0x64: /* FS override */
588 override_base = &ctxt->fs_base;
589 break;
590 case 0x65: /* GS override */
591 override_base = &ctxt->gs_base;
592 break;
593 case 0x36: /* SS override */
594 override_base = &ctxt->ss_base;
595 break;
596 case 0xf0: /* LOCK */
597 lock_prefix = 1;
598 break;
ae6200ba 599 case 0xf2: /* REPNE/REPNZ */
6aa8b732
AK		 600 case 0xf3: /* REP/REPE/REPZ */
601 rep_prefix = 1;
602 break;
6aa8b732
AK		 603 default:
604 goto done_prefixes;
605 }
606 }
607
608done_prefixes:
609
610 /* REX prefix. */
611 if ((mode == X86EMUL_MODE_PROT64) && ((b & 0xf0) == 0x40)) {
612 rex_prefix = b;
613 if (b & 8)
614 op_bytes = 8; /* REX.W */
615 modrm_reg = (b & 4) << 1; /* REX.R */
616 index_reg = (b & 2) << 2; /* REX.X */
617 modrm_rm = base_reg = (b & 1) << 3; /* REG.B */
618 b = insn_fetch(u8, 1, _eip);
619 }
620
621 /* Opcode byte(s). */
622 d = opcode_table[b];
623 if (d == 0) {
624 /* Two-byte opcode? */
625 if (b == 0x0f) {
626 twobyte = 1;
627 b = insn_fetch(u8, 1, _eip);
628 d = twobyte_table[b];
629 }
630
631 /* Unrecognised? */
632 if (d == 0)
633 goto cannot_emulate;
634 }
635
636 /* ModRM and SIB bytes. */
637 if (d & ModRM) {
638 modrm = insn_fetch(u8, 1, _eip);
639 modrm_mod |= (modrm & 0xc0) >> 6;
640 modrm_reg |= (modrm & 0x38) >> 3;
641 modrm_rm |= (modrm & 0x07);
642 modrm_ea = 0;
643 use_modrm_ea = 1;
644
645 if (modrm_mod == 3) {
646 modrm_val = *(unsigned long *)
647 decode_register(modrm_rm, _regs, d & ByteOp);
648 goto modrm_done;
649 }
650
651 if (ad_bytes == 2) {
652 unsigned bx = _regs[VCPU_REGS_RBX];
653 unsigned bp = _regs[VCPU_REGS_RBP];
654 unsigned si = _regs[VCPU_REGS_RSI];
655 unsigned di = _regs[VCPU_REGS_RDI];
656
657 /* 16-bit ModR/M decode. */
658 switch (modrm_mod) {
659 case 0:
660 if (modrm_rm == 6)
661 modrm_ea += insn_fetch(u16, 2, _eip);
662 break;
663 case 1:
664 modrm_ea += insn_fetch(s8, 1, _eip);
665 break;
666 case 2:
667 modrm_ea += insn_fetch(u16, 2, _eip);
668 break;
669 }
670 switch (modrm_rm) {
671 case 0:
672 modrm_ea += bx + si;
673 break;
674 case 1:
675 modrm_ea += bx + di;
676 break;
677 case 2:
678 modrm_ea += bp + si;
679 break;
680 case 3:
681 modrm_ea += bp + di;
682 break;
683 case 4:
684 modrm_ea += si;
685 break;
686 case 5:
687 modrm_ea += di;
688 break;
689 case 6:
690 if (modrm_mod != 0)
691 modrm_ea += bp;
692 break;
693 case 7:
694 modrm_ea += bx;
695 break;
696 }
697 if (modrm_rm == 2 || modrm_rm == 3 ||
698 (modrm_rm == 6 && modrm_mod != 0))
699 if (!override_base)
700 override_base = &ctxt->ss_base;
701 modrm_ea = (u16)modrm_ea;
702 } else {
703 /* 32/64-bit ModR/M decode. */
704 switch (modrm_rm) {
705 case 4:
706 case 12:
707 sib = insn_fetch(u8, 1, _eip);
708 index_reg |= (sib >> 3) & 7;
709 base_reg |= sib & 7;
710 scale = sib >> 6;
711
712 switch (base_reg) {
713 case 5:
714 if (modrm_mod != 0)
715 modrm_ea += _regs[base_reg];
716 else
717 modrm_ea += insn_fetch(s32, 4, _eip);
718 break;
719 default:
720 modrm_ea += _regs[base_reg];
721 }
722 switch (index_reg) {
723 case 4:
724 break;
725 default:
726 modrm_ea += _regs[index_reg] << scale;
727
728 }
729 break;
730 case 5:
731 if (modrm_mod != 0)
732 modrm_ea += _regs[modrm_rm];
733 else if (mode == X86EMUL_MODE_PROT64)
734 rip_relative = 1;
735 break;
736 default:
737 modrm_ea += _regs[modrm_rm];
738 break;
739 }
740 switch (modrm_mod) {
741 case 0:
742 if (modrm_rm == 5)
743 modrm_ea += insn_fetch(s32, 4, _eip);
744 break;
745 case 1:
746 modrm_ea += insn_fetch(s8, 1, _eip);
747 break;
748 case 2:
749 modrm_ea += insn_fetch(s32, 4, _eip);
750 break;
751 }
752 }
753 if (!override_base)
754 override_base = &ctxt->ds_base;
755 if (mode == X86EMUL_MODE_PROT64 &&
756 override_base != &ctxt->fs_base &&
757 override_base != &ctxt->gs_base)
758 override_base = NULL;
759
760 if (override_base)
761 modrm_ea += *override_base;
762
763 if (rip_relative) {
764 modrm_ea += _eip;
765 switch (d & SrcMask) {
766 case SrcImmByte:
767 modrm_ea += 1;
768 break;
769 case SrcImm:
770 if (d & ByteOp)
771 modrm_ea += 1;
772 else
773 if (op_bytes == 8)
774 modrm_ea += 4;
775 else
776 modrm_ea += op_bytes;
777 }
778 }
779 if (ad_bytes != 8)
780 modrm_ea = (u32)modrm_ea;
781 cr2 = modrm_ea;
782 modrm_done:
783 ;
784 }
785
6aa8b732
AK		 786 /*
787 * Decode and fetch the source operand: register, memory
788 * or immediate.
789 */
790 switch (d & SrcMask) {
791 case SrcNone:
792 break;
793 case SrcReg:
794 src.type = OP_REG;
795 if (d & ByteOp) {
796 src.ptr = decode_register(modrm_reg, _regs,
797 (rex_prefix == 0));
798 src.val = src.orig_val = *(u8 *) src.ptr;
799 src.bytes = 1;
800 } else {
801 src.ptr = decode_register(modrm_reg, _regs, 0);
802 switch ((src.bytes = op_bytes)) {
803 case 2:
804 src.val = src.orig_val = *(u16 *) src.ptr;
805 break;
806 case 4:
807 src.val = src.orig_val = *(u32 *) src.ptr;
808 break;
809 case 8:
810 src.val = src.orig_val = *(u64 *) src.ptr;
811 break;
812 }
813 }
814 break;
815 case SrcMem16:
816 src.bytes = 2;
817 goto srcmem_common;
818 case SrcMem32:
819 src.bytes = 4;
820 goto srcmem_common;
821 case SrcMem:
822 src.bytes = (d & ByteOp) ? 1 : op_bytes;
b85b9ee9
RR		 823 /* Don't fetch the address for invlpg: it could be unmapped. */
824 if (twobyte && b == 0x01 && modrm_reg == 7)
825 break;
6aa8b732
AK		 826 srcmem_common:
827 src.type = OP_MEM;
828 src.ptr = (unsigned long *)cr2;
12fa272e 829 src.val = 0;
6aa8b732 830 if ((rc = ops->read_emulated((unsigned long)src.ptr,
cebff02b 831 &src.val, src.bytes, ctxt->vcpu)) != 0)
6aa8b732
AK		 832 goto done;
833 src.orig_val = src.val;
834 break;
835 case SrcImm:
836 src.type = OP_IMM;
837 src.ptr = (unsigned long *)_eip;
838 src.bytes = (d & ByteOp) ? 1 : op_bytes;
839 if (src.bytes == 8)
840 src.bytes = 4;
841 /* NB. Immediates are sign-extended as necessary. */
842 switch (src.bytes) {
843 case 1:
844 src.val = insn_fetch(s8, 1, _eip);
845 break;
846 case 2:
847 src.val = insn_fetch(s16, 2, _eip);
848 break;
849 case 4:
850 src.val = insn_fetch(s32, 4, _eip);
851 break;
852 }
853 break;
854 case SrcImmByte:
855 src.type = OP_IMM;
856 src.ptr = (unsigned long *)_eip;
857 src.bytes = 1;
858 src.val = insn_fetch(s8, 1, _eip);
859 break;
860 }
861
038e51de
AK		 862 /* Decode and fetch the destination operand: register or memory. */
863 switch (d & DstMask) {
864 case ImplicitOps:
865 /* Special instructions do their own operand decoding. */
866 goto special_insn;
867 case DstReg:
868 dst.type = OP_REG;
869 if ((d & ByteOp)
394b6e59 870 && !(twobyte && (b == 0xb6 || b == 0xb7))) {
038e51de
AK		 871 dst.ptr = decode_register(modrm_reg, _regs,
872 (rex_prefix == 0));
873 dst.val = *(u8 *) dst.ptr;
874 dst.bytes = 1;
875 } else {
876 dst.ptr = decode_register(modrm_reg, _regs, 0);
877 switch ((dst.bytes = op_bytes)) {
878 case 2:
879 dst.val = *(u16 *)dst.ptr;
880 break;
881 case 4:
882 dst.val = *(u32 *)dst.ptr;
883 break;
884 case 8:
885 dst.val = *(u64 *)dst.ptr;
886 break;
887 }
888 }
889 break;
890 case DstMem:
891 dst.type = OP_MEM;
892 dst.ptr = (unsigned long *)cr2;
893 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
12fa272e 894 dst.val = 0;
038e51de 895 if (d & BitOp) {
df513e2c
AK		 896 unsigned long mask = ~(dst.bytes * 8 - 1);
897
898 dst.ptr = (void *)dst.ptr + (src.val & mask) / 8;
038e51de
AK		 899 }
900 if (!(d & Mov) && /* optimisation - avoid slow emulated read */
901 ((rc = ops->read_emulated((unsigned long)dst.ptr,
cebff02b 902 &dst.val, dst.bytes, ctxt->vcpu)) != 0))
038e51de
AK		 903 goto done;
904 break;
905 }
906 dst.orig_val = dst.val;
907
6aa8b732
AK		 908 if (twobyte)
909 goto twobyte_insn;
910
911 switch (b) {
912 case 0x00 ... 0x05:
913 add: /* add */
914 emulate_2op_SrcV("add", src, dst, _eflags);
915 break;
916 case 0x08 ... 0x0d:
917 or: /* or */
918 emulate_2op_SrcV("or", src, dst, _eflags);
919 break;
920 case 0x10 ... 0x15:
921 adc: /* adc */
922 emulate_2op_SrcV("adc", src, dst, _eflags);
923 break;
924 case 0x18 ... 0x1d:
925 sbb: /* sbb */
926 emulate_2op_SrcV("sbb", src, dst, _eflags);
927 break;
19eb938e 928 case 0x20 ... 0x23:
6aa8b732
AK		 929 and: /* and */
930 emulate_2op_SrcV("and", src, dst, _eflags);
931 break;
19eb938e
NK		 932 case 0x24: /* and al imm8 */
933 dst.type = OP_REG;
934 dst.ptr = &_regs[VCPU_REGS_RAX];
935 dst.val = *(u8 *)dst.ptr;
936 dst.bytes = 1;
937 dst.orig_val = dst.val;
938 goto and;
939 case 0x25: /* and ax imm16, or eax imm32 */
940 dst.type = OP_REG;
941 dst.bytes = op_bytes;
942 dst.ptr = &_regs[VCPU_REGS_RAX];
943 if (op_bytes == 2)
944 dst.val = *(u16 *)dst.ptr;
945 else
946 dst.val = *(u32 *)dst.ptr;
947 dst.orig_val = dst.val;
948 goto and;
6aa8b732
AK		 949 case 0x28 ... 0x2d:
950 sub: /* sub */
951 emulate_2op_SrcV("sub", src, dst, _eflags);
952 break;
953 case 0x30 ... 0x35:
954 xor: /* xor */
955 emulate_2op_SrcV("xor", src, dst, _eflags);
956 break;
957 case 0x38 ... 0x3d:
958 cmp: /* cmp */
959 emulate_2op_SrcV("cmp", src, dst, _eflags);
960 break;
961 case 0x63: /* movsxd */
962 if (mode != X86EMUL_MODE_PROT64)
963 goto cannot_emulate;
964 dst.val = (s32) src.val;
965 break;
7d316911
NK		 966 case 0x6a: /* push imm8 */
967 src.val = 0L;
968 src.val = insn_fetch(s8, 1, _eip);
969push:
970 dst.type = OP_MEM;
971 dst.bytes = op_bytes;
972 dst.val = src.val;
973 register_address_increment(_regs[VCPU_REGS_RSP], -op_bytes);
fd2a7608
NK		 974 dst.ptr = (void *) register_address(ctxt->ss_base,
975 _regs[VCPU_REGS_RSP]);
7d316911 976 break;
6aa8b732
AK		 977 case 0x80 ... 0x83: /* Grp1 */
978 switch (modrm_reg) {
979 case 0:
980 goto add;
981 case 1:
982 goto or;
983 case 2:
984 goto adc;
985 case 3:
986 goto sbb;
987 case 4:
988 goto and;
989 case 5:
990 goto sub;
991 case 6:
992 goto xor;
993 case 7:
994 goto cmp;
995 }
996 break;
997 case 0x84 ... 0x85:
998 test: /* test */
999 emulate_2op_SrcV("test", src, dst, _eflags);
1000 break;
1001 case 0x86 ... 0x87: /* xchg */
1002 /* Write back the register source. */
1003 switch (dst.bytes) {
1004 case 1:
1005 *(u8 *) src.ptr = (u8) dst.val;
1006 break;
1007 case 2:
1008 *(u16 *) src.ptr = (u16) dst.val;
1009 break;
1010 case 4:
1011 *src.ptr = (u32) dst.val;
1012 break; /* 64b reg: zero-extend */
1013 case 8:
1014 *src.ptr = dst.val;
1015 break;
1016 }
1017 /*
1018 * Write back the memory destination with implicit LOCK
1019 * prefix.
1020 */
1021 dst.val = src.val;
1022 lock_prefix = 1;
1023 break;
6aa8b732 1024 case 0x88 ... 0x8b: /* mov */
7de75248 1025 goto mov;
7e0b54b1
NK		 1026 case 0x8d: /* lea r16/r32, m */
1027 dst.val = modrm_val;
1028 break;
6aa8b732
AK		 1029 case 0x8f: /* pop (sole member of Grp1a) */
1030 /* 64-bit mode: POP always pops a 64-bit operand. */
1031 if (mode == X86EMUL_MODE_PROT64)
1032 dst.bytes = 8;
1033 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1034 _regs[VCPU_REGS_RSP]),
cebff02b 1035 &dst.val, dst.bytes, ctxt->vcpu)) != 0)
6aa8b732
AK		 1036 goto done;
1037 register_address_increment(_regs[VCPU_REGS_RSP], dst.bytes);
1038 break;
7de75248
NK		 1039 case 0xa0 ... 0xa1: /* mov */
1040 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1041 dst.val = src.val;
1042 _eip += ad_bytes; /* skip src displacement */
1043 break;
1044 case 0xa2 ... 0xa3: /* mov */
1045 dst.val = (unsigned long)_regs[VCPU_REGS_RAX];
1046 _eip += ad_bytes; /* skip dst displacement */
1047 break;
6aa8b732
AK		 1048 case 0xc0 ... 0xc1:
1049 grp2: /* Grp2 */
1050 switch (modrm_reg) {
1051 case 0: /* rol */
1052 emulate_2op_SrcB("rol", src, dst, _eflags);
1053 break;
1054 case 1: /* ror */
1055 emulate_2op_SrcB("ror", src, dst, _eflags);
1056 break;
1057 case 2: /* rcl */
1058 emulate_2op_SrcB("rcl", src, dst, _eflags);
1059 break;
1060 case 3: /* rcr */
1061 emulate_2op_SrcB("rcr", src, dst, _eflags);
1062 break;
1063 case 4: /* sal/shl */
1064 case 6: /* sal/shl */
1065 emulate_2op_SrcB("sal", src, dst, _eflags);
1066 break;
1067 case 5: /* shr */
1068 emulate_2op_SrcB("shr", src, dst, _eflags);
1069 break;
1070 case 7: /* sar */
1071 emulate_2op_SrcB("sar", src, dst, _eflags);
1072 break;
1073 }
1074 break;
7de75248
NK		 1075 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1076 mov:
1077 dst.val = src.val;
1078 break;
6aa8b732
AK		 1079 case 0xd0 ... 0xd1: /* Grp2 */
1080 src.val = 1;
1081 goto grp2;
1082 case 0xd2 ... 0xd3: /* Grp2 */
1083 src.val = _regs[VCPU_REGS_RCX];
1084 goto grp2;
1085 case 0xf6 ... 0xf7: /* Grp3 */
1086 switch (modrm_reg) {
1087 case 0 ... 1: /* test */
1088 /*
1089 * Special case in Grp3: test has an immediate
1090 * source operand.
1091 */
1092 src.type = OP_IMM;
1093 src.ptr = (unsigned long *)_eip;
1094 src.bytes = (d & ByteOp) ? 1 : op_bytes;
1095 if (src.bytes == 8)
1096 src.bytes = 4;
1097 switch (src.bytes) {
1098 case 1:
1099 src.val = insn_fetch(s8, 1, _eip);
1100 break;
1101 case 2:
1102 src.val = insn_fetch(s16, 2, _eip);
1103 break;
1104 case 4:
1105 src.val = insn_fetch(s32, 4, _eip);
1106 break;
1107 }
1108 goto test;
1109 case 2: /* not */
1110 dst.val = ~dst.val;
1111 break;
1112 case 3: /* neg */
1113 emulate_1op("neg", dst, _eflags);
1114 break;
1115 default:
1116 goto cannot_emulate;
1117 }
1118 break;
1119 case 0xfe ... 0xff: /* Grp4/Grp5 */
1120 switch (modrm_reg) {
1121 case 0: /* inc */
1122 emulate_1op("inc", dst, _eflags);
1123 break;
1124 case 1: /* dec */
1125 emulate_1op("dec", dst, _eflags);
1126 break;
26a3e983
NK		 1127 case 4: /* jmp abs */
1128 if (b == 0xff)
1129 _eip = dst.val;
1130 else
1131 goto cannot_emulate;
1132 break;
6aa8b732
AK		 1133 case 6: /* push */
1134 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1135 if (mode == X86EMUL_MODE_PROT64) {
1136 dst.bytes = 8;
1137 if ((rc = ops->read_std((unsigned long)dst.ptr,
1138 &dst.val, 8,
cebff02b 1139 ctxt->vcpu)) != 0)
6aa8b732
AK		 1140 goto done;
1141 }
1142 register_address_increment(_regs[VCPU_REGS_RSP],
1143 -dst.bytes);
1144 if ((rc = ops->write_std(
1145 register_address(ctxt->ss_base,
1146 _regs[VCPU_REGS_RSP]),
cebff02b 1147 &dst.val, dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1148 goto done;
02c03a32 1149 no_wb = 1;
6aa8b732
AK		 1150 break;
1151 default:
1152 goto cannot_emulate;
1153 }
1154 break;
1155 }
1156
1157writeback:
02c03a32 1158 if (!no_wb) {
6aa8b732
AK		 1159 switch (dst.type) {
1160 case OP_REG:
1161 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1162 switch (dst.bytes) {
1163 case 1:
1164 *(u8 *)dst.ptr = (u8)dst.val;
1165 break;
1166 case 2:
1167 *(u16 *)dst.ptr = (u16)dst.val;
1168 break;
1169 case 4:
1170 *dst.ptr = (u32)dst.val;
1171 break; /* 64b: zero-ext */
1172 case 8:
1173 *dst.ptr = dst.val;
1174 break;
1175 }
1176 break;
1177 case OP_MEM:
1178 if (lock_prefix)
1179 rc = ops->cmpxchg_emulated((unsigned long)dst.
4c690a1e
AK		 1180 ptr, &dst.orig_val,
1181 &dst.val, dst.bytes,
cebff02b 1182 ctxt->vcpu);
6aa8b732
AK		 1183 else
1184 rc = ops->write_emulated((unsigned long)dst.ptr,
4c690a1e 1185 &dst.val, dst.bytes,
cebff02b 1186 ctxt->vcpu);
6aa8b732
AK		 1187 if (rc != 0)
1188 goto done;
1189 default:
1190 break;
1191 }
1192 }
1193
1194 /* Commit shadow register state. */
1195 memcpy(ctxt->vcpu->regs, _regs, sizeof _regs);
1196 ctxt->eflags = _eflags;
1197 ctxt->vcpu->rip = _eip;
1198
1199done:
1200 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1201
1202special_insn:
1203 if (twobyte)
1204 goto twobyte_special_insn;
e70669ab 1205 switch(b) {
7e778161
NK		 1206 case 0x50 ... 0x57: /* push reg */
1207 if (op_bytes == 2)
1208 src.val = (u16) _regs[b & 0x7];
1209 else
1210 src.val = (u32) _regs[b & 0x7];
1211 dst.type = OP_MEM;
1212 dst.bytes = op_bytes;
1213 dst.val = src.val;
1214 register_address_increment(_regs[VCPU_REGS_RSP], -op_bytes);
1215 dst.ptr = (void *) register_address(
1216 ctxt->ss_base, _regs[VCPU_REGS_RSP]);
7e778161 1217 break;
7de75248
NK		 1218 case 0x58 ... 0x5f: /* pop reg */
1219 dst.ptr = (unsigned long *)&_regs[b & 0x7];
1220 pop_instruction:
1221 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1222 _regs[VCPU_REGS_RSP]), dst.ptr, op_bytes, ctxt->vcpu))
1223 != 0)
1224 goto done;
1225
1226 register_address_increment(_regs[VCPU_REGS_RSP], op_bytes);
1227 no_wb = 1; /* Disable writeback. */
1228 break;
e70669ab
LV		 1229 case 0x6c: /* insb */
1230 case 0x6d: /* insw/insd */
3090dd73 1231 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e70669ab
LV		 1232 1, /* in */
1233 (d & ByteOp) ? 1 : op_bytes, /* size */
1234 rep_prefix ?
1235 address_mask(_regs[VCPU_REGS_RCX]) : 1, /* count */
e70669ab
LV		 1236 (_eflags & EFLG_DF), /* down */
1237 register_address(ctxt->es_base,
1238 _regs[VCPU_REGS_RDI]), /* address */
1239 rep_prefix,
1240 _regs[VCPU_REGS_RDX] /* port */
1241 ) == 0)
1242 return -1;
1243 return 0;
1244 case 0x6e: /* outsb */
1245 case 0x6f: /* outsw/outsd */
3090dd73 1246 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e70669ab
LV		 1247 0, /* in */
1248 (d & ByteOp) ? 1 : op_bytes, /* size */
1249 rep_prefix ?
1250 address_mask(_regs[VCPU_REGS_RCX]) : 1, /* count */
e70669ab
LV		 1251 (_eflags & EFLG_DF), /* down */
1252 register_address(override_base ?
1253 *override_base : ctxt->ds_base,
1254 _regs[VCPU_REGS_RSI]), /* address */
1255 rep_prefix,
1256 _regs[VCPU_REGS_RDX] /* port */
1257 ) == 0)
1258 return -1;
1259 return 0;
55bebde4
NK		 1260 case 0x70 ... 0x7f: /* jcc (short) */ {
1261 int rel = insn_fetch(s8, 1, _eip);
1262
1263 if (test_cc(b, _eflags))
1264 JMP_REL(rel);
1265 break;
1266 }
fd2a7608
NK		 1267 case 0x9c: /* pushf */
1268 src.val = (unsigned long) _eflags;
1269 goto push;
535eabcf
NK		 1270 case 0x9d: /* popf */
1271 dst.ptr = (unsigned long *) &_eflags;
1272 goto pop_instruction;
7de75248
NK		 1273 case 0xc3: /* ret */
1274 dst.ptr = &_eip;
1275 goto pop_instruction;
1276 case 0xf4: /* hlt */
1277 ctxt->vcpu->halt_request = 1;
1278 goto done;
e70669ab 1279 }
6aa8b732
AK		 1280 if (rep_prefix) {
1281 if (_regs[VCPU_REGS_RCX] == 0) {
1282 ctxt->vcpu->rip = _eip;
1283 goto done;
1284 }
1285 _regs[VCPU_REGS_RCX]--;
1286 _eip = ctxt->vcpu->rip;
1287 }
1288 switch (b) {
1289 case 0xa4 ... 0xa5: /* movs */
1290 dst.type = OP_MEM;
1291 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1292 dst.ptr = (unsigned long *)register_address(ctxt->es_base,
1293 _regs[VCPU_REGS_RDI]);
1294 if ((rc = ops->read_emulated(register_address(
1295 override_base ? *override_base : ctxt->ds_base,
cebff02b 1296 _regs[VCPU_REGS_RSI]), &dst.val, dst.bytes, ctxt->vcpu)) != 0)
6aa8b732
AK		 1297 goto done;
1298 register_address_increment(_regs[VCPU_REGS_RSI],
1299 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1300 register_address_increment(_regs[VCPU_REGS_RDI],
1301 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1302 break;
1303 case 0xa6 ... 0xa7: /* cmps */
1304 DPRINTF("Urk! I don't handle CMPS.\n");
1305 goto cannot_emulate;
1306 case 0xaa ... 0xab: /* stos */
1307 dst.type = OP_MEM;
1308 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1309 dst.ptr = (unsigned long *)cr2;
1310 dst.val = _regs[VCPU_REGS_RAX];
1311 register_address_increment(_regs[VCPU_REGS_RDI],
1312 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1313 break;
1314 case 0xac ... 0xad: /* lods */
1315 dst.type = OP_REG;
1316 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1317 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
cebff02b
LV		 1318 if ((rc = ops->read_emulated(cr2, &dst.val, dst.bytes,
1319 ctxt->vcpu)) != 0)
6aa8b732
AK		 1320 goto done;
1321 register_address_increment(_regs[VCPU_REGS_RSI],
1322 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1323 break;
1324 case 0xae ... 0xaf: /* scas */
1325 DPRINTF("Urk! I don't handle SCAS.\n");
1326 goto cannot_emulate;
1a52e051
NK		 1327 case 0xe8: /* call (near) */ {
1328 long int rel;
1329 switch (op_bytes) {
1330 case 2:
1331 rel = insn_fetch(s16, 2, _eip);
1332 break;
1333 case 4:
1334 rel = insn_fetch(s32, 4, _eip);
1335 break;
1336 case 8:
1337 rel = insn_fetch(s64, 8, _eip);
1338 break;
1339 default:
1340 DPRINTF("Call: Invalid op_bytes\n");
1341 goto cannot_emulate;
1342 }
1343 src.val = (unsigned long) _eip;
1344 JMP_REL(rel);
1345 goto push;
1346 }
1347 case 0xe9: /* jmp rel */
1348 case 0xeb: /* jmp rel short */
1349 JMP_REL(src.val);
1350 no_wb = 1; /* Disable writeback. */
1351 break;
1352
7f0aaee0 1353
6aa8b732
AK		 1354 }
1355 goto writeback;
1356
1357twobyte_insn:
1358 switch (b) {
1359 case 0x01: /* lgdt, lidt, lmsw */
d37c8557
AJ		 1360 /* Disable writeback. */
1361 no_wb = 1;
6aa8b732
AK		 1362 switch (modrm_reg) {
1363 u16 size;
1364 unsigned long address;
1365
1366 case 2: /* lgdt */
1367 rc = read_descriptor(ctxt, ops, src.ptr,
1368 &size, &address, op_bytes);
1369 if (rc)
1370 goto done;
1371 realmode_lgdt(ctxt->vcpu, size, address);
1372 break;
1373 case 3: /* lidt */
1374 rc = read_descriptor(ctxt, ops, src.ptr,
1375 &size, &address, op_bytes);
1376 if (rc)
1377 goto done;
1378 realmode_lidt(ctxt->vcpu, size, address);
1379 break;
1380 case 4: /* smsw */
1381 if (modrm_mod != 3)
1382 goto cannot_emulate;
1383 *(u16 *)&_regs[modrm_rm]
1384 = realmode_get_cr(ctxt->vcpu, 0);
1385 break;
1386 case 6: /* lmsw */
1387 if (modrm_mod != 3)
1388 goto cannot_emulate;
1389 realmode_lmsw(ctxt->vcpu, (u16)modrm_val, &_eflags);
1390 break;
1391 case 7: /* invlpg*/
1392 emulate_invlpg(ctxt->vcpu, cr2);
1393 break;
1394 default:
1395 goto cannot_emulate;
1396 }
1397 break;
1398 case 0x21: /* mov from dr to reg */
bac27d35 1399 no_wb = 1;
6aa8b732
AK		 1400 if (modrm_mod != 3)
1401 goto cannot_emulate;
1402 rc = emulator_get_dr(ctxt, modrm_reg, &_regs[modrm_rm]);
1403 break;
1404 case 0x23: /* mov from reg to dr */
bac27d35 1405 no_wb = 1;
6aa8b732
AK		 1406 if (modrm_mod != 3)
1407 goto cannot_emulate;
1408 rc = emulator_set_dr(ctxt, modrm_reg, _regs[modrm_rm]);
1409 break;
1410 case 0x40 ... 0x4f: /* cmov */
1411 dst.val = dst.orig_val = src.val;
e3243452 1412 no_wb = 1;
6aa8b732
AK		 1413 /*
1414 * First, assume we're decoding an even cmov opcode
1415 * (lsb == 0).
1416 */
1417 switch ((b & 15) >> 1) {
1418 case 0: /* cmovo */
e3243452 1419 no_wb = (_eflags & EFLG_OF) ? 0 : 1;
6aa8b732
AK		 1420 break;
1421 case 1: /* cmovb/cmovc/cmovnae */
e3243452 1422 no_wb = (_eflags & EFLG_CF) ? 0 : 1;
6aa8b732
AK		 1423 break;
1424 case 2: /* cmovz/cmove */
e3243452 1425 no_wb = (_eflags & EFLG_ZF) ? 0 : 1;
6aa8b732
AK		 1426 break;
1427 case 3: /* cmovbe/cmovna */
e3243452 1428 no_wb = (_eflags & (EFLG_CF | EFLG_ZF)) ? 0 : 1;
6aa8b732
AK		 1429 break;
1430 case 4: /* cmovs */
e3243452 1431 no_wb = (_eflags & EFLG_SF) ? 0 : 1;
6aa8b732
AK		 1432 break;
1433 case 5: /* cmovp/cmovpe */
e3243452 1434 no_wb = (_eflags & EFLG_PF) ? 0 : 1;
6aa8b732
AK		 1435 break;
1436 case 7: /* cmovle/cmovng */
e3243452 1437 no_wb = (_eflags & EFLG_ZF) ? 0 : 1;
6aa8b732
AK		 1438 /* fall through */
1439 case 6: /* cmovl/cmovnge */
e3243452
AK		 1440 no_wb &= (!(_eflags & EFLG_SF) !=
1441 !(_eflags & EFLG_OF)) ? 0 : 1;
6aa8b732
AK		 1442 break;
1443 }
1444 /* Odd cmov opcodes (lsb == 1) have inverted sense. */
e3243452 1445 no_wb ^= b & 1;
6aa8b732 1446 break;
7de75248
NK		 1447 case 0xa3:
1448 bt: /* bt */
1449 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1450 emulate_2op_SrcV_nobyte("bt", src, dst, _eflags);
1451 break;
1452 case 0xab:
1453 bts: /* bts */
1454 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1455 emulate_2op_SrcV_nobyte("bts", src, dst, _eflags);
1456 break;
6aa8b732
AK		 1457 case 0xb0 ... 0xb1: /* cmpxchg */
1458 /*
1459 * Save real source value, then compare EAX against
1460 * destination.
1461 */
1462 src.orig_val = src.val;
1463 src.val = _regs[VCPU_REGS_RAX];
1464 emulate_2op_SrcV("cmp", src, dst, _eflags);
6aa8b732
AK		 1465 if (_eflags & EFLG_ZF) {
1466 /* Success: write back to memory. */
1467 dst.val = src.orig_val;
1468 } else {
1469 /* Failure: write the value we saw to EAX. */
1470 dst.type = OP_REG;
1471 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1472 }
1473 break;
6aa8b732
AK		 1474 case 0xb3:
1475 btr: /* btr */
1476 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1477 emulate_2op_SrcV_nobyte("btr", src, dst, _eflags);
1478 break;
6aa8b732
AK		 1479 case 0xb6 ... 0xb7: /* movzx */
1480 dst.bytes = op_bytes;
1481 dst.val = (d & ByteOp) ? (u8) src.val : (u16) src.val;
1482 break;
6aa8b732
AK		 1483 case 0xba: /* Grp8 */
1484 switch (modrm_reg & 3) {
1485 case 0:
1486 goto bt;
1487 case 1:
1488 goto bts;
1489 case 2:
1490 goto btr;
1491 case 3:
1492 goto btc;
1493 }
1494 break;
7de75248
NK		 1495 case 0xbb:
1496 btc: /* btc */
1497 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1498 emulate_2op_SrcV_nobyte("btc", src, dst, _eflags);
1499 break;
6aa8b732
AK		 1500 case 0xbe ... 0xbf: /* movsx */
1501 dst.bytes = op_bytes;
1502 dst.val = (d & ByteOp) ? (s8) src.val : (s16) src.val;
1503 break;
1504 }
1505 goto writeback;
1506
1507twobyte_special_insn:
1508 /* Disable writeback. */
02c03a32 1509 no_wb = 1;
6aa8b732 1510 switch (b) {
7de75248
NK		 1511 case 0x06:
1512 emulate_clts(ctxt->vcpu);
1513 break;
687fdbfe
AK		 1514 case 0x09: /* wbinvd */
1515 break;
6aa8b732
AK		 1516 case 0x0d: /* GrpP (prefetch) */
1517 case 0x18: /* Grp16 (prefetch/nop) */
1518 break;
6aa8b732
AK		 1519 case 0x20: /* mov cr, reg */
1520 if (modrm_mod != 3)
1521 goto cannot_emulate;
1522 _regs[modrm_rm] = realmode_get_cr(ctxt->vcpu, modrm_reg);
1523 break;
1524 case 0x22: /* mov reg, cr */
1525 if (modrm_mod != 3)
1526 goto cannot_emulate;
1527 realmode_set_cr(ctxt->vcpu, modrm_reg, modrm_val, &_eflags);
1528 break;
35f3f286
AK		 1529 case 0x30:
1530 /* wrmsr */
1531 msr_data = (u32)_regs[VCPU_REGS_RAX]
1532 | ((u64)_regs[VCPU_REGS_RDX] << 32);
1533 rc = kvm_set_msr(ctxt->vcpu, _regs[VCPU_REGS_RCX], msr_data);
1534 if (rc) {
cbdd1bea 1535 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
35f3f286
AK		 1536 _eip = ctxt->vcpu->rip;
1537 }
1538 rc = X86EMUL_CONTINUE;
1539 break;
1540 case 0x32:
1541 /* rdmsr */
1542 rc = kvm_get_msr(ctxt->vcpu, _regs[VCPU_REGS_RCX], &msr_data);
1543 if (rc) {
cbdd1bea 1544 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
35f3f286
AK		 1545 _eip = ctxt->vcpu->rip;
1546 } else {
1547 _regs[VCPU_REGS_RAX] = (u32)msr_data;
1548 _regs[VCPU_REGS_RDX] = msr_data >> 32;
1549 }
1550 rc = X86EMUL_CONTINUE;
1551 break;
bbe9abbd
NK		 1552 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1553 long int rel;
1554
1555 switch (op_bytes) {
1556 case 2:
1557 rel = insn_fetch(s16, 2, _eip);
1558 break;
1559 case 4:
1560 rel = insn_fetch(s32, 4, _eip);
1561 break;
1562 case 8:
1563 rel = insn_fetch(s64, 8, _eip);
1564 break;
1565 default:
1566 DPRINTF("jnz: Invalid op_bytes\n");
1567 goto cannot_emulate;
1568 }
1569 if (test_cc(b, _eflags))
1570 JMP_REL(rel);
1571 break;
1572 }
6aa8b732 1573 case 0xc7: /* Grp9 (cmpxchg8b) */
6aa8b732 1574 {
4c690a1e 1575 u64 old, new;
cebff02b
LV		 1576 if ((rc = ops->read_emulated(cr2, &old, 8, ctxt->vcpu))
1577 != 0)
6aa8b732
AK		 1578 goto done;
1579 if (((u32) (old >> 0) != (u32) _regs[VCPU_REGS_RAX]) ||
1580 ((u32) (old >> 32) != (u32) _regs[VCPU_REGS_RDX])) {
1581 _regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1582 _regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1583 _eflags &= ~EFLG_ZF;
1584 } else {
4c690a1e
AK		 1585 new = ((u64)_regs[VCPU_REGS_RCX] << 32)
1586 | (u32) _regs[VCPU_REGS_RBX];
1587 if ((rc = ops->cmpxchg_emulated(cr2, &old,
cebff02b 1588 &new, 8, ctxt->vcpu)) != 0)
6aa8b732
AK		 1589 goto done;
1590 _eflags |= EFLG_ZF;
1591 }
1592 break;
1593 }
6aa8b732
AK		 1594 }
1595 goto writeback;
1596
1597cannot_emulate:
1598 DPRINTF("Cannot emulate %02x\n", b);
1599 return -1;
1600}
1601
1602#ifdef __XEN__
1603
1604#include <asm/mm.h>
1605#include <asm/uaccess.h>
1606
1607int
1608x86_emulate_read_std(unsigned long addr,
1609 unsigned long *val,
1610 unsigned int bytes, struct x86_emulate_ctxt *ctxt)
1611{
1612 unsigned int rc;
1613
1614 *val = 0;
1615
1616 if ((rc = copy_from_user((void *)val, (void *)addr, bytes)) != 0) {
1617 propagate_page_fault(addr + bytes - rc, 0); /* read fault */
1618 return X86EMUL_PROPAGATE_FAULT;
1619 }
1620
1621 return X86EMUL_CONTINUE;
1622}
1623
1624int
1625x86_emulate_write_std(unsigned long addr,
1626 unsigned long val,
1627 unsigned int bytes, struct x86_emulate_ctxt *ctxt)
1628{
1629 unsigned int rc;
1630
1631 if ((rc = copy_to_user((void *)addr, (void *)&val, bytes)) != 0) {
1632 propagate_page_fault(addr + bytes - rc, PGERR_write_access);
1633 return X86EMUL_PROPAGATE_FAULT;
1634 }
1635
1636 return X86EMUL_CONTINUE;
1637}
1638
1639#endif
Linux kernel - Deliverables
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