projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: Purify x86_decode_insn() error case management
[deliverable/linux.git] / drivers / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
26#define DPRINTF(_f, _a ...) printf( _f , ## _a )
27#else
28#include "kvm.h"
29#define DPRINTF(x...) do {} while (0)
30#endif
31#include "x86_emulate.h"
32#include <linux/module.h>
33
34/*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43/* Operand sizes: 8-bit operands or specified/overridden size. */
44#define ByteOp (1<<0) /* 8-bit operands. */
45/* Destination operand type. */
46#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47#define DstReg (2<<1) /* Register operand. */
48#define DstMem (3<<1) /* Memory operand. */
49#define DstMask (3<<1)
50/* Source operand type. */
51#define SrcNone (0<<3) /* No source operand. */
52#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53#define SrcReg (1<<3) /* Register operand. */
54#define SrcMem (2<<3) /* Memory operand. */
55#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57#define SrcImm (5<<3) /* Immediate operand. */
58#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59#define SrcMask (7<<3)
60/* Generic ModRM decode. */
61#define ModRM (1<<6)
62/* Destination is only written; never read. */
63#define Mov (1<<7)
038e51de 64#define BitOp (1<<8)
6aa8b732
AK		 65
66static u8 opcode_table[256] = {
67 /* 0x00 - 0x07 */
68 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
69 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
70 0, 0, 0, 0,
71 /* 0x08 - 0x0F */
72 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
73 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
74 0, 0, 0, 0,
75 /* 0x10 - 0x17 */
76 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
77 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
78 0, 0, 0, 0,
79 /* 0x18 - 0x1F */
80 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
81 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
82 0, 0, 0, 0,
83 /* 0x20 - 0x27 */
84 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
85 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 86 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 87 /* 0x28 - 0x2F */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 0, 0, 0, 0,
91 /* 0x30 - 0x37 */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x38 - 0x3F */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 0, 0, 0, 0,
99 /* 0x40 - 0x4F */
100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7f0aaee0 101 /* 0x50 - 0x57 */
7e778161
NK		 102 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
103 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7f0aaee0
NK		 104 /* 0x58 - 0x5F */
105 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
106 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7d316911 107 /* 0x60 - 0x67 */
6aa8b732 108 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 109 0, 0, 0, 0,
110 /* 0x68 - 0x6F */
111 0, 0, ImplicitOps|Mov, 0,
e70669ab
LV		 112 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
113 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 114 /* 0x70 - 0x77 */
115 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
116 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
117 /* 0x78 - 0x7F */
118 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
119 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 120 /* 0x80 - 0x87 */
121 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
122 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
123 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
124 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
125 /* 0x88 - 0x8F */
126 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
127 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
7e0b54b1 128 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov,
6aa8b732 129 /* 0x90 - 0x9F */
535eabcf 130 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0,
6aa8b732
AK		 131 /* 0xA0 - 0xA7 */
132 ByteOp | DstReg | SrcMem | Mov, DstReg | SrcMem | Mov,
133 ByteOp | DstMem | SrcReg | Mov, DstMem | SrcReg | Mov,
134 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
135 ByteOp | ImplicitOps, ImplicitOps,
136 /* 0xA8 - 0xAF */
137 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
138 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
139 ByteOp | ImplicitOps, ImplicitOps,
140 /* 0xB0 - 0xBF */
141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
142 /* 0xC0 - 0xC7 */
d9413cd7
NK		 143 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
144 0, ImplicitOps, 0, 0,
145 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 146 /* 0xC8 - 0xCF */
147 0, 0, 0, 0, 0, 0, 0, 0,
148 /* 0xD0 - 0xD7 */
149 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
150 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
151 0, 0, 0, 0,
152 /* 0xD8 - 0xDF */
153 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 154 /* 0xE0 - 0xE7 */
155 0, 0, 0, 0, 0, 0, 0, 0,
156 /* 0xE8 - 0xEF */
f6eed391 157 ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0,
6aa8b732
AK		 158 /* 0xF0 - 0xF7 */
159 0, 0, 0, 0,
72d6e5a0
AK		 160 ImplicitOps, 0,
161 ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
6aa8b732
AK		 162 /* 0xF8 - 0xFF */
163 0, 0, 0, 0,
164 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
165};
166
038e51de 167static u16 twobyte_table[256] = {
6aa8b732
AK		 168 /* 0x00 - 0x0F */
169 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 170 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 171 /* 0x10 - 0x1F */
172 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
173 /* 0x20 - 0x2F */
174 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
175 0, 0, 0, 0, 0, 0, 0, 0,
176 /* 0x30 - 0x3F */
35f3f286 177 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 178 /* 0x40 - 0x47 */
179 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
180 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
181 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
182 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
183 /* 0x48 - 0x4F */
184 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
185 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
186 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
187 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
188 /* 0x50 - 0x5F */
189 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
190 /* 0x60 - 0x6F */
191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
192 /* 0x70 - 0x7F */
193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
194 /* 0x80 - 0x8F */
bbe9abbd
NK		 195 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
196 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
197 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
198 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 199 /* 0x90 - 0x9F */
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
201 /* 0xA0 - 0xA7 */
038e51de 202 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 203 /* 0xA8 - 0xAF */
038e51de 204 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 205 /* 0xB0 - 0xB7 */
206 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 207 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 208 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
209 DstReg | SrcMem16 | ModRM | Mov,
210 /* 0xB8 - 0xBF */
038e51de 211 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 212 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem16 | ModRM | Mov,
214 /* 0xC0 - 0xCF */
a012e65a
SY		 215 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
216 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 217 /* 0xD0 - 0xDF */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
219 /* 0xE0 - 0xEF */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0xF0 - 0xFF */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
223};
224
6aa8b732
AK		 225/* EFLAGS bit definitions. */
226#define EFLG_OF (1<<11)
227#define EFLG_DF (1<<10)
228#define EFLG_SF (1<<7)
229#define EFLG_ZF (1<<6)
230#define EFLG_AF (1<<4)
231#define EFLG_PF (1<<2)
232#define EFLG_CF (1<<0)
233
234/*
235 * Instruction emulation:
236 * Most instructions are emulated directly via a fragment of inline assembly
237 * code. This allows us to save/restore EFLAGS and thus very easily pick up
238 * any modified flags.
239 */
240
05b3e0c2 241#if defined(CONFIG_X86_64)
6aa8b732
AK		 242#define _LO32 "k" /* force 32-bit operand */
243#define _STK "%%rsp" /* stack pointer */
244#elif defined(__i386__)
245#define _LO32 "" /* force 32-bit operand */
246#define _STK "%%esp" /* stack pointer */
247#endif
248
249/*
250 * These EFLAGS bits are restored from saved value during emulation, and
251 * any changes are written back to the saved value after emulation.
252 */
253#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
254
255/* Before executing instruction: restore necessary bits in EFLAGS. */
256#define _PRE_EFLAGS(_sav, _msk, _tmp) \
257 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \
258 "push %"_sav"; " \
259 "movl %"_msk",%"_LO32 _tmp"; " \
260 "andl %"_LO32 _tmp",("_STK"); " \
261 "pushf; " \
262 "notl %"_LO32 _tmp"; " \
263 "andl %"_LO32 _tmp",("_STK"); " \
264 "pop %"_tmp"; " \
265 "orl %"_LO32 _tmp",("_STK"); " \
266 "popf; " \
267 /* _sav &= ~msk; */ \
268 "movl %"_msk",%"_LO32 _tmp"; " \
269 "notl %"_LO32 _tmp"; " \
270 "andl %"_LO32 _tmp",%"_sav"; "
271
272/* After executing instruction: write-back necessary bits in EFLAGS. */
273#define _POST_EFLAGS(_sav, _msk, _tmp) \
274 /* _sav |= EFLAGS & _msk; */ \
275 "pushf; " \
276 "pop %"_tmp"; " \
277 "andl %"_msk",%"_LO32 _tmp"; " \
278 "orl %"_LO32 _tmp",%"_sav"; "
279
280/* Raw emulation: instruction has two explicit operands. */
281#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
282 do { \
283 unsigned long _tmp; \
284 \
285 switch ((_dst).bytes) { \
286 case 2: \
287 __asm__ __volatile__ ( \
288 _PRE_EFLAGS("0","4","2") \
289 _op"w %"_wx"3,%1; " \
290 _POST_EFLAGS("0","4","2") \
291 : "=m" (_eflags), "=m" ((_dst).val), \
292 "=&r" (_tmp) \
293 : _wy ((_src).val), "i" (EFLAGS_MASK) ); \
294 break; \
295 case 4: \
296 __asm__ __volatile__ ( \
297 _PRE_EFLAGS("0","4","2") \
298 _op"l %"_lx"3,%1; " \
299 _POST_EFLAGS("0","4","2") \
300 : "=m" (_eflags), "=m" ((_dst).val), \
301 "=&r" (_tmp) \
302 : _ly ((_src).val), "i" (EFLAGS_MASK) ); \
303 break; \
304 case 8: \
305 __emulate_2op_8byte(_op, _src, _dst, \
306 _eflags, _qx, _qy); \
307 break; \
308 } \
309 } while (0)
310
311#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
312 do { \
313 unsigned long _tmp; \
314 switch ( (_dst).bytes ) \
315 { \
316 case 1: \
317 __asm__ __volatile__ ( \
318 _PRE_EFLAGS("0","4","2") \
319 _op"b %"_bx"3,%1; " \
320 _POST_EFLAGS("0","4","2") \
321 : "=m" (_eflags), "=m" ((_dst).val), \
322 "=&r" (_tmp) \
323 : _by ((_src).val), "i" (EFLAGS_MASK) ); \
324 break; \
325 default: \
326 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
327 _wx, _wy, _lx, _ly, _qx, _qy); \
328 break; \
329 } \
330 } while (0)
331
332/* Source operand is byte-sized and may be restricted to just %cl. */
333#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
334 __emulate_2op(_op, _src, _dst, _eflags, \
335 "b", "c", "b", "c", "b", "c", "b", "c")
336
337/* Source operand is byte, word, long or quad sized. */
338#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
339 __emulate_2op(_op, _src, _dst, _eflags, \
340 "b", "q", "w", "r", _LO32, "r", "", "r")
341
342/* Source operand is word, long or quad sized. */
343#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
344 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
345 "w", "r", _LO32, "r", "", "r")
346
347/* Instruction has only one explicit operand (no source operand). */
348#define emulate_1op(_op, _dst, _eflags) \
349 do { \
350 unsigned long _tmp; \
351 \
352 switch ( (_dst).bytes ) \
353 { \
354 case 1: \
355 __asm__ __volatile__ ( \
356 _PRE_EFLAGS("0","3","2") \
357 _op"b %1; " \
358 _POST_EFLAGS("0","3","2") \
359 : "=m" (_eflags), "=m" ((_dst).val), \
360 "=&r" (_tmp) \
361 : "i" (EFLAGS_MASK) ); \
362 break; \
363 case 2: \
364 __asm__ __volatile__ ( \
365 _PRE_EFLAGS("0","3","2") \
366 _op"w %1; " \
367 _POST_EFLAGS("0","3","2") \
368 : "=m" (_eflags), "=m" ((_dst).val), \
369 "=&r" (_tmp) \
370 : "i" (EFLAGS_MASK) ); \
371 break; \
372 case 4: \
373 __asm__ __volatile__ ( \
374 _PRE_EFLAGS("0","3","2") \
375 _op"l %1; " \
376 _POST_EFLAGS("0","3","2") \
377 : "=m" (_eflags), "=m" ((_dst).val), \
378 "=&r" (_tmp) \
379 : "i" (EFLAGS_MASK) ); \
380 break; \
381 case 8: \
382 __emulate_1op_8byte(_op, _dst, _eflags); \
383 break; \
384 } \
385 } while (0)
386
387/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 388#if defined(CONFIG_X86_64)
6aa8b732
AK		 389#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
390 do { \
391 __asm__ __volatile__ ( \
392 _PRE_EFLAGS("0","4","2") \
393 _op"q %"_qx"3,%1; " \
394 _POST_EFLAGS("0","4","2") \
395 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
396 : _qy ((_src).val), "i" (EFLAGS_MASK) ); \
397 } while (0)
398
399#define __emulate_1op_8byte(_op, _dst, _eflags) \
400 do { \
401 __asm__ __volatile__ ( \
402 _PRE_EFLAGS("0","3","2") \
403 _op"q %1; " \
404 _POST_EFLAGS("0","3","2") \
405 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
406 : "i" (EFLAGS_MASK) ); \
407 } while (0)
408
409#elif defined(__i386__)
410#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
411#define __emulate_1op_8byte(_op, _dst, _eflags)
412#endif /* __i386__ */
413
414/* Fetch next part of the instruction being emulated. */
415#define insn_fetch(_type, _size, _eip) \
416({ unsigned long _x; \
417 rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x, \
cebff02b 418 (_size), ctxt->vcpu); \
6aa8b732
AK		 419 if ( rc != 0 ) \
420 goto done; \
421 (_eip) += (_size); \
422 (_type)_x; \
423})
424
425/* Access/update address held in a register, based on addressing mode. */
e70669ab 426#define address_mask(reg) \
e4e03ded
LV		 427 ((c->ad_bytes == sizeof(unsigned long)) ? \
428 (reg) : ((reg) & ((1UL << (c->ad_bytes << 3)) - 1)))
6aa8b732 429#define register_address(base, reg) \
e70669ab 430 ((base) + address_mask(reg))
6aa8b732
AK		 431#define register_address_increment(reg, inc) \
432 do { \
433 /* signed type ensures sign extension to long */ \
434 int _inc = (inc); \
e4e03ded 435 if (c->ad_bytes == sizeof(unsigned long)) \
6aa8b732
AK		 436 (reg) += _inc; \
437 else \
e4e03ded
LV		 438 (reg) = ((reg) & \
439 ~((1UL << (c->ad_bytes << 3)) - 1)) | \
440 (((reg) + _inc) & \
441 ((1UL << (c->ad_bytes << 3)) - 1)); \
6aa8b732
AK		 442 } while (0)
443
098c937b
NK		 444#define JMP_REL(rel) \
445 do { \
e4e03ded 446 register_address_increment(c->eip, rel); \
098c937b
NK		 447 } while (0)
448
1e3c5cb0
RR		 449/*
450 * Given the 'reg' portion of a ModRM byte, and a register block, return a
451 * pointer into the block that addresses the relevant register.
452 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
453 */
454static void *decode_register(u8 modrm_reg, unsigned long *regs,
455 int highbyte_regs)
6aa8b732
AK		 456{
457 void *p;
458
459 p = &regs[modrm_reg];
460 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
461 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
462 return p;
463}
464
465static int read_descriptor(struct x86_emulate_ctxt *ctxt,
466 struct x86_emulate_ops *ops,
467 void *ptr,
468 u16 *size, unsigned long *address, int op_bytes)
469{
470 int rc;
471
472 if (op_bytes == 2)
473 op_bytes = 3;
474 *address = 0;
cebff02b
LV		 475 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
476 ctxt->vcpu);
6aa8b732
AK		 477 if (rc)
478 return rc;
cebff02b
LV		 479 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
480 ctxt->vcpu);
6aa8b732
AK		 481 return rc;
482}
483
bbe9abbd
NK		 484static int test_cc(unsigned int condition, unsigned int flags)
485{
486 int rc = 0;
487
488 switch ((condition & 15) >> 1) {
489 case 0: /* o */
490 rc |= (flags & EFLG_OF);
491 break;
492 case 1: /* b/c/nae */
493 rc |= (flags & EFLG_CF);
494 break;
495 case 2: /* z/e */
496 rc |= (flags & EFLG_ZF);
497 break;
498 case 3: /* be/na */
499 rc |= (flags & (EFLG_CF|EFLG_ZF));
500 break;
501 case 4: /* s */
502 rc |= (flags & EFLG_SF);
503 break;
504 case 5: /* p/pe */
505 rc |= (flags & EFLG_PF);
506 break;
507 case 7: /* le/ng */
508 rc |= (flags & EFLG_ZF);
509 /* fall through */
510 case 6: /* l/nge */
511 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
512 break;
513 }
514
515 /* Odd condition identifiers (lsb == 1) have inverted sense. */
516 return (!!rc ^ (condition & 1));
517}
518
6aa8b732 519int
8b4caf66 520x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 521{
e4e03ded
LV		 522 struct decode_cache *c = &ctxt->decode;
523 u8 sib, rex_prefix = 0;
524 unsigned int i;
6aa8b732 525 int rc = 0;
6aa8b732 526 int mode = ctxt->mode;
e4e03ded 527 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
6aa8b732
AK		 528
529 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 530
e4e03ded
LV		 531 memset(c, 0, sizeof(struct decode_cache));
532 c->eip = ctxt->vcpu->rip;
533 memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs);
6aa8b732
AK		 534
535 switch (mode) {
536 case X86EMUL_MODE_REAL:
537 case X86EMUL_MODE_PROT16:
e4e03ded 538 c->op_bytes = c->ad_bytes = 2;
6aa8b732
AK		 539 break;
540 case X86EMUL_MODE_PROT32:
e4e03ded 541 c->op_bytes = c->ad_bytes = 4;
6aa8b732 542 break;
05b3e0c2 543#ifdef CONFIG_X86_64
6aa8b732 544 case X86EMUL_MODE_PROT64:
e4e03ded
LV		 545 c->op_bytes = 4;
546 c->ad_bytes = 8;
6aa8b732
AK		 547 break;
548#endif
549 default:
550 return -1;
551 }
552
553 /* Legacy prefixes. */
554 for (i = 0; i < 8; i++) {
e4e03ded 555 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 556 case 0x66: /* operand-size override */
e4e03ded 557 c->op_bytes ^= 6; /* switch between 2/4 bytes */
6aa8b732
AK		 558 break;
559 case 0x67: /* address-size override */
560 if (mode == X86EMUL_MODE_PROT64)
e4e03ded
LV		 561 /* switch between 4/8 bytes */
562 c->ad_bytes ^= 12;
6aa8b732 563 else
e4e03ded
LV		 564 /* switch between 2/4 bytes */
565 c->ad_bytes ^= 6;
6aa8b732
AK		 566 break;
567 case 0x2e: /* CS override */
e4e03ded 568 c->override_base = &ctxt->cs_base;
6aa8b732
AK		 569 break;
570 case 0x3e: /* DS override */
e4e03ded 571 c->override_base = &ctxt->ds_base;
6aa8b732
AK		 572 break;
573 case 0x26: /* ES override */
e4e03ded 574 c->override_base = &ctxt->es_base;
6aa8b732
AK		 575 break;
576 case 0x64: /* FS override */
e4e03ded 577 c->override_base = &ctxt->fs_base;
6aa8b732
AK		 578 break;
579 case 0x65: /* GS override */
e4e03ded 580 c->override_base = &ctxt->gs_base;
6aa8b732
AK		 581 break;
582 case 0x36: /* SS override */
e4e03ded 583 c->override_base = &ctxt->ss_base;
6aa8b732
AK		 584 break;
585 case 0xf0: /* LOCK */
e4e03ded 586 c->lock_prefix = 1;
6aa8b732 587 break;
ae6200ba 588 case 0xf2: /* REPNE/REPNZ */
6aa8b732 589 case 0xf3: /* REP/REPE/REPZ */
e4e03ded 590 c->rep_prefix = 1;
6aa8b732 591 break;
6aa8b732
AK		 592 default:
593 goto done_prefixes;
594 }
595 }
596
597done_prefixes:
598
599 /* REX prefix. */
e4e03ded
LV		 600 if ((mode == X86EMUL_MODE_PROT64) && ((c->b & 0xf0) == 0x40)) {
601 rex_prefix = c->b;
602 if (c->b & 8)
603 c->op_bytes = 8; /* REX.W */
604 c->modrm_reg = (c->b & 4) << 1; /* REX.R */
605 index_reg = (c->b & 2) << 2; /* REX.X */
606 c->modrm_rm = base_reg = (c->b & 1) << 3; /* REG.B */
607 c->b = insn_fetch(u8, 1, c->eip);
6aa8b732
AK		 608 }
609
610 /* Opcode byte(s). */
e4e03ded
LV		 611 c->d = opcode_table[c->b];
612 if (c->d == 0) {
6aa8b732 613 /* Two-byte opcode? */
e4e03ded
LV		 614 if (c->b == 0x0f) {
615 c->twobyte = 1;
616 c->b = insn_fetch(u8, 1, c->eip);
617 c->d = twobyte_table[c->b];
6aa8b732
AK		 618 }
619
620 /* Unrecognised? */
8b4caf66
LV		 621 if (c->d == 0) {
622 DPRINTF("Cannot emulate %02x\n", c->b);
623 return -1;
624 }
6aa8b732
AK		 625 }
626
627 /* ModRM and SIB bytes. */
e4e03ded
LV		 628 if (c->d & ModRM) {
629 c->modrm = insn_fetch(u8, 1, c->eip);
630 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
631 c->modrm_reg |= (c->modrm & 0x38) >> 3;
632 c->modrm_rm |= (c->modrm & 0x07);
633 c->modrm_ea = 0;
634 c->use_modrm_ea = 1;
635
636 if (c->modrm_mod == 3) {
637 c->modrm_val = *(unsigned long *)
638 decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
6aa8b732
AK		 639 goto modrm_done;
640 }
641
e4e03ded
LV		 642 if (c->ad_bytes == 2) {
643 unsigned bx = c->regs[VCPU_REGS_RBX];
644 unsigned bp = c->regs[VCPU_REGS_RBP];
645 unsigned si = c->regs[VCPU_REGS_RSI];
646 unsigned di = c->regs[VCPU_REGS_RDI];
6aa8b732
AK		 647
648 /* 16-bit ModR/M decode. */
e4e03ded 649 switch (c->modrm_mod) {
6aa8b732 650 case 0:
e4e03ded
LV		 651 if (c->modrm_rm == 6)
652 c->modrm_ea +=
653 insn_fetch(u16, 2, c->eip);
6aa8b732
AK		 654 break;
655 case 1:
e4e03ded 656 c->modrm_ea += insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 657 break;
658 case 2:
e4e03ded 659 c->modrm_ea += insn_fetch(u16, 2, c->eip);
6aa8b732
AK		 660 break;
661 }
e4e03ded 662 switch (c->modrm_rm) {
6aa8b732 663 case 0:
e4e03ded 664 c->modrm_ea += bx + si;
6aa8b732
AK		 665 break;
666 case 1:
e4e03ded 667 c->modrm_ea += bx + di;
6aa8b732
AK		 668 break;
669 case 2:
e4e03ded 670 c->modrm_ea += bp + si;
6aa8b732
AK		 671 break;
672 case 3:
e4e03ded 673 c->modrm_ea += bp + di;
6aa8b732
AK		 674 break;
675 case 4:
e4e03ded 676 c->modrm_ea += si;
6aa8b732
AK		 677 break;
678 case 5:
e4e03ded 679 c->modrm_ea += di;
6aa8b732
AK		 680 break;
681 case 6:
e4e03ded
LV		 682 if (c->modrm_mod != 0)
683 c->modrm_ea += bp;
6aa8b732
AK		 684 break;
685 case 7:
e4e03ded 686 c->modrm_ea += bx;
6aa8b732
AK		 687 break;
688 }
e4e03ded
LV		 689 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
690 (c->modrm_rm == 6 && c->modrm_mod != 0))
691 if (!c->override_base)
692 c->override_base = &ctxt->ss_base;
693 c->modrm_ea = (u16)c->modrm_ea;
6aa8b732
AK		 694 } else {
695 /* 32/64-bit ModR/M decode. */
e4e03ded 696 switch (c->modrm_rm) {
6aa8b732
AK		 697 case 4:
698 case 12:
e4e03ded 699 sib = insn_fetch(u8, 1, c->eip);
6aa8b732
AK		 700 index_reg |= (sib >> 3) & 7;
701 base_reg |= sib & 7;
702 scale = sib >> 6;
703
704 switch (base_reg) {
705 case 5:
e4e03ded
LV		 706 if (c->modrm_mod != 0)
707 c->modrm_ea +=
708 c->regs[base_reg];
6aa8b732 709 else
e4e03ded
LV		 710 c->modrm_ea +=
711 insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 712 break;
713 default:
e4e03ded 714 c->modrm_ea += c->regs[base_reg];
6aa8b732
AK		 715 }
716 switch (index_reg) {
717 case 4:
718 break;
719 default:
e4e03ded
LV		 720 c->modrm_ea +=
721 c->regs[index_reg] << scale;
6aa8b732
AK		 722
723 }
724 break;
725 case 5:
e4e03ded
LV		 726 if (c->modrm_mod != 0)
727 c->modrm_ea += c->regs[c->modrm_rm];
6aa8b732
AK		 728 else if (mode == X86EMUL_MODE_PROT64)
729 rip_relative = 1;
730 break;
731 default:
e4e03ded 732 c->modrm_ea += c->regs[c->modrm_rm];
6aa8b732
AK		 733 break;
734 }
e4e03ded 735 switch (c->modrm_mod) {
6aa8b732 736 case 0:
e4e03ded
LV		 737 if (c->modrm_rm == 5)
738 c->modrm_ea +=
739 insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 740 break;
741 case 1:
e4e03ded 742 c->modrm_ea += insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 743 break;
744 case 2:
e4e03ded 745 c->modrm_ea += insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 746 break;
747 }
748 }
e4e03ded
LV		 749 if (!c->override_base)
750 c->override_base = &ctxt->ds_base;
6aa8b732 751 if (mode == X86EMUL_MODE_PROT64 &&
e4e03ded
LV		 752 c->override_base != &ctxt->fs_base &&
753 c->override_base != &ctxt->gs_base)
754 c->override_base = NULL;
6aa8b732 755
e4e03ded
LV		 756 if (c->override_base)
757 c->modrm_ea += *c->override_base;
6aa8b732
AK		 758
759 if (rip_relative) {
e4e03ded
LV		 760 c->modrm_ea += c->eip;
761 switch (c->d & SrcMask) {
6aa8b732 762 case SrcImmByte:
e4e03ded 763 c->modrm_ea += 1;
6aa8b732
AK		 764 break;
765 case SrcImm:
e4e03ded
LV		 766 if (c->d & ByteOp)
767 c->modrm_ea += 1;
6aa8b732 768 else
e4e03ded
LV		 769 if (c->op_bytes == 8)
770 c->modrm_ea += 4;
6aa8b732 771 else
e4e03ded 772 c->modrm_ea += c->op_bytes;
6aa8b732
AK		 773 }
774 }
e4e03ded
LV		 775 if (c->ad_bytes != 8)
776 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 777 modrm_done:
778 ;
779 }
780
6aa8b732
AK		 781 /*
782 * Decode and fetch the source operand: register, memory
783 * or immediate.
784 */
e4e03ded 785 switch (c->d & SrcMask) {
6aa8b732
AK		 786 case SrcNone:
787 break;
788 case SrcReg:
e4e03ded
LV		 789 c->src.type = OP_REG;
790 if (c->d & ByteOp) {
791 c->src.ptr =
792 decode_register(c->modrm_reg, c->regs,
6aa8b732 793 (rex_prefix == 0));
e4e03ded
LV		 794 c->src.val = c->src.orig_val = *(u8 *)c->src.ptr;
795 c->src.bytes = 1;
6aa8b732 796 } else {
e4e03ded
LV		 797 c->src.ptr =
798 decode_register(c->modrm_reg, c->regs, 0);
799 switch ((c->src.bytes = c->op_bytes)) {
6aa8b732 800 case 2:
e4e03ded
LV		 801 c->src.val = c->src.orig_val =
802 *(u16 *) c->src.ptr;
6aa8b732
AK		 803 break;
804 case 4:
e4e03ded
LV		 805 c->src.val = c->src.orig_val =
806 *(u32 *) c->src.ptr;
6aa8b732
AK		 807 break;
808 case 8:
e4e03ded
LV		 809 c->src.val = c->src.orig_val =
810 *(u64 *) c->src.ptr;
6aa8b732
AK		 811 break;
812 }
813 }
814 break;
815 case SrcMem16:
e4e03ded 816 c->src.bytes = 2;
6aa8b732
AK		 817 goto srcmem_common;
818 case SrcMem32:
e4e03ded 819 c->src.bytes = 4;
6aa8b732
AK		 820 goto srcmem_common;
821 case SrcMem:
e4e03ded
LV		 822 c->src.bytes = (c->d & ByteOp) ? 1 :
823 c->op_bytes;
b85b9ee9 824 /* Don't fetch the address for invlpg: it could be unmapped. */
e4e03ded
LV		 825 if (c->twobyte && c->b == 0x01
826 && c->modrm_reg == 7)
b85b9ee9 827 break;
6aa8b732 828 srcmem_common:
4e62417b
AJ		 829 /*
830 * For instructions with a ModR/M byte, switch to register
831 * access if Mod = 3.
832 */
e4e03ded
LV		 833 if ((c->d & ModRM) && c->modrm_mod == 3) {
834 c->src.type = OP_REG;
4e62417b
AJ		 835 break;
836 }
e4e03ded 837 c->src.type = OP_MEM;
6aa8b732
AK		 838 break;
839 case SrcImm:
e4e03ded
LV		 840 c->src.type = OP_IMM;
841 c->src.ptr = (unsigned long *)c->eip;
842 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
843 if (c->src.bytes == 8)
844 c->src.bytes = 4;
6aa8b732 845 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 846 switch (c->src.bytes) {
6aa8b732 847 case 1:
e4e03ded 848 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 849 break;
850 case 2:
e4e03ded 851 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 852 break;
853 case 4:
e4e03ded 854 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 855 break;
856 }
857 break;
858 case SrcImmByte:
e4e03ded
LV		 859 c->src.type = OP_IMM;
860 c->src.ptr = (unsigned long *)c->eip;
861 c->src.bytes = 1;
862 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 863 break;
864 }
865
038e51de 866 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 867 switch (c->d & DstMask) {
038e51de
AK		 868 case ImplicitOps:
869 /* Special instructions do their own operand decoding. */
8b4caf66 870 return 0;
038e51de 871 case DstReg:
e4e03ded
LV		 872 c->dst.type = OP_REG;
873 if ((c->d & ByteOp)
874 && !(c->twobyte &&
875 (c->b == 0xb6 || c->b == 0xb7))) {
876 c->dst.ptr =
877 decode_register(c->modrm_reg, c->regs,
038e51de 878 (rex_prefix == 0));
e4e03ded
LV		 879 c->dst.val = *(u8 *) c->dst.ptr;
880 c->dst.bytes = 1;
038e51de 881 } else {
e4e03ded
LV		 882 c->dst.ptr =
883 decode_register(c->modrm_reg, c->regs, 0);
884 switch ((c->dst.bytes = c->op_bytes)) {
038e51de 885 case 2:
e4e03ded 886 c->dst.val = *(u16 *)c->dst.ptr;
038e51de
AK		 887 break;
888 case 4:
e4e03ded 889 c->dst.val = *(u32 *)c->dst.ptr;
038e51de
AK		 890 break;
891 case 8:
e4e03ded 892 c->dst.val = *(u64 *)c->dst.ptr;
038e51de
AK		 893 break;
894 }
895 }
896 break;
897 case DstMem:
e4e03ded
LV		 898 if ((c->d & ModRM) && c->modrm_mod == 3) {
899 c->dst.type = OP_REG;
4e62417b
AJ		 900 break;
901 }
8b4caf66
LV		 902 c->dst.type = OP_MEM;
903 break;
904 }
905
906done:
907 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
908}
909
8cdbd2c9
LV		 910static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
911{
912 struct decode_cache *c = &ctxt->decode;
913
914 c->dst.type = OP_MEM;
915 c->dst.bytes = c->op_bytes;
916 c->dst.val = c->src.val;
917 register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes);
918 c->dst.ptr = (void *) register_address(ctxt->ss_base,
919 c->regs[VCPU_REGS_RSP]);
920}
921
922static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
923 struct x86_emulate_ops *ops)
924{
925 struct decode_cache *c = &ctxt->decode;
926 int rc;
927
928 /* 64-bit mode: POP always pops a 64-bit operand. */
929
930 if (ctxt->mode == X86EMUL_MODE_PROT64)
931 c->dst.bytes = 8;
932
933 rc = ops->read_std(register_address(ctxt->ss_base,
934 c->regs[VCPU_REGS_RSP]),
935 &c->dst.val, c->dst.bytes, ctxt->vcpu);
936 if (rc != 0)
937 return rc;
938
939 register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes);
940
941 return 0;
942}
943
05f086f8 944static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 945{
05f086f8 946 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 947 switch (c->modrm_reg) {
948 case 0: /* rol */
05f086f8 949 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 950 break;
951 case 1: /* ror */
05f086f8 952 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 953 break;
954 case 2: /* rcl */
05f086f8 955 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 956 break;
957 case 3: /* rcr */
05f086f8 958 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 959 break;
960 case 4: /* sal/shl */
961 case 6: /* sal/shl */
05f086f8 962 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 963 break;
964 case 5: /* shr */
05f086f8 965 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 966 break;
967 case 7: /* sar */
05f086f8 968 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 969 break;
970 }
971}
972
973static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 974 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 975{
976 struct decode_cache *c = &ctxt->decode;
977 int rc = 0;
978
979 switch (c->modrm_reg) {
980 case 0 ... 1: /* test */
981 /*
982 * Special case in Grp3: test has an immediate
983 * source operand.
984 */
985 c->src.type = OP_IMM;
986 c->src.ptr = (unsigned long *)c->eip;
987 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
988 if (c->src.bytes == 8)
989 c->src.bytes = 4;
990 switch (c->src.bytes) {
991 case 1:
992 c->src.val = insn_fetch(s8, 1, c->eip);
993 break;
994 case 2:
995 c->src.val = insn_fetch(s16, 2, c->eip);
996 break;
997 case 4:
998 c->src.val = insn_fetch(s32, 4, c->eip);
999 break;
1000 }
05f086f8 1001 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1002 break;
1003 case 2: /* not */
1004 c->dst.val = ~c->dst.val;
1005 break;
1006 case 3: /* neg */
05f086f8 1007 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1008 break;
1009 default:
1010 DPRINTF("Cannot emulate %02x\n", c->b);
1011 rc = X86EMUL_UNHANDLEABLE;
1012 break;
1013 }
1014done:
1015 return rc;
1016}
1017
1018static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1019 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1020{
1021 struct decode_cache *c = &ctxt->decode;
1022 int rc;
1023
1024 switch (c->modrm_reg) {
1025 case 0: /* inc */
05f086f8 1026 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1027 break;
1028 case 1: /* dec */
05f086f8 1029 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1030 break;
1031 case 4: /* jmp abs */
1032 if (c->b == 0xff)
1033 c->eip = c->dst.val;
1034 else {
1035 DPRINTF("Cannot emulate %02x\n", c->b);
1036 return X86EMUL_UNHANDLEABLE;
1037 }
1038 break;
1039 case 6: /* push */
1040
1041 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1042
1043 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1044 c->dst.bytes = 8;
1045 rc = ops->read_std((unsigned long)c->dst.ptr,
1046 &c->dst.val, 8, ctxt->vcpu);
1047 if (rc != 0)
1048 return rc;
1049 }
1050 register_address_increment(c->regs[VCPU_REGS_RSP],
1051 -c->dst.bytes);
1052 rc = ops->write_emulated(register_address(ctxt->ss_base,
1053 c->regs[VCPU_REGS_RSP]), &c->dst.val,
1054 c->dst.bytes, ctxt->vcpu);
1055 if (rc != 0)
1056 return rc;
a01af5ec 1057 c->dst.type = OP_NONE;
8cdbd2c9
LV		 1058 break;
1059 default:
1060 DPRINTF("Cannot emulate %02x\n", c->b);
1061 return X86EMUL_UNHANDLEABLE;
1062 }
1063 return 0;
1064}
1065
1066static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1067 struct x86_emulate_ops *ops,
8cdbd2c9
LV		 1068 unsigned long cr2)
1069{
1070 struct decode_cache *c = &ctxt->decode;
1071 u64 old, new;
1072 int rc;
1073
1074 rc = ops->read_emulated(cr2, &old, 8, ctxt->vcpu);
1075 if (rc != 0)
1076 return rc;
1077
1078 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1079 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1080
1081 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1082 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1083 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1084
1085 } else {
1086 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1087 (u32) c->regs[VCPU_REGS_RBX];
1088
1089 rc = ops->cmpxchg_emulated(cr2, &old, &new, 8, ctxt->vcpu);
1090 if (rc != 0)
1091 return rc;
05f086f8 1092 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1093 }
1094 return 0;
1095}
1096
1097static inline int writeback(struct x86_emulate_ctxt *ctxt,
1098 struct x86_emulate_ops *ops)
1099{
1100 int rc;
1101 struct decode_cache *c = &ctxt->decode;
1102
1103 switch (c->dst.type) {
1104 case OP_REG:
1105 /* The 4-byte case *is* correct:
1106 * in 64-bit mode we zero-extend.
1107 */
1108 switch (c->dst.bytes) {
1109 case 1:
1110 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1111 break;
1112 case 2:
1113 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1114 break;
1115 case 4:
1116 *c->dst.ptr = (u32)c->dst.val;
1117 break; /* 64b: zero-ext */
1118 case 8:
1119 *c->dst.ptr = c->dst.val;
1120 break;
1121 }
1122 break;
1123 case OP_MEM:
1124 if (c->lock_prefix)
1125 rc = ops->cmpxchg_emulated(
1126 (unsigned long)c->dst.ptr,
1127 &c->dst.orig_val,
1128 &c->dst.val,
1129 c->dst.bytes,
1130 ctxt->vcpu);
1131 else
1132 rc = ops->write_emulated(
1133 (unsigned long)c->dst.ptr,
1134 &c->dst.val,
1135 c->dst.bytes,
1136 ctxt->vcpu);
1137 if (rc != 0)
1138 return rc;
a01af5ec
LV		 1139 break;
1140 case OP_NONE:
1141 /* no writeback */
1142 break;
8cdbd2c9
LV		 1143 default:
1144 break;
1145 }
1146 return 0;
1147}
1148
8b4caf66 1149int
1be3aa47 1150x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66
LV		 1151{
1152 unsigned long cr2 = ctxt->cr2;
8b4caf66 1153 u64 msr_data;
3427318f 1154 unsigned long saved_eip = 0;
8b4caf66 1155 struct decode_cache *c = &ctxt->decode;
1be3aa47 1156 int rc = 0;
8b4caf66 1157
3427318f
LV		 1158 /* Shadow copy of register state. Committed on successful emulation.
1159 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1160 * modify them.
1161 */
1162
1163 memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs);
1164 saved_eip = c->eip;
1165
8b4caf66
LV		 1166 if ((c->d & ModRM) && (c->modrm_mod != 3))
1167 cr2 = c->modrm_ea;
1168
1169 if (c->src.type == OP_MEM) {
1170 c->src.ptr = (unsigned long *)cr2;
1171 c->src.val = 0;
1172 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1173 &c->src.val,
1174 c->src.bytes,
1175 ctxt->vcpu)) != 0)
1176 goto done;
1177 c->src.orig_val = c->src.val;
1178 }
1179
1180 if ((c->d & DstMask) == ImplicitOps)
1181 goto special_insn;
1182
1183
1184 if (c->dst.type == OP_MEM) {
1185 c->dst.ptr = (unsigned long *)cr2;
1186 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1187 c->dst.val = 0;
e4e03ded
LV		 1188 if (c->d & BitOp) {
1189 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1190
e4e03ded
LV		 1191 c->dst.ptr = (void *)c->dst.ptr +
1192 (c->src.val & mask) / 8;
038e51de 1193 }
e4e03ded
LV		 1194 if (!(c->d & Mov) &&
1195 /* optimisation - avoid slow emulated read */
1196 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1197 &c->dst.val,
1198 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1199 goto done;
038e51de 1200 }
e4e03ded 1201 c->dst.orig_val = c->dst.val;
038e51de 1202
e4e03ded 1203 if (c->twobyte)
6aa8b732
AK		 1204 goto twobyte_insn;
1205
e4e03ded 1206 switch (c->b) {
6aa8b732
AK		 1207 case 0x00 ... 0x05:
1208 add: /* add */
05f086f8 1209 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1210 break;
1211 case 0x08 ... 0x0d:
1212 or: /* or */
05f086f8 1213 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1214 break;
1215 case 0x10 ... 0x15:
1216 adc: /* adc */
05f086f8 1217 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1218 break;
1219 case 0x18 ... 0x1d:
1220 sbb: /* sbb */
05f086f8 1221 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1222 break;
19eb938e 1223 case 0x20 ... 0x23:
6aa8b732 1224 and: /* and */
05f086f8 1225 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1226 break;
19eb938e 1227 case 0x24: /* and al imm8 */
e4e03ded
LV		 1228 c->dst.type = OP_REG;
1229 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1230 c->dst.val = *(u8 *)c->dst.ptr;
1231 c->dst.bytes = 1;
1232 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1233 goto and;
1234 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1235 c->dst.type = OP_REG;
1236 c->dst.bytes = c->op_bytes;
1237 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1238 if (c->op_bytes == 2)
1239 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1240 else
e4e03ded
LV		 1241 c->dst.val = *(u32 *)c->dst.ptr;
1242 c->dst.orig_val = c->dst.val;
19eb938e 1243 goto and;
6aa8b732
AK		 1244 case 0x28 ... 0x2d:
1245 sub: /* sub */
05f086f8 1246 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1247 break;
1248 case 0x30 ... 0x35:
1249 xor: /* xor */
05f086f8 1250 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1251 break;
1252 case 0x38 ... 0x3d:
1253 cmp: /* cmp */
05f086f8 1254 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1255 break;
1256 case 0x63: /* movsxd */
8b4caf66 1257 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1258 goto cannot_emulate;
e4e03ded 1259 c->dst.val = (s32) c->src.val;
6aa8b732
AK		 1260 break;
1261 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1262 switch (c->modrm_reg) {
6aa8b732
AK		 1263 case 0:
1264 goto add;
1265 case 1:
1266 goto or;
1267 case 2:
1268 goto adc;
1269 case 3:
1270 goto sbb;
1271 case 4:
1272 goto and;
1273 case 5:
1274 goto sub;
1275 case 6:
1276 goto xor;
1277 case 7:
1278 goto cmp;
1279 }
1280 break;
1281 case 0x84 ... 0x85:
05f086f8 1282 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1283 break;
1284 case 0x86 ... 0x87: /* xchg */
1285 /* Write back the register source. */
e4e03ded 1286 switch (c->dst.bytes) {
6aa8b732 1287 case 1:
e4e03ded 1288 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1289 break;
1290 case 2:
e4e03ded 1291 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1292 break;
1293 case 4:
e4e03ded 1294 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1295 break; /* 64b reg: zero-extend */
1296 case 8:
e4e03ded 1297 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1298 break;
1299 }
1300 /*
1301 * Write back the memory destination with implicit LOCK
1302 * prefix.
1303 */
e4e03ded
LV		 1304 c->dst.val = c->src.val;
1305 c->lock_prefix = 1;
6aa8b732 1306 break;
6aa8b732 1307 case 0x88 ... 0x8b: /* mov */
7de75248 1308 goto mov;
7e0b54b1 1309 case 0x8d: /* lea r16/r32, m */
e4e03ded 1310 c->dst.val = c->modrm_val;
7e0b54b1 1311 break;
6aa8b732 1312 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1313 rc = emulate_grp1a(ctxt, ops);
1314 if (rc != 0)
6aa8b732 1315 goto done;
6aa8b732 1316 break;
7de75248 1317 case 0xa0 ... 0xa1: /* mov */
e4e03ded
LV		 1318 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1319 c->dst.val = c->src.val;
1320 /* skip src displacement */
1321 c->eip += c->ad_bytes;
7de75248
NK		 1322 break;
1323 case 0xa2 ... 0xa3: /* mov */
e4e03ded
LV		 1324 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1325 /* skip c->dst displacement */
1326 c->eip += c->ad_bytes;
7de75248 1327 break;
6aa8b732 1328 case 0xc0 ... 0xc1:
05f086f8 1329 emulate_grp2(ctxt);
6aa8b732 1330 break;
7de75248
NK		 1331 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1332 mov:
e4e03ded 1333 c->dst.val = c->src.val;
7de75248 1334 break;
6aa8b732 1335 case 0xd0 ... 0xd1: /* Grp2 */
e4e03ded 1336 c->src.val = 1;
05f086f8 1337 emulate_grp2(ctxt);
8cdbd2c9 1338 break;
6aa8b732 1339 case 0xd2 ... 0xd3: /* Grp2 */
e4e03ded 1340 c->src.val = c->regs[VCPU_REGS_RCX];
05f086f8 1341 emulate_grp2(ctxt);
8cdbd2c9 1342 break;
6aa8b732 1343 case 0xf6 ... 0xf7: /* Grp3 */
05f086f8 1344 rc = emulate_grp3(ctxt, ops);
8cdbd2c9
LV		 1345 if (rc != 0)
1346 goto done;
6aa8b732
AK		 1347 break;
1348 case 0xfe ... 0xff: /* Grp4/Grp5 */
a01af5ec 1349 rc = emulate_grp45(ctxt, ops);
8cdbd2c9
LV		 1350 if (rc != 0)
1351 goto done;
6aa8b732
AK		 1352 break;
1353 }
1354
1355writeback:
a01af5ec
LV		 1356 rc = writeback(ctxt, ops);
1357 if (rc != 0)
1358 goto done;
6aa8b732
AK		 1359
1360 /* Commit shadow register state. */
e4e03ded 1361 memcpy(ctxt->vcpu->regs, c->regs, sizeof c->regs);
e4e03ded 1362 ctxt->vcpu->rip = c->eip;
6aa8b732
AK		 1363
1364done:
3427318f
LV		 1365 if (rc == X86EMUL_UNHANDLEABLE) {
1366 c->eip = saved_eip;
1367 return -1;
1368 }
1369 return 0;
6aa8b732
AK		 1370
1371special_insn:
e4e03ded 1372 if (c->twobyte)
6aa8b732 1373 goto twobyte_special_insn;
e4e03ded 1374 switch (c->b) {
7e778161 1375 case 0x50 ... 0x57: /* push reg */
e4e03ded
LV		 1376 if (c->op_bytes == 2)
1377 c->src.val = (u16) c->regs[c->b & 0x7];
7e778161 1378 else
e4e03ded
LV		 1379 c->src.val = (u32) c->regs[c->b & 0x7];
1380 c->dst.type = OP_MEM;
1381 c->dst.bytes = c->op_bytes;
1382 c->dst.val = c->src.val;
1383 register_address_increment(c->regs[VCPU_REGS_RSP],
1384 -c->op_bytes);
1385 c->dst.ptr = (void *) register_address(
1386 ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
7e778161 1387 break;
7de75248 1388 case 0x58 ... 0x5f: /* pop reg */
8cdbd2c9 1389 c->dst.ptr = (unsigned long *)&c->regs[c->b & 0x7];
7de75248
NK		 1390 pop_instruction:
1391 if ((rc = ops->read_std(register_address(ctxt->ss_base,
e4e03ded
LV		 1392 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1393 c->op_bytes, ctxt->vcpu)) != 0)
7de75248
NK		 1394 goto done;
1395
e4e03ded
LV		 1396 register_address_increment(c->regs[VCPU_REGS_RSP],
1397 c->op_bytes);
a01af5ec 1398 c->dst.type = OP_NONE; /* Disable writeback. */
7de75248 1399 break;
1e35d3c4 1400 case 0x6a: /* push imm8 */
e4e03ded
LV		 1401 c->src.val = 0L;
1402 c->src.val = insn_fetch(s8, 1, c->eip);
8cdbd2c9 1403 emulate_push(ctxt);
1e35d3c4 1404 break;
e70669ab
LV		 1405 case 0x6c: /* insb */
1406 case 0x6d: /* insw/insd */
3090dd73 1407 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e4e03ded
LV		 1408 1,
1409 (c->d & ByteOp) ? 1 : c->op_bytes,
1410 c->rep_prefix ?
1411 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
05f086f8 1412 (ctxt->eflags & EFLG_DF),
e70669ab 1413 register_address(ctxt->es_base,
e4e03ded
LV		 1414 c->regs[VCPU_REGS_RDI]),
1415 c->rep_prefix,
3427318f
LV		 1416 c->regs[VCPU_REGS_RDX]) == 0) {
1417 c->eip = saved_eip;
e70669ab 1418 return -1;
3427318f 1419 }
e70669ab
LV		 1420 return 0;
1421 case 0x6e: /* outsb */
1422 case 0x6f: /* outsw/outsd */
3090dd73 1423 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e4e03ded
LV		 1424 0,
1425 (c->d & ByteOp) ? 1 : c->op_bytes,
1426 c->rep_prefix ?
1427 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
05f086f8 1428 (ctxt->eflags & EFLG_DF),
e4e03ded
LV		 1429 register_address(c->override_base ?
1430 *c->override_base :
1431 ctxt->ds_base,
1432 c->regs[VCPU_REGS_RSI]),
1433 c->rep_prefix,
3427318f
LV		 1434 c->regs[VCPU_REGS_RDX]) == 0) {
1435 c->eip = saved_eip;
e70669ab 1436 return -1;
3427318f 1437 }
e70669ab 1438 return 0;
55bebde4 1439 case 0x70 ... 0x7f: /* jcc (short) */ {
e4e03ded 1440 int rel = insn_fetch(s8, 1, c->eip);
55bebde4 1441
05f086f8 1442 if (test_cc(c->b, ctxt->eflags))
55bebde4
NK		 1443 JMP_REL(rel);
1444 break;
1445 }
fd2a7608 1446 case 0x9c: /* pushf */
05f086f8 1447 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1448 emulate_push(ctxt);
1449 break;
535eabcf 1450 case 0x9d: /* popf */
05f086f8 1451 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1452 goto pop_instruction;
7de75248 1453 case 0xc3: /* ret */
e4e03ded 1454 c->dst.ptr = &c->eip;
7de75248
NK		 1455 goto pop_instruction;
1456 case 0xf4: /* hlt */
1457 ctxt->vcpu->halt_request = 1;
1458 goto done;
e70669ab 1459 }
e4e03ded
LV		 1460 if (c->rep_prefix) {
1461 if (c->regs[VCPU_REGS_RCX] == 0) {
1462 ctxt->vcpu->rip = c->eip;
6aa8b732
AK		 1463 goto done;
1464 }
e4e03ded
LV		 1465 c->regs[VCPU_REGS_RCX]--;
1466 c->eip = ctxt->vcpu->rip;
6aa8b732 1467 }
e4e03ded 1468 switch (c->b) {
6aa8b732 1469 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1470 c->dst.type = OP_MEM;
1471 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1472 c->dst.ptr = (unsigned long *)register_address(
1473 ctxt->es_base,
1474 c->regs[VCPU_REGS_RDI]);
6aa8b732 1475 if ((rc = ops->read_emulated(register_address(
e4e03ded
LV		 1476 c->override_base ? *c->override_base :
1477 ctxt->ds_base,
1478 c->regs[VCPU_REGS_RSI]),
1479 &c->dst.val,
1480 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1481 goto done;
e4e03ded 1482 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1483 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded
LV		 1484 : c->dst.bytes);
1485 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1486 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1487 : c->dst.bytes);
6aa8b732
AK		 1488 break;
1489 case 0xa6 ... 0xa7: /* cmps */
1490 DPRINTF("Urk! I don't handle CMPS.\n");
1491 goto cannot_emulate;
1492 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1493 c->dst.type = OP_MEM;
1494 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1495 c->dst.ptr = (unsigned long *)cr2;
1496 c->dst.val = c->regs[VCPU_REGS_RAX];
1497 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1498 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1499 : c->dst.bytes);
6aa8b732
AK		 1500 break;
1501 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1502 c->dst.type = OP_REG;
1503 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1504 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1505 if ((rc = ops->read_emulated(cr2, &c->dst.val,
1506 c->dst.bytes,
cebff02b 1507 ctxt->vcpu)) != 0)
6aa8b732 1508 goto done;
e4e03ded 1509 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1510 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1511 : c->dst.bytes);
6aa8b732
AK		 1512 break;
1513 case 0xae ... 0xaf: /* scas */
1514 DPRINTF("Urk! I don't handle SCAS.\n");
1515 goto cannot_emulate;
1a52e051
NK		 1516 case 0xe8: /* call (near) */ {
1517 long int rel;
e4e03ded 1518 switch (c->op_bytes) {
1a52e051 1519 case 2:
e4e03ded 1520 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1521 break;
1522 case 4:
e4e03ded 1523 rel = insn_fetch(s32, 4, c->eip);
1a52e051
NK		 1524 break;
1525 case 8:
e4e03ded 1526 rel = insn_fetch(s64, 8, c->eip);
1a52e051
NK		 1527 break;
1528 default:
1529 DPRINTF("Call: Invalid op_bytes\n");
1530 goto cannot_emulate;
1531 }
e4e03ded 1532 c->src.val = (unsigned long) c->eip;
1a52e051 1533 JMP_REL(rel);
e4e03ded 1534 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1535 emulate_push(ctxt);
1536 break;
1a52e051
NK		 1537 }
1538 case 0xe9: /* jmp rel */
1539 case 0xeb: /* jmp rel short */
e4e03ded 1540 JMP_REL(c->src.val);
a01af5ec 1541 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051
NK		 1542 break;
1543
7f0aaee0 1544
6aa8b732
AK		 1545 }
1546 goto writeback;
1547
1548twobyte_insn:
e4e03ded 1549 switch (c->b) {
6aa8b732 1550 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1551 switch (c->modrm_reg) {
6aa8b732
AK		 1552 u16 size;
1553 unsigned long address;
1554
aca7f966 1555 case 0: /* vmcall */
e4e03ded 1556 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1557 goto cannot_emulate;
1558
7aa81cc0
AL		 1559 rc = kvm_fix_hypercall(ctxt->vcpu);
1560 if (rc)
1561 goto done;
1562
1563 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1564 break;
6aa8b732 1565 case 2: /* lgdt */
e4e03ded
LV		 1566 rc = read_descriptor(ctxt, ops, c->src.ptr,
1567 &size, &address, c->op_bytes);
6aa8b732
AK		 1568 if (rc)
1569 goto done;
1570 realmode_lgdt(ctxt->vcpu, size, address);
1571 break;
aca7f966 1572 case 3: /* lidt/vmmcall */
e4e03ded 1573 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1574 rc = kvm_fix_hypercall(ctxt->vcpu);
1575 if (rc)
1576 goto done;
1577 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1578 } else {
e4e03ded 1579 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1580 &size, &address,
e4e03ded 1581 c->op_bytes);
aca7f966
AL		 1582 if (rc)
1583 goto done;
1584 realmode_lidt(ctxt->vcpu, size, address);
1585 }
6aa8b732
AK		 1586 break;
1587 case 4: /* smsw */
e4e03ded 1588 if (c->modrm_mod != 3)
6aa8b732 1589 goto cannot_emulate;
e4e03ded 1590 *(u16 *)&c->regs[c->modrm_rm]
6aa8b732
AK		 1591 = realmode_get_cr(ctxt->vcpu, 0);
1592 break;
1593 case 6: /* lmsw */
e4e03ded 1594 if (c->modrm_mod != 3)
6aa8b732 1595 goto cannot_emulate;
05f086f8
LV		 1596 realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val,
1597 &ctxt->eflags);
6aa8b732
AK		 1598 break;
1599 case 7: /* invlpg*/
1600 emulate_invlpg(ctxt->vcpu, cr2);
1601 break;
1602 default:
1603 goto cannot_emulate;
1604 }
a01af5ec
LV		 1605 /* Disable writeback. */
1606 c->dst.type = OP_NONE;
6aa8b732
AK		 1607 break;
1608 case 0x21: /* mov from dr to reg */
e4e03ded 1609 if (c->modrm_mod != 3)
6aa8b732 1610 goto cannot_emulate;
8cdbd2c9 1611 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1612 if (rc)
1613 goto cannot_emulate;
1614 c->dst.type = OP_NONE; /* no writeback */
6aa8b732
AK		 1615 break;
1616 case 0x23: /* mov from reg to dr */
e4e03ded 1617 if (c->modrm_mod != 3)
6aa8b732 1618 goto cannot_emulate;
e4e03ded
LV		 1619 rc = emulator_set_dr(ctxt, c->modrm_reg,
1620 c->regs[c->modrm_rm]);
a01af5ec
LV		 1621 if (rc)
1622 goto cannot_emulate;
1623 c->dst.type = OP_NONE; /* no writeback */
6aa8b732
AK		 1624 break;
1625 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1626 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1627 if (!test_cc(c->b, ctxt->eflags))
1628 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1629 break;
7de75248
NK		 1630 case 0xa3:
1631 bt: /* bt */
e4f8e039 1632 c->dst.type = OP_NONE;
e4e03ded
LV		 1633 /* only subword offset */
1634 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1635 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1636 break;
1637 case 0xab:
1638 bts: /* bts */
e4e03ded
LV		 1639 /* only subword offset */
1640 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1641 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1642 break;
6aa8b732
AK		 1643 case 0xb0 ... 0xb1: /* cmpxchg */
1644 /*
1645 * Save real source value, then compare EAX against
1646 * destination.
1647 */
e4e03ded
LV		 1648 c->src.orig_val = c->src.val;
1649 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1650 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1651 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1652 /* Success: write back to memory. */
e4e03ded 1653 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1654 } else {
1655 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1656 c->dst.type = OP_REG;
1657 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1658 }
1659 break;
6aa8b732
AK		 1660 case 0xb3:
1661 btr: /* btr */
e4e03ded
LV		 1662 /* only subword offset */
1663 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1664 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1665 break;
6aa8b732 1666 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1667 c->dst.bytes = c->op_bytes;
1668 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1669 : (u16) c->src.val;
6aa8b732 1670 break;
6aa8b732 1671 case 0xba: /* Grp8 */
e4e03ded 1672 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1673 case 0:
1674 goto bt;
1675 case 1:
1676 goto bts;
1677 case 2:
1678 goto btr;
1679 case 3:
1680 goto btc;
1681 }
1682 break;
7de75248
NK		 1683 case 0xbb:
1684 btc: /* btc */
e4e03ded
LV		 1685 /* only subword offset */
1686 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1687 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 1688 break;
6aa8b732 1689 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 1690 c->dst.bytes = c->op_bytes;
1691 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1692 (s16) c->src.val;
6aa8b732 1693 break;
a012e65a 1694 case 0xc3: /* movnti */
e4e03ded
LV		 1695 c->dst.bytes = c->op_bytes;
1696 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1697 (u64) c->src.val;
a012e65a 1698 break;
6aa8b732
AK		 1699 }
1700 goto writeback;
1701
1702twobyte_special_insn:
e4e03ded 1703 switch (c->b) {
7de75248
NK		 1704 case 0x06:
1705 emulate_clts(ctxt->vcpu);
1706 break;
651a3e29
AK		 1707 case 0x08: /* invd */
1708 break;
687fdbfe
AK		 1709 case 0x09: /* wbinvd */
1710 break;
6aa8b732
AK		 1711 case 0x0d: /* GrpP (prefetch) */
1712 case 0x18: /* Grp16 (prefetch/nop) */
1713 break;
6aa8b732 1714 case 0x20: /* mov cr, reg */
e4e03ded 1715 if (c->modrm_mod != 3)
6aa8b732 1716 goto cannot_emulate;
e4e03ded
LV		 1717 c->regs[c->modrm_rm] =
1718 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
6aa8b732
AK		 1719 break;
1720 case 0x22: /* mov reg, cr */
e4e03ded 1721 if (c->modrm_mod != 3)
6aa8b732 1722 goto cannot_emulate;
e4e03ded 1723 realmode_set_cr(ctxt->vcpu,
05f086f8 1724 c->modrm_reg, c->modrm_val, &ctxt->eflags);
6aa8b732 1725 break;
35f3f286
AK		 1726 case 0x30:
1727 /* wrmsr */
e4e03ded
LV		 1728 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1729 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1730 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
35f3f286 1731 if (rc) {
cbdd1bea 1732 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
e4e03ded 1733 c->eip = ctxt->vcpu->rip;
35f3f286
AK		 1734 }
1735 rc = X86EMUL_CONTINUE;
1736 break;
1737 case 0x32:
1738 /* rdmsr */
8cdbd2c9 1739 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
35f3f286 1740 if (rc) {
cbdd1bea 1741 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
e4e03ded 1742 c->eip = ctxt->vcpu->rip;
35f3f286 1743 } else {
e4e03ded
LV		 1744 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1745 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
35f3f286
AK		 1746 }
1747 rc = X86EMUL_CONTINUE;
1748 break;
bbe9abbd
NK		 1749 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1750 long int rel;
1751
e4e03ded 1752 switch (c->op_bytes) {
bbe9abbd 1753 case 2:
e4e03ded 1754 rel = insn_fetch(s16, 2, c->eip);
bbe9abbd
NK		 1755 break;
1756 case 4:
e4e03ded 1757 rel = insn_fetch(s32, 4, c->eip);
bbe9abbd
NK		 1758 break;
1759 case 8:
e4e03ded 1760 rel = insn_fetch(s64, 8, c->eip);
bbe9abbd
NK		 1761 break;
1762 default:
1763 DPRINTF("jnz: Invalid op_bytes\n");
1764 goto cannot_emulate;
1765 }
05f086f8 1766 if (test_cc(c->b, ctxt->eflags))
bbe9abbd
NK		 1767 JMP_REL(rel);
1768 break;
1769 }
6aa8b732 1770 case 0xc7: /* Grp9 (cmpxchg8b) */
05f086f8 1771 rc = emulate_grp9(ctxt, ops, cr2);
8cdbd2c9
LV		 1772 if (rc != 0)
1773 goto done;
1774 break;
6aa8b732 1775 }
a01af5ec
LV		 1776 /* Disable writeback. */
1777 c->dst.type = OP_NONE;
6aa8b732
AK		 1778 goto writeback;
1779
1780cannot_emulate:
e4e03ded 1781 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 1782 c->eip = saved_eip;
6aa8b732
AK		 1783 return -1;
1784}
Linux kernel - Deliverables
This page took 0.225175 seconds and 5 git commands to generate.