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1 | /****************************************************************************** |
2 | * x86_emulate.c | |
3 | * | |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
12 | * | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
20 | */ | |
21 | ||
22 | #ifndef __KERNEL__ | |
23 | #include <stdio.h> | |
24 | #include <stdint.h> | |
25 | #include <public/xen.h> | |
d77c26fc | 26 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 AK |
27 | #else |
28 | #include "kvm.h" | |
34c16eec | 29 | #include "x86.h" |
6aa8b732 AK |
30 | #define DPRINTF(x...) do {} while (0) |
31 | #endif | |
32 | #include "x86_emulate.h" | |
33 | #include <linux/module.h> | |
34 | ||
35 | /* | |
36 | * Opcode effective-address decode tables. | |
37 | * Note that we only emulate instructions that have at least one memory | |
38 | * operand (excluding implicit stack references). We assume that stack | |
39 | * references and instruction fetches will never occur in special memory | |
40 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
41 | * not be handled. | |
42 | */ | |
43 | ||
44 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
45 | #define ByteOp (1<<0) /* 8-bit operands. */ | |
46 | /* Destination operand type. */ | |
47 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ | |
48 | #define DstReg (2<<1) /* Register operand. */ | |
49 | #define DstMem (3<<1) /* Memory operand. */ | |
50 | #define DstMask (3<<1) | |
51 | /* Source operand type. */ | |
52 | #define SrcNone (0<<3) /* No source operand. */ | |
53 | #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */ | |
54 | #define SrcReg (1<<3) /* Register operand. */ | |
55 | #define SrcMem (2<<3) /* Memory operand. */ | |
56 | #define SrcMem16 (3<<3) /* Memory operand (16-bit). */ | |
57 | #define SrcMem32 (4<<3) /* Memory operand (32-bit). */ | |
58 | #define SrcImm (5<<3) /* Immediate operand. */ | |
59 | #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */ | |
60 | #define SrcMask (7<<3) | |
61 | /* Generic ModRM decode. */ | |
62 | #define ModRM (1<<6) | |
63 | /* Destination is only written; never read. */ | |
64 | #define Mov (1<<7) | |
038e51de | 65 | #define BitOp (1<<8) |
c7e75a3d | 66 | #define MemAbs (1<<9) /* Memory operand is absolute displacement */ |
6aa8b732 | 67 | |
c7e75a3d | 68 | static u16 opcode_table[256] = { |
6aa8b732 AK |
69 | /* 0x00 - 0x07 */ |
70 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
71 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
72 | 0, 0, 0, 0, | |
73 | /* 0x08 - 0x0F */ | |
74 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
75 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
76 | 0, 0, 0, 0, | |
77 | /* 0x10 - 0x17 */ | |
78 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
79 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
80 | 0, 0, 0, 0, | |
81 | /* 0x18 - 0x1F */ | |
82 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
83 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
84 | 0, 0, 0, 0, | |
85 | /* 0x20 - 0x27 */ | |
86 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
87 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
19eb938e | 88 | SrcImmByte, SrcImm, 0, 0, |
6aa8b732 AK |
89 | /* 0x28 - 0x2F */ |
90 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
91 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
92 | 0, 0, 0, 0, | |
93 | /* 0x30 - 0x37 */ | |
94 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
95 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
96 | 0, 0, 0, 0, | |
97 | /* 0x38 - 0x3F */ | |
98 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
99 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
100 | 0, 0, 0, 0, | |
d77a2507 | 101 | /* 0x40 - 0x47 */ |
33615aa9 | 102 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
d77a2507 | 103 | /* 0x48 - 0x4F */ |
33615aa9 | 104 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
7f0aaee0 | 105 | /* 0x50 - 0x57 */ |
33615aa9 | 106 | SrcReg, SrcReg, SrcReg, SrcReg, SrcReg, SrcReg, SrcReg, SrcReg, |
7f0aaee0 | 107 | /* 0x58 - 0x5F */ |
33615aa9 | 108 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
7d316911 | 109 | /* 0x60 - 0x67 */ |
6aa8b732 | 110 | 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ , |
7d316911 NK |
111 | 0, 0, 0, 0, |
112 | /* 0x68 - 0x6F */ | |
113 | 0, 0, ImplicitOps|Mov, 0, | |
e70669ab LV |
114 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */ |
115 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */ | |
55bebde4 NK |
116 | /* 0x70 - 0x77 */ |
117 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
118 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
119 | /* 0x78 - 0x7F */ | |
120 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
121 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
6aa8b732 AK |
122 | /* 0x80 - 0x87 */ |
123 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
124 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, | |
125 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
126 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
127 | /* 0x88 - 0x8F */ | |
128 | ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov, | |
129 | ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
7e0b54b1 | 130 | 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov, |
6aa8b732 | 131 | /* 0x90 - 0x9F */ |
535eabcf | 132 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0, |
6aa8b732 | 133 | /* 0xA0 - 0xA7 */ |
c7e75a3d AK |
134 | ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs, |
135 | ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs, | |
6aa8b732 AK |
136 | ByteOp | ImplicitOps | Mov, ImplicitOps | Mov, |
137 | ByteOp | ImplicitOps, ImplicitOps, | |
138 | /* 0xA8 - 0xAF */ | |
139 | 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov, | |
140 | ByteOp | ImplicitOps | Mov, ImplicitOps | Mov, | |
141 | ByteOp | ImplicitOps, ImplicitOps, | |
142 | /* 0xB0 - 0xBF */ | |
143 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
144 | /* 0xC0 - 0xC7 */ | |
d9413cd7 NK |
145 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, |
146 | 0, ImplicitOps, 0, 0, | |
147 | ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov, | |
6aa8b732 AK |
148 | /* 0xC8 - 0xCF */ |
149 | 0, 0, 0, 0, 0, 0, 0, 0, | |
150 | /* 0xD0 - 0xD7 */ | |
151 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
152 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
153 | 0, 0, 0, 0, | |
154 | /* 0xD8 - 0xDF */ | |
155 | 0, 0, 0, 0, 0, 0, 0, 0, | |
098c937b NK |
156 | /* 0xE0 - 0xE7 */ |
157 | 0, 0, 0, 0, 0, 0, 0, 0, | |
158 | /* 0xE8 - 0xEF */ | |
f6eed391 | 159 | ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0, |
6aa8b732 AK |
160 | /* 0xF0 - 0xF7 */ |
161 | 0, 0, 0, 0, | |
b284be57 | 162 | ImplicitOps, ImplicitOps, |
72d6e5a0 | 163 | ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, |
6aa8b732 | 164 | /* 0xF8 - 0xFF */ |
b284be57 | 165 | ImplicitOps, 0, ImplicitOps, ImplicitOps, |
6aa8b732 AK |
166 | 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM |
167 | }; | |
168 | ||
038e51de | 169 | static u16 twobyte_table[256] = { |
6aa8b732 AK |
170 | /* 0x00 - 0x0F */ |
171 | 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0, | |
651a3e29 | 172 | ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0, |
6aa8b732 AK |
173 | /* 0x10 - 0x1F */ |
174 | 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, | |
175 | /* 0x20 - 0x2F */ | |
176 | ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0, | |
177 | 0, 0, 0, 0, 0, 0, 0, 0, | |
178 | /* 0x30 - 0x3F */ | |
35f3f286 | 179 | ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
6aa8b732 AK |
180 | /* 0x40 - 0x47 */ |
181 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
182 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
183 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
184 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
185 | /* 0x48 - 0x4F */ | |
186 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
187 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
188 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
189 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
190 | /* 0x50 - 0x5F */ | |
191 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
192 | /* 0x60 - 0x6F */ | |
193 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
194 | /* 0x70 - 0x7F */ | |
195 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
196 | /* 0x80 - 0x8F */ | |
bbe9abbd NK |
197 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
198 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
199 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
200 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
6aa8b732 AK |
201 | /* 0x90 - 0x9F */ |
202 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
203 | /* 0xA0 - 0xA7 */ | |
038e51de | 204 | 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0, |
6aa8b732 | 205 | /* 0xA8 - 0xAF */ |
038e51de | 206 | 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0, |
6aa8b732 AK |
207 | /* 0xB0 - 0xB7 */ |
208 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0, | |
038e51de | 209 | DstMem | SrcReg | ModRM | BitOp, |
6aa8b732 AK |
210 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
211 | DstReg | SrcMem16 | ModRM | Mov, | |
212 | /* 0xB8 - 0xBF */ | |
038e51de | 213 | 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp, |
6aa8b732 AK |
214 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
215 | DstReg | SrcMem16 | ModRM | Mov, | |
216 | /* 0xC0 - 0xCF */ | |
a012e65a SY |
217 | 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM, |
218 | 0, 0, 0, 0, 0, 0, 0, 0, | |
6aa8b732 AK |
219 | /* 0xD0 - 0xDF */ |
220 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
221 | /* 0xE0 - 0xEF */ | |
222 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
223 | /* 0xF0 - 0xFF */ | |
224 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 | |
225 | }; | |
226 | ||
6aa8b732 AK |
227 | /* EFLAGS bit definitions. */ |
228 | #define EFLG_OF (1<<11) | |
229 | #define EFLG_DF (1<<10) | |
230 | #define EFLG_SF (1<<7) | |
231 | #define EFLG_ZF (1<<6) | |
232 | #define EFLG_AF (1<<4) | |
233 | #define EFLG_PF (1<<2) | |
234 | #define EFLG_CF (1<<0) | |
235 | ||
236 | /* | |
237 | * Instruction emulation: | |
238 | * Most instructions are emulated directly via a fragment of inline assembly | |
239 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
240 | * any modified flags. | |
241 | */ | |
242 | ||
05b3e0c2 | 243 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
244 | #define _LO32 "k" /* force 32-bit operand */ |
245 | #define _STK "%%rsp" /* stack pointer */ | |
246 | #elif defined(__i386__) | |
247 | #define _LO32 "" /* force 32-bit operand */ | |
248 | #define _STK "%%esp" /* stack pointer */ | |
249 | #endif | |
250 | ||
251 | /* | |
252 | * These EFLAGS bits are restored from saved value during emulation, and | |
253 | * any changes are written back to the saved value after emulation. | |
254 | */ | |
255 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
256 | ||
257 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
258 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ | |
259 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \ | |
260 | "push %"_sav"; " \ | |
261 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
262 | "andl %"_LO32 _tmp",("_STK"); " \ | |
263 | "pushf; " \ | |
264 | "notl %"_LO32 _tmp"; " \ | |
265 | "andl %"_LO32 _tmp",("_STK"); " \ | |
266 | "pop %"_tmp"; " \ | |
267 | "orl %"_LO32 _tmp",("_STK"); " \ | |
268 | "popf; " \ | |
269 | /* _sav &= ~msk; */ \ | |
270 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
271 | "notl %"_LO32 _tmp"; " \ | |
272 | "andl %"_LO32 _tmp",%"_sav"; " | |
273 | ||
274 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
275 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
276 | /* _sav |= EFLAGS & _msk; */ \ | |
277 | "pushf; " \ | |
278 | "pop %"_tmp"; " \ | |
279 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
280 | "orl %"_LO32 _tmp",%"_sav"; " | |
281 | ||
282 | /* Raw emulation: instruction has two explicit operands. */ | |
283 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
284 | do { \ | |
285 | unsigned long _tmp; \ | |
286 | \ | |
287 | switch ((_dst).bytes) { \ | |
288 | case 2: \ | |
289 | __asm__ __volatile__ ( \ | |
d77c26fc | 290 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 291 | _op"w %"_wx"3,%1; " \ |
d77c26fc | 292 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 AK |
293 | : "=m" (_eflags), "=m" ((_dst).val), \ |
294 | "=&r" (_tmp) \ | |
d77c26fc | 295 | : _wy ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
296 | break; \ |
297 | case 4: \ | |
298 | __asm__ __volatile__ ( \ | |
d77c26fc | 299 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 300 | _op"l %"_lx"3,%1; " \ |
d77c26fc | 301 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 AK |
302 | : "=m" (_eflags), "=m" ((_dst).val), \ |
303 | "=&r" (_tmp) \ | |
d77c26fc | 304 | : _ly ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
305 | break; \ |
306 | case 8: \ | |
307 | __emulate_2op_8byte(_op, _src, _dst, \ | |
308 | _eflags, _qx, _qy); \ | |
309 | break; \ | |
310 | } \ | |
311 | } while (0) | |
312 | ||
313 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
314 | do { \ | |
315 | unsigned long _tmp; \ | |
d77c26fc | 316 | switch ((_dst).bytes) { \ |
6aa8b732 AK |
317 | case 1: \ |
318 | __asm__ __volatile__ ( \ | |
d77c26fc | 319 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 320 | _op"b %"_bx"3,%1; " \ |
d77c26fc | 321 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 AK |
322 | : "=m" (_eflags), "=m" ((_dst).val), \ |
323 | "=&r" (_tmp) \ | |
d77c26fc | 324 | : _by ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
325 | break; \ |
326 | default: \ | |
327 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
328 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
329 | break; \ | |
330 | } \ | |
331 | } while (0) | |
332 | ||
333 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
334 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
335 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
336 | "b", "c", "b", "c", "b", "c", "b", "c") | |
337 | ||
338 | /* Source operand is byte, word, long or quad sized. */ | |
339 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
340 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
341 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
342 | ||
343 | /* Source operand is word, long or quad sized. */ | |
344 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
345 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
346 | "w", "r", _LO32, "r", "", "r") | |
347 | ||
348 | /* Instruction has only one explicit operand (no source operand). */ | |
349 | #define emulate_1op(_op, _dst, _eflags) \ | |
350 | do { \ | |
351 | unsigned long _tmp; \ | |
352 | \ | |
d77c26fc | 353 | switch ((_dst).bytes) { \ |
6aa8b732 AK |
354 | case 1: \ |
355 | __asm__ __volatile__ ( \ | |
d77c26fc | 356 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 357 | _op"b %1; " \ |
d77c26fc | 358 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
359 | : "=m" (_eflags), "=m" ((_dst).val), \ |
360 | "=&r" (_tmp) \ | |
d77c26fc | 361 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
362 | break; \ |
363 | case 2: \ | |
364 | __asm__ __volatile__ ( \ | |
d77c26fc | 365 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 366 | _op"w %1; " \ |
d77c26fc | 367 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
368 | : "=m" (_eflags), "=m" ((_dst).val), \ |
369 | "=&r" (_tmp) \ | |
d77c26fc | 370 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
371 | break; \ |
372 | case 4: \ | |
373 | __asm__ __volatile__ ( \ | |
d77c26fc | 374 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 375 | _op"l %1; " \ |
d77c26fc | 376 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
377 | : "=m" (_eflags), "=m" ((_dst).val), \ |
378 | "=&r" (_tmp) \ | |
d77c26fc | 379 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
380 | break; \ |
381 | case 8: \ | |
382 | __emulate_1op_8byte(_op, _dst, _eflags); \ | |
383 | break; \ | |
384 | } \ | |
385 | } while (0) | |
386 | ||
387 | /* Emulate an instruction with quadword operands (x86/64 only). */ | |
05b3e0c2 | 388 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
389 | #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \ |
390 | do { \ | |
391 | __asm__ __volatile__ ( \ | |
d77c26fc | 392 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 393 | _op"q %"_qx"3,%1; " \ |
d77c26fc | 394 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 | 395 | : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \ |
d77c26fc | 396 | : _qy ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
397 | } while (0) |
398 | ||
399 | #define __emulate_1op_8byte(_op, _dst, _eflags) \ | |
400 | do { \ | |
401 | __asm__ __volatile__ ( \ | |
d77c26fc | 402 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 403 | _op"q %1; " \ |
d77c26fc | 404 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 | 405 | : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \ |
d77c26fc | 406 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
407 | } while (0) |
408 | ||
409 | #elif defined(__i386__) | |
410 | #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) | |
411 | #define __emulate_1op_8byte(_op, _dst, _eflags) | |
412 | #endif /* __i386__ */ | |
413 | ||
414 | /* Fetch next part of the instruction being emulated. */ | |
415 | #define insn_fetch(_type, _size, _eip) \ | |
416 | ({ unsigned long _x; \ | |
62266869 | 417 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
d77c26fc | 418 | if (rc != 0) \ |
6aa8b732 AK |
419 | goto done; \ |
420 | (_eip) += (_size); \ | |
421 | (_type)_x; \ | |
422 | }) | |
423 | ||
424 | /* Access/update address held in a register, based on addressing mode. */ | |
e70669ab | 425 | #define address_mask(reg) \ |
e4e03ded LV |
426 | ((c->ad_bytes == sizeof(unsigned long)) ? \ |
427 | (reg) : ((reg) & ((1UL << (c->ad_bytes << 3)) - 1))) | |
6aa8b732 | 428 | #define register_address(base, reg) \ |
e70669ab | 429 | ((base) + address_mask(reg)) |
6aa8b732 AK |
430 | #define register_address_increment(reg, inc) \ |
431 | do { \ | |
432 | /* signed type ensures sign extension to long */ \ | |
433 | int _inc = (inc); \ | |
e4e03ded | 434 | if (c->ad_bytes == sizeof(unsigned long)) \ |
6aa8b732 AK |
435 | (reg) += _inc; \ |
436 | else \ | |
e4e03ded LV |
437 | (reg) = ((reg) & \ |
438 | ~((1UL << (c->ad_bytes << 3)) - 1)) | \ | |
439 | (((reg) + _inc) & \ | |
440 | ((1UL << (c->ad_bytes << 3)) - 1)); \ | |
6aa8b732 AK |
441 | } while (0) |
442 | ||
098c937b NK |
443 | #define JMP_REL(rel) \ |
444 | do { \ | |
e4e03ded | 445 | register_address_increment(c->eip, rel); \ |
098c937b NK |
446 | } while (0) |
447 | ||
62266869 AK |
448 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
449 | struct x86_emulate_ops *ops, | |
450 | unsigned long linear, u8 *dest) | |
451 | { | |
452 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
453 | int rc; | |
454 | int size; | |
455 | ||
456 | if (linear < fc->start || linear >= fc->end) { | |
457 | size = min(15UL, PAGE_SIZE - offset_in_page(linear)); | |
458 | rc = ops->read_std(linear, fc->data, size, ctxt->vcpu); | |
459 | if (rc) | |
460 | return rc; | |
461 | fc->start = linear; | |
462 | fc->end = linear + size; | |
463 | } | |
464 | *dest = fc->data[linear - fc->start]; | |
465 | return 0; | |
466 | } | |
467 | ||
468 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
469 | struct x86_emulate_ops *ops, | |
470 | unsigned long eip, void *dest, unsigned size) | |
471 | { | |
472 | int rc = 0; | |
473 | ||
474 | eip += ctxt->cs_base; | |
475 | while (size--) { | |
476 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
477 | if (rc) | |
478 | return rc; | |
479 | } | |
480 | return 0; | |
481 | } | |
482 | ||
1e3c5cb0 RR |
483 | /* |
484 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
485 | * pointer into the block that addresses the relevant register. | |
486 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
487 | */ | |
488 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
489 | int highbyte_regs) | |
6aa8b732 AK |
490 | { |
491 | void *p; | |
492 | ||
493 | p = ®s[modrm_reg]; | |
494 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
495 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
496 | return p; | |
497 | } | |
498 | ||
499 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
500 | struct x86_emulate_ops *ops, | |
501 | void *ptr, | |
502 | u16 *size, unsigned long *address, int op_bytes) | |
503 | { | |
504 | int rc; | |
505 | ||
506 | if (op_bytes == 2) | |
507 | op_bytes = 3; | |
508 | *address = 0; | |
cebff02b LV |
509 | rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, |
510 | ctxt->vcpu); | |
6aa8b732 AK |
511 | if (rc) |
512 | return rc; | |
cebff02b LV |
513 | rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, |
514 | ctxt->vcpu); | |
6aa8b732 AK |
515 | return rc; |
516 | } | |
517 | ||
bbe9abbd NK |
518 | static int test_cc(unsigned int condition, unsigned int flags) |
519 | { | |
520 | int rc = 0; | |
521 | ||
522 | switch ((condition & 15) >> 1) { | |
523 | case 0: /* o */ | |
524 | rc |= (flags & EFLG_OF); | |
525 | break; | |
526 | case 1: /* b/c/nae */ | |
527 | rc |= (flags & EFLG_CF); | |
528 | break; | |
529 | case 2: /* z/e */ | |
530 | rc |= (flags & EFLG_ZF); | |
531 | break; | |
532 | case 3: /* be/na */ | |
533 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
534 | break; | |
535 | case 4: /* s */ | |
536 | rc |= (flags & EFLG_SF); | |
537 | break; | |
538 | case 5: /* p/pe */ | |
539 | rc |= (flags & EFLG_PF); | |
540 | break; | |
541 | case 7: /* le/ng */ | |
542 | rc |= (flags & EFLG_ZF); | |
543 | /* fall through */ | |
544 | case 6: /* l/nge */ | |
545 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
546 | break; | |
547 | } | |
548 | ||
549 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
550 | return (!!rc ^ (condition & 1)); | |
551 | } | |
552 | ||
3c118e24 AK |
553 | static void decode_register_operand(struct operand *op, |
554 | struct decode_cache *c, | |
3c118e24 AK |
555 | int inhibit_bytereg) |
556 | { | |
33615aa9 | 557 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 558 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
559 | |
560 | if (!(c->d & ModRM)) | |
561 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
562 | op->type = OP_REG; |
563 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
33615aa9 | 564 | op->ptr = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
565 | op->val = *(u8 *)op->ptr; |
566 | op->bytes = 1; | |
567 | } else { | |
33615aa9 | 568 | op->ptr = decode_register(reg, c->regs, 0); |
3c118e24 AK |
569 | op->bytes = c->op_bytes; |
570 | switch (op->bytes) { | |
571 | case 2: | |
572 | op->val = *(u16 *)op->ptr; | |
573 | break; | |
574 | case 4: | |
575 | op->val = *(u32 *)op->ptr; | |
576 | break; | |
577 | case 8: | |
578 | op->val = *(u64 *) op->ptr; | |
579 | break; | |
580 | } | |
581 | } | |
582 | op->orig_val = op->val; | |
583 | } | |
584 | ||
1c73ef66 AK |
585 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
586 | struct x86_emulate_ops *ops) | |
587 | { | |
588 | struct decode_cache *c = &ctxt->decode; | |
589 | u8 sib; | |
590 | int index_reg = 0, base_reg = 0, scale, rip_relative = 0; | |
591 | int rc = 0; | |
592 | ||
593 | if (c->rex_prefix) { | |
594 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
595 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
596 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
597 | } | |
598 | ||
599 | c->modrm = insn_fetch(u8, 1, c->eip); | |
600 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
601 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
602 | c->modrm_rm |= (c->modrm & 0x07); | |
603 | c->modrm_ea = 0; | |
604 | c->use_modrm_ea = 1; | |
605 | ||
606 | if (c->modrm_mod == 3) { | |
607 | c->modrm_val = *(unsigned long *) | |
608 | decode_register(c->modrm_rm, c->regs, c->d & ByteOp); | |
609 | return rc; | |
610 | } | |
611 | ||
612 | if (c->ad_bytes == 2) { | |
613 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
614 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
615 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
616 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
617 | ||
618 | /* 16-bit ModR/M decode. */ | |
619 | switch (c->modrm_mod) { | |
620 | case 0: | |
621 | if (c->modrm_rm == 6) | |
622 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
623 | break; | |
624 | case 1: | |
625 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
626 | break; | |
627 | case 2: | |
628 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
629 | break; | |
630 | } | |
631 | switch (c->modrm_rm) { | |
632 | case 0: | |
633 | c->modrm_ea += bx + si; | |
634 | break; | |
635 | case 1: | |
636 | c->modrm_ea += bx + di; | |
637 | break; | |
638 | case 2: | |
639 | c->modrm_ea += bp + si; | |
640 | break; | |
641 | case 3: | |
642 | c->modrm_ea += bp + di; | |
643 | break; | |
644 | case 4: | |
645 | c->modrm_ea += si; | |
646 | break; | |
647 | case 5: | |
648 | c->modrm_ea += di; | |
649 | break; | |
650 | case 6: | |
651 | if (c->modrm_mod != 0) | |
652 | c->modrm_ea += bp; | |
653 | break; | |
654 | case 7: | |
655 | c->modrm_ea += bx; | |
656 | break; | |
657 | } | |
658 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
659 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
660 | if (!c->override_base) | |
661 | c->override_base = &ctxt->ss_base; | |
662 | c->modrm_ea = (u16)c->modrm_ea; | |
663 | } else { | |
664 | /* 32/64-bit ModR/M decode. */ | |
665 | switch (c->modrm_rm) { | |
666 | case 4: | |
667 | case 12: | |
668 | sib = insn_fetch(u8, 1, c->eip); | |
669 | index_reg |= (sib >> 3) & 7; | |
670 | base_reg |= sib & 7; | |
671 | scale = sib >> 6; | |
672 | ||
673 | switch (base_reg) { | |
674 | case 5: | |
675 | if (c->modrm_mod != 0) | |
676 | c->modrm_ea += c->regs[base_reg]; | |
677 | else | |
678 | c->modrm_ea += | |
679 | insn_fetch(s32, 4, c->eip); | |
680 | break; | |
681 | default: | |
682 | c->modrm_ea += c->regs[base_reg]; | |
683 | } | |
684 | switch (index_reg) { | |
685 | case 4: | |
686 | break; | |
687 | default: | |
688 | c->modrm_ea += c->regs[index_reg] << scale; | |
689 | } | |
690 | break; | |
691 | case 5: | |
692 | if (c->modrm_mod != 0) | |
693 | c->modrm_ea += c->regs[c->modrm_rm]; | |
694 | else if (ctxt->mode == X86EMUL_MODE_PROT64) | |
695 | rip_relative = 1; | |
696 | break; | |
697 | default: | |
698 | c->modrm_ea += c->regs[c->modrm_rm]; | |
699 | break; | |
700 | } | |
701 | switch (c->modrm_mod) { | |
702 | case 0: | |
703 | if (c->modrm_rm == 5) | |
704 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
705 | break; | |
706 | case 1: | |
707 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
708 | break; | |
709 | case 2: | |
710 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
711 | break; | |
712 | } | |
713 | } | |
714 | if (rip_relative) { | |
715 | c->modrm_ea += c->eip; | |
716 | switch (c->d & SrcMask) { | |
717 | case SrcImmByte: | |
718 | c->modrm_ea += 1; | |
719 | break; | |
720 | case SrcImm: | |
721 | if (c->d & ByteOp) | |
722 | c->modrm_ea += 1; | |
723 | else | |
724 | if (c->op_bytes == 8) | |
725 | c->modrm_ea += 4; | |
726 | else | |
727 | c->modrm_ea += c->op_bytes; | |
728 | } | |
729 | } | |
730 | done: | |
731 | return rc; | |
732 | } | |
733 | ||
734 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
735 | struct x86_emulate_ops *ops) | |
736 | { | |
737 | struct decode_cache *c = &ctxt->decode; | |
738 | int rc = 0; | |
739 | ||
740 | switch (c->ad_bytes) { | |
741 | case 2: | |
742 | c->modrm_ea = insn_fetch(u16, 2, c->eip); | |
743 | break; | |
744 | case 4: | |
745 | c->modrm_ea = insn_fetch(u32, 4, c->eip); | |
746 | break; | |
747 | case 8: | |
748 | c->modrm_ea = insn_fetch(u64, 8, c->eip); | |
749 | break; | |
750 | } | |
751 | done: | |
752 | return rc; | |
753 | } | |
754 | ||
6aa8b732 | 755 | int |
8b4caf66 | 756 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
6aa8b732 | 757 | { |
e4e03ded | 758 | struct decode_cache *c = &ctxt->decode; |
6aa8b732 | 759 | int rc = 0; |
6aa8b732 | 760 | int mode = ctxt->mode; |
f21b8bf4 | 761 | int def_op_bytes, def_ad_bytes; |
6aa8b732 AK |
762 | |
763 | /* Shadow copy of register state. Committed on successful emulation. */ | |
6aa8b732 | 764 | |
e4e03ded LV |
765 | memset(c, 0, sizeof(struct decode_cache)); |
766 | c->eip = ctxt->vcpu->rip; | |
767 | memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs); | |
6aa8b732 AK |
768 | |
769 | switch (mode) { | |
770 | case X86EMUL_MODE_REAL: | |
771 | case X86EMUL_MODE_PROT16: | |
f21b8bf4 | 772 | def_op_bytes = def_ad_bytes = 2; |
6aa8b732 AK |
773 | break; |
774 | case X86EMUL_MODE_PROT32: | |
f21b8bf4 | 775 | def_op_bytes = def_ad_bytes = 4; |
6aa8b732 | 776 | break; |
05b3e0c2 | 777 | #ifdef CONFIG_X86_64 |
6aa8b732 | 778 | case X86EMUL_MODE_PROT64: |
f21b8bf4 AK |
779 | def_op_bytes = 4; |
780 | def_ad_bytes = 8; | |
6aa8b732 AK |
781 | break; |
782 | #endif | |
783 | default: | |
784 | return -1; | |
785 | } | |
786 | ||
f21b8bf4 AK |
787 | c->op_bytes = def_op_bytes; |
788 | c->ad_bytes = def_ad_bytes; | |
789 | ||
6aa8b732 | 790 | /* Legacy prefixes. */ |
b4c6abfe | 791 | for (;;) { |
e4e03ded | 792 | switch (c->b = insn_fetch(u8, 1, c->eip)) { |
6aa8b732 | 793 | case 0x66: /* operand-size override */ |
f21b8bf4 AK |
794 | /* switch between 2/4 bytes */ |
795 | c->op_bytes = def_op_bytes ^ 6; | |
6aa8b732 AK |
796 | break; |
797 | case 0x67: /* address-size override */ | |
798 | if (mode == X86EMUL_MODE_PROT64) | |
e4e03ded | 799 | /* switch between 4/8 bytes */ |
f21b8bf4 | 800 | c->ad_bytes = def_ad_bytes ^ 12; |
6aa8b732 | 801 | else |
e4e03ded | 802 | /* switch between 2/4 bytes */ |
f21b8bf4 | 803 | c->ad_bytes = def_ad_bytes ^ 6; |
6aa8b732 AK |
804 | break; |
805 | case 0x2e: /* CS override */ | |
e4e03ded | 806 | c->override_base = &ctxt->cs_base; |
6aa8b732 AK |
807 | break; |
808 | case 0x3e: /* DS override */ | |
e4e03ded | 809 | c->override_base = &ctxt->ds_base; |
6aa8b732 AK |
810 | break; |
811 | case 0x26: /* ES override */ | |
e4e03ded | 812 | c->override_base = &ctxt->es_base; |
6aa8b732 AK |
813 | break; |
814 | case 0x64: /* FS override */ | |
e4e03ded | 815 | c->override_base = &ctxt->fs_base; |
6aa8b732 AK |
816 | break; |
817 | case 0x65: /* GS override */ | |
e4e03ded | 818 | c->override_base = &ctxt->gs_base; |
6aa8b732 AK |
819 | break; |
820 | case 0x36: /* SS override */ | |
e4e03ded | 821 | c->override_base = &ctxt->ss_base; |
6aa8b732 | 822 | break; |
b4c6abfe LV |
823 | case 0x40 ... 0x4f: /* REX */ |
824 | if (mode != X86EMUL_MODE_PROT64) | |
825 | goto done_prefixes; | |
33615aa9 | 826 | c->rex_prefix = c->b; |
b4c6abfe | 827 | continue; |
6aa8b732 | 828 | case 0xf0: /* LOCK */ |
e4e03ded | 829 | c->lock_prefix = 1; |
6aa8b732 | 830 | break; |
ae6200ba | 831 | case 0xf2: /* REPNE/REPNZ */ |
90e0a28f GT |
832 | c->rep_prefix = REPNE_PREFIX; |
833 | break; | |
6aa8b732 | 834 | case 0xf3: /* REP/REPE/REPZ */ |
90e0a28f | 835 | c->rep_prefix = REPE_PREFIX; |
6aa8b732 | 836 | break; |
6aa8b732 AK |
837 | default: |
838 | goto done_prefixes; | |
839 | } | |
b4c6abfe LV |
840 | |
841 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
842 | ||
33615aa9 | 843 | c->rex_prefix = 0; |
6aa8b732 AK |
844 | } |
845 | ||
846 | done_prefixes: | |
847 | ||
848 | /* REX prefix. */ | |
1c73ef66 | 849 | if (c->rex_prefix) |
33615aa9 | 850 | if (c->rex_prefix & 8) |
e4e03ded | 851 | c->op_bytes = 8; /* REX.W */ |
6aa8b732 AK |
852 | |
853 | /* Opcode byte(s). */ | |
e4e03ded LV |
854 | c->d = opcode_table[c->b]; |
855 | if (c->d == 0) { | |
6aa8b732 | 856 | /* Two-byte opcode? */ |
e4e03ded LV |
857 | if (c->b == 0x0f) { |
858 | c->twobyte = 1; | |
859 | c->b = insn_fetch(u8, 1, c->eip); | |
860 | c->d = twobyte_table[c->b]; | |
6aa8b732 AK |
861 | } |
862 | ||
863 | /* Unrecognised? */ | |
8b4caf66 LV |
864 | if (c->d == 0) { |
865 | DPRINTF("Cannot emulate %02x\n", c->b); | |
866 | return -1; | |
867 | } | |
6aa8b732 AK |
868 | } |
869 | ||
870 | /* ModRM and SIB bytes. */ | |
1c73ef66 AK |
871 | if (c->d & ModRM) |
872 | rc = decode_modrm(ctxt, ops); | |
873 | else if (c->d & MemAbs) | |
874 | rc = decode_abs(ctxt, ops); | |
875 | if (rc) | |
876 | goto done; | |
6aa8b732 | 877 | |
c7e75a3d AK |
878 | if (!c->override_base) |
879 | c->override_base = &ctxt->ds_base; | |
880 | if (mode == X86EMUL_MODE_PROT64 && | |
881 | c->override_base != &ctxt->fs_base && | |
882 | c->override_base != &ctxt->gs_base) | |
883 | c->override_base = NULL; | |
884 | ||
885 | if (c->override_base) | |
886 | c->modrm_ea += *c->override_base; | |
887 | ||
888 | if (c->ad_bytes != 8) | |
889 | c->modrm_ea = (u32)c->modrm_ea; | |
6aa8b732 AK |
890 | /* |
891 | * Decode and fetch the source operand: register, memory | |
892 | * or immediate. | |
893 | */ | |
e4e03ded | 894 | switch (c->d & SrcMask) { |
6aa8b732 AK |
895 | case SrcNone: |
896 | break; | |
897 | case SrcReg: | |
9f1ef3f8 | 898 | decode_register_operand(&c->src, c, 0); |
6aa8b732 AK |
899 | break; |
900 | case SrcMem16: | |
e4e03ded | 901 | c->src.bytes = 2; |
6aa8b732 AK |
902 | goto srcmem_common; |
903 | case SrcMem32: | |
e4e03ded | 904 | c->src.bytes = 4; |
6aa8b732 AK |
905 | goto srcmem_common; |
906 | case SrcMem: | |
e4e03ded LV |
907 | c->src.bytes = (c->d & ByteOp) ? 1 : |
908 | c->op_bytes; | |
b85b9ee9 | 909 | /* Don't fetch the address for invlpg: it could be unmapped. */ |
d77c26fc | 910 | if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7) |
b85b9ee9 | 911 | break; |
d77c26fc | 912 | srcmem_common: |
4e62417b AJ |
913 | /* |
914 | * For instructions with a ModR/M byte, switch to register | |
915 | * access if Mod = 3. | |
916 | */ | |
e4e03ded LV |
917 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
918 | c->src.type = OP_REG; | |
4e62417b AJ |
919 | break; |
920 | } | |
e4e03ded | 921 | c->src.type = OP_MEM; |
6aa8b732 AK |
922 | break; |
923 | case SrcImm: | |
e4e03ded LV |
924 | c->src.type = OP_IMM; |
925 | c->src.ptr = (unsigned long *)c->eip; | |
926 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
927 | if (c->src.bytes == 8) | |
928 | c->src.bytes = 4; | |
6aa8b732 | 929 | /* NB. Immediates are sign-extended as necessary. */ |
e4e03ded | 930 | switch (c->src.bytes) { |
6aa8b732 | 931 | case 1: |
e4e03ded | 932 | c->src.val = insn_fetch(s8, 1, c->eip); |
6aa8b732 AK |
933 | break; |
934 | case 2: | |
e4e03ded | 935 | c->src.val = insn_fetch(s16, 2, c->eip); |
6aa8b732 AK |
936 | break; |
937 | case 4: | |
e4e03ded | 938 | c->src.val = insn_fetch(s32, 4, c->eip); |
6aa8b732 AK |
939 | break; |
940 | } | |
941 | break; | |
942 | case SrcImmByte: | |
e4e03ded LV |
943 | c->src.type = OP_IMM; |
944 | c->src.ptr = (unsigned long *)c->eip; | |
945 | c->src.bytes = 1; | |
946 | c->src.val = insn_fetch(s8, 1, c->eip); | |
6aa8b732 AK |
947 | break; |
948 | } | |
949 | ||
038e51de | 950 | /* Decode and fetch the destination operand: register or memory. */ |
e4e03ded | 951 | switch (c->d & DstMask) { |
038e51de AK |
952 | case ImplicitOps: |
953 | /* Special instructions do their own operand decoding. */ | |
8b4caf66 | 954 | return 0; |
038e51de | 955 | case DstReg: |
9f1ef3f8 | 956 | decode_register_operand(&c->dst, c, |
3c118e24 | 957 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); |
038e51de AK |
958 | break; |
959 | case DstMem: | |
e4e03ded LV |
960 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
961 | c->dst.type = OP_REG; | |
4e62417b AJ |
962 | break; |
963 | } | |
8b4caf66 LV |
964 | c->dst.type = OP_MEM; |
965 | break; | |
966 | } | |
967 | ||
968 | done: | |
969 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
970 | } | |
971 | ||
8cdbd2c9 LV |
972 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt) |
973 | { | |
974 | struct decode_cache *c = &ctxt->decode; | |
975 | ||
976 | c->dst.type = OP_MEM; | |
977 | c->dst.bytes = c->op_bytes; | |
978 | c->dst.val = c->src.val; | |
979 | register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes); | |
980 | c->dst.ptr = (void *) register_address(ctxt->ss_base, | |
981 | c->regs[VCPU_REGS_RSP]); | |
982 | } | |
983 | ||
984 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, | |
985 | struct x86_emulate_ops *ops) | |
986 | { | |
987 | struct decode_cache *c = &ctxt->decode; | |
988 | int rc; | |
989 | ||
990 | /* 64-bit mode: POP always pops a 64-bit operand. */ | |
991 | ||
992 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
993 | c->dst.bytes = 8; | |
994 | ||
995 | rc = ops->read_std(register_address(ctxt->ss_base, | |
996 | c->regs[VCPU_REGS_RSP]), | |
997 | &c->dst.val, c->dst.bytes, ctxt->vcpu); | |
998 | if (rc != 0) | |
999 | return rc; | |
1000 | ||
1001 | register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes); | |
1002 | ||
1003 | return 0; | |
1004 | } | |
1005 | ||
05f086f8 | 1006 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1007 | { |
05f086f8 | 1008 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1009 | switch (c->modrm_reg) { |
1010 | case 0: /* rol */ | |
05f086f8 | 1011 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1012 | break; |
1013 | case 1: /* ror */ | |
05f086f8 | 1014 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1015 | break; |
1016 | case 2: /* rcl */ | |
05f086f8 | 1017 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1018 | break; |
1019 | case 3: /* rcr */ | |
05f086f8 | 1020 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1021 | break; |
1022 | case 4: /* sal/shl */ | |
1023 | case 6: /* sal/shl */ | |
05f086f8 | 1024 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1025 | break; |
1026 | case 5: /* shr */ | |
05f086f8 | 1027 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1028 | break; |
1029 | case 7: /* sar */ | |
05f086f8 | 1030 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1031 | break; |
1032 | } | |
1033 | } | |
1034 | ||
1035 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1036 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1037 | { |
1038 | struct decode_cache *c = &ctxt->decode; | |
1039 | int rc = 0; | |
1040 | ||
1041 | switch (c->modrm_reg) { | |
1042 | case 0 ... 1: /* test */ | |
1043 | /* | |
1044 | * Special case in Grp3: test has an immediate | |
1045 | * source operand. | |
1046 | */ | |
1047 | c->src.type = OP_IMM; | |
1048 | c->src.ptr = (unsigned long *)c->eip; | |
1049 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1050 | if (c->src.bytes == 8) | |
1051 | c->src.bytes = 4; | |
1052 | switch (c->src.bytes) { | |
1053 | case 1: | |
1054 | c->src.val = insn_fetch(s8, 1, c->eip); | |
1055 | break; | |
1056 | case 2: | |
1057 | c->src.val = insn_fetch(s16, 2, c->eip); | |
1058 | break; | |
1059 | case 4: | |
1060 | c->src.val = insn_fetch(s32, 4, c->eip); | |
1061 | break; | |
1062 | } | |
05f086f8 | 1063 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1064 | break; |
1065 | case 2: /* not */ | |
1066 | c->dst.val = ~c->dst.val; | |
1067 | break; | |
1068 | case 3: /* neg */ | |
05f086f8 | 1069 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1070 | break; |
1071 | default: | |
1072 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1073 | rc = X86EMUL_UNHANDLEABLE; | |
1074 | break; | |
1075 | } | |
1076 | done: | |
1077 | return rc; | |
1078 | } | |
1079 | ||
1080 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1081 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1082 | { |
1083 | struct decode_cache *c = &ctxt->decode; | |
1084 | int rc; | |
1085 | ||
1086 | switch (c->modrm_reg) { | |
1087 | case 0: /* inc */ | |
05f086f8 | 1088 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1089 | break; |
1090 | case 1: /* dec */ | |
05f086f8 | 1091 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1092 | break; |
1093 | case 4: /* jmp abs */ | |
1094 | if (c->b == 0xff) | |
1095 | c->eip = c->dst.val; | |
1096 | else { | |
1097 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1098 | return X86EMUL_UNHANDLEABLE; | |
1099 | } | |
1100 | break; | |
1101 | case 6: /* push */ | |
1102 | ||
1103 | /* 64-bit mode: PUSH always pushes a 64-bit operand. */ | |
1104 | ||
1105 | if (ctxt->mode == X86EMUL_MODE_PROT64) { | |
1106 | c->dst.bytes = 8; | |
1107 | rc = ops->read_std((unsigned long)c->dst.ptr, | |
1108 | &c->dst.val, 8, ctxt->vcpu); | |
1109 | if (rc != 0) | |
1110 | return rc; | |
1111 | } | |
1112 | register_address_increment(c->regs[VCPU_REGS_RSP], | |
1113 | -c->dst.bytes); | |
1114 | rc = ops->write_emulated(register_address(ctxt->ss_base, | |
1115 | c->regs[VCPU_REGS_RSP]), &c->dst.val, | |
1116 | c->dst.bytes, ctxt->vcpu); | |
1117 | if (rc != 0) | |
1118 | return rc; | |
a01af5ec | 1119 | c->dst.type = OP_NONE; |
8cdbd2c9 LV |
1120 | break; |
1121 | default: | |
1122 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1123 | return X86EMUL_UNHANDLEABLE; | |
1124 | } | |
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
1129 | struct x86_emulate_ops *ops, | |
e8d8d7fe | 1130 | unsigned long memop) |
8cdbd2c9 LV |
1131 | { |
1132 | struct decode_cache *c = &ctxt->decode; | |
1133 | u64 old, new; | |
1134 | int rc; | |
1135 | ||
e8d8d7fe | 1136 | rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu); |
8cdbd2c9 LV |
1137 | if (rc != 0) |
1138 | return rc; | |
1139 | ||
1140 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1141 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
1142 | ||
1143 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); | |
1144 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1145 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 LV |
1146 | |
1147 | } else { | |
1148 | new = ((u64)c->regs[VCPU_REGS_RCX] << 32) | | |
1149 | (u32) c->regs[VCPU_REGS_RBX]; | |
1150 | ||
e8d8d7fe | 1151 | rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu); |
8cdbd2c9 LV |
1152 | if (rc != 0) |
1153 | return rc; | |
05f086f8 | 1154 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 LV |
1155 | } |
1156 | return 0; | |
1157 | } | |
1158 | ||
1159 | static inline int writeback(struct x86_emulate_ctxt *ctxt, | |
1160 | struct x86_emulate_ops *ops) | |
1161 | { | |
1162 | int rc; | |
1163 | struct decode_cache *c = &ctxt->decode; | |
1164 | ||
1165 | switch (c->dst.type) { | |
1166 | case OP_REG: | |
1167 | /* The 4-byte case *is* correct: | |
1168 | * in 64-bit mode we zero-extend. | |
1169 | */ | |
1170 | switch (c->dst.bytes) { | |
1171 | case 1: | |
1172 | *(u8 *)c->dst.ptr = (u8)c->dst.val; | |
1173 | break; | |
1174 | case 2: | |
1175 | *(u16 *)c->dst.ptr = (u16)c->dst.val; | |
1176 | break; | |
1177 | case 4: | |
1178 | *c->dst.ptr = (u32)c->dst.val; | |
1179 | break; /* 64b: zero-ext */ | |
1180 | case 8: | |
1181 | *c->dst.ptr = c->dst.val; | |
1182 | break; | |
1183 | } | |
1184 | break; | |
1185 | case OP_MEM: | |
1186 | if (c->lock_prefix) | |
1187 | rc = ops->cmpxchg_emulated( | |
1188 | (unsigned long)c->dst.ptr, | |
1189 | &c->dst.orig_val, | |
1190 | &c->dst.val, | |
1191 | c->dst.bytes, | |
1192 | ctxt->vcpu); | |
1193 | else | |
1194 | rc = ops->write_emulated( | |
1195 | (unsigned long)c->dst.ptr, | |
1196 | &c->dst.val, | |
1197 | c->dst.bytes, | |
1198 | ctxt->vcpu); | |
1199 | if (rc != 0) | |
1200 | return rc; | |
a01af5ec LV |
1201 | break; |
1202 | case OP_NONE: | |
1203 | /* no writeback */ | |
1204 | break; | |
8cdbd2c9 LV |
1205 | default: |
1206 | break; | |
1207 | } | |
1208 | return 0; | |
1209 | } | |
1210 | ||
8b4caf66 | 1211 | int |
1be3aa47 | 1212 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8b4caf66 | 1213 | { |
e8d8d7fe | 1214 | unsigned long memop = 0; |
8b4caf66 | 1215 | u64 msr_data; |
3427318f | 1216 | unsigned long saved_eip = 0; |
8b4caf66 | 1217 | struct decode_cache *c = &ctxt->decode; |
1be3aa47 | 1218 | int rc = 0; |
8b4caf66 | 1219 | |
3427318f LV |
1220 | /* Shadow copy of register state. Committed on successful emulation. |
1221 | * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't | |
1222 | * modify them. | |
1223 | */ | |
1224 | ||
1225 | memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs); | |
1226 | saved_eip = c->eip; | |
1227 | ||
c7e75a3d | 1228 | if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs)) |
e8d8d7fe | 1229 | memop = c->modrm_ea; |
8b4caf66 LV |
1230 | |
1231 | if (c->src.type == OP_MEM) { | |
e8d8d7fe | 1232 | c->src.ptr = (unsigned long *)memop; |
8b4caf66 | 1233 | c->src.val = 0; |
d77c26fc MD |
1234 | rc = ops->read_emulated((unsigned long)c->src.ptr, |
1235 | &c->src.val, | |
1236 | c->src.bytes, | |
1237 | ctxt->vcpu); | |
1238 | if (rc != 0) | |
8b4caf66 LV |
1239 | goto done; |
1240 | c->src.orig_val = c->src.val; | |
1241 | } | |
1242 | ||
1243 | if ((c->d & DstMask) == ImplicitOps) | |
1244 | goto special_insn; | |
1245 | ||
1246 | ||
1247 | if (c->dst.type == OP_MEM) { | |
e8d8d7fe | 1248 | c->dst.ptr = (unsigned long *)memop; |
8b4caf66 LV |
1249 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
1250 | c->dst.val = 0; | |
e4e03ded LV |
1251 | if (c->d & BitOp) { |
1252 | unsigned long mask = ~(c->dst.bytes * 8 - 1); | |
df513e2c | 1253 | |
e4e03ded LV |
1254 | c->dst.ptr = (void *)c->dst.ptr + |
1255 | (c->src.val & mask) / 8; | |
038e51de | 1256 | } |
e4e03ded LV |
1257 | if (!(c->d & Mov) && |
1258 | /* optimisation - avoid slow emulated read */ | |
1259 | ((rc = ops->read_emulated((unsigned long)c->dst.ptr, | |
1260 | &c->dst.val, | |
1261 | c->dst.bytes, ctxt->vcpu)) != 0)) | |
038e51de | 1262 | goto done; |
038e51de | 1263 | } |
e4e03ded | 1264 | c->dst.orig_val = c->dst.val; |
038e51de | 1265 | |
e4e03ded | 1266 | if (c->twobyte) |
6aa8b732 AK |
1267 | goto twobyte_insn; |
1268 | ||
e4e03ded | 1269 | switch (c->b) { |
6aa8b732 AK |
1270 | case 0x00 ... 0x05: |
1271 | add: /* add */ | |
05f086f8 | 1272 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1273 | break; |
1274 | case 0x08 ... 0x0d: | |
1275 | or: /* or */ | |
05f086f8 | 1276 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1277 | break; |
1278 | case 0x10 ... 0x15: | |
1279 | adc: /* adc */ | |
05f086f8 | 1280 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1281 | break; |
1282 | case 0x18 ... 0x1d: | |
1283 | sbb: /* sbb */ | |
05f086f8 | 1284 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1285 | break; |
19eb938e | 1286 | case 0x20 ... 0x23: |
6aa8b732 | 1287 | and: /* and */ |
05f086f8 | 1288 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1289 | break; |
19eb938e | 1290 | case 0x24: /* and al imm8 */ |
e4e03ded LV |
1291 | c->dst.type = OP_REG; |
1292 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; | |
1293 | c->dst.val = *(u8 *)c->dst.ptr; | |
1294 | c->dst.bytes = 1; | |
1295 | c->dst.orig_val = c->dst.val; | |
19eb938e NK |
1296 | goto and; |
1297 | case 0x25: /* and ax imm16, or eax imm32 */ | |
e4e03ded LV |
1298 | c->dst.type = OP_REG; |
1299 | c->dst.bytes = c->op_bytes; | |
1300 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; | |
1301 | if (c->op_bytes == 2) | |
1302 | c->dst.val = *(u16 *)c->dst.ptr; | |
19eb938e | 1303 | else |
e4e03ded LV |
1304 | c->dst.val = *(u32 *)c->dst.ptr; |
1305 | c->dst.orig_val = c->dst.val; | |
19eb938e | 1306 | goto and; |
6aa8b732 AK |
1307 | case 0x28 ... 0x2d: |
1308 | sub: /* sub */ | |
05f086f8 | 1309 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1310 | break; |
1311 | case 0x30 ... 0x35: | |
1312 | xor: /* xor */ | |
05f086f8 | 1313 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1314 | break; |
1315 | case 0x38 ... 0x3d: | |
1316 | cmp: /* cmp */ | |
05f086f8 | 1317 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1318 | break; |
33615aa9 AK |
1319 | case 0x40 ... 0x47: /* inc r16/r32 */ |
1320 | emulate_1op("inc", c->dst, ctxt->eflags); | |
1321 | break; | |
1322 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
1323 | emulate_1op("dec", c->dst, ctxt->eflags); | |
1324 | break; | |
1325 | case 0x50 ... 0x57: /* push reg */ | |
1326 | c->dst.type = OP_MEM; | |
1327 | c->dst.bytes = c->op_bytes; | |
1328 | c->dst.val = c->src.val; | |
1329 | register_address_increment(c->regs[VCPU_REGS_RSP], | |
1330 | -c->op_bytes); | |
1331 | c->dst.ptr = (void *) register_address( | |
1332 | ctxt->ss_base, c->regs[VCPU_REGS_RSP]); | |
1333 | break; | |
1334 | case 0x58 ... 0x5f: /* pop reg */ | |
1335 | pop_instruction: | |
1336 | if ((rc = ops->read_std(register_address(ctxt->ss_base, | |
1337 | c->regs[VCPU_REGS_RSP]), c->dst.ptr, | |
1338 | c->op_bytes, ctxt->vcpu)) != 0) | |
1339 | goto done; | |
1340 | ||
1341 | register_address_increment(c->regs[VCPU_REGS_RSP], | |
1342 | c->op_bytes); | |
1343 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1344 | break; | |
6aa8b732 | 1345 | case 0x63: /* movsxd */ |
8b4caf66 | 1346 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 1347 | goto cannot_emulate; |
e4e03ded | 1348 | c->dst.val = (s32) c->src.val; |
6aa8b732 AK |
1349 | break; |
1350 | case 0x80 ... 0x83: /* Grp1 */ | |
e4e03ded | 1351 | switch (c->modrm_reg) { |
6aa8b732 AK |
1352 | case 0: |
1353 | goto add; | |
1354 | case 1: | |
1355 | goto or; | |
1356 | case 2: | |
1357 | goto adc; | |
1358 | case 3: | |
1359 | goto sbb; | |
1360 | case 4: | |
1361 | goto and; | |
1362 | case 5: | |
1363 | goto sub; | |
1364 | case 6: | |
1365 | goto xor; | |
1366 | case 7: | |
1367 | goto cmp; | |
1368 | } | |
1369 | break; | |
1370 | case 0x84 ... 0x85: | |
05f086f8 | 1371 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1372 | break; |
1373 | case 0x86 ... 0x87: /* xchg */ | |
1374 | /* Write back the register source. */ | |
e4e03ded | 1375 | switch (c->dst.bytes) { |
6aa8b732 | 1376 | case 1: |
e4e03ded | 1377 | *(u8 *) c->src.ptr = (u8) c->dst.val; |
6aa8b732 AK |
1378 | break; |
1379 | case 2: | |
e4e03ded | 1380 | *(u16 *) c->src.ptr = (u16) c->dst.val; |
6aa8b732 AK |
1381 | break; |
1382 | case 4: | |
e4e03ded | 1383 | *c->src.ptr = (u32) c->dst.val; |
6aa8b732 AK |
1384 | break; /* 64b reg: zero-extend */ |
1385 | case 8: | |
e4e03ded | 1386 | *c->src.ptr = c->dst.val; |
6aa8b732 AK |
1387 | break; |
1388 | } | |
1389 | /* | |
1390 | * Write back the memory destination with implicit LOCK | |
1391 | * prefix. | |
1392 | */ | |
e4e03ded LV |
1393 | c->dst.val = c->src.val; |
1394 | c->lock_prefix = 1; | |
6aa8b732 | 1395 | break; |
6aa8b732 | 1396 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 1397 | goto mov; |
7e0b54b1 | 1398 | case 0x8d: /* lea r16/r32, m */ |
e4e03ded | 1399 | c->dst.val = c->modrm_val; |
7e0b54b1 | 1400 | break; |
6aa8b732 | 1401 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 LV |
1402 | rc = emulate_grp1a(ctxt, ops); |
1403 | if (rc != 0) | |
6aa8b732 | 1404 | goto done; |
6aa8b732 | 1405 | break; |
7de75248 | 1406 | case 0xa0 ... 0xa1: /* mov */ |
e4e03ded LV |
1407 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
1408 | c->dst.val = c->src.val; | |
7de75248 NK |
1409 | break; |
1410 | case 0xa2 ... 0xa3: /* mov */ | |
e4e03ded | 1411 | c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX]; |
7de75248 | 1412 | break; |
6aa8b732 | 1413 | case 0xc0 ... 0xc1: |
05f086f8 | 1414 | emulate_grp2(ctxt); |
6aa8b732 | 1415 | break; |
7de75248 NK |
1416 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
1417 | mov: | |
e4e03ded | 1418 | c->dst.val = c->src.val; |
7de75248 | 1419 | break; |
6aa8b732 | 1420 | case 0xd0 ... 0xd1: /* Grp2 */ |
e4e03ded | 1421 | c->src.val = 1; |
05f086f8 | 1422 | emulate_grp2(ctxt); |
8cdbd2c9 | 1423 | break; |
6aa8b732 | 1424 | case 0xd2 ... 0xd3: /* Grp2 */ |
e4e03ded | 1425 | c->src.val = c->regs[VCPU_REGS_RCX]; |
05f086f8 | 1426 | emulate_grp2(ctxt); |
8cdbd2c9 | 1427 | break; |
6aa8b732 | 1428 | case 0xf6 ... 0xf7: /* Grp3 */ |
05f086f8 | 1429 | rc = emulate_grp3(ctxt, ops); |
8cdbd2c9 LV |
1430 | if (rc != 0) |
1431 | goto done; | |
6aa8b732 AK |
1432 | break; |
1433 | case 0xfe ... 0xff: /* Grp4/Grp5 */ | |
a01af5ec | 1434 | rc = emulate_grp45(ctxt, ops); |
8cdbd2c9 LV |
1435 | if (rc != 0) |
1436 | goto done; | |
6aa8b732 AK |
1437 | break; |
1438 | } | |
1439 | ||
1440 | writeback: | |
a01af5ec LV |
1441 | rc = writeback(ctxt, ops); |
1442 | if (rc != 0) | |
1443 | goto done; | |
6aa8b732 AK |
1444 | |
1445 | /* Commit shadow register state. */ | |
e4e03ded | 1446 | memcpy(ctxt->vcpu->regs, c->regs, sizeof c->regs); |
e4e03ded | 1447 | ctxt->vcpu->rip = c->eip; |
6aa8b732 AK |
1448 | |
1449 | done: | |
3427318f LV |
1450 | if (rc == X86EMUL_UNHANDLEABLE) { |
1451 | c->eip = saved_eip; | |
1452 | return -1; | |
1453 | } | |
1454 | return 0; | |
6aa8b732 AK |
1455 | |
1456 | special_insn: | |
e4e03ded | 1457 | if (c->twobyte) |
6aa8b732 | 1458 | goto twobyte_special_insn; |
e4e03ded | 1459 | switch (c->b) { |
1e35d3c4 | 1460 | case 0x6a: /* push imm8 */ |
e4e03ded LV |
1461 | c->src.val = 0L; |
1462 | c->src.val = insn_fetch(s8, 1, c->eip); | |
8cdbd2c9 | 1463 | emulate_push(ctxt); |
1e35d3c4 | 1464 | break; |
e70669ab LV |
1465 | case 0x6c: /* insb */ |
1466 | case 0x6d: /* insw/insd */ | |
3090dd73 | 1467 | if (kvm_emulate_pio_string(ctxt->vcpu, NULL, |
e4e03ded LV |
1468 | 1, |
1469 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
1470 | c->rep_prefix ? | |
1471 | address_mask(c->regs[VCPU_REGS_RCX]) : 1, | |
05f086f8 | 1472 | (ctxt->eflags & EFLG_DF), |
e70669ab | 1473 | register_address(ctxt->es_base, |
e4e03ded LV |
1474 | c->regs[VCPU_REGS_RDI]), |
1475 | c->rep_prefix, | |
3427318f LV |
1476 | c->regs[VCPU_REGS_RDX]) == 0) { |
1477 | c->eip = saved_eip; | |
e70669ab | 1478 | return -1; |
3427318f | 1479 | } |
e70669ab LV |
1480 | return 0; |
1481 | case 0x6e: /* outsb */ | |
1482 | case 0x6f: /* outsw/outsd */ | |
3090dd73 | 1483 | if (kvm_emulate_pio_string(ctxt->vcpu, NULL, |
e4e03ded LV |
1484 | 0, |
1485 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
1486 | c->rep_prefix ? | |
1487 | address_mask(c->regs[VCPU_REGS_RCX]) : 1, | |
05f086f8 | 1488 | (ctxt->eflags & EFLG_DF), |
e4e03ded LV |
1489 | register_address(c->override_base ? |
1490 | *c->override_base : | |
1491 | ctxt->ds_base, | |
1492 | c->regs[VCPU_REGS_RSI]), | |
1493 | c->rep_prefix, | |
3427318f LV |
1494 | c->regs[VCPU_REGS_RDX]) == 0) { |
1495 | c->eip = saved_eip; | |
e70669ab | 1496 | return -1; |
3427318f | 1497 | } |
e70669ab | 1498 | return 0; |
55bebde4 | 1499 | case 0x70 ... 0x7f: /* jcc (short) */ { |
e4e03ded | 1500 | int rel = insn_fetch(s8, 1, c->eip); |
55bebde4 | 1501 | |
05f086f8 | 1502 | if (test_cc(c->b, ctxt->eflags)) |
55bebde4 NK |
1503 | JMP_REL(rel); |
1504 | break; | |
1505 | } | |
fd2a7608 | 1506 | case 0x9c: /* pushf */ |
05f086f8 | 1507 | c->src.val = (unsigned long) ctxt->eflags; |
8cdbd2c9 LV |
1508 | emulate_push(ctxt); |
1509 | break; | |
535eabcf | 1510 | case 0x9d: /* popf */ |
05f086f8 | 1511 | c->dst.ptr = (unsigned long *) &ctxt->eflags; |
535eabcf | 1512 | goto pop_instruction; |
7de75248 | 1513 | case 0xc3: /* ret */ |
e4e03ded | 1514 | c->dst.ptr = &c->eip; |
7de75248 NK |
1515 | goto pop_instruction; |
1516 | case 0xf4: /* hlt */ | |
1517 | ctxt->vcpu->halt_request = 1; | |
1518 | goto done; | |
b284be57 NK |
1519 | case 0xf5: /* cmc */ |
1520 | /* complement carry flag from eflags reg */ | |
1521 | ctxt->eflags ^= EFLG_CF; | |
1522 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1523 | break; | |
1524 | case 0xf8: /* clc */ | |
1525 | ctxt->eflags &= ~EFLG_CF; | |
1526 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1527 | break; | |
1528 | case 0xfa: /* cli */ | |
1529 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
1530 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1531 | break; | |
1532 | case 0xfb: /* sti */ | |
1533 | ctxt->eflags |= X86_EFLAGS_IF; | |
1534 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1535 | break; | |
e70669ab | 1536 | } |
e4e03ded LV |
1537 | if (c->rep_prefix) { |
1538 | if (c->regs[VCPU_REGS_RCX] == 0) { | |
1539 | ctxt->vcpu->rip = c->eip; | |
6aa8b732 AK |
1540 | goto done; |
1541 | } | |
e4e03ded LV |
1542 | c->regs[VCPU_REGS_RCX]--; |
1543 | c->eip = ctxt->vcpu->rip; | |
6aa8b732 | 1544 | } |
e4e03ded | 1545 | switch (c->b) { |
6aa8b732 | 1546 | case 0xa4 ... 0xa5: /* movs */ |
e4e03ded LV |
1547 | c->dst.type = OP_MEM; |
1548 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1549 | c->dst.ptr = (unsigned long *)register_address( | |
1550 | ctxt->es_base, | |
1551 | c->regs[VCPU_REGS_RDI]); | |
6aa8b732 | 1552 | if ((rc = ops->read_emulated(register_address( |
e4e03ded LV |
1553 | c->override_base ? *c->override_base : |
1554 | ctxt->ds_base, | |
1555 | c->regs[VCPU_REGS_RSI]), | |
1556 | &c->dst.val, | |
1557 | c->dst.bytes, ctxt->vcpu)) != 0) | |
6aa8b732 | 1558 | goto done; |
e4e03ded | 1559 | register_address_increment(c->regs[VCPU_REGS_RSI], |
05f086f8 | 1560 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded LV |
1561 | : c->dst.bytes); |
1562 | register_address_increment(c->regs[VCPU_REGS_RDI], | |
05f086f8 | 1563 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1564 | : c->dst.bytes); |
6aa8b732 AK |
1565 | break; |
1566 | case 0xa6 ... 0xa7: /* cmps */ | |
1567 | DPRINTF("Urk! I don't handle CMPS.\n"); | |
1568 | goto cannot_emulate; | |
1569 | case 0xaa ... 0xab: /* stos */ | |
e4e03ded LV |
1570 | c->dst.type = OP_MEM; |
1571 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
a7e6c88a SY |
1572 | c->dst.ptr = (unsigned long *)register_address( |
1573 | ctxt->es_base, | |
1574 | c->regs[VCPU_REGS_RDI]); | |
e4e03ded LV |
1575 | c->dst.val = c->regs[VCPU_REGS_RAX]; |
1576 | register_address_increment(c->regs[VCPU_REGS_RDI], | |
05f086f8 | 1577 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1578 | : c->dst.bytes); |
6aa8b732 AK |
1579 | break; |
1580 | case 0xac ... 0xad: /* lods */ | |
e4e03ded LV |
1581 | c->dst.type = OP_REG; |
1582 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1583 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
a7e6c88a SY |
1584 | if ((rc = ops->read_emulated(register_address( |
1585 | c->override_base ? *c->override_base : | |
1586 | ctxt->ds_base, | |
1587 | c->regs[VCPU_REGS_RSI]), | |
1588 | &c->dst.val, | |
1589 | c->dst.bytes, | |
1590 | ctxt->vcpu)) != 0) | |
6aa8b732 | 1591 | goto done; |
e4e03ded | 1592 | register_address_increment(c->regs[VCPU_REGS_RSI], |
05f086f8 | 1593 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1594 | : c->dst.bytes); |
6aa8b732 AK |
1595 | break; |
1596 | case 0xae ... 0xaf: /* scas */ | |
1597 | DPRINTF("Urk! I don't handle SCAS.\n"); | |
1598 | goto cannot_emulate; | |
1a52e051 NK |
1599 | case 0xe8: /* call (near) */ { |
1600 | long int rel; | |
e4e03ded | 1601 | switch (c->op_bytes) { |
1a52e051 | 1602 | case 2: |
e4e03ded | 1603 | rel = insn_fetch(s16, 2, c->eip); |
1a52e051 NK |
1604 | break; |
1605 | case 4: | |
e4e03ded | 1606 | rel = insn_fetch(s32, 4, c->eip); |
1a52e051 | 1607 | break; |
1a52e051 NK |
1608 | default: |
1609 | DPRINTF("Call: Invalid op_bytes\n"); | |
1610 | goto cannot_emulate; | |
1611 | } | |
e4e03ded | 1612 | c->src.val = (unsigned long) c->eip; |
1a52e051 | 1613 | JMP_REL(rel); |
e4e03ded | 1614 | c->op_bytes = c->ad_bytes; |
8cdbd2c9 LV |
1615 | emulate_push(ctxt); |
1616 | break; | |
1a52e051 NK |
1617 | } |
1618 | case 0xe9: /* jmp rel */ | |
1619 | case 0xeb: /* jmp rel short */ | |
e4e03ded | 1620 | JMP_REL(c->src.val); |
a01af5ec | 1621 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 NK |
1622 | break; |
1623 | ||
7f0aaee0 | 1624 | |
6aa8b732 AK |
1625 | } |
1626 | goto writeback; | |
1627 | ||
1628 | twobyte_insn: | |
e4e03ded | 1629 | switch (c->b) { |
6aa8b732 | 1630 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 1631 | switch (c->modrm_reg) { |
6aa8b732 AK |
1632 | u16 size; |
1633 | unsigned long address; | |
1634 | ||
aca7f966 | 1635 | case 0: /* vmcall */ |
e4e03ded | 1636 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
1637 | goto cannot_emulate; |
1638 | ||
7aa81cc0 AL |
1639 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1640 | if (rc) | |
1641 | goto done; | |
1642 | ||
1643 | kvm_emulate_hypercall(ctxt->vcpu); | |
aca7f966 | 1644 | break; |
6aa8b732 | 1645 | case 2: /* lgdt */ |
e4e03ded LV |
1646 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
1647 | &size, &address, c->op_bytes); | |
6aa8b732 AK |
1648 | if (rc) |
1649 | goto done; | |
1650 | realmode_lgdt(ctxt->vcpu, size, address); | |
1651 | break; | |
aca7f966 | 1652 | case 3: /* lidt/vmmcall */ |
e4e03ded | 1653 | if (c->modrm_mod == 3 && c->modrm_rm == 1) { |
7aa81cc0 AL |
1654 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1655 | if (rc) | |
1656 | goto done; | |
1657 | kvm_emulate_hypercall(ctxt->vcpu); | |
aca7f966 | 1658 | } else { |
e4e03ded | 1659 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
aca7f966 | 1660 | &size, &address, |
e4e03ded | 1661 | c->op_bytes); |
aca7f966 AL |
1662 | if (rc) |
1663 | goto done; | |
1664 | realmode_lidt(ctxt->vcpu, size, address); | |
1665 | } | |
6aa8b732 AK |
1666 | break; |
1667 | case 4: /* smsw */ | |
e4e03ded | 1668 | if (c->modrm_mod != 3) |
6aa8b732 | 1669 | goto cannot_emulate; |
e4e03ded | 1670 | *(u16 *)&c->regs[c->modrm_rm] |
6aa8b732 AK |
1671 | = realmode_get_cr(ctxt->vcpu, 0); |
1672 | break; | |
1673 | case 6: /* lmsw */ | |
e4e03ded | 1674 | if (c->modrm_mod != 3) |
6aa8b732 | 1675 | goto cannot_emulate; |
05f086f8 LV |
1676 | realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val, |
1677 | &ctxt->eflags); | |
6aa8b732 AK |
1678 | break; |
1679 | case 7: /* invlpg*/ | |
e8d8d7fe | 1680 | emulate_invlpg(ctxt->vcpu, memop); |
6aa8b732 AK |
1681 | break; |
1682 | default: | |
1683 | goto cannot_emulate; | |
1684 | } | |
a01af5ec LV |
1685 | /* Disable writeback. */ |
1686 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
1687 | break; |
1688 | case 0x21: /* mov from dr to reg */ | |
e4e03ded | 1689 | if (c->modrm_mod != 3) |
6aa8b732 | 1690 | goto cannot_emulate; |
8cdbd2c9 | 1691 | rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]); |
a01af5ec LV |
1692 | if (rc) |
1693 | goto cannot_emulate; | |
1694 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 AK |
1695 | break; |
1696 | case 0x23: /* mov from reg to dr */ | |
e4e03ded | 1697 | if (c->modrm_mod != 3) |
6aa8b732 | 1698 | goto cannot_emulate; |
e4e03ded LV |
1699 | rc = emulator_set_dr(ctxt, c->modrm_reg, |
1700 | c->regs[c->modrm_rm]); | |
a01af5ec LV |
1701 | if (rc) |
1702 | goto cannot_emulate; | |
1703 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 AK |
1704 | break; |
1705 | case 0x40 ... 0x4f: /* cmov */ | |
e4e03ded | 1706 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
1707 | if (!test_cc(c->b, ctxt->eflags)) |
1708 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 1709 | break; |
7de75248 NK |
1710 | case 0xa3: |
1711 | bt: /* bt */ | |
e4f8e039 | 1712 | c->dst.type = OP_NONE; |
e4e03ded LV |
1713 | /* only subword offset */ |
1714 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1715 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 NK |
1716 | break; |
1717 | case 0xab: | |
1718 | bts: /* bts */ | |
e4e03ded LV |
1719 | /* only subword offset */ |
1720 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1721 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 1722 | break; |
6aa8b732 AK |
1723 | case 0xb0 ... 0xb1: /* cmpxchg */ |
1724 | /* | |
1725 | * Save real source value, then compare EAX against | |
1726 | * destination. | |
1727 | */ | |
e4e03ded LV |
1728 | c->src.orig_val = c->src.val; |
1729 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
1730 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
1731 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 1732 | /* Success: write back to memory. */ |
e4e03ded | 1733 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
1734 | } else { |
1735 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded LV |
1736 | c->dst.type = OP_REG; |
1737 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
6aa8b732 AK |
1738 | } |
1739 | break; | |
6aa8b732 AK |
1740 | case 0xb3: |
1741 | btr: /* btr */ | |
e4e03ded LV |
1742 | /* only subword offset */ |
1743 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1744 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1745 | break; |
6aa8b732 | 1746 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
1747 | c->dst.bytes = c->op_bytes; |
1748 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
1749 | : (u16) c->src.val; | |
6aa8b732 | 1750 | break; |
6aa8b732 | 1751 | case 0xba: /* Grp8 */ |
e4e03ded | 1752 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
1753 | case 0: |
1754 | goto bt; | |
1755 | case 1: | |
1756 | goto bts; | |
1757 | case 2: | |
1758 | goto btr; | |
1759 | case 3: | |
1760 | goto btc; | |
1761 | } | |
1762 | break; | |
7de75248 NK |
1763 | case 0xbb: |
1764 | btc: /* btc */ | |
e4e03ded LV |
1765 | /* only subword offset */ |
1766 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1767 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 1768 | break; |
6aa8b732 | 1769 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
1770 | c->dst.bytes = c->op_bytes; |
1771 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
1772 | (s16) c->src.val; | |
6aa8b732 | 1773 | break; |
a012e65a | 1774 | case 0xc3: /* movnti */ |
e4e03ded LV |
1775 | c->dst.bytes = c->op_bytes; |
1776 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
1777 | (u64) c->src.val; | |
a012e65a | 1778 | break; |
6aa8b732 AK |
1779 | } |
1780 | goto writeback; | |
1781 | ||
1782 | twobyte_special_insn: | |
e4e03ded | 1783 | switch (c->b) { |
7de75248 NK |
1784 | case 0x06: |
1785 | emulate_clts(ctxt->vcpu); | |
1786 | break; | |
651a3e29 AK |
1787 | case 0x08: /* invd */ |
1788 | break; | |
687fdbfe AK |
1789 | case 0x09: /* wbinvd */ |
1790 | break; | |
6aa8b732 AK |
1791 | case 0x0d: /* GrpP (prefetch) */ |
1792 | case 0x18: /* Grp16 (prefetch/nop) */ | |
1793 | break; | |
6aa8b732 | 1794 | case 0x20: /* mov cr, reg */ |
e4e03ded | 1795 | if (c->modrm_mod != 3) |
6aa8b732 | 1796 | goto cannot_emulate; |
e4e03ded LV |
1797 | c->regs[c->modrm_rm] = |
1798 | realmode_get_cr(ctxt->vcpu, c->modrm_reg); | |
6aa8b732 AK |
1799 | break; |
1800 | case 0x22: /* mov reg, cr */ | |
e4e03ded | 1801 | if (c->modrm_mod != 3) |
6aa8b732 | 1802 | goto cannot_emulate; |
e4e03ded | 1803 | realmode_set_cr(ctxt->vcpu, |
05f086f8 | 1804 | c->modrm_reg, c->modrm_val, &ctxt->eflags); |
6aa8b732 | 1805 | break; |
35f3f286 AK |
1806 | case 0x30: |
1807 | /* wrmsr */ | |
e4e03ded LV |
1808 | msr_data = (u32)c->regs[VCPU_REGS_RAX] |
1809 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
1810 | rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data); | |
35f3f286 | 1811 | if (rc) { |
cbdd1bea | 1812 | kvm_x86_ops->inject_gp(ctxt->vcpu, 0); |
e4e03ded | 1813 | c->eip = ctxt->vcpu->rip; |
35f3f286 AK |
1814 | } |
1815 | rc = X86EMUL_CONTINUE; | |
1816 | break; | |
1817 | case 0x32: | |
1818 | /* rdmsr */ | |
8cdbd2c9 | 1819 | rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data); |
35f3f286 | 1820 | if (rc) { |
cbdd1bea | 1821 | kvm_x86_ops->inject_gp(ctxt->vcpu, 0); |
e4e03ded | 1822 | c->eip = ctxt->vcpu->rip; |
35f3f286 | 1823 | } else { |
e4e03ded LV |
1824 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; |
1825 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
35f3f286 AK |
1826 | } |
1827 | rc = X86EMUL_CONTINUE; | |
1828 | break; | |
bbe9abbd NK |
1829 | case 0x80 ... 0x8f: /* jnz rel, etc*/ { |
1830 | long int rel; | |
1831 | ||
e4e03ded | 1832 | switch (c->op_bytes) { |
bbe9abbd | 1833 | case 2: |
e4e03ded | 1834 | rel = insn_fetch(s16, 2, c->eip); |
bbe9abbd NK |
1835 | break; |
1836 | case 4: | |
e4e03ded | 1837 | rel = insn_fetch(s32, 4, c->eip); |
bbe9abbd NK |
1838 | break; |
1839 | case 8: | |
e4e03ded | 1840 | rel = insn_fetch(s64, 8, c->eip); |
bbe9abbd NK |
1841 | break; |
1842 | default: | |
1843 | DPRINTF("jnz: Invalid op_bytes\n"); | |
1844 | goto cannot_emulate; | |
1845 | } | |
05f086f8 | 1846 | if (test_cc(c->b, ctxt->eflags)) |
bbe9abbd NK |
1847 | JMP_REL(rel); |
1848 | break; | |
1849 | } | |
6aa8b732 | 1850 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
e8d8d7fe | 1851 | rc = emulate_grp9(ctxt, ops, memop); |
8cdbd2c9 LV |
1852 | if (rc != 0) |
1853 | goto done; | |
1854 | break; | |
6aa8b732 | 1855 | } |
a01af5ec LV |
1856 | /* Disable writeback. */ |
1857 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
1858 | goto writeback; |
1859 | ||
1860 | cannot_emulate: | |
e4e03ded | 1861 | DPRINTF("Cannot emulate %02x\n", c->b); |
3427318f | 1862 | c->eip = saved_eip; |
6aa8b732 AK |
1863 | return -1; |
1864 | } |