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625efab1 JS |
1 | /* |
2 | * Copyright (C) 2006, Rusty Russell <rusty@rustcorp.com.au> IBM Corporation. | |
3 | * Copyright (C) 2007, Jes Sorensen <jes@sgi.com> SGI. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
13 | * NON INFRINGEMENT. See the GNU General Public License for more | |
14 | * details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
2e04ef76 RR |
20 | /*P:450 |
21 | * This file contains the x86-specific lguest code. It used to be all | |
a6bd8e13 RR |
22 | * mixed in with drivers/lguest/core.c but several foolhardy code slashers |
23 | * wrestled most of the dependencies out to here in preparation for porting | |
24 | * lguest to other architectures (see what I mean by foolhardy?). | |
25 | * | |
26 | * This also contains a couple of non-obvious setup and teardown pieces which | |
2e04ef76 RR |
27 | * were implemented after days of debugging pain. |
28 | :*/ | |
625efab1 JS |
29 | #include <linux/kernel.h> |
30 | #include <linux/start_kernel.h> | |
31 | #include <linux/string.h> | |
32 | #include <linux/console.h> | |
33 | #include <linux/screen_info.h> | |
34 | #include <linux/irq.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/clocksource.h> | |
37 | #include <linux/clockchips.h> | |
38 | #include <linux/cpu.h> | |
39 | #include <linux/lguest.h> | |
40 | #include <linux/lguest_launcher.h> | |
625efab1 JS |
41 | #include <asm/paravirt.h> |
42 | #include <asm/param.h> | |
43 | #include <asm/page.h> | |
44 | #include <asm/pgtable.h> | |
45 | #include <asm/desc.h> | |
46 | #include <asm/setup.h> | |
47 | #include <asm/lguest.h> | |
48 | #include <asm/uaccess.h> | |
49 | #include <asm/i387.h> | |
50 | #include "../lg.h" | |
51 | ||
52 | static int cpu_had_pge; | |
53 | ||
54 | static struct { | |
55 | unsigned long offset; | |
56 | unsigned short segment; | |
57 | } lguest_entry; | |
58 | ||
59 | /* Offset from where switcher.S was compiled to where we've copied it */ | |
60 | static unsigned long switcher_offset(void) | |
61 | { | |
406a590b | 62 | return switcher_addr - (unsigned long)start_switcher_text; |
625efab1 JS |
63 | } |
64 | ||
93a2cdff | 65 | /* This cpu's struct lguest_pages (after the Switcher text page) */ |
625efab1 JS |
66 | static struct lguest_pages *lguest_pages(unsigned int cpu) |
67 | { | |
93a2cdff | 68 | return &(((struct lguest_pages *)(switcher_addr + PAGE_SIZE))[cpu]); |
625efab1 JS |
69 | } |
70 | ||
390dfd95 | 71 | static DEFINE_PER_CPU(struct lg_cpu *, lg_last_cpu); |
625efab1 JS |
72 | |
73 | /*S:010 | |
e1e72965 | 74 | * We approach the Switcher. |
625efab1 JS |
75 | * |
76 | * Remember that each CPU has two pages which are visible to the Guest when it | |
77 | * runs on that CPU. This has to contain the state for that Guest: we copy the | |
78 | * state in just before we run the Guest. | |
79 | * | |
80 | * Each Guest has "changed" flags which indicate what has changed in the Guest | |
81 | * since it last ran. We saw this set in interrupts_and_traps.c and | |
82 | * segments.c. | |
83 | */ | |
d0953d42 | 84 | static void copy_in_guest_info(struct lg_cpu *cpu, struct lguest_pages *pages) |
625efab1 | 85 | { |
2e04ef76 RR |
86 | /* |
87 | * Copying all this data can be quite expensive. We usually run the | |
625efab1 JS |
88 | * same Guest we ran last time (and that Guest hasn't run anywhere else |
89 | * meanwhile). If that's not the case, we pretend everything in the | |
2e04ef76 RR |
90 | * Guest has changed. |
91 | */ | |
c9f29549 | 92 | if (__this_cpu_read(lg_last_cpu) != cpu || cpu->last_pages != pages) { |
ced05dd7 | 93 | __this_cpu_write(lg_last_cpu, cpu); |
f34f8c5f | 94 | cpu->last_pages = pages; |
ae3749dc | 95 | cpu->changed = CHANGED_ALL; |
625efab1 JS |
96 | } |
97 | ||
2e04ef76 RR |
98 | /* |
99 | * These copies are pretty cheap, so we do them unconditionally: */ | |
100 | /* Save the current Host top-level page directory. | |
101 | */ | |
625efab1 | 102 | pages->state.host_cr3 = __pa(current->mm->pgd); |
2e04ef76 RR |
103 | /* |
104 | * Set up the Guest's page tables to see this CPU's pages (and no | |
105 | * other CPU's pages). | |
106 | */ | |
0c78441c | 107 | map_switcher_in_guest(cpu, pages); |
2e04ef76 RR |
108 | /* |
109 | * Set up the two "TSS" members which tell the CPU what stack to use | |
625efab1 | 110 | * for traps which do directly into the Guest (ie. traps at privilege |
2e04ef76 RR |
111 | * level 1). |
112 | */ | |
e95035c6 | 113 | pages->state.guest_tss.sp1 = cpu->esp1; |
4665ac8e | 114 | pages->state.guest_tss.ss1 = cpu->ss1; |
625efab1 JS |
115 | |
116 | /* Copy direct-to-Guest trap entries. */ | |
ae3749dc | 117 | if (cpu->changed & CHANGED_IDT) |
fc708b3e | 118 | copy_traps(cpu, pages->state.guest_idt, default_idt_entries); |
625efab1 JS |
119 | |
120 | /* Copy all GDT entries which the Guest can change. */ | |
ae3749dc | 121 | if (cpu->changed & CHANGED_GDT) |
fc708b3e | 122 | copy_gdt(cpu, pages->state.guest_gdt); |
625efab1 | 123 | /* If only the TLS entries have changed, copy them. */ |
ae3749dc | 124 | else if (cpu->changed & CHANGED_GDT_TLS) |
fc708b3e | 125 | copy_gdt_tls(cpu, pages->state.guest_gdt); |
625efab1 JS |
126 | |
127 | /* Mark the Guest as unchanged for next time. */ | |
ae3749dc | 128 | cpu->changed = 0; |
625efab1 JS |
129 | } |
130 | ||
131 | /* Finally: the code to actually call into the Switcher to run the Guest. */ | |
d0953d42 | 132 | static void run_guest_once(struct lg_cpu *cpu, struct lguest_pages *pages) |
625efab1 JS |
133 | { |
134 | /* This is a dummy value we need for GCC's sake. */ | |
135 | unsigned int clobber; | |
136 | ||
2e04ef76 RR |
137 | /* |
138 | * Copy the guest-specific information into this CPU's "struct | |
139 | * lguest_pages". | |
140 | */ | |
d0953d42 | 141 | copy_in_guest_info(cpu, pages); |
625efab1 | 142 | |
2e04ef76 RR |
143 | /* |
144 | * Set the trap number to 256 (impossible value). If we fault while | |
625efab1 | 145 | * switching to the Guest (bad segment registers or bug), this will |
2e04ef76 RR |
146 | * cause us to abort the Guest. |
147 | */ | |
a53a35a8 | 148 | cpu->regs->trapnum = 256; |
625efab1 | 149 | |
2e04ef76 RR |
150 | /* |
151 | * Now: we push the "eflags" register on the stack, then do an "lcall". | |
625efab1 JS |
152 | * This is how we change from using the kernel code segment to using |
153 | * the dedicated lguest code segment, as well as jumping into the | |
154 | * Switcher. | |
155 | * | |
156 | * The lcall also pushes the old code segment (KERNEL_CS) onto the | |
157 | * stack, then the address of this call. This stack layout happens to | |
2e04ef76 RR |
158 | * exactly match the stack layout created by an interrupt... |
159 | */ | |
625efab1 | 160 | asm volatile("pushf; lcall *lguest_entry" |
2e04ef76 RR |
161 | /* |
162 | * This is how we tell GCC that %eax ("a") and %ebx ("b") | |
163 | * are changed by this routine. The "=" means output. | |
164 | */ | |
625efab1 | 165 | : "=a"(clobber), "=b"(clobber) |
2e04ef76 RR |
166 | /* |
167 | * %eax contains the pages pointer. ("0" refers to the | |
625efab1 JS |
168 | * 0-th argument above, ie "a"). %ebx contains the |
169 | * physical address of the Guest's top-level page | |
2e04ef76 RR |
170 | * directory. |
171 | */ | |
382ac6b3 | 172 | : "0"(pages), "1"(__pa(cpu->lg->pgdirs[cpu->cpu_pgd].pgdir)) |
2e04ef76 RR |
173 | /* |
174 | * We tell gcc that all these registers could change, | |
625efab1 | 175 | * which means we don't have to save and restore them in |
2e04ef76 RR |
176 | * the Switcher. |
177 | */ | |
625efab1 JS |
178 | : "memory", "%edx", "%ecx", "%edi", "%esi"); |
179 | } | |
180 | /*:*/ | |
181 | ||
2e04ef76 RR |
182 | /*M:002 |
183 | * There are hooks in the scheduler which we can register to tell when we | |
e1e72965 RR |
184 | * get kicked off the CPU (preempt_notifier_register()). This would allow us |
185 | * to lazily disable SYSENTER which would regain some performance, and should | |
186 | * also simplify copy_in_guest_info(). Note that we'd still need to restore | |
187 | * things when we exit to Launcher userspace, but that's fairly easy. | |
188 | * | |
a91d74a3 | 189 | * We could also try using these hooks for PGE, but that might be too expensive. |
a6bd8e13 | 190 | * |
2e04ef76 RR |
191 | * The hooks were designed for KVM, but we can also put them to good use. |
192 | :*/ | |
e1e72965 | 193 | |
2e04ef76 RR |
194 | /*H:040 |
195 | * This is the i386-specific code to setup and run the Guest. Interrupts | |
196 | * are disabled: we own the CPU. | |
197 | */ | |
d0953d42 | 198 | void lguest_arch_run_guest(struct lg_cpu *cpu) |
625efab1 | 199 | { |
2e04ef76 RR |
200 | /* |
201 | * Remember the awfully-named TS bit? If the Guest has asked to set it | |
e1e72965 | 202 | * we set it now, so we can trap and pass that trap to the Guest if it |
2e04ef76 RR |
203 | * uses the FPU. |
204 | */ | |
9c6ff8bb SS |
205 | if (cpu->ts && user_has_fpu()) |
206 | stts(); | |
625efab1 | 207 | |
2e04ef76 RR |
208 | /* |
209 | * SYSENTER is an optimized way of doing system calls. We can't allow | |
e1e72965 RR |
210 | * it because it always jumps to privilege level 0. A normal Guest |
211 | * won't try it because we don't advertise it in CPUID, but a malicious | |
212 | * Guest (or malicious Guest userspace program) could, so we tell the | |
2e04ef76 RR |
213 | * CPU to disable it before running the Guest. |
214 | */ | |
625efab1 JS |
215 | if (boot_cpu_has(X86_FEATURE_SEP)) |
216 | wrmsr(MSR_IA32_SYSENTER_CS, 0, 0); | |
217 | ||
2e04ef76 RR |
218 | /* |
219 | * Now we actually run the Guest. It will return when something | |
e1e72965 | 220 | * interesting happens, and we can examine its registers to see what it |
2e04ef76 RR |
221 | * was doing. |
222 | */ | |
d0953d42 | 223 | run_guest_once(cpu, lguest_pages(raw_smp_processor_id())); |
625efab1 | 224 | |
2e04ef76 RR |
225 | /* |
226 | * Note that the "regs" structure contains two extra entries which are | |
e1e72965 RR |
227 | * not really registers: a trap number which says what interrupt or |
228 | * trap made the switcher code come back, and an error code which some | |
2e04ef76 RR |
229 | * traps set. |
230 | */ | |
625efab1 | 231 | |
54481cf8 SS |
232 | /* Restore SYSENTER if it's supposed to be on. */ |
233 | if (boot_cpu_has(X86_FEATURE_SEP)) | |
234 | wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0); | |
235 | ||
9c6ff8bb SS |
236 | /* Clear the host TS bit if it was set above. */ |
237 | if (cpu->ts && user_has_fpu()) | |
238 | clts(); | |
239 | ||
2e04ef76 RR |
240 | /* |
241 | * If the Guest page faulted, then the cr2 register will tell us the | |
e1e72965 RR |
242 | * bad virtual address. We have to grab this now, because once we |
243 | * re-enable interrupts an interrupt could fault and thus overwrite | |
2e04ef76 RR |
244 | * cr2, or we could even move off to a different CPU. |
245 | */ | |
a53a35a8 | 246 | if (cpu->regs->trapnum == 14) |
fc708b3e | 247 | cpu->arch.last_pagefault = read_cr2(); |
2e04ef76 RR |
248 | /* |
249 | * Similarly, if we took a trap because the Guest used the FPU, | |
54481cf8 SS |
250 | * we have to restore the FPU it expects to see. |
251 | * math_state_restore() may sleep and we may even move off to | |
252 | * a different CPU. So all the critical stuff should be done | |
2e04ef76 RR |
253 | * before this. |
254 | */ | |
9c6ff8bb | 255 | else if (cpu->regs->trapnum == 7 && !user_has_fpu()) |
625efab1 | 256 | math_state_restore(); |
625efab1 JS |
257 | } |
258 | ||
2e04ef76 RR |
259 | /*H:130 |
260 | * Now we've examined the hypercall code; our Guest can make requests. | |
e1e72965 RR |
261 | * Our Guest is usually so well behaved; it never tries to do things it isn't |
262 | * allowed to, and uses hypercalls instead. Unfortunately, Linux's paravirtual | |
263 | * infrastructure isn't quite complete, because it doesn't contain replacements | |
264 | * for the Intel I/O instructions. As a result, the Guest sometimes fumbles | |
265 | * across one during the boot process as it probes for various things which are | |
266 | * usually attached to a PC. | |
625efab1 | 267 | * |
e1e72965 | 268 | * When the Guest uses one of these instructions, we get a trap (General |
625efab1 | 269 | * Protection Fault) and come here. We see if it's one of those troublesome |
2e04ef76 RR |
270 | * instructions and skip over it. We return true if we did. |
271 | */ | |
a3863f68 | 272 | static int emulate_insn(struct lg_cpu *cpu) |
625efab1 JS |
273 | { |
274 | u8 insn; | |
996ba96a | 275 | unsigned int insnlen = 0, in = 0, small_operand = 0; |
2e04ef76 RR |
276 | /* |
277 | * The eip contains the *virtual* address of the Guest's instruction: | |
9f54288d | 278 | * walk the Guest's page tables to find the "physical" address. |
2e04ef76 | 279 | */ |
1713608f | 280 | unsigned long physaddr = guest_pa(cpu, cpu->regs->eip); |
625efab1 | 281 | |
2e04ef76 RR |
282 | /* |
283 | * This must be the Guest kernel trying to do something, not userspace! | |
47436aa4 | 284 | * The bottom two bits of the CS segment register are the privilege |
2e04ef76 RR |
285 | * level. |
286 | */ | |
a53a35a8 | 287 | if ((cpu->regs->cs & 3) != GUEST_PL) |
625efab1 JS |
288 | return 0; |
289 | ||
290 | /* Decoding x86 instructions is icky. */ | |
382ac6b3 | 291 | insn = lgread(cpu, physaddr, u8); |
625efab1 | 292 | |
5094aeaf RR |
293 | /* |
294 | * Around 2.6.33, the kernel started using an emulation for the | |
295 | * cmpxchg8b instruction in early boot on many configurations. This | |
296 | * code isn't paravirtualized, and it tries to disable interrupts. | |
297 | * Ignore it, which will Mostly Work. | |
298 | */ | |
299 | if (insn == 0xfa) { | |
300 | /* "cli", or Clear Interrupt Enable instruction. Skip it. */ | |
301 | cpu->regs->eip++; | |
302 | return 1; | |
303 | } | |
304 | ||
2e04ef76 | 305 | /* |
996ba96a | 306 | * 0x66 is an "operand prefix". It means a 16, not 32 bit in/out. |
2e04ef76 | 307 | */ |
625efab1 | 308 | if (insn == 0x66) { |
996ba96a | 309 | small_operand = 1; |
625efab1 JS |
310 | /* The instruction is 1 byte so far, read the next byte. */ |
311 | insnlen = 1; | |
382ac6b3 | 312 | insn = lgread(cpu, physaddr + insnlen, u8); |
625efab1 JS |
313 | } |
314 | ||
2e04ef76 RR |
315 | /* |
316 | * We can ignore the lower bit for the moment and decode the 4 opcodes | |
317 | * we need to emulate. | |
318 | */ | |
625efab1 JS |
319 | switch (insn & 0xFE) { |
320 | case 0xE4: /* in <next byte>,%al */ | |
321 | insnlen += 2; | |
322 | in = 1; | |
323 | break; | |
324 | case 0xEC: /* in (%dx),%al */ | |
325 | insnlen += 1; | |
326 | in = 1; | |
327 | break; | |
328 | case 0xE6: /* out %al,<next byte> */ | |
329 | insnlen += 2; | |
330 | break; | |
331 | case 0xEE: /* out %al,(%dx) */ | |
332 | insnlen += 1; | |
333 | break; | |
334 | default: | |
335 | /* OK, we don't know what this is, can't emulate. */ | |
336 | return 0; | |
337 | } | |
338 | ||
2e04ef76 RR |
339 | /* |
340 | * If it was an "IN" instruction, they expect the result to be read | |
625efab1 | 341 | * into %eax, so we change %eax. We always return all-ones, which |
2e04ef76 RR |
342 | * traditionally means "there's nothing there". |
343 | */ | |
625efab1 | 344 | if (in) { |
996ba96a RR |
345 | /* Lower bit tells means it's a 32/16 bit access */ |
346 | if (insn & 0x1) { | |
347 | if (small_operand) | |
348 | cpu->regs->eax |= 0xFFFF; | |
349 | else | |
350 | cpu->regs->eax = 0xFFFFFFFF; | |
351 | } else | |
352 | cpu->regs->eax |= 0xFF; | |
625efab1 JS |
353 | } |
354 | /* Finally, we've "done" the instruction, so move past it. */ | |
a53a35a8 | 355 | cpu->regs->eip += insnlen; |
625efab1 JS |
356 | /* Success! */ |
357 | return 1; | |
358 | } | |
359 | ||
360 | /*H:050 Once we've re-enabled interrupts, we look at why the Guest exited. */ | |
73044f05 | 361 | void lguest_arch_handle_trap(struct lg_cpu *cpu) |
625efab1 | 362 | { |
a53a35a8 | 363 | switch (cpu->regs->trapnum) { |
e1e72965 | 364 | case 13: /* We've intercepted a General Protection Fault. */ |
2e04ef76 RR |
365 | /* |
366 | * Check if this was one of those annoying IN or OUT | |
e1e72965 | 367 | * instructions which we need to emulate. If so, we just go |
2e04ef76 RR |
368 | * back into the Guest after we've done it. |
369 | */ | |
a53a35a8 | 370 | if (cpu->regs->errcode == 0) { |
a3863f68 | 371 | if (emulate_insn(cpu)) |
625efab1 JS |
372 | return; |
373 | } | |
374 | break; | |
e1e72965 | 375 | case 14: /* We've intercepted a Page Fault. */ |
2e04ef76 RR |
376 | /* |
377 | * The Guest accessed a virtual address that wasn't mapped. | |
a6bd8e13 RR |
378 | * This happens a lot: we don't actually set up most of the page |
379 | * tables for the Guest at all when we start: as it runs it asks | |
380 | * for more and more, and we set them up as required. In this | |
381 | * case, we don't even tell the Guest that the fault happened. | |
e1e72965 RR |
382 | * |
383 | * The errcode tells whether this was a read or a write, and | |
2e04ef76 RR |
384 | * whether kernel or userspace code. |
385 | */ | |
1713608f GOC |
386 | if (demand_page(cpu, cpu->arch.last_pagefault, |
387 | cpu->regs->errcode)) | |
625efab1 JS |
388 | return; |
389 | ||
2e04ef76 RR |
390 | /* |
391 | * OK, it's really not there (or not OK): the Guest needs to | |
e1e72965 RR |
392 | * know. We write out the cr2 value so it knows where the |
393 | * fault occurred. | |
394 | * | |
395 | * Note that if the Guest were really messed up, this could | |
396 | * happen before it's done the LHCALL_LGUEST_INIT hypercall, so | |
2e04ef76 RR |
397 | * lg->lguest_data could be NULL |
398 | */ | |
382ac6b3 GOC |
399 | if (cpu->lg->lguest_data && |
400 | put_user(cpu->arch.last_pagefault, | |
401 | &cpu->lg->lguest_data->cr2)) | |
402 | kill_guest(cpu, "Writing cr2"); | |
625efab1 JS |
403 | break; |
404 | case 7: /* We've intercepted a Device Not Available fault. */ | |
2e04ef76 RR |
405 | /* |
406 | * If the Guest doesn't want to know, we already restored the | |
407 | * Floating Point Unit, so we just continue without telling it. | |
408 | */ | |
4665ac8e | 409 | if (!cpu->ts) |
625efab1 JS |
410 | return; |
411 | break; | |
412 | case 32 ... 255: | |
2e04ef76 RR |
413 | /* |
414 | * These values mean a real interrupt occurred, in which case | |
4cd8b5e2 | 415 | * the Host handler has already been run. We just do a |
cc6d4fbc | 416 | * friendly check if another process should now be run, then |
9f54288d | 417 | * return to run the Guest again. |
2e04ef76 | 418 | */ |
625efab1 | 419 | cond_resched(); |
cc6d4fbc RR |
420 | return; |
421 | case LGUEST_TRAP_ENTRY: | |
2e04ef76 RR |
422 | /* |
423 | * Our 'struct hcall_args' maps directly over our regs: we set | |
424 | * up the pointer now to indicate a hypercall is pending. | |
425 | */ | |
a53a35a8 | 426 | cpu->hcall = (struct hcall_args *)cpu->regs; |
625efab1 JS |
427 | return; |
428 | } | |
429 | ||
430 | /* We didn't handle the trap, so it needs to go to the Guest. */ | |
a53a35a8 | 431 | if (!deliver_trap(cpu, cpu->regs->trapnum)) |
2e04ef76 RR |
432 | /* |
433 | * If the Guest doesn't have a handler (either it hasn't | |
625efab1 | 434 | * registered any yet, or it's one of the faults we don't let |
2e04ef76 RR |
435 | * it handle), it dies with this cryptic error message. |
436 | */ | |
382ac6b3 | 437 | kill_guest(cpu, "unhandled trap %li at %#lx (%#lx)", |
a53a35a8 | 438 | cpu->regs->trapnum, cpu->regs->eip, |
fc708b3e | 439 | cpu->regs->trapnum == 14 ? cpu->arch.last_pagefault |
a53a35a8 | 440 | : cpu->regs->errcode); |
625efab1 JS |
441 | } |
442 | ||
2e04ef76 RR |
443 | /* |
444 | * Now we can look at each of the routines this calls, in increasing order of | |
625efab1 JS |
445 | * complexity: do_hypercalls(), emulate_insn(), maybe_do_interrupt(), |
446 | * deliver_trap() and demand_page(). After all those, we'll be ready to | |
447 | * examine the Switcher, and our philosophical understanding of the Host/Guest | |
2e04ef76 RR |
448 | * duality will be complete. |
449 | :*/ | |
625efab1 JS |
450 | static void adjust_pge(void *on) |
451 | { | |
452 | if (on) | |
453 | write_cr4(read_cr4() | X86_CR4_PGE); | |
454 | else | |
455 | write_cr4(read_cr4() & ~X86_CR4_PGE); | |
456 | } | |
457 | ||
2e04ef76 RR |
458 | /*H:020 |
459 | * Now the Switcher is mapped and every thing else is ready, we need to do | |
460 | * some more i386-specific initialization. | |
461 | */ | |
625efab1 JS |
462 | void __init lguest_arch_host_init(void) |
463 | { | |
464 | int i; | |
465 | ||
2e04ef76 | 466 | /* |
9f54288d | 467 | * Most of the x86/switcher_32.S doesn't care that it's been moved; on |
625efab1 JS |
468 | * Intel, jumps are relative, and it doesn't access any references to |
469 | * external code or data. | |
470 | * | |
471 | * The only exception is the interrupt handlers in switcher.S: their | |
472 | * addresses are placed in a table (default_idt_entries), so we need to | |
473 | * update the table with the new addresses. switcher_offset() is a | |
a6bd8e13 | 474 | * convenience function which returns the distance between the |
2e04ef76 RR |
475 | * compiled-in switcher code and the high-mapped copy we just made. |
476 | */ | |
625efab1 JS |
477 | for (i = 0; i < IDT_ENTRIES; i++) |
478 | default_idt_entries[i] += switcher_offset(); | |
479 | ||
480 | /* | |
481 | * Set up the Switcher's per-cpu areas. | |
482 | * | |
483 | * Each CPU gets two pages of its own within the high-mapped region | |
484 | * (aka. "struct lguest_pages"). Much of this can be initialized now, | |
485 | * but some depends on what Guest we are running (which is set up in | |
486 | * copy_in_guest_info()). | |
487 | */ | |
488 | for_each_possible_cpu(i) { | |
489 | /* lguest_pages() returns this CPU's two pages. */ | |
490 | struct lguest_pages *pages = lguest_pages(i); | |
2e04ef76 | 491 | /* This is a convenience pointer to make the code neater. */ |
625efab1 JS |
492 | struct lguest_ro_state *state = &pages->state; |
493 | ||
2e04ef76 RR |
494 | /* |
495 | * The Global Descriptor Table: the Host has a different one | |
625efab1 JS |
496 | * for each CPU. We keep a descriptor for the GDT which says |
497 | * where it is and how big it is (the size is actually the last | |
2e04ef76 RR |
498 | * byte, not the size, hence the "-1"). |
499 | */ | |
625efab1 JS |
500 | state->host_gdt_desc.size = GDT_SIZE-1; |
501 | state->host_gdt_desc.address = (long)get_cpu_gdt_table(i); | |
502 | ||
2e04ef76 RR |
503 | /* |
504 | * All CPUs on the Host use the same Interrupt Descriptor | |
625efab1 | 505 | * Table, so we just use store_idt(), which gets this CPU's IDT |
2e04ef76 RR |
506 | * descriptor. |
507 | */ | |
625efab1 JS |
508 | store_idt(&state->host_idt_desc); |
509 | ||
2e04ef76 RR |
510 | /* |
511 | * The descriptors for the Guest's GDT and IDT can be filled | |
625efab1 | 512 | * out now, too. We copy the GDT & IDT into ->guest_gdt and |
2e04ef76 RR |
513 | * ->guest_idt before actually running the Guest. |
514 | */ | |
625efab1 JS |
515 | state->guest_idt_desc.size = sizeof(state->guest_idt)-1; |
516 | state->guest_idt_desc.address = (long)&state->guest_idt; | |
517 | state->guest_gdt_desc.size = sizeof(state->guest_gdt)-1; | |
518 | state->guest_gdt_desc.address = (long)&state->guest_gdt; | |
519 | ||
2e04ef76 RR |
520 | /* |
521 | * We know where we want the stack to be when the Guest enters | |
a6bd8e13 | 522 | * the Switcher: in pages->regs. The stack grows upwards, so |
2e04ef76 RR |
523 | * we start it at the end of that structure. |
524 | */ | |
faca6227 | 525 | state->guest_tss.sp0 = (long)(&pages->regs + 1); |
2e04ef76 RR |
526 | /* |
527 | * And this is the GDT entry to use for the stack: we keep a | |
528 | * couple of special LGUEST entries. | |
529 | */ | |
625efab1 JS |
530 | state->guest_tss.ss0 = LGUEST_DS; |
531 | ||
2e04ef76 RR |
532 | /* |
533 | * x86 can have a finegrained bitmap which indicates what I/O | |
625efab1 | 534 | * ports the process can use. We set it to the end of our |
2e04ef76 RR |
535 | * structure, meaning "none". |
536 | */ | |
625efab1 JS |
537 | state->guest_tss.io_bitmap_base = sizeof(state->guest_tss); |
538 | ||
2e04ef76 RR |
539 | /* |
540 | * Some GDT entries are the same across all Guests, so we can | |
541 | * set them up now. | |
542 | */ | |
625efab1 JS |
543 | setup_default_gdt_entries(state); |
544 | /* Most IDT entries are the same for all Guests, too.*/ | |
545 | setup_default_idt_entries(state, default_idt_entries); | |
546 | ||
2e04ef76 RR |
547 | /* |
548 | * The Host needs to be able to use the LGUEST segments on this | |
549 | * CPU, too, so put them in the Host GDT. | |
550 | */ | |
625efab1 JS |
551 | get_cpu_gdt_table(i)[GDT_ENTRY_LGUEST_CS] = FULL_EXEC_SEGMENT; |
552 | get_cpu_gdt_table(i)[GDT_ENTRY_LGUEST_DS] = FULL_SEGMENT; | |
553 | } | |
554 | ||
2e04ef76 RR |
555 | /* |
556 | * In the Switcher, we want the %cs segment register to use the | |
625efab1 JS |
557 | * LGUEST_CS GDT entry: we've put that in the Host and Guest GDTs, so |
558 | * it will be undisturbed when we switch. To change %cs and jump we | |
2e04ef76 RR |
559 | * need this structure to feed to Intel's "lcall" instruction. |
560 | */ | |
625efab1 JS |
561 | lguest_entry.offset = (long)switch_to_guest + switcher_offset(); |
562 | lguest_entry.segment = LGUEST_CS; | |
563 | ||
2e04ef76 RR |
564 | /* |
565 | * Finally, we need to turn off "Page Global Enable". PGE is an | |
625efab1 JS |
566 | * optimization where page table entries are specially marked to show |
567 | * they never change. The Host kernel marks all the kernel pages this | |
568 | * way because it's always present, even when userspace is running. | |
569 | * | |
570 | * Lguest breaks this: unbeknownst to the rest of the Host kernel, we | |
571 | * switch to the Guest kernel. If you don't disable this on all CPUs, | |
572 | * you'll get really weird bugs that you'll chase for two days. | |
573 | * | |
574 | * I used to turn PGE off every time we switched to the Guest and back | |
2e04ef76 RR |
575 | * on when we return, but that slowed the Switcher down noticibly. |
576 | */ | |
625efab1 | 577 | |
2e04ef76 RR |
578 | /* |
579 | * We don't need the complexity of CPUs coming and going while we're | |
580 | * doing this. | |
581 | */ | |
86ef5c9a | 582 | get_online_cpus(); |
625efab1 JS |
583 | if (cpu_has_pge) { /* We have a broader idea of "global". */ |
584 | /* Remember that this was originally set (for cleanup). */ | |
585 | cpu_had_pge = 1; | |
2e04ef76 RR |
586 | /* |
587 | * adjust_pge is a helper function which sets or unsets the PGE | |
588 | * bit on its CPU, depending on the argument (0 == unset). | |
589 | */ | |
15c8b6c1 | 590 | on_each_cpu(adjust_pge, (void *)0, 1); |
625efab1 | 591 | /* Turn off the feature in the global feature set. */ |
cf485e56 | 592 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_PGE); |
625efab1 | 593 | } |
86ef5c9a | 594 | put_online_cpus(); |
9f54288d | 595 | } |
625efab1 JS |
596 | /*:*/ |
597 | ||
598 | void __exit lguest_arch_host_fini(void) | |
599 | { | |
600 | /* If we had PGE before we started, turn it back on now. */ | |
86ef5c9a | 601 | get_online_cpus(); |
625efab1 | 602 | if (cpu_had_pge) { |
cf485e56 | 603 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_PGE); |
625efab1 | 604 | /* adjust_pge's argument "1" means set PGE. */ |
15c8b6c1 | 605 | on_each_cpu(adjust_pge, (void *)1, 1); |
625efab1 | 606 | } |
86ef5c9a | 607 | put_online_cpus(); |
625efab1 | 608 | } |
b410e7b1 JS |
609 | |
610 | ||
611 | /*H:122 The i386-specific hypercalls simply farm out to the right functions. */ | |
73044f05 | 612 | int lguest_arch_do_hcall(struct lg_cpu *cpu, struct hcall_args *args) |
b410e7b1 JS |
613 | { |
614 | switch (args->arg0) { | |
a489f0b5 RR |
615 | case LHCALL_LOAD_GDT_ENTRY: |
616 | load_guest_gdt_entry(cpu, args->arg1, args->arg2, args->arg3); | |
b410e7b1 JS |
617 | break; |
618 | case LHCALL_LOAD_IDT_ENTRY: | |
fc708b3e | 619 | load_guest_idt_entry(cpu, args->arg1, args->arg2, args->arg3); |
b410e7b1 JS |
620 | break; |
621 | case LHCALL_LOAD_TLS: | |
fc708b3e | 622 | guest_load_tls(cpu, args->arg1); |
b410e7b1 JS |
623 | break; |
624 | default: | |
625 | /* Bad Guest. Bad! */ | |
626 | return -EIO; | |
627 | } | |
628 | return 0; | |
629 | } | |
630 | ||
631 | /*H:126 i386-specific hypercall initialization: */ | |
73044f05 | 632 | int lguest_arch_init_hypercalls(struct lg_cpu *cpu) |
b410e7b1 JS |
633 | { |
634 | u32 tsc_speed; | |
635 | ||
2e04ef76 RR |
636 | /* |
637 | * The pointer to the Guest's "struct lguest_data" is the only argument. | |
638 | * We check that address now. | |
639 | */ | |
382ac6b3 GOC |
640 | if (!lguest_address_ok(cpu->lg, cpu->hcall->arg1, |
641 | sizeof(*cpu->lg->lguest_data))) | |
b410e7b1 JS |
642 | return -EFAULT; |
643 | ||
2e04ef76 RR |
644 | /* |
645 | * Having checked it, we simply set lg->lguest_data to point straight | |
b410e7b1 JS |
646 | * into the Launcher's memory at the right place and then use |
647 | * copy_to_user/from_user from now on, instead of lgread/write. I put | |
648 | * this in to show that I'm not immune to writing stupid | |
2e04ef76 RR |
649 | * optimizations. |
650 | */ | |
382ac6b3 | 651 | cpu->lg->lguest_data = cpu->lg->mem_base + cpu->hcall->arg1; |
b410e7b1 | 652 | |
2e04ef76 RR |
653 | /* |
654 | * We insist that the Time Stamp Counter exist and doesn't change with | |
b410e7b1 JS |
655 | * cpu frequency. Some devious chip manufacturers decided that TSC |
656 | * changes could be handled in software. I decided that time going | |
657 | * backwards might be good for benchmarks, but it's bad for users. | |
658 | * | |
659 | * We also insist that the TSC be stable: the kernel detects unreliable | |
2e04ef76 RR |
660 | * TSCs for its own purposes, and we use that here. |
661 | */ | |
b410e7b1 JS |
662 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC) && !check_tsc_unstable()) |
663 | tsc_speed = tsc_khz; | |
664 | else | |
665 | tsc_speed = 0; | |
382ac6b3 | 666 | if (put_user(tsc_speed, &cpu->lg->lguest_data->tsc_khz)) |
b410e7b1 JS |
667 | return -EFAULT; |
668 | ||
c18acd73 | 669 | /* The interrupt code might not like the system call vector. */ |
382ac6b3 GOC |
670 | if (!check_syscall_vector(cpu->lg)) |
671 | kill_guest(cpu, "bad syscall vector"); | |
c18acd73 | 672 | |
b410e7b1 JS |
673 | return 0; |
674 | } | |
a6bd8e13 | 675 | /*:*/ |
d612cde0 | 676 | |
2e04ef76 | 677 | /*L:030 |
d612cde0 | 678 | * Most of the Guest's registers are left alone: we used get_zeroed_page() to |
2e04ef76 RR |
679 | * allocate the structure, so they will be 0. |
680 | */ | |
a53a35a8 | 681 | void lguest_arch_setup_regs(struct lg_cpu *cpu, unsigned long start) |
d612cde0 | 682 | { |
a53a35a8 | 683 | struct lguest_regs *regs = cpu->regs; |
d612cde0 | 684 | |
2e04ef76 RR |
685 | /* |
686 | * There are four "segment" registers which the Guest needs to boot: | |
d612cde0 JS |
687 | * The "code segment" register (cs) refers to the kernel code segment |
688 | * __KERNEL_CS, and the "data", "extra" and "stack" segment registers | |
689 | * refer to the kernel data segment __KERNEL_DS. | |
690 | * | |
691 | * The privilege level is packed into the lower bits. The Guest runs | |
2e04ef76 RR |
692 | * at privilege level 1 (GUEST_PL). |
693 | */ | |
d612cde0 JS |
694 | regs->ds = regs->es = regs->ss = __KERNEL_DS|GUEST_PL; |
695 | regs->cs = __KERNEL_CS|GUEST_PL; | |
696 | ||
2e04ef76 RR |
697 | /* |
698 | * The "eflags" register contains miscellaneous flags. Bit 1 (0x002) | |
d612cde0 JS |
699 | * is supposed to always be "1". Bit 9 (0x200) controls whether |
700 | * interrupts are enabled. We always leave interrupts enabled while | |
2e04ef76 RR |
701 | * running the Guest. |
702 | */ | |
1cf8343f | 703 | regs->eflags = X86_EFLAGS_IF | X86_EFLAGS_BIT1; |
d612cde0 | 704 | |
2e04ef76 RR |
705 | /* |
706 | * The "Extended Instruction Pointer" register says where the Guest is | |
707 | * running. | |
708 | */ | |
d612cde0 JS |
709 | regs->eip = start; |
710 | ||
2e04ef76 RR |
711 | /* |
712 | * %esi points to our boot information, at physical address 0, so don't | |
713 | * touch it. | |
714 | */ | |
e1e72965 | 715 | |
2e04ef76 | 716 | /* There are a couple of GDT entries the Guest expects at boot. */ |
fc708b3e | 717 | setup_guest_gdt(cpu); |
d612cde0 | 718 | } |