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2819639b PB |
1 | /* This file is part of linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III |
2 | * | |
3 | * register descriptions | |
4 | * | |
5 | * see flexcop.c for copyright information. | |
6 | */ | |
7 | ||
8 | /* This file is automatically generated, do not edit things here. */ | |
9 | #ifndef __FLEXCOP_IBI_VALUE_INCLUDED__ | |
10 | #define __FLEXCOP_IBI_VALUE_INCLUDED__ | |
11 | ||
12 | typedef union { | |
13 | u32 raw; | |
14 | ||
15 | struct { | |
16 | u32 dma_0start : 1; | |
17 | u32 dma_0No_update : 1; | |
18 | u32 dma_address0 :30; | |
19 | } dma_0x0; | |
20 | ||
21 | struct { | |
22 | u32 DMA_maxpackets : 8; | |
23 | u32 dma_addr_size :24; | |
24 | } dma_0x4_remap; | |
25 | ||
26 | struct { | |
27 | u32 dma1timer : 7; | |
28 | u32 unused : 1; | |
29 | u32 dma_addr_size :24; | |
30 | } dma_0x4_read; | |
31 | ||
32 | struct { | |
33 | u32 unused : 1; | |
34 | u32 dmatimer : 7; | |
35 | u32 dma_addr_size :24; | |
36 | } dma_0x4_write; | |
37 | ||
38 | struct { | |
39 | u32 unused : 2; | |
40 | u32 dma_cur_addr :30; | |
41 | } dma_0x8; | |
42 | ||
43 | struct { | |
44 | u32 dma_1start : 1; | |
45 | u32 remap_enable : 1; | |
46 | u32 dma_address1 :30; | |
47 | } dma_0xc; | |
48 | ||
49 | struct { | |
50 | u32 chipaddr : 7; | |
51 | u32 reserved1 : 1; | |
52 | u32 baseaddr : 8; | |
53 | u32 data1_reg : 8; | |
54 | u32 working_start : 1; | |
55 | u32 twoWS_rw : 1; | |
56 | u32 total_bytes : 2; | |
57 | u32 twoWS_port_reg : 2; | |
58 | u32 no_base_addr_ack_error : 1; | |
59 | u32 st_done : 1; | |
60 | } tw_sm_c_100; | |
61 | ||
62 | struct { | |
63 | u32 data2_reg : 8; | |
64 | u32 data3_reg : 8; | |
65 | u32 data4_reg : 8; | |
66 | u32 exlicit_stops : 1; | |
67 | u32 force_stop : 1; | |
68 | u32 unused : 6; | |
69 | } tw_sm_c_104; | |
70 | ||
71 | struct { | |
72 | u32 thi1 : 6; | |
73 | u32 reserved1 : 2; | |
74 | u32 tlo1 : 5; | |
75 | u32 reserved2 :19; | |
76 | } tw_sm_c_108; | |
77 | ||
78 | struct { | |
79 | u32 thi1 : 6; | |
80 | u32 reserved1 : 2; | |
81 | u32 tlo1 : 5; | |
82 | u32 reserved2 :19; | |
83 | } tw_sm_c_10c; | |
84 | ||
85 | struct { | |
86 | u32 thi1 : 6; | |
87 | u32 reserved1 : 2; | |
88 | u32 tlo1 : 5; | |
89 | u32 reserved2 :19; | |
90 | } tw_sm_c_110; | |
91 | ||
92 | struct { | |
93 | u32 LNB_CTLHighCount_sig :15; | |
94 | u32 LNB_CTLLowCount_sig :15; | |
95 | u32 LNB_CTLPrescaler_sig : 2; | |
96 | } lnb_switch_freq_200; | |
97 | ||
98 | struct { | |
99 | u32 ACPI1_sig : 1; | |
100 | u32 ACPI3_sig : 1; | |
101 | u32 LNB_L_H_sig : 1; | |
102 | u32 Per_reset_sig : 1; | |
103 | u32 reserved :20; | |
104 | u32 Rev_N_sig_revision_hi : 4; | |
105 | u32 Rev_N_sig_reserved1 : 2; | |
106 | u32 Rev_N_sig_caps : 1; | |
107 | u32 Rev_N_sig_reserved2 : 1; | |
108 | } misc_204; | |
109 | ||
110 | struct { | |
111 | u32 Stream1_filter_sig : 1; | |
112 | u32 Stream2_filter_sig : 1; | |
113 | u32 PCR_filter_sig : 1; | |
114 | u32 PMT_filter_sig : 1; | |
115 | u32 EMM_filter_sig : 1; | |
116 | u32 ECM_filter_sig : 1; | |
117 | u32 Null_filter_sig : 1; | |
118 | u32 Mask_filter_sig : 1; | |
119 | u32 WAN_Enable_sig : 1; | |
120 | u32 WAN_CA_Enable_sig : 1; | |
121 | u32 CA_Enable_sig : 1; | |
122 | u32 SMC_Enable_sig : 1; | |
123 | u32 Per_CA_Enable_sig : 1; | |
124 | u32 Multi2_Enable_sig : 1; | |
125 | u32 MAC_filter_Mode_sig : 1; | |
126 | u32 Rcv_Data_sig : 1; | |
127 | u32 DMA1_IRQ_Enable_sig : 1; | |
128 | u32 DMA1_Timer_Enable_sig : 1; | |
129 | u32 DMA2_IRQ_Enable_sig : 1; | |
130 | u32 DMA2_Timer_Enable_sig : 1; | |
131 | u32 DMA1_Size_IRQ_Enable_sig : 1; | |
132 | u32 DMA2_Size_IRQ_Enable_sig : 1; | |
133 | u32 Mailbox_from_V8_Enable_sig : 1; | |
134 | u32 unused : 9; | |
135 | } ctrl_208; | |
136 | ||
137 | struct { | |
138 | u32 DMA1_IRQ_Status : 1; | |
139 | u32 DMA1_Timer_Status : 1; | |
140 | u32 DMA2_IRQ_Status : 1; | |
141 | u32 DMA2_Timer_Status : 1; | |
142 | u32 DMA1_Size_IRQ_Status : 1; | |
143 | u32 DMA2_Size_IRQ_Status : 1; | |
144 | u32 Mailbox_from_V8_Status_sig : 1; | |
145 | u32 Data_receiver_error : 1; | |
146 | u32 Continuity_error_flag : 1; | |
147 | u32 LLC_SNAP_FLAG_set : 1; | |
148 | u32 Transport_Error : 1; | |
149 | u32 reserved :21; | |
150 | } irq_20c; | |
151 | ||
152 | struct { | |
64221be7 PB |
153 | u32 reset_block_000 : 1; |
154 | u32 reset_block_100 : 1; | |
155 | u32 reset_block_200 : 1; | |
156 | u32 reset_block_300 : 1; | |
157 | u32 reset_block_400 : 1; | |
158 | u32 reset_block_500 : 1; | |
159 | u32 reset_block_600 : 1; | |
160 | u32 reset_block_700 : 1; | |
2819639b PB |
161 | u32 Block_reset_enable : 8; |
162 | u32 Special_controls :16; | |
163 | } sw_reset_210; | |
164 | ||
165 | struct { | |
166 | u32 vuart_oe_sig : 1; | |
167 | u32 v2WS_oe_sig : 1; | |
168 | u32 halt_V8_sig : 1; | |
169 | u32 section_pkg_enable_sig : 1; | |
170 | u32 s2p_sel_sig : 1; | |
171 | u32 unused1 : 3; | |
172 | u32 polarity_PS_CLK_sig : 1; | |
173 | u32 polarity_PS_VALID_sig : 1; | |
174 | u32 polarity_PS_SYNC_sig : 1; | |
175 | u32 polarity_PS_ERR_sig : 1; | |
176 | u32 unused2 :20; | |
177 | } misc_214; | |
178 | ||
179 | struct { | |
180 | u32 Mailbox_from_V8 :32; | |
181 | } mbox_v8_to_host_218; | |
182 | ||
183 | struct { | |
184 | u32 sysramaccess_data : 8; | |
185 | u32 sysramaccess_addr :15; | |
186 | u32 unused : 7; | |
187 | u32 sysramaccess_write : 1; | |
188 | u32 sysramaccess_busmuster : 1; | |
189 | } mbox_host_to_v8_21c; | |
190 | ||
191 | struct { | |
192 | u32 Stream1_PID :13; | |
193 | u32 Stream1_trans : 1; | |
194 | u32 MAC_Multicast_filter : 1; | |
195 | u32 debug_flag_pid_saved : 1; | |
196 | u32 Stream2_PID :13; | |
197 | u32 Stream2_trans : 1; | |
198 | u32 debug_flag_write_status00 : 1; | |
199 | u32 debug_fifo_problem : 1; | |
200 | } pid_filter_300; | |
201 | ||
202 | struct { | |
203 | u32 PCR_PID :13; | |
204 | u32 PCR_trans : 1; | |
205 | u32 debug_overrun3 : 1; | |
206 | u32 debug_overrun2 : 1; | |
207 | u32 PMT_PID :13; | |
208 | u32 PMT_trans : 1; | |
209 | u32 reserved : 2; | |
210 | } pid_filter_304; | |
211 | ||
212 | struct { | |
213 | u32 EMM_PID :13; | |
214 | u32 EMM_trans : 1; | |
215 | u32 EMM_filter_4 : 1; | |
216 | u32 EMM_filter_6 : 1; | |
217 | u32 ECM_PID :13; | |
218 | u32 ECM_trans : 1; | |
219 | u32 reserved : 2; | |
220 | } pid_filter_308; | |
221 | ||
222 | struct { | |
223 | u32 Group_PID :13; | |
224 | u32 Group_trans : 1; | |
225 | u32 unused1 : 2; | |
226 | u32 Group_mask :13; | |
227 | u32 unused2 : 3; | |
228 | } pid_filter_30c_ext_ind_0_7; | |
229 | ||
230 | struct { | |
231 | u32 net_master_read :17; | |
232 | u32 unused :15; | |
233 | } pid_filter_30c_ext_ind_1; | |
234 | ||
235 | struct { | |
236 | u32 net_master_write :17; | |
237 | u32 unused :15; | |
238 | } pid_filter_30c_ext_ind_2; | |
239 | ||
240 | struct { | |
241 | u32 next_net_master_write :17; | |
242 | u32 unused :15; | |
243 | } pid_filter_30c_ext_ind_3; | |
244 | ||
245 | struct { | |
246 | u32 unused1 : 1; | |
247 | u32 state_write :10; | |
248 | u32 reserved1 : 6; | |
249 | u32 stack_read :10; | |
250 | u32 reserved2 : 5; | |
251 | } pid_filter_30c_ext_ind_4; | |
252 | ||
253 | struct { | |
254 | u32 stack_cnt :10; | |
255 | u32 unused :22; | |
256 | } pid_filter_30c_ext_ind_5; | |
257 | ||
258 | struct { | |
259 | u32 pid_fsm_save_reg0 : 2; | |
260 | u32 pid_fsm_save_reg1 : 2; | |
261 | u32 pid_fsm_save_reg2 : 2; | |
262 | u32 pid_fsm_save_reg3 : 2; | |
263 | u32 pid_fsm_save_reg4 : 2; | |
264 | u32 pid_fsm_save_reg300 : 2; | |
265 | u32 write_status1 : 2; | |
266 | u32 write_status4 : 2; | |
267 | u32 data_size_reg :12; | |
268 | u32 unused : 4; | |
269 | } pid_filter_30c_ext_ind_6; | |
270 | ||
271 | struct { | |
272 | u32 index_reg : 5; | |
273 | u32 extra_index_reg : 3; | |
274 | u32 AB_select : 1; | |
275 | u32 pass_alltables : 1; | |
276 | u32 unused :22; | |
277 | } index_reg_310; | |
278 | ||
279 | struct { | |
280 | u32 PID :13; | |
281 | u32 PID_trans : 1; | |
282 | u32 PID_enable_bit : 1; | |
283 | u32 reserved :17; | |
284 | } pid_n_reg_314; | |
285 | ||
286 | struct { | |
287 | u32 A4_byte : 8; | |
288 | u32 A5_byte : 8; | |
289 | u32 A6_byte : 8; | |
290 | u32 Enable_bit : 1; | |
291 | u32 HighAB_bit : 1; | |
292 | u32 reserved : 6; | |
293 | } mac_low_reg_318; | |
294 | ||
295 | struct { | |
296 | u32 A1_byte : 8; | |
297 | u32 A2_byte : 8; | |
298 | u32 A3_byte : 8; | |
299 | u32 reserved : 8; | |
300 | } mac_high_reg_31c; | |
301 | ||
302 | struct { | |
303 | u32 reserved :16; | |
304 | u32 data_Tag_ID :16; | |
305 | } data_tag_400; | |
306 | ||
307 | struct { | |
308 | u32 Card_IDbyte6 : 8; | |
309 | u32 Card_IDbyte5 : 8; | |
310 | u32 Card_IDbyte4 : 8; | |
311 | u32 Card_IDbyte3 : 8; | |
312 | } card_id_408; | |
313 | ||
314 | struct { | |
315 | u32 Card_IDbyte2 : 8; | |
316 | u32 Card_IDbyte1 : 8; | |
317 | } card_id_40c; | |
318 | ||
319 | struct { | |
320 | u32 MAC1 : 8; | |
321 | u32 MAC2 : 8; | |
322 | u32 MAC3 : 8; | |
323 | u32 MAC6 : 8; | |
324 | } mac_address_418; | |
325 | ||
326 | struct { | |
327 | u32 MAC7 : 8; | |
328 | u32 MAC8 : 8; | |
329 | u32 reserved :16; | |
330 | } mac_address_41c; | |
331 | ||
332 | struct { | |
333 | u32 transmitter_data_byte : 8; | |
334 | u32 ReceiveDataReady : 1; | |
335 | u32 ReceiveByteFrameError : 1; | |
336 | u32 txbuffempty : 1; | |
337 | u32 reserved :21; | |
338 | } ci_600; | |
339 | ||
340 | struct { | |
341 | u32 pi_d : 8; | |
342 | u32 pi_ha :20; | |
343 | u32 pi_rw : 1; | |
344 | u32 pi_component_reg : 3; | |
345 | } pi_604; | |
346 | ||
347 | struct { | |
348 | u32 serialReset : 1; | |
349 | u32 oncecycle_read : 1; | |
350 | u32 Timer_Read_req : 1; | |
351 | u32 Timer_Load_req : 1; | |
352 | u32 timer_data : 7; | |
353 | u32 unused : 1; | |
354 | u32 Timer_addr : 5; | |
355 | u32 reserved : 3; | |
356 | u32 pcmcia_a_mod_pwr_n : 1; | |
357 | u32 pcmcia_b_mod_pwr_n : 1; | |
358 | u32 config_Done_stat : 1; | |
359 | u32 config_Init_stat : 1; | |
360 | u32 config_Prog_n : 1; | |
361 | u32 config_wr_n : 1; | |
362 | u32 config_cs_n : 1; | |
363 | u32 config_cclk : 1; | |
364 | u32 pi_CiMax_IRQ_n : 1; | |
365 | u32 pi_timeout_status : 1; | |
366 | u32 pi_wait_n : 1; | |
367 | u32 pi_busy_n : 1; | |
368 | } pi_608; | |
369 | ||
370 | struct { | |
371 | u32 PID :13; | |
372 | u32 key_enable : 1; | |
373 | u32 key_code : 2; | |
374 | u32 key_array_col : 3; | |
375 | u32 key_array_row : 5; | |
376 | u32 dvb_en : 1; | |
377 | u32 rw_flag : 1; | |
378 | u32 reserved : 6; | |
379 | } dvb_reg_60c; | |
380 | ||
381 | struct { | |
382 | u32 sram_addr :15; | |
383 | u32 sram_rw : 1; | |
384 | u32 sram_data : 8; | |
385 | u32 sc_xfer_bit : 1; | |
386 | u32 reserved1 : 3; | |
387 | u32 oe_pin_reg : 1; | |
388 | u32 ce_pin_reg : 1; | |
389 | u32 reserved2 : 1; | |
390 | u32 start_sram_ibi : 1; | |
391 | } sram_ctrl_reg_700; | |
392 | ||
393 | struct { | |
394 | u32 net_addr_read :16; | |
395 | u32 net_addr_write :16; | |
396 | } net_buf_reg_704; | |
397 | ||
398 | struct { | |
399 | u32 cai_read :11; | |
400 | u32 reserved1 : 5; | |
401 | u32 cai_write :11; | |
402 | u32 reserved2 : 6; | |
403 | u32 cai_cnt : 4; | |
404 | } cai_buf_reg_708; | |
405 | ||
406 | struct { | |
407 | u32 cao_read :11; | |
408 | u32 reserved1 : 5; | |
409 | u32 cap_write :11; | |
410 | u32 reserved2 : 6; | |
411 | u32 cao_cnt : 4; | |
412 | } cao_buf_reg_70c; | |
413 | ||
414 | struct { | |
415 | u32 media_read :11; | |
416 | u32 reserved1 : 5; | |
417 | u32 media_write :11; | |
418 | u32 reserved2 : 6; | |
419 | u32 media_cnt : 4; | |
420 | } media_buf_reg_710; | |
421 | ||
422 | struct { | |
423 | u32 NET_Dest : 2; | |
424 | u32 CAI_Dest : 2; | |
425 | u32 CAO_Dest : 2; | |
426 | u32 MEDIA_Dest : 2; | |
427 | u32 net_ovflow_error : 1; | |
428 | u32 media_ovflow_error : 1; | |
429 | u32 cai_ovflow_error : 1; | |
430 | u32 cao_ovflow_error : 1; | |
431 | u32 ctrl_usb_wan : 1; | |
432 | u32 ctrl_sramdma : 1; | |
433 | u32 ctrl_maximumfill : 1; | |
434 | u32 reserved :17; | |
435 | } sram_dest_reg_714; | |
436 | ||
437 | struct { | |
438 | u32 net_cnt :12; | |
439 | u32 reserved1 : 4; | |
440 | u32 net_addr_read : 1; | |
441 | u32 reserved2 : 3; | |
442 | u32 net_addr_write : 1; | |
443 | u32 reserved3 :11; | |
444 | } net_buf_reg_718; | |
445 | ||
446 | struct { | |
447 | u32 wan_speed_sig : 2; | |
448 | u32 reserved1 : 6; | |
449 | u32 wan_wait_state : 8; | |
450 | u32 sram_chip : 2; | |
451 | u32 sram_memmap : 2; | |
452 | u32 reserved2 : 4; | |
453 | u32 wan_pkt_frame : 4; | |
454 | u32 reserved3 : 4; | |
455 | } wan_ctrl_reg_71c; | |
456 | } flexcop_ibi_value; | |
457 | ||
458 | #endif |