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switch device_get_devnode() and ->devnode() to umode_t *
[deliverable/linux.git] / drivers / media / dvb / ddbridge / ddbridge-core.c
CommitLineData
ccad0457
RM		 1/*
2 * ddbridge.c: Digital Devices PCIe bridge driver
3 *
4 * Copyright (C) 2010-2011 Digital Devices GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/slab.h>
29#include <linux/poll.h>
28d45a5d 30#include <linux/io.h>
ccad0457
RM		 31#include <linux/pci.h>
32#include <linux/pci_ids.h>
33#include <linux/timer.h>
34#include <linux/version.h>
35#include <linux/i2c.h>
36#include <linux/swab.h>
37#include <linux/vmalloc.h>
38#include "ddbridge.h"
39
40#include "ddbridge-regs.h"
41
42#include "tda18271c2dd.h"
43#include "stv6110x.h"
44#include "stv090x.h"
45#include "lnbh24.h"
46#include "drxk.h"
47
48DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
49
50/* MSI had problems with lost interrupts, fixed but needs testing */
51#undef CONFIG_PCI_MSI
52
53/******************************************************************************/
54
55static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
56{
57 struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
4f1f3107 58 .buf = val, .len = 1 } };
ccad0457
RM		 59 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
60}
61
62static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val)
63{
64 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
65 .buf = &reg, .len = 1 },
66 {.addr = adr, .flags = I2C_M_RD,
4f1f3107 67 .buf = val, .len = 1 } };
ccad0457
RM		 68 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
69}
70
71static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr,
72 u16 reg, u8 *val)
73{
74 u8 msg[2] = {reg>>8, reg&0xff};
75 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
76 .buf = msg, .len = 2},
77 {.addr = adr, .flags = I2C_M_RD,
4f1f3107 78 .buf = val, .len = 1} };
ccad0457
RM		 79 return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
80}
81
82static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
83{
84 struct ddb *dev = i2c->dev;
85 int stat;
86 u32 val;
87
88 i2c->done = 0;
89 ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND);
90 stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ);
91 if (stat <= 0) {
4f1f3107 92 printk(KERN_ERR "I2C timeout\n");
ccad0457
RM		 93 { /* MSI debugging*/
94 u32 istat = ddbreadl(INTERRUPT_STATUS);
4f1f3107 95 printk(KERN_ERR "IRS %08x\n", istat);
ccad0457
RM		 96 ddbwritel(istat, INTERRUPT_ACK);
97 }
98 return -EIO;
99 }
4f1f3107 100 val = ddbreadl(i2c->regs+I2C_COMMAND);
ccad0457
RM		 101 if (val & 0x70000)
102 return -EIO;
103 return 0;
104}
105
106static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
107 struct i2c_msg msg[], int num)
108{
109 struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter);
110 struct ddb *dev = i2c->dev;
4f1f3107 111 u8 addr = 0;
ccad0457
RM		 112
113 if (num)
114 addr = msg[0].addr;
115
116 if (num == 2 && msg[1].flags & I2C_M_RD &&
117 !(msg[0].flags & I2C_M_RD)) {
118 memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf,
4f1f3107 119 msg[0].buf, msg[0].len);
ccad0457
RM		 120 ddbwritel(msg[0].len|(msg[1].len << 16),
121 i2c->regs+I2C_TASKLENGTH);
122 if (!ddb_i2c_cmd(i2c, addr, 1)) {
123 memcpy_fromio(msg[1].buf,
124 dev->regs + I2C_TASKMEM_BASE + i2c->rbuf,
125 msg[1].len);
126 return num;
127 }
128 }
129
130 if (num == 1 && !(msg[0].flags & I2C_M_RD)) {
4f1f3107 131 ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len);
ccad0457
RM		 132 ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH);
133 if (!ddb_i2c_cmd(i2c, addr, 2))
134 return num;
135 }
136 if (num == 1 && (msg[0].flags & I2C_M_RD)) {
137 ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH);
138 if (!ddb_i2c_cmd(i2c, addr, 3)) {
139 ddbcpyfrom(msg[0].buf,
140 I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len);
141 return num;
142 }
143 }
144 return -EIO;
145}
146
147
148static u32 ddb_i2c_functionality(struct i2c_adapter *adap)
149{
150 return I2C_FUNC_SMBUS_EMUL;
151}
152
153struct i2c_algorithm ddb_i2c_algo = {
154 .master_xfer = ddb_i2c_master_xfer,
155 .functionality = ddb_i2c_functionality,
156};
157
158static void ddb_i2c_release(struct ddb *dev)
159{
160 int i;
161 struct ddb_i2c *i2c;
162 struct i2c_adapter *adap;
163
164 for (i = 0; i < dev->info->port_num; i++) {
165 i2c = &dev->i2c[i];
166 adap = &i2c->adap;
167 i2c_del_adapter(adap);
168 }
169}
170
171static int ddb_i2c_init(struct ddb *dev)
172{
173 int i, j, stat = 0;
174 struct ddb_i2c *i2c;
175 struct i2c_adapter *adap;
176
177 for (i = 0; i < dev->info->port_num; i++) {
178 i2c = &dev->i2c[i];
179 i2c->dev = dev;
180 i2c->nr = i;
181 i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4);
182 i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8);
183 i2c->regs = 0x80 + i * 0x20;
184 ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING);
185 ddbwritel((i2c->rbuf << 16) | i2c->wbuf,
186 i2c->regs + I2C_TASKADDRESS);
187 init_waitqueue_head(&i2c->wq);
188
189 adap = &i2c->adap;
190 i2c_set_adapdata(adap, i2c);
191#ifdef I2C_ADAP_CLASS_TV_DIGITAL
192 adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG;
193#else
194#ifdef I2C_CLASS_TV_ANALOG
195 adap->class = I2C_CLASS_TV_ANALOG;
196#endif
197#endif
198 strcpy(adap->name, "ddbridge");
199 adap->algo = &ddb_i2c_algo;
200 adap->algo_data = (void *)i2c;
201 adap->dev.parent = &dev->pdev->dev;
202 stat = i2c_add_adapter(adap);
203 if (stat)
204 break;
205 }
206 if (stat)
207 for (j = 0; j < i; j++) {
208 i2c = &dev->i2c[j];
209 adap = &i2c->adap;
210 i2c_del_adapter(adap);
211 }
212 return stat;
213}
214
215
216/******************************************************************************/
217/******************************************************************************/
218/******************************************************************************/
219
4f1f3107 220#if 0
ccad0457
RM		 221static void set_table(struct ddb *dev, u32 off,
222 dma_addr_t *pbuf, u32 num)
223{
224 u32 i, base;
225 u64 mem;
226
227 base = DMA_BASE_ADDRESS_TABLE + off;
228 for (i = 0; i < num; i++) {
229 mem = pbuf[i];
230 ddbwritel(mem & 0xffffffff, base + i * 8);
231 ddbwritel(mem >> 32, base + i * 8 + 4);
232 }
233}
4f1f3107 234#endif
ccad0457
RM		 235
236static void ddb_address_table(struct ddb *dev)
237{
238 u32 i, j, base;
239 u64 mem;
240 dma_addr_t *pbuf;
241
242 for (i = 0; i < dev->info->port_num * 2; i++) {
243 base = DMA_BASE_ADDRESS_TABLE + i * 0x100;
244 pbuf = dev->input[i].pbuf;
245 for (j = 0; j < dev->input[i].dma_buf_num; j++) {
246 mem = pbuf[j];
247 ddbwritel(mem & 0xffffffff, base + j * 8);
248 ddbwritel(mem >> 32, base + j * 8 + 4);
249 }
250 }
251 for (i = 0; i < dev->info->port_num; i++) {
252 base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100;
253 pbuf = dev->output[i].pbuf;
254 for (j = 0; j < dev->output[i].dma_buf_num; j++) {
255 mem = pbuf[j];
256 ddbwritel(mem & 0xffffffff, base + j * 8);
257 ddbwritel(mem >> 32, base + j * 8 + 4);
258 }
259 }
260}
261
262static void io_free(struct pci_dev *pdev, u8 **vbuf,
263 dma_addr_t *pbuf, u32 size, int num)
264{
265 int i;
266
267 for (i = 0; i < num; i++) {
268 if (vbuf[i]) {
269 pci_free_consistent(pdev, size, vbuf[i], pbuf[i]);
270 vbuf[i] = 0;
271 }
272 }
273}
274
275static int io_alloc(struct pci_dev *pdev, u8 **vbuf,
276 dma_addr_t *pbuf, u32 size, int num)
277{
278 int i;
279
280 for (i = 0; i < num; i++) {
281 vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]);
282 if (!vbuf[i])
283 return -ENOMEM;
284 }
285 return 0;
286}
287
288static int ddb_buffers_alloc(struct ddb *dev)
289{
290 int i;
291 struct ddb_port *port;
292
293 for (i = 0; i < dev->info->port_num; i++) {
294 port = &dev->port[i];
295 switch (port->class) {
296 case DDB_PORT_TUNER:
297 if (io_alloc(dev->pdev, port->input[0]->vbuf,
298 port->input[0]->pbuf,
299 port->input[0]->dma_buf_size,
300 port->input[0]->dma_buf_num) < 0)
301 return -1;
302 if (io_alloc(dev->pdev, port->input[1]->vbuf,
303 port->input[1]->pbuf,
304 port->input[1]->dma_buf_size,
305 port->input[1]->dma_buf_num) < 0)
306 return -1;
307 break;
308 case DDB_PORT_CI:
309 if (io_alloc(dev->pdev, port->input[0]->vbuf,
310 port->input[0]->pbuf,
311 port->input[0]->dma_buf_size,
312 port->input[0]->dma_buf_num) < 0)
313 return -1;
314 if (io_alloc(dev->pdev, port->output->vbuf,
315 port->output->pbuf,
316 port->output->dma_buf_size,
317 port->output->dma_buf_num) < 0)
318 return -1;
319 break;
320 default:
321 break;
322 }
323 }
324 ddb_address_table(dev);
325 return 0;
326}
327
328static void ddb_buffers_free(struct ddb *dev)
329{
330 int i;
331 struct ddb_port *port;
332
333 for (i = 0; i < dev->info->port_num; i++) {
334 port = &dev->port[i];
335 io_free(dev->pdev, port->input[0]->vbuf,
336 port->input[0]->pbuf,
337 port->input[0]->dma_buf_size,
338 port->input[0]->dma_buf_num);
339 io_free(dev->pdev, port->input[1]->vbuf,
340 port->input[1]->pbuf,
341 port->input[1]->dma_buf_size,
342 port->input[1]->dma_buf_num);
343 io_free(dev->pdev, port->output->vbuf,
344 port->output->pbuf,
345 port->output->dma_buf_size,
346 port->output->dma_buf_num);
347 }
348}
349
350static void ddb_input_start(struct ddb_input *input)
351{
352 struct ddb *dev = input->port->dev;
353
354 spin_lock_irq(&input->lock);
355 input->cbuf = 0;
356 input->coff = 0;
357
358 /* reset */
359 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
360 ddbwritel(2, TS_INPUT_CONTROL(input->nr));
361 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
362
363 ddbwritel((1 << 16) |
364 (input->dma_buf_num << 11) |
365 (input->dma_buf_size >> 7),
366 DMA_BUFFER_SIZE(input->nr));
367 ddbwritel(0, DMA_BUFFER_ACK(input->nr));
368
369 ddbwritel(1, DMA_BASE_WRITE);
370 ddbwritel(3, DMA_BUFFER_CONTROL(input->nr));
371 ddbwritel(9, TS_INPUT_CONTROL(input->nr));
372 input->running = 1;
373 spin_unlock_irq(&input->lock);
374}
375
376static void ddb_input_stop(struct ddb_input *input)
377{
378 struct ddb *dev = input->port->dev;
379
380 spin_lock_irq(&input->lock);
381 ddbwritel(0, TS_INPUT_CONTROL(input->nr));
382 ddbwritel(0, DMA_BUFFER_CONTROL(input->nr));
383 input->running = 0;
384 spin_unlock_irq(&input->lock);
385}
386
387static void ddb_output_start(struct ddb_output *output)
388{
389 struct ddb *dev = output->port->dev;
390
391 spin_lock_irq(&output->lock);
392 output->cbuf = 0;
393 output->coff = 0;
394 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
395 ddbwritel(2, TS_OUTPUT_CONTROL(output->nr));
396 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
397 ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr));
398 ddbwritel((1 << 16) |
399 (output->dma_buf_num << 11) |
400 (output->dma_buf_size >> 7),
401 DMA_BUFFER_SIZE(output->nr + 8));
402 ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8));
403
404 ddbwritel(1, DMA_BASE_READ);
405 ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8));
4f1f3107 406 /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */
ccad0457
RM		 407 ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr));
408 output->running = 1;
409 spin_unlock_irq(&output->lock);
410}
411
412static void ddb_output_stop(struct ddb_output *output)
413{
414 struct ddb *dev = output->port->dev;
415
416 spin_lock_irq(&output->lock);
417 ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
418 ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8));
419 output->running = 0;
420 spin_unlock_irq(&output->lock);
421}
422
423static u32 ddb_output_free(struct ddb_output *output)
424{
425 u32 idx, off, stat = output->stat;
426 s32 diff;
427
428 idx = (stat >> 11) & 0x1f;
429 off = (stat & 0x7ff) << 7;
430
431 if (output->cbuf != idx) {
432 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
433 (output->dma_buf_size - output->coff <= 188))
434 return 0;
435 return 188;
436 }
437 diff = off - output->coff;
438 if (diff <= 0 || diff > 188)
439 return 188;
440 return 0;
441}
442
4f1f3107 443static ssize_t ddb_output_write(struct ddb_output *output,
ccad0457
RM		 444 const u8 *buf, size_t count)
445{
446 struct ddb *dev = output->port->dev;
447 u32 idx, off, stat = output->stat;
448 u32 left = count, len;
449
450 idx = (stat >> 11) & 0x1f;
451 off = (stat & 0x7ff) << 7;
452
453 while (left) {
454 len = output->dma_buf_size - output->coff;
455 if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
456 (off == 0)) {
4f1f3107 457 if (len <= 188)
ccad0457 458 break;
4f1f3107 459 len -= 188;
ccad0457
RM		 460 }
461 if (output->cbuf == idx) {
462 if (off > output->coff) {
463#if 1
464 len = off - output->coff;
465 len -= (len % 188);
466 if (len <= 188)
467
468#endif
469 break;
470 len -= 188;
471 }
472 }
473 if (len > left)
474 len = left;
475 if (copy_from_user(output->vbuf[output->cbuf] + output->coff,
476 buf, len))
477 return -EIO;
478 left -= len;
479 buf += len;
480 output->coff += len;
481 if (output->coff == output->dma_buf_size) {
482 output->coff = 0;
483 output->cbuf = ((output->cbuf + 1) % output->dma_buf_num);
484 }
485 ddbwritel((output->cbuf << 11) | (output->coff >> 7),
486 DMA_BUFFER_ACK(output->nr + 8));
487 }
488 return count - left;
489}
490
491static u32 ddb_input_avail(struct ddb_input *input)
492{
493 struct ddb *dev = input->port->dev;
494 u32 idx, off, stat = input->stat;
495 u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr));
496
497 idx = (stat >> 11) & 0x1f;
498 off = (stat & 0x7ff) << 7;
499
500 if (ctrl & 4) {
4f1f3107 501 printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl);
ccad0457
RM		 502 ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr));
503 return 0;
504 }
505 if (input->cbuf != idx)
506 return 188;
507 return 0;
508}
509
2122eaf6 510static ssize_t ddb_input_read(struct ddb_input *input, u8 *buf, size_t count)
ccad0457
RM		 511{
512 struct ddb *dev = input->port->dev;
513 u32 left = count;
2122eaf6 514 u32 idx, free, stat = input->stat;
ccad0457
RM		 515 int ret;
516
517 idx = (stat >> 11) & 0x1f;
ccad0457
RM		 518
519 while (left) {
520 if (input->cbuf == idx)
521 return count - left;
522 free = input->dma_buf_size - input->coff;
523 if (free > left)
524 free = left;
525 ret = copy_to_user(buf, input->vbuf[input->cbuf] +
526 input->coff, free);
2122eaf6
HV		 527 if (ret)
528 return -EFAULT;
ccad0457
RM		 529 input->coff += free;
530 if (input->coff == input->dma_buf_size) {
531 input->coff = 0;
532 input->cbuf = (input->cbuf+1) % input->dma_buf_num;
533 }
534 left -= free;
535 ddbwritel((input->cbuf << 11) | (input->coff >> 7),
536 DMA_BUFFER_ACK(input->nr));
537 }
538 return count;
539}
540
541/******************************************************************************/
542/******************************************************************************/
543/******************************************************************************/
544
545#if 0
546static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe)
547{
548 int i;
549
550 for (i = 0; i < dev->info->port_num * 2; i++) {
4f1f3107 551 if (dev->input[i].fe == fe)
ccad0457
RM		 552 return &dev->input[i];
553 }
554 return NULL;
555}
556#endif
557
558static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
559{
560 struct ddb_input *input = fe->sec_priv;
561 struct ddb_port *port = input->port;
562 int status;
563
564 if (enable) {
565 mutex_lock(&port->i2c_gate_lock);
566 status = input->gate_ctrl(fe, 1);
567 } else {
568 status = input->gate_ctrl(fe, 0);
569 mutex_unlock(&port->i2c_gate_lock);
570 }
571 return status;
572}
573
574static int demod_attach_drxk(struct ddb_input *input)
575{
576 struct i2c_adapter *i2c = &input->port->i2c->adap;
577 struct dvb_frontend *fe;
0fc55e81 578 struct drxk_config config;
ccad0457 579
0fc55e81
MCC		 580 memset(&config, 0, sizeof(config));
581 config.adr = 0x29 + (input->nr & 1);
582
583 fe = input->fe = dvb_attach(drxk_attach, &config, i2c, &input->fe2);
ccad0457 584 if (!input->fe) {
4f1f3107 585 printk(KERN_ERR "No DRXK found!\n");
ccad0457
RM		 586 return -ENODEV;
587 }
588 fe->sec_priv = input;
589 input->gate_ctrl = fe->ops.i2c_gate_ctrl;
590 fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
591 return 0;
592}
593
594static int tuner_attach_tda18271(struct ddb_input *input)
595{
596 struct i2c_adapter *i2c = &input->port->i2c->adap;
597 struct dvb_frontend *fe;
598
599 if (input->fe->ops.i2c_gate_ctrl)
600 input->fe->ops.i2c_gate_ctrl(input->fe, 1);
601 fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60);
602 if (!fe) {
4f1f3107 603 printk(KERN_ERR "No TDA18271 found!\n");
ccad0457
RM		 604 return -ENODEV;
605 }
606 if (input->fe->ops.i2c_gate_ctrl)
607 input->fe->ops.i2c_gate_ctrl(input->fe, 0);
608 return 0;
609}
610
611/******************************************************************************/
612/******************************************************************************/
613/******************************************************************************/
614
615static struct stv090x_config stv0900 = {
616 .device = STV0900,
617 .demod_mode = STV090x_DUAL,
618 .clk_mode = STV090x_CLK_EXT,
619
620 .xtal = 27000000,
621 .address = 0x69,
622
623 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
624 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
625
626 .repeater_level = STV090x_RPTLEVEL_16,
627
628 .adc1_range = STV090x_ADC_1Vpp,
629 .adc2_range = STV090x_ADC_1Vpp,
630
631 .diseqc_envelope_mode = true,
632};
633
634static struct stv090x_config stv0900_aa = {
635 .device = STV0900,
636 .demod_mode = STV090x_DUAL,
637 .clk_mode = STV090x_CLK_EXT,
638
639 .xtal = 27000000,
640 .address = 0x68,
641
642 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
643 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
644
645 .repeater_level = STV090x_RPTLEVEL_16,
646
647 .adc1_range = STV090x_ADC_1Vpp,
648 .adc2_range = STV090x_ADC_1Vpp,
649
650 .diseqc_envelope_mode = true,
651};
652
653static struct stv6110x_config stv6110a = {
654 .addr = 0x60,
655 .refclk = 27000000,
656 .clk_div = 1,
657};
658
659static struct stv6110x_config stv6110b = {
660 .addr = 0x63,
661 .refclk = 27000000,
662 .clk_div = 1,
663};
664
665static int demod_attach_stv0900(struct ddb_input *input, int type)
666{
667 struct i2c_adapter *i2c = &input->port->i2c->adap;
668 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
669
4f1f3107
OE		 670 input->fe = dvb_attach(stv090x_attach, feconf, i2c,
671 (input->nr & 1) ? STV090x_DEMODULATOR_1
672 : STV090x_DEMODULATOR_0);
ccad0457 673 if (!input->fe) {
4f1f3107 674 printk(KERN_ERR "No STV0900 found!\n");
ccad0457
RM		 675 return -ENODEV;
676 }
677 if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0,
678 0, (input->nr & 1) ?
679 (0x09 - type) : (0x0b - type))) {
4f1f3107 680 printk(KERN_ERR "No LNBH24 found!\n");
ccad0457
RM		 681 return -ENODEV;
682 }
683 return 0;
684}
685
686static int tuner_attach_stv6110(struct ddb_input *input, int type)
687{
688 struct i2c_adapter *i2c = &input->port->i2c->adap;
689 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
690 struct stv6110x_config *tunerconf = (input->nr & 1) ?
691 &stv6110b : &stv6110a;
692 struct stv6110x_devctl *ctl;
693
694 ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c);
695 if (!ctl) {
4f1f3107 696 printk(KERN_ERR "No STV6110X found!\n");
ccad0457
RM		 697 return -ENODEV;
698 }
4f1f3107
OE		 699 printk(KERN_INFO "attach tuner input %d adr %02x\n",
700 input->nr, tunerconf->addr);
ccad0457
RM		 701
702 feconf->tuner_init = ctl->tuner_init;
703 feconf->tuner_sleep = ctl->tuner_sleep;
704 feconf->tuner_set_mode = ctl->tuner_set_mode;
705 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
706 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
707 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
708 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
709 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
710 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
711 feconf->tuner_set_refclk = ctl->tuner_set_refclk;
712 feconf->tuner_get_status = ctl->tuner_get_status;
713
714 return 0;
715}
716
805e6874 717static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
ccad0457
RM		 718 int (*start_feed)(struct dvb_demux_feed *),
719 int (*stop_feed)(struct dvb_demux_feed *),
720 void *priv)
721{
722 dvbdemux->priv = priv;
723
724 dvbdemux->filternum = 256;
725 dvbdemux->feednum = 256;
726 dvbdemux->start_feed = start_feed;
727 dvbdemux->stop_feed = stop_feed;
728 dvbdemux->write_to_decoder = NULL;
729 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
730 DMX_SECTION_FILTERING |
731 DMX_MEMORY_BASED_FILTERING);
732 return dvb_dmx_init(dvbdemux);
733}
734
805e6874 735static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
ccad0457
RM		 736 struct dvb_demux *dvbdemux,
737 struct dmx_frontend *hw_frontend,
738 struct dmx_frontend *mem_frontend,
739 struct dvb_adapter *dvb_adapter)
740{
741 int ret;
742
743 dmxdev->filternum = 256;
744 dmxdev->demux = &dvbdemux->dmx;
745 dmxdev->capabilities = 0;
746 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
747 if (ret < 0)
748 return ret;
749
750 hw_frontend->source = DMX_FRONTEND_0;
751 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
752 mem_frontend->source = DMX_MEMORY_FE;
753 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
754 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
755}
756
757static int start_feed(struct dvb_demux_feed *dvbdmxfeed)
758{
759 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
760 struct ddb_input *input = dvbdmx->priv;
761
762 if (!input->users)
763 ddb_input_start(input);
764
765 return ++input->users;
766}
767
768static int stop_feed(struct dvb_demux_feed *dvbdmxfeed)
769{
770 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
771 struct ddb_input *input = dvbdmx->priv;
772
773 if (--input->users)
774 return input->users;
775
776 ddb_input_stop(input);
777 return 0;
778}
779
780
781static void dvb_input_detach(struct ddb_input *input)
782{
783 struct dvb_adapter *adap = &input->adap;
784 struct dvb_demux *dvbdemux = &input->demux;
785
786 switch (input->attached) {
787 case 5:
788 if (input->fe2)
789 dvb_unregister_frontend(input->fe2);
790 if (input->fe) {
791 dvb_unregister_frontend(input->fe);
792 dvb_frontend_detach(input->fe);
793 input->fe = NULL;
794 }
795 case 4:
796 dvb_net_release(&input->dvbnet);
797
798 case 3:
799 dvbdemux->dmx.close(&dvbdemux->dmx);
800 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
801 &input->hw_frontend);
802 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
803 &input->mem_frontend);
804 dvb_dmxdev_release(&input->dmxdev);
805
806 case 2:
807 dvb_dmx_release(&input->demux);
808
809 case 1:
810 dvb_unregister_adapter(adap);
811 }
812 input->attached = 0;
813}
814
815static int dvb_input_attach(struct ddb_input *input)
816{
817 int ret;
818 struct ddb_port *port = input->port;
819 struct dvb_adapter *adap = &input->adap;
820 struct dvb_demux *dvbdemux = &input->demux;
821
4f1f3107 822 ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE,
ccad0457
RM		 823 &input->port->dev->pdev->dev,
824 adapter_nr);
825 if (ret < 0) {
4f1f3107 826 printk(KERN_ERR "ddbridge: Could not register adapter."
ccad0457
RM		 827 "Check if you enabled enough adapters in dvb-core!\n");
828 return ret;
829 }
830 input->attached = 1;
831
832 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
833 start_feed,
834 stop_feed, input);
835 if (ret < 0)
836 return ret;
837 input->attached = 2;
838
839 ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux,
840 &input->hw_frontend,
841 &input->mem_frontend, adap);
842 if (ret < 0)
843 return ret;
844 input->attached = 3;
845
846 ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux);
847 if (ret < 0)
848 return ret;
849 input->attached = 4;
850
851 input->fe = 0;
852 switch (port->type) {
853 case DDB_TUNER_DVBS_ST:
854 if (demod_attach_stv0900(input, 0) < 0)
855 return -ENODEV;
856 if (tuner_attach_stv6110(input, 0) < 0)
857 return -ENODEV;
858 if (input->fe) {
859 if (dvb_register_frontend(adap, input->fe) < 0)
860 return -ENODEV;
861 }
862 break;
863 case DDB_TUNER_DVBS_ST_AA:
864 if (demod_attach_stv0900(input, 1) < 0)
865 return -ENODEV;
866 if (tuner_attach_stv6110(input, 1) < 0)
867 return -ENODEV;
868 if (input->fe) {
869 if (dvb_register_frontend(adap, input->fe) < 0)
870 return -ENODEV;
871 }
872 break;
873 case DDB_TUNER_DVBCT_TR:
874 if (demod_attach_drxk(input) < 0)
875 return -ENODEV;
876 if (tuner_attach_tda18271(input) < 0)
877 return -ENODEV;
878 if (input->fe) {
879 if (dvb_register_frontend(adap, input->fe) < 0)
880 return -ENODEV;
881 }
882 if (input->fe2) {
883 if (dvb_register_frontend(adap, input->fe2) < 0)
884 return -ENODEV;
4f1f3107 885 input->fe2->tuner_priv = input->fe->tuner_priv;
ccad0457
RM		 886 memcpy(&input->fe2->ops.tuner_ops,
887 &input->fe->ops.tuner_ops,
888 sizeof(struct dvb_tuner_ops));
889 }
890 break;
891 }
892 input->attached = 5;
893 return 0;
894}
895
896/****************************************************************************/
897/****************************************************************************/
898
899static ssize_t ts_write(struct file *file, const char *buf,
900 size_t count, loff_t *ppos)
901{
902 struct dvb_device *dvbdev = file->private_data;
903 struct ddb_output *output = dvbdev->priv;
904 size_t left = count;
905 int stat;
906
907 while (left) {
908 if (ddb_output_free(output) < 188) {
909 if (file->f_flags & O_NONBLOCK)
910 break;
911 if (wait_event_interruptible(
912 output->wq, ddb_output_free(output) >= 188) < 0)
913 break;
914 }
915 stat = ddb_output_write(output, buf, left);
916 if (stat < 0)
917 break;
918 buf += stat;
919 left -= stat;
920 }
921 return (left == count) ? -EAGAIN : (count - left);
922}
923
924static ssize_t ts_read(struct file *file, char *buf,
925 size_t count, loff_t *ppos)
926{
927 struct dvb_device *dvbdev = file->private_data;
928 struct ddb_output *output = dvbdev->priv;
929 struct ddb_input *input = output->port->input[0];
930 int left, read;
931
932 count -= count % 188;
933 left = count;
934 while (left) {
935 if (ddb_input_avail(input) < 188) {
936 if (file->f_flags & O_NONBLOCK)
937 break;
938 if (wait_event_interruptible(
939 input->wq, ddb_input_avail(input) >= 188) < 0)
940 break;
941 }
942 read = ddb_input_read(input, buf, left);
2122eaf6
HV		 943 if (read < 0)
944 return read;
ccad0457
RM		 945 left -= read;
946 buf += read;
947 }
948 return (left == count) ? -EAGAIN : (count - left);
949}
950
951static unsigned int ts_poll(struct file *file, poll_table *wait)
952{
4f1f3107 953 /*
ccad0457
RM		 954 struct dvb_device *dvbdev = file->private_data;
955 struct ddb_output *output = dvbdev->priv;
956 struct ddb_input *input = output->port->input[0];
4f1f3107 957 */
ccad0457
RM		 958 unsigned int mask = 0;
959
960#if 0
961 if (data_avail_to_read)
962 mask |= POLLIN | POLLRDNORM;
963 if (data_avail_to_write)
964 mask |= POLLOUT | POLLWRNORM;
965
966 poll_wait(file, &read_queue, wait);
967 poll_wait(file, &write_queue, wait);
968#endif
969 return mask;
970}
971
4f1f3107 972static const struct file_operations ci_fops = {
ccad0457
RM		 973 .owner = THIS_MODULE,
974 .read = ts_read,
975 .write = ts_write,
976 .open = dvb_generic_open,
977 .release = dvb_generic_release,
978 .poll = ts_poll,
979 .mmap = 0,
980};
981
982static struct dvb_device dvbdev_ci = {
983 .priv = 0,
984 .readers = -1,
985 .writers = -1,
986 .users = -1,
987 .fops = &ci_fops,
988};
989
990/****************************************************************************/
991/****************************************************************************/
992/****************************************************************************/
993
994static void input_tasklet(unsigned long data)
995{
996 struct ddb_input *input = (struct ddb_input *) data;
997 struct ddb *dev = input->port->dev;
998
999 spin_lock(&input->lock);
1000 if (!input->running) {
1001 spin_unlock(&input->lock);
1002 return;
1003 }
1004 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
1005
1006 if (input->port->class == DDB_PORT_TUNER) {
1007 if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))
4f1f3107 1008 printk(KERN_ERR "Overflow input %d\n", input->nr);
ccad0457
RM		 1009 while (input->cbuf != ((input->stat >> 11) & 0x1f)
1010 || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) {
1011 dvb_dmx_swfilter_packets(&input->demux,
1012 input->vbuf[input->cbuf],
1013 input->dma_buf_size / 188);
1014
1015 input->cbuf = (input->cbuf + 1) % input->dma_buf_num;
1016 ddbwritel((input->cbuf << 11),
1017 DMA_BUFFER_ACK(input->nr));
1018 input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
1019 }
1020 }
1021 if (input->port->class == DDB_PORT_CI)
1022 wake_up(&input->wq);
1023 spin_unlock(&input->lock);
1024}
1025
1026static void output_tasklet(unsigned long data)
1027{
1028 struct ddb_output *output = (struct ddb_output *) data;
1029 struct ddb *dev = output->port->dev;
1030
1031 spin_lock(&output->lock);
1032 if (!output->running) {
1033 spin_unlock(&output->lock);
1034 return;
1035 }
1036 output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8));
1037 wake_up(&output->wq);
1038 spin_unlock(&output->lock);
1039}
1040
1041
1042struct cxd2099_cfg cxd_cfg = {
1043 .bitrate = 62000,
1044 .adr = 0x40,
1045 .polarity = 1,
1046 .clock_mode = 1,
1047};
1048
1049static int ddb_ci_attach(struct ddb_port *port)
1050{
1051 int ret;
1052
1053 ret = dvb_register_adapter(&port->output->adap,
1054 "DDBridge",
1055 THIS_MODULE,
1056 &port->dev->pdev->dev,
1057 adapter_nr);
1058 if (ret < 0)
1059 return ret;
1060 port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap);
1061 if (!port->en) {
1062 dvb_unregister_adapter(&port->output->adap);
1063 return -ENODEV;
1064 }
1065 ddb_input_start(port->input[0]);
1066 ddb_output_start(port->output);
1067 dvb_ca_en50221_init(&port->output->adap,
1068 port->en, 0, 1);
4f1f3107
OE		 1069 ret = dvb_register_device(&port->output->adap, &port->output->dev,
1070 &dvbdev_ci, (void *) port->output,
1071 DVB_DEVICE_SEC);
ccad0457
RM		 1072 return ret;
1073}
1074
1075static int ddb_port_attach(struct ddb_port *port)
1076{
1077 int ret = 0;
1078
1079 switch (port->class) {
1080 case DDB_PORT_TUNER:
1081 ret = dvb_input_attach(port->input[0]);
4f1f3107 1082 if (ret < 0)
ccad0457
RM		 1083 break;
1084 ret = dvb_input_attach(port->input[1]);
1085 break;
1086 case DDB_PORT_CI:
1087 ret = ddb_ci_attach(port);
1088 break;
1089 default:
1090 break;
1091 }
1092 if (ret < 0)
4f1f3107 1093 printk(KERN_ERR "port_attach on port %d failed\n", port->nr);
ccad0457
RM		 1094 return ret;
1095}
1096
1097static int ddb_ports_attach(struct ddb *dev)
1098{
1099 int i, ret = 0;
1100 struct ddb_port *port;
1101
1102 for (i = 0; i < dev->info->port_num; i++) {
1103 port = &dev->port[i];
1104 ret = ddb_port_attach(port);
1105 if (ret < 0)
1106 break;
1107 }
1108 return ret;
1109}
1110
1111static void ddb_ports_detach(struct ddb *dev)
1112{
1113 int i;
1114 struct ddb_port *port;
1115
1116 for (i = 0; i < dev->info->port_num; i++) {
1117 port = &dev->port[i];
1118 switch (port->class) {
1119 case DDB_PORT_TUNER:
1120 dvb_input_detach(port->input[0]);
1121 dvb_input_detach(port->input[1]);
1122 break;
1123 case DDB_PORT_CI:
1124 if (port->output->dev)
1125 dvb_unregister_device(port->output->dev);
1126 if (port->en) {
1127 ddb_input_stop(port->input[0]);
1128 ddb_output_stop(port->output);
1129 dvb_ca_en50221_release(port->en);
1130 kfree(port->en);
1131 port->en = 0;
1132 dvb_unregister_adapter(&port->output->adap);
1133 }
1134 break;
1135 }
1136 }
1137}
1138
1139/****************************************************************************/
1140/****************************************************************************/
1141
1142static int port_has_ci(struct ddb_port *port)
1143{
1144 u8 val;
4f1f3107 1145 return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1;
ccad0457
RM		 1146}
1147
1148static int port_has_stv0900(struct ddb_port *port)
1149{
1150 u8 val;
1151 if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0)
1152 return 0;
1153 return 1;
1154}
1155
1156static int port_has_stv0900_aa(struct ddb_port *port)
1157{
1158 u8 val;
1159 if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0)
1160 return 0;
1161 return 1;
1162}
1163
1164static int port_has_drxks(struct ddb_port *port)
1165{
1166 u8 val;
1167 if (i2c_read(&port->i2c->adap, 0x29, &val) < 0)
1168 return 0;
1169 if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0)
1170 return 0;
1171 return 1;
1172}
1173
1174static void ddb_port_probe(struct ddb_port *port)
1175{
1176 struct ddb *dev = port->dev;
1177 char *modname = "NO MODULE";
1178
1179 port->class = DDB_PORT_NONE;
1180
1181 if (port_has_ci(port)) {
1182 modname = "CI";
1183 port->class = DDB_PORT_CI;
1184 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
1185 } else if (port_has_stv0900(port)) {
1186 modname = "DUAL DVB-S2";
1187 port->class = DDB_PORT_TUNER;
1188 port->type = DDB_TUNER_DVBS_ST;
1189 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
1190 } else if (port_has_stv0900_aa(port)) {
1191 modname = "DUAL DVB-S2";
1192 port->class = DDB_PORT_TUNER;
1193 port->type = DDB_TUNER_DVBS_ST_AA;
1194 ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
1195 } else if (port_has_drxks(port)) {
1196 modname = "DUAL DVB-C/T";
1197 port->class = DDB_PORT_TUNER;
1198 port->type = DDB_TUNER_DVBCT_TR;
1199 ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
1200 }
4f1f3107
OE		 1201 printk(KERN_INFO "Port %d (TAB %d): %s\n",
1202 port->nr, port->nr+1, modname);
ccad0457
RM		 1203}
1204
1205static void ddb_input_init(struct ddb_port *port, int nr)
1206{
1207 struct ddb *dev = port->dev;
1208 struct ddb_input *input = &dev->input[nr];
1209
1210 input->nr = nr;
1211 input->port = port;
1212 input->dma_buf_num = INPUT_DMA_BUFS;
1213 input->dma_buf_size = INPUT_DMA_SIZE;
1214 ddbwritel(0, TS_INPUT_CONTROL(nr));
1215 ddbwritel(2, TS_INPUT_CONTROL(nr));
1216 ddbwritel(0, TS_INPUT_CONTROL(nr));
1217 ddbwritel(0, DMA_BUFFER_ACK(nr));
1218 tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input);
1219 spin_lock_init(&input->lock);
1220 init_waitqueue_head(&input->wq);
1221}
1222
1223static void ddb_output_init(struct ddb_port *port, int nr)
1224{
1225 struct ddb *dev = port->dev;
1226 struct ddb_output *output = &dev->output[nr];
1227 output->nr = nr;
1228 output->port = port;
1229 output->dma_buf_num = OUTPUT_DMA_BUFS;
1230 output->dma_buf_size = OUTPUT_DMA_SIZE;
1231
1232 ddbwritel(0, TS_OUTPUT_CONTROL(nr));
1233 ddbwritel(2, TS_OUTPUT_CONTROL(nr));
1234 ddbwritel(0, TS_OUTPUT_CONTROL(nr));
1235 tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output);
1236 init_waitqueue_head(&output->wq);
1237}
1238
1239static void ddb_ports_init(struct ddb *dev)
1240{
1241 int i;
1242 struct ddb_port *port;
1243
1244 for (i = 0; i < dev->info->port_num; i++) {
1245 port = &dev->port[i];
1246 port->dev = dev;
1247 port->nr = i;
1248 port->i2c = &dev->i2c[i];
1249 port->input[0] = &dev->input[2 * i];
1250 port->input[1] = &dev->input[2 * i + 1];
1251 port->output = &dev->output[i];
1252
1253 mutex_init(&port->i2c_gate_lock);
1254 ddb_port_probe(port);
1255 ddb_input_init(port, 2 * i);
1256 ddb_input_init(port, 2 * i + 1);
1257 ddb_output_init(port, i);
1258 }
1259}
1260
1261static void ddb_ports_release(struct ddb *dev)
1262{
1263 int i;
1264 struct ddb_port *port;
1265
1266 for (i = 0; i < dev->info->port_num; i++) {
1267 port = &dev->port[i];
1268 port->dev = dev;
1269 tasklet_kill(&port->input[0]->tasklet);
1270 tasklet_kill(&port->input[1]->tasklet);
1271 tasklet_kill(&port->output->tasklet);
1272 }
1273}
1274
1275/****************************************************************************/
1276/****************************************************************************/
1277/****************************************************************************/
1278
1279static void irq_handle_i2c(struct ddb *dev, int n)
1280{
1281 struct ddb_i2c *i2c = &dev->i2c[n];
1282
1283 i2c->done = 1;
1284 wake_up(&i2c->wq);
1285}
1286
1287static irqreturn_t irq_handler(int irq, void *dev_id)
1288{
1289 struct ddb *dev = (struct ddb *) dev_id;
1290 u32 s = ddbreadl(INTERRUPT_STATUS);
1291
1292 if (!s)
1293 return IRQ_NONE;
1294
1295 do {
1296 ddbwritel(s, INTERRUPT_ACK);
1297
4f1f3107
OE		 1298 if (s & 0x00000001)
1299 irq_handle_i2c(dev, 0);
1300 if (s & 0x00000002)
1301 irq_handle_i2c(dev, 1);
1302 if (s & 0x00000004)
1303 irq_handle_i2c(dev, 2);
1304 if (s & 0x00000008)
1305 irq_handle_i2c(dev, 3);
1306
1307 if (s & 0x00000100)
1308 tasklet_schedule(&dev->input[0].tasklet);
1309 if (s & 0x00000200)
1310 tasklet_schedule(&dev->input[1].tasklet);
1311 if (s & 0x00000400)
1312 tasklet_schedule(&dev->input[2].tasklet);
1313 if (s & 0x00000800)
1314 tasklet_schedule(&dev->input[3].tasklet);
1315 if (s & 0x00001000)
1316 tasklet_schedule(&dev->input[4].tasklet);
1317 if (s & 0x00002000)
1318 tasklet_schedule(&dev->input[5].tasklet);
1319 if (s & 0x00004000)
1320 tasklet_schedule(&dev->input[6].tasklet);
1321 if (s & 0x00008000)
1322 tasklet_schedule(&dev->input[7].tasklet);
1323
1324 if (s & 0x00010000)
1325 tasklet_schedule(&dev->output[0].tasklet);
1326 if (s & 0x00020000)
1327 tasklet_schedule(&dev->output[1].tasklet);
1328 if (s & 0x00040000)
1329 tasklet_schedule(&dev->output[2].tasklet);
1330 if (s & 0x00080000)
1331 tasklet_schedule(&dev->output[3].tasklet);
1332
1333 /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */
ccad0457
RM		 1334 } while ((s = ddbreadl(INTERRUPT_STATUS)));
1335
1336 return IRQ_HANDLED;
1337}
1338
1339/******************************************************************************/
1340/******************************************************************************/
1341/******************************************************************************/
1342
1343static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen)
1344{
1345 u32 data, shift;
1346
1347 if (wlen > 4)
1348 ddbwritel(1, SPI_CONTROL);
1349 while (wlen > 4) {
1350 /* FIXME: check for big-endian */
1351 data = swab32(*(u32 *)wbuf);
1352 wbuf += 4;
1353 wlen -= 4;
1354 ddbwritel(data, SPI_DATA);
4f1f3107
OE		 1355 while (ddbreadl(SPI_CONTROL) & 0x0004)
1356 ;
ccad0457
RM		 1357 }
1358
1359 if (rlen)
1360 ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
1361 else
1362 ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
1363
4f1f3107 1364 data = 0;
ccad0457
RM		 1365 shift = ((4 - wlen) * 8);
1366 while (wlen) {
1367 data <<= 8;
1368 data |= *wbuf;
1369 wlen--;
1370 wbuf++;
1371 }
1372 if (shift)
1373 data <<= shift;
1374 ddbwritel(data, SPI_DATA);
4f1f3107
OE		 1375 while (ddbreadl(SPI_CONTROL) & 0x0004)
1376 ;
ccad0457
RM		 1377
1378 if (!rlen) {
1379 ddbwritel(0, SPI_CONTROL);
1380 return 0;
1381 }
1382 if (rlen > 4)
1383 ddbwritel(1, SPI_CONTROL);
1384
1385 while (rlen > 4) {
1386 ddbwritel(0xffffffff, SPI_DATA);
4f1f3107
OE		 1387 while (ddbreadl(SPI_CONTROL) & 0x0004)
1388 ;
ccad0457
RM		 1389 data = ddbreadl(SPI_DATA);
1390 *(u32 *) rbuf = swab32(data);
1391 rbuf += 4;
1392 rlen -= 4;
1393 }
1394 ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL);
1395 ddbwritel(0xffffffff, SPI_DATA);
4f1f3107
OE		 1396 while (ddbreadl(SPI_CONTROL) & 0x0004)
1397 ;
ccad0457
RM		 1398
1399 data = ddbreadl(SPI_DATA);
1400 ddbwritel(0, SPI_CONTROL);
1401
1402 if (rlen < 4)
1403 data <<= ((4 - rlen) * 8);
1404
1405 while (rlen > 0) {
1406 *rbuf = ((data >> 24) & 0xff);
1407 data <<= 8;
1408 rbuf++;
1409 rlen--;
1410 }
1411 return 0;
1412}
1413
1414#define DDB_MAGIC 'd'
1415
1416struct ddb_flashio {
1417 __u8 *write_buf;
1418 __u32 write_len;
1419 __u8 *read_buf;
1420 __u32 read_len;
1421};
1422
1423#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio)
1424
1425#define DDB_NAME "ddbridge"
1426
1427static u32 ddb_num;
1428static struct ddb *ddbs[32];
1429static struct class *ddb_class;
1430static int ddb_major;
1431
1432static int ddb_open(struct inode *inode, struct file *file)
1433{
1434 struct ddb *dev = ddbs[iminor(inode)];
1435
1436 file->private_data = dev;
1437 return 0;
1438}
1439
1440static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1441{
1442 struct ddb *dev = file->private_data;
1443 void *parg = (void *)arg;
e9013fb6 1444 int res;
ccad0457
RM		 1445
1446 switch (cmd) {
1447 case IOCTL_DDB_FLASHIO:
1448 {
1449 struct ddb_flashio fio;
1450 u8 *rbuf, *wbuf;
1451
1452 if (copy_from_user(&fio, parg, sizeof(fio)))
e9013fb6
DC		 1453 return -EFAULT;
1454
1455 if (fio.write_len > 1028 || fio.read_len > 1028)
1456 return -EINVAL;
1457 if (fio.write_len + fio.read_len > 1028)
1458 return -EINVAL;
1459
ccad0457 1460 wbuf = &dev->iobuf[0];
ccad0457 1461 rbuf = wbuf + fio.write_len;
e9013fb6
DC		 1462
1463 if (copy_from_user(wbuf, fio.write_buf, fio.write_len))
1464 return -EFAULT;
1465 res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len);
1466 if (res)
1467 return res;
ccad0457 1468 if (copy_to_user(fio.read_buf, rbuf, fio.read_len))
e9013fb6 1469 return -EFAULT;
ccad0457
RM		 1470 break;
1471 }
1472 default:
e9013fb6 1473 return -ENOTTY;
ccad0457 1474 }
e9013fb6 1475 return 0;
ccad0457
RM		 1476}
1477
4f1f3107 1478static const struct file_operations ddb_fops = {
ccad0457
RM		 1479 .unlocked_ioctl = ddb_ioctl,
1480 .open = ddb_open,
1481};
1482
2c9ede55 1483static char *ddb_devnode(struct device *device, umode_t *mode)
ccad0457
RM		 1484{
1485 struct ddb *dev = dev_get_drvdata(device);
1486
1487 return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr);
1488}
1489
1490static int ddb_class_create(void)
1491{
4f1f3107
OE		 1492 ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops);
1493 if (ddb_major < 0)
ccad0457
RM		 1494 return ddb_major;
1495
1496 ddb_class = class_create(THIS_MODULE, DDB_NAME);
1497 if (IS_ERR(ddb_class)) {
1498 unregister_chrdev(ddb_major, DDB_NAME);
1499 return -1;
1500 }
1501 ddb_class->devnode = ddb_devnode;
1502 return 0;
1503}
1504
1505static void ddb_class_destroy(void)
1506{
1507 class_destroy(ddb_class);
1508 unregister_chrdev(ddb_major, DDB_NAME);
1509}
1510
1511static int ddb_device_create(struct ddb *dev)
1512{
1513 dev->nr = ddb_num++;
1514 dev->ddb_dev = device_create(ddb_class, NULL,
1515 MKDEV(ddb_major, dev->nr),
1516 dev, "ddbridge%d", dev->nr);
1517 ddbs[dev->nr] = dev;
1518 if (IS_ERR(dev->ddb_dev))
1519 return -1;
1520 return 0;
1521}
1522
1523static void ddb_device_destroy(struct ddb *dev)
1524{
1525 ddb_num--;
1526 if (IS_ERR(dev->ddb_dev))
1527 return;
1528 device_destroy(ddb_class, MKDEV(ddb_major, 0));
1529}
1530
1531
1532/****************************************************************************/
1533/****************************************************************************/
1534/****************************************************************************/
1535
1536static void ddb_unmap(struct ddb *dev)
1537{
1538 if (dev->regs)
1539 iounmap(dev->regs);
1540 vfree(dev);
1541}
1542
1543
1544static void __devexit ddb_remove(struct pci_dev *pdev)
1545{
1546 struct ddb *dev = (struct ddb *) pci_get_drvdata(pdev);
1547
1548 ddb_ports_detach(dev);
1549 ddb_i2c_release(dev);
1550
1551 ddbwritel(0, INTERRUPT_ENABLE);
1552 free_irq(dev->pdev->irq, dev);
1553#ifdef CONFIG_PCI_MSI
1554 if (dev->msi)
1555 pci_disable_msi(dev->pdev);
1556#endif
1557 ddb_ports_release(dev);
1558 ddb_buffers_free(dev);
1559 ddb_device_destroy(dev);
1560
1561 ddb_unmap(dev);
1562 pci_set_drvdata(pdev, 0);
1563 pci_disable_device(pdev);
1564}
1565
1566
1567static int __devinit ddb_probe(struct pci_dev *pdev,
1568 const struct pci_device_id *id)
1569{
1570 struct ddb *dev;
4f1f3107 1571 int stat = 0;
ccad0457
RM		 1572 int irq_flag = IRQF_SHARED;
1573
4f1f3107 1574 if (pci_enable_device(pdev) < 0)
ccad0457
RM		 1575 return -ENODEV;
1576
1577 dev = vmalloc(sizeof(struct ddb));
1578 if (dev == NULL)
1579 return -ENOMEM;
1580 memset(dev, 0, sizeof(struct ddb));
1581
1582 dev->pdev = pdev;
1583 pci_set_drvdata(pdev, dev);
1584 dev->info = (struct ddb_info *) id->driver_data;
4f1f3107 1585 printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name);
ccad0457 1586
4f1f3107
OE		 1587 dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
1588 pci_resource_len(dev->pdev, 0));
ccad0457
RM		 1589 if (!dev->regs) {
1590 stat = -ENOMEM;
1591 goto fail;
1592 }
4f1f3107 1593 printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4));
ccad0457
RM		 1594
1595#ifdef CONFIG_PCI_MSI
1596 if (pci_msi_enabled())
1597 stat = pci_enable_msi(dev->pdev);
1598 if (stat) {
1599 printk(KERN_INFO ": MSI not available.\n");
1600 } else {
1601 irq_flag = 0;
1602 dev->msi = 1;
1603 }
1604#endif
4f1f3107
OE		 1605 stat = request_irq(dev->pdev->irq, irq_handler,
1606 irq_flag, "DDBridge", (void *) dev);
1607 if (stat < 0)
ccad0457
RM		 1608 goto fail1;
1609 ddbwritel(0, DMA_BASE_WRITE);
1610 ddbwritel(0, DMA_BASE_READ);
1611 ddbwritel(0xffffffff, INTERRUPT_ACK);
1612 ddbwritel(0xfff0f, INTERRUPT_ENABLE);
1613 ddbwritel(0, MSI1_ENABLE);
1614
1615 if (ddb_i2c_init(dev) < 0)
1616 goto fail1;
1617 ddb_ports_init(dev);
1618 if (ddb_buffers_alloc(dev) < 0) {
1619 printk(KERN_INFO ": Could not allocate buffer memory\n");
1620 goto fail2;
1621 }
1622 if (ddb_ports_attach(dev) < 0)
1623 goto fail3;
1624 ddb_device_create(dev);
1625 return 0;
1626
1627fail3:
1628 ddb_ports_detach(dev);
4f1f3107 1629 printk(KERN_ERR "fail3\n");
ccad0457
RM		 1630 ddb_ports_release(dev);
1631fail2:
4f1f3107 1632 printk(KERN_ERR "fail2\n");
ccad0457
RM		 1633 ddb_buffers_free(dev);
1634fail1:
4f1f3107 1635 printk(KERN_ERR "fail1\n");
ccad0457
RM		 1636 if (dev->msi)
1637 pci_disable_msi(dev->pdev);
1638 free_irq(dev->pdev->irq, dev);
1639fail:
4f1f3107 1640 printk(KERN_ERR "fail\n");
ccad0457
RM		 1641 ddb_unmap(dev);
1642 pci_set_drvdata(pdev, 0);
1643 pci_disable_device(pdev);
1644 return -1;
1645}
1646
1647/******************************************************************************/
1648/******************************************************************************/
1649/******************************************************************************/
1650
1651static struct ddb_info ddb_none = {
1652 .type = DDB_NONE,
1653 .name = "Digital Devices PCIe bridge",
1654};
1655
1656static struct ddb_info ddb_octopus = {
1657 .type = DDB_OCTOPUS,
1658 .name = "Digital Devices Octopus DVB adapter",
1659 .port_num = 4,
1660};
1661
1662static struct ddb_info ddb_octopus_le = {
1663 .type = DDB_OCTOPUS,
1664 .name = "Digital Devices Octopus LE DVB adapter",
1665 .port_num = 2,
1666};
1667
1668static struct ddb_info ddb_v6 = {
1669 .type = DDB_OCTOPUS,
1670 .name = "Digital Devices Cine S2 V6 DVB adapter",
1671 .port_num = 3,
1672};
1673
1674#define DDVID 0xdd01 /* Digital Devices Vendor ID */
1675
4f1f3107 1676#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \
ccad0457
RM		 1677 .vendor = _vend, .device = _dev, \
1678 .subvendor = _subvend, .subdevice = _subdev, \
1679 .driver_data = (unsigned long)&_driverdata }
1680
1681static const struct pci_device_id ddb_id_tbl[] __devinitdata = {
1682 DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus),
1683 DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus),
1684 DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le),
1685 DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus),
1686 DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6),
1687 /* in case sub-ids got deleted in flash */
1688 DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
1689 {0}
1690};
1691MODULE_DEVICE_TABLE(pci, ddb_id_tbl);
1692
1693
1694static struct pci_driver ddb_pci_driver = {
1695 .name = "DDBridge",
1696 .id_table = ddb_id_tbl,
1697 .probe = ddb_probe,
1698 .remove = ddb_remove,
1699};
1700
1701static __init int module_init_ddbridge(void)
1702{
4f1f3107 1703 printk(KERN_INFO "Digital Devices PCIE bridge driver, "
ccad0457
RM		 1704 "Copyright (C) 2010-11 Digital Devices GmbH\n");
1705 if (ddb_class_create())
1706 return -1;
1707 return pci_register_driver(&ddb_pci_driver);
1708}
1709
1710static __exit void module_exit_ddbridge(void)
1711{
1712 pci_unregister_driver(&ddb_pci_driver);
1713 ddb_class_destroy();
1714}
1715
1716module_init(module_init_ddbridge);
1717module_exit(module_exit_ddbridge);
1718
1719MODULE_DESCRIPTION("Digital Devices PCIe Bridge");
1720MODULE_AUTHOR("Ralph Metzler");
1721MODULE_LICENSE("GPL");
1722MODULE_VERSION("0.5");
Linux kernel - Deliverables
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