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1da177e4 LT |
1 | /* |
2 | * dib3000mc_priv.h | |
3 | * | |
4 | * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@desy.de) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation, version 2. | |
9 | * | |
10 | * for more information see dib3000mc.c . | |
11 | */ | |
12 | ||
13 | #ifndef __DIB3000MC_PRIV_H__ | |
14 | #define __DIB3000MC_PRIV_H__ | |
15 | ||
16 | /* | |
17 | * Demodulator parameters | |
18 | * reg: 0 1 1 1 11 11 111 | |
19 | * | | | | | | | |
20 | * | | | | | +-- alpha (000=0, 001=1, 010=2, 100=4) | |
21 | * | | | | +----- constellation (00=QPSK, 01=16QAM, 10=64QAM) | |
22 | * | | | +-------- guard (00=1/32, 01=1/16, 10=1/8, 11=1/4) | |
23 | * | | +----------- transmission mode (0=2k, 1=8k) | |
24 | * | | | |
25 | * | +-------------- restart autosearch for parameters | |
26 | * +---------------- restart the demodulator | |
27 | * reg: 181 1 111 1 | |
28 | * | | | | |
29 | * | | +- FEC applies for HP or LP (0=LP, 1=HP) | |
30 | * | +---- FEC rate (001=1/2, 010=2/3, 011=3/4, 101=5/6, 111=7/8) | |
31 | * +------- hierarchy on (0=no, 1=yes) | |
32 | */ | |
33 | ||
34 | /* demodulator tuning parameter and restart options */ | |
35 | #define DIB3000MC_REG_DEMOD_PARM ( 0) | |
36 | #define DIB3000MC_DEMOD_PARM(a,c,g,t) ( \ | |
37 | (0x7 & a) | \ | |
38 | ((0x3 & c) << 3) | \ | |
39 | ((0x3 & g) << 5) | \ | |
40 | ((0x1 & t) << 7) ) | |
41 | #define DIB3000MC_DEMOD_RST_AUTO_SRCH_ON (1 << 8) | |
42 | #define DIB3000MC_DEMOD_RST_AUTO_SRCH_OFF (0 << 8) | |
43 | #define DIB3000MC_DEMOD_RST_DEMOD_ON (1 << 9) | |
44 | #define DIB3000MC_DEMOD_RST_DEMOD_OFF (0 << 9) | |
45 | ||
46 | /* register for hierarchy parameters */ | |
47 | #define DIB3000MC_REG_HRCH_PARM ( 181) | |
48 | #define DIB3000MC_HRCH_PARM(s,f,h) ( \ | |
49 | (0x1 & s) | \ | |
50 | ((0x7 & f) << 1) | \ | |
51 | ((0x1 & h) << 4) ) | |
52 | ||
53 | /* timeout ??? */ | |
54 | #define DIB3000MC_REG_UNK_1 ( 1) | |
55 | #define DIB3000MC_UNK_1 ( 0x04) | |
56 | ||
57 | /* timeout ??? */ | |
58 | #define DIB3000MC_REG_UNK_2 ( 2) | |
59 | #define DIB3000MC_UNK_2 ( 0x04) | |
60 | ||
61 | /* timeout ??? */ | |
62 | #define DIB3000MC_REG_UNK_3 ( 3) | |
63 | #define DIB3000MC_UNK_3 (0x1000) | |
64 | ||
65 | #define DIB3000MC_REG_UNK_4 ( 4) | |
66 | #define DIB3000MC_UNK_4 (0x0814) | |
67 | ||
68 | /* timeout ??? */ | |
69 | #define DIB3000MC_REG_SEQ_TPS ( 5) | |
70 | #define DIB3000MC_SEQ_TPS_DEFAULT ( 1) | |
71 | #define DIB3000MC_SEQ_TPS(s,t) ( \ | |
72 | ((s & 0x0f) << 4) | \ | |
73 | ((t & 0x01) << 8) ) | |
74 | #define DIB3000MC_IS_TPS(v) ((v << 8) & 0x1) | |
75 | #define DIB3000MC_IS_AS(v) ((v >> 4) & 0xf) | |
76 | ||
77 | /* parameters for the bandwidth */ | |
78 | #define DIB3000MC_REG_BW_TIMOUT_MSB ( 6) | |
79 | #define DIB3000MC_REG_BW_TIMOUT_LSB ( 7) | |
80 | ||
81 | static u16 dib3000mc_reg_bandwidth[] = { 6,7,8,9,10,11,16,17 }; | |
82 | ||
83 | /*static u16 dib3000mc_bandwidth_5mhz[] = | |
84 | { 0x28, 0x9380, 0x87, 0x4100, 0x2a4, 0x4500, 0x1, 0xb0d0 };*/ | |
85 | ||
86 | static u16 dib3000mc_bandwidth_6mhz[] = | |
87 | { 0x21, 0xd040, 0x70, 0xb62b, 0x233, 0x8ed5, 0x1, 0xb0d0 }; | |
88 | ||
89 | static u16 dib3000mc_bandwidth_7mhz[] = | |
90 | { 0x1c, 0xfba5, 0x60, 0x9c25, 0x1e3, 0x0cb7, 0x1, 0xb0d0 }; | |
91 | ||
92 | static u16 dib3000mc_bandwidth_8mhz[] = | |
93 | { 0x19, 0x5c30, 0x54, 0x88a0, 0x1a6, 0xab20, 0x1, 0xb0d0 }; | |
94 | ||
95 | static u16 dib3000mc_reg_bandwidth_general[] = { 12,13,14,15 }; | |
96 | static u16 dib3000mc_bandwidth_general[] = { 0x0000, 0x03e8, 0x0000, 0x03f2 }; | |
97 | ||
98 | /* lock mask */ | |
99 | #define DIB3000MC_REG_LOCK_MASK ( 15) | |
100 | #define DIB3000MC_ACTIVATE_LOCK_MASK (0x0800) | |
101 | ||
102 | /* reset the uncorrected packet count (??? do it 5 times) */ | |
103 | #define DIB3000MC_REG_RST_UNC ( 18) | |
104 | #define DIB3000MC_RST_UNC_ON ( 1) | |
105 | #define DIB3000MC_RST_UNC_OFF ( 0) | |
106 | ||
107 | #define DIB3000MC_REG_UNK_19 ( 19) | |
108 | #define DIB3000MC_UNK_19 ( 0) | |
109 | ||
110 | /* DDS frequency value (IF position) and inversion bit */ | |
111 | #define DIB3000MC_REG_INVERSION ( 21) | |
112 | #define DIB3000MC_REG_SET_DDS_FREQ_MSB ( 21) | |
113 | #define DIB3000MC_DDS_FREQ_MSB_INV_OFF (0x0164) | |
114 | #define DIB3000MC_DDS_FREQ_MSB_INV_ON (0x0364) | |
115 | ||
116 | #define DIB3000MC_REG_SET_DDS_FREQ_LSB ( 22) | |
117 | #define DIB3000MC_DDS_FREQ_LSB (0x463d) | |
118 | ||
119 | /* timing frequencies setting */ | |
120 | #define DIB3000MC_REG_TIMING_FREQ_MSB ( 23) | |
121 | #define DIB3000MC_REG_TIMING_FREQ_LSB ( 24) | |
122 | #define DIB3000MC_CLOCK_REF (0x151fd1) | |
123 | ||
124 | //static u16 dib3000mc_reg_timing_freq[] = { 23,24 }; | |
125 | ||
126 | //static u16 dib3000mc_timing_freq[][2] = { | |
127 | // { 0x69, 0x9f18 }, /* 5 MHz */ | |
128 | // { 0x7e ,0xbee9 }, /* 6 MHz */ | |
129 | // { 0x93 ,0xdebb }, /* 7 MHz */ | |
130 | // { 0xa8 ,0xfe8c }, /* 8 MHz */ | |
131 | //}; | |
132 | ||
133 | /* timeout ??? */ | |
134 | static u16 dib3000mc_reg_offset[] = { 26,33 }; | |
135 | ||
136 | static u16 dib3000mc_offset[][2] = { | |
137 | { 26240, 5 }, /* default */ | |
138 | { 30336, 6 }, /* 8K */ | |
139 | { 38528, 8 }, /* 2K */ | |
140 | }; | |
141 | ||
142 | #define DIB3000MC_REG_ISI ( 29) | |
143 | #define DIB3000MC_ISI_DEFAULT (0x1073) | |
144 | #define DIB3000MC_ISI_ACTIVATE (0x0000) | |
145 | #define DIB3000MC_ISI_INHIBIT (0x0200) | |
146 | ||
147 | /* impulse noise control */ | |
148 | static u16 dib3000mc_reg_imp_noise_ctl[] = { 34,35 }; | |
149 | ||
150 | static u16 dib3000mc_imp_noise_ctl[][2] = { | |
151 | { 0x1294, 0x1ff8 }, /* mode 0 */ | |
152 | { 0x1294, 0x1ff8 }, /* mode 1 */ | |
153 | { 0x1294, 0x1ff8 }, /* mode 2 */ | |
154 | { 0x1294, 0x1ff8 }, /* mode 3 */ | |
155 | { 0x1294, 0x1ff8 }, /* mode 4 */ | |
156 | }; | |
157 | ||
1da177e4 LT |
158 | /* AGC loop bandwidth */ |
159 | static u16 dib3000mc_reg_agc_bandwidth[] = { 40,41 }; | |
160 | static u16 dib3000mc_agc_bandwidth[] = { 0x119,0x330 }; | |
161 | ||
162 | static u16 dib3000mc_reg_agc_bandwidth_general[] = { 50,51,52,53,54 }; | |
163 | static u16 dib3000mc_agc_bandwidth_general[] = | |
164 | { 0x8000, 0x91ca, 0x01ba, 0x0087, 0x0087 }; | |
165 | ||
166 | #define DIB3000MC_REG_IMP_NOISE_55 ( 55) | |
167 | #define DIB3000MC_IMP_NEW_ALGO(w) (w | (1<<10)) | |
168 | ||
169 | /* Impulse noise params */ | |
170 | static u16 dib3000mc_reg_impulse_noise[] = { 55,56,57 }; | |
171 | static u16 dib3000mc_impluse_noise[][3] = { | |
172 | { 0x489, 0x89, 0x72 }, /* 5 MHz */ | |
173 | { 0x4a5, 0xa5, 0x89 }, /* 6 MHz */ | |
174 | { 0x4c0, 0xc0, 0xa0 }, /* 7 MHz */ | |
175 | { 0x4db, 0xdb, 0xb7 }, /* 8 Mhz */ | |
176 | }; | |
177 | ||
178 | static u16 dib3000mc_reg_fft[] = { | |
179 | 58,59,60,61,62,63,64,65,66,67,68,69, | |
180 | 70,71,72,73,74,75,76,77,78,79,80,81, | |
181 | 82,83,84,85,86 | |
182 | }; | |
183 | ||
184 | static u16 dib3000mc_fft_modes[][29] = { | |
185 | { 0x38, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c, | |
186 | 0x3ffe, 0x7f3, 0x2d94, 0x76, 0x53d, | |
187 | 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3, | |
188 | 0x3feb, 0x7d2, 0x365e, 0x76, 0x48c, | |
189 | 0x3ffe, 0x5b3, 0x3feb, 0x76, 0x0, 0xd | |
190 | }, /* fft mode 0 */ | |
191 | { 0x3b, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c, | |
192 | 0x3ffe, 0x7f3, 0x2d94, 0x76, 0x53d, | |
193 | 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3, | |
194 | 0x3feb, 0x7d2, 0x365e, 0x76, 0x48c, | |
195 | 0x3ffe, 0x5b3, 0x3feb, 0x0, 0x8200, 0xd | |
196 | }, /* fft mode 1 */ | |
197 | }; | |
198 | ||
199 | #define DIB3000MC_REG_UNK_88 ( 88) | |
200 | #define DIB3000MC_UNK_88 (0x0410) | |
201 | ||
202 | static u16 dib3000mc_reg_bw[] = { 93,94,95,96,97,98 }; | |
203 | static u16 dib3000mc_bw[][6] = { | |
204 | { 0,0,0,0,0,0 }, /* 5 MHz */ | |
205 | { 0,0,0,0,0,0 }, /* 6 MHz */ | |
206 | { 0,0,0,0,0,0 }, /* 7 MHz */ | |
207 | { 0x20, 0x21, 0x20, 0x23, 0x20, 0x27 }, /* 8 MHz */ | |
208 | }; | |
209 | ||
210 | ||
211 | /* phase noise control */ | |
212 | #define DIB3000MC_REG_UNK_99 ( 99) | |
213 | #define DIB3000MC_UNK_99 (0x0220) | |
214 | ||
215 | #define DIB3000MC_REG_SCAN_BOOST ( 100) | |
216 | #define DIB3000MC_SCAN_BOOST_ON ((11 << 6) + 6) | |
217 | #define DIB3000MC_SCAN_BOOST_OFF ((16 << 6) + 9) | |
218 | ||
219 | /* timeout ??? */ | |
220 | #define DIB3000MC_REG_UNK_110 ( 110) | |
221 | #define DIB3000MC_UNK_110 ( 3277) | |
222 | ||
223 | #define DIB3000MC_REG_UNK_111 ( 111) | |
224 | #define DIB3000MC_UNK_111_PH_N_MODE_0 ( 0) | |
225 | #define DIB3000MC_UNK_111_PH_N_MODE_1 (1 << 1) | |
226 | ||
227 | /* superious rm config */ | |
228 | #define DIB3000MC_REG_UNK_120 ( 120) | |
229 | #define DIB3000MC_UNK_120 ( 8207) | |
230 | ||
231 | #define DIB3000MC_REG_UNK_133 ( 133) | |
232 | #define DIB3000MC_UNK_133 ( 15564) | |
233 | ||
234 | #define DIB3000MC_REG_UNK_134 ( 134) | |
235 | #define DIB3000MC_UNK_134 ( 0) | |
236 | ||
237 | /* adapter config for constellation */ | |
238 | static u16 dib3000mc_reg_adp_cfg[] = { 129, 130, 131, 132 }; | |
239 | ||
240 | static u16 dib3000mc_adp_cfg[][4] = { | |
241 | { 0x99a, 0x7fae, 0x333, 0x7ff0 }, /* QPSK */ | |
242 | { 0x23d, 0x7fdf, 0x0a4, 0x7ff0 }, /* 16-QAM */ | |
243 | { 0x148, 0x7ff0, 0x0a4, 0x7ff8 }, /* 64-QAM */ | |
244 | }; | |
245 | ||
246 | static u16 dib3000mc_reg_mobile_mode[] = { 139, 140, 141, 175, 1032 }; | |
247 | ||
248 | static u16 dib3000mc_mobile_mode[][5] = { | |
249 | { 0x01, 0x0, 0x0, 0x00, 0x12c }, /* fixed */ | |
250 | { 0x01, 0x0, 0x0, 0x00, 0x12c }, /* portable */ | |
251 | { 0x00, 0x0, 0x0, 0x02, 0x000 }, /* mobile */ | |
252 | { 0x00, 0x0, 0x0, 0x02, 0x000 }, /* auto */ | |
253 | }; | |
254 | ||
255 | #define DIB3000MC_REG_DIVERSITY1 ( 177) | |
256 | #define DIB3000MC_DIVERSITY1_DEFAULT ( 1) | |
257 | ||
258 | #define DIB3000MC_REG_DIVERSITY2 ( 178) | |
259 | #define DIB3000MC_DIVERSITY2_DEFAULT ( 1) | |
260 | ||
261 | #define DIB3000MC_REG_DIVERSITY3 ( 180) | |
262 | #define DIB3000MC_DIVERSITY3_IN_OFF (0xfff0) | |
263 | #define DIB3000MC_DIVERSITY3_IN_ON (0xfff6) | |
264 | ||
265 | #define DIB3000MC_REG_FEC_CFG ( 195) | |
266 | #define DIB3000MC_FEC_CFG ( 0x10) | |
267 | ||
268 | /* | |
269 | * reg 206, output mode | |
270 | * 1111 1111 | |
271 | * |||| |||| | |
272 | * |||| |||+- unk | |
273 | * |||| ||+-- unk | |
274 | * |||| |+--- unk (on by default) | |
275 | * |||| +---- fifo_ctrl (1 = inhibit (flushed), 0 = active (unflushed)) | |
276 | * |||+------ pid_parse (1 = enabled, 0 = disabled) | |
277 | * ||+------- outp_188 (1 = TS packet size 188, 0 = packet size 204) | |
278 | * |+-------- unk | |
279 | * +--------- unk | |
280 | */ | |
281 | ||
282 | #define DIB3000MC_REG_SMO_MODE ( 206) | |
283 | #define DIB3000MC_SMO_MODE_DEFAULT (1 << 2) | |
284 | #define DIB3000MC_SMO_MODE_FIFO_FLUSH (1 << 3) | |
285 | #define DIB3000MC_SMO_MODE_FIFO_UNFLUSH (0xfff7) | |
286 | #define DIB3000MC_SMO_MODE_PID_PARSE (1 << 4) | |
287 | #define DIB3000MC_SMO_MODE_NO_PID_PARSE (0xffef) | |
288 | #define DIB3000MC_SMO_MODE_188 (1 << 5) | |
289 | #define DIB3000MC_SMO_MODE_SLAVE (DIB3000MC_SMO_MODE_DEFAULT | \ | |
290 | DIB3000MC_SMO_MODE_188 | DIB3000MC_SMO_MODE_PID_PARSE | (1<<1)) | |
291 | ||
292 | #define DIB3000MC_REG_FIFO_THRESHOLD ( 207) | |
293 | #define DIB3000MC_FIFO_THRESHOLD_DEFAULT ( 1792) | |
294 | #define DIB3000MC_FIFO_THRESHOLD_SLAVE ( 512) | |
295 | /* | |
296 | * pidfilter | |
297 | * it is not a hardware pidfilter but a filter which drops all pids | |
298 | * except the ones set. When connected to USB1.1 bandwidth this is important. | |
299 | * DiB3000P/M-C can filter up to 32 PIDs | |
300 | */ | |
301 | #define DIB3000MC_REG_FIRST_PID ( 212) | |
302 | #define DIB3000MC_NUM_PIDS ( 32) | |
303 | ||
304 | #define DIB3000MC_REG_OUTMODE ( 244) | |
305 | #define DIB3000MC_OM_PARALLEL_GATED_CLK ( 0) | |
306 | #define DIB3000MC_OM_PAR_CONT_CLK (1 << 11) | |
307 | #define DIB3000MC_OM_SERIAL (2 << 11) | |
308 | #define DIB3000MC_OM_DIVOUT_ON (4 << 11) | |
309 | #define DIB3000MC_OM_SLAVE (DIB3000MC_OM_DIVOUT_ON | DIB3000MC_OM_PAR_CONT_CLK) | |
310 | ||
311 | #define DIB3000MC_REG_RF_POWER ( 392) | |
312 | ||
313 | #define DIB3000MC_REG_FFT_POSITION ( 407) | |
314 | ||
315 | #define DIB3000MC_REG_DDS_FREQ_MSB ( 414) | |
316 | #define DIB3000MC_REG_DDS_FREQ_LSB ( 415) | |
317 | ||
318 | #define DIB3000MC_REG_TIMING_OFFS_MSB ( 416) | |
319 | #define DIB3000MC_REG_TIMING_OFFS_LSB ( 417) | |
320 | ||
321 | #define DIB3000MC_REG_TUNING_PARM ( 458) | |
322 | #define DIB3000MC_TP_QAM(v) ((v >> 13) & 0x03) | |
323 | #define DIB3000MC_TP_HRCH(v) ((v >> 12) & 0x01) | |
324 | #define DIB3000MC_TP_ALPHA(v) ((v >> 9) & 0x07) | |
325 | #define DIB3000MC_TP_FFT(v) ((v >> 8) & 0x01) | |
326 | #define DIB3000MC_TP_FEC_CR_HP(v) ((v >> 5) & 0x07) | |
327 | #define DIB3000MC_TP_FEC_CR_LP(v) ((v >> 2) & 0x07) | |
328 | #define DIB3000MC_TP_GUARD(v) (v & 0x03) | |
329 | ||
330 | #define DIB3000MC_REG_SIGNAL_NOISE_MSB ( 483) | |
331 | #define DIB3000MC_REG_SIGNAL_NOISE_LSB ( 484) | |
332 | ||
333 | #define DIB3000MC_REG_MER ( 485) | |
334 | ||
335 | #define DIB3000MC_REG_BER_MSB ( 500) | |
336 | #define DIB3000MC_REG_BER_LSB ( 501) | |
337 | ||
338 | #define DIB3000MC_REG_PACKET_ERRORS ( 503) | |
339 | ||
340 | #define DIB3000MC_REG_PACKET_ERROR_COUNT ( 506) | |
341 | ||
342 | #define DIB3000MC_REG_LOCK_507 ( 507) | |
343 | #define DIB3000MC_LOCK_507 (0x0002) // ? name correct ? | |
344 | ||
345 | #define DIB3000MC_REG_LOCKING ( 509) | |
346 | #define DIB3000MC_AGC_LOCK(v) (v & 0x8000) | |
347 | #define DIB3000MC_CARRIER_LOCK(v) (v & 0x2000) | |
348 | #define DIB3000MC_MPEG_SYNC_LOCK(v) (v & 0x0080) | |
349 | #define DIB3000MC_MPEG_DATA_LOCK(v) (v & 0x0040) | |
350 | #define DIB3000MC_TPS_LOCK(v) (v & 0x0004) | |
351 | ||
352 | #define DIB3000MC_REG_AS_IRQ ( 511) | |
353 | #define DIB3000MC_AS_IRQ_SUCCESS (1 << 1) | |
354 | #define DIB3000MC_AS_IRQ_FAIL ( 1) | |
355 | ||
356 | #define DIB3000MC_REG_TUNER ( 769) | |
357 | ||
358 | #define DIB3000MC_REG_RST_I2C_ADDR ( 1024) | |
359 | #define DIB3000MC_DEMOD_ADDR_ON ( 1) | |
360 | #define DIB3000MC_DEMOD_ADDR(a) ((a << 4) & 0x03F0) | |
361 | ||
362 | #define DIB3000MC_REG_RESTART ( 1027) | |
363 | #define DIB3000MC_RESTART_OFF (0x0000) | |
364 | #define DIB3000MC_RESTART_AGC (0x0800) | |
365 | #define DIB3000MC_RESTART_CONFIG (0x8000) | |
366 | ||
367 | #define DIB3000MC_REG_RESTART_VIT ( 1028) | |
368 | #define DIB3000MC_RESTART_VIT_OFF ( 0) | |
369 | #define DIB3000MC_RESTART_VIT_ON ( 1) | |
370 | ||
371 | #define DIB3000MC_REG_CLK_CFG_1 ( 1031) | |
372 | #define DIB3000MC_CLK_CFG_1_POWER_UP ( 0) | |
373 | #define DIB3000MC_CLK_CFG_1_POWER_DOWN (0xffff) | |
374 | ||
375 | #define DIB3000MC_REG_CLK_CFG_2 ( 1032) | |
376 | #define DIB3000MC_CLK_CFG_2_PUP_FIXED (0x012c) | |
377 | #define DIB3000MC_CLK_CFG_2_PUP_PORT (0x0104) | |
378 | #define DIB3000MC_CLK_CFG_2_PUP_MOBILE (0x0000) | |
379 | #define DIB3000MC_CLK_CFG_2_POWER_DOWN (0xffff) | |
380 | ||
381 | #define DIB3000MC_REG_CLK_CFG_3 ( 1033) | |
382 | #define DIB3000MC_CLK_CFG_3_POWER_UP ( 0) | |
383 | #define DIB3000MC_CLK_CFG_3_POWER_DOWN (0xfff5) | |
384 | ||
385 | #define DIB3000MC_REG_CLK_CFG_7 ( 1037) | |
386 | #define DIB3000MC_CLK_CFG_7_INIT ( 12592) | |
387 | #define DIB3000MC_CLK_CFG_7_POWER_UP (~0x0003) | |
388 | #define DIB3000MC_CLK_CFG_7_PWR_DOWN (0x0003) | |
389 | #define DIB3000MC_CLK_CFG_7_DIV_IN_OFF (1 << 8) | |
390 | ||
391 | /* was commented out ??? */ | |
392 | #define DIB3000MC_REG_CLK_CFG_8 ( 1038) | |
393 | #define DIB3000MC_CLK_CFG_8_POWER_UP (0x160c) | |
394 | ||
395 | #define DIB3000MC_REG_CLK_CFG_9 ( 1039) | |
396 | #define DIB3000MC_CLK_CFG_9_POWER_UP ( 0) | |
397 | ||
398 | /* also clock ??? */ | |
399 | #define DIB3000MC_REG_ELEC_OUT ( 1040) | |
400 | #define DIB3000MC_ELEC_OUT_HIGH_Z ( 0) | |
401 | #define DIB3000MC_ELEC_OUT_DIV_OUT_ON ( 1) | |
402 | #define DIB3000MC_ELEC_OUT_SLAVE ( 3) | |
403 | ||
404 | #endif |