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[media] DIB9000: initial support added
[deliverable/linux.git] / drivers / media / dvb / frontends / dib9000.c
CommitLineData
dd316c6b
OG		 1/*
2 * Linux-DVB Driver for DiBcom's DiB9000 and demodulator-family.
3 *
4 * Copyright (C) 2005-10 DiBcom (http://www.dibcom.fr/)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
9 */
10#include <linux/kernel.h>
11#include <linux/i2c.h>
12#include <linux/mutex.h>
13
14#include "dvb_math.h"
15#include "dvb_frontend.h"
16
17#include "dib9000.h"
18#include "dibx000_common.h"
19
20static int debug;
21module_param(debug, int, 0644);
22MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
23
24#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB9000: "); printk(args); printk("\n"); } } while (0)
25#define MAX_NUMBER_OF_FRONTENDS 6
26
27struct i2c_device {
28 struct i2c_adapter *i2c_adap;
29 u8 i2c_addr;
30};
31
32/* lock */
33#define DIB_LOCK struct mutex
34#define DibAcquireLock(lock) do { if (mutex_lock_interruptible(lock)<0) dprintk("could not get the lock"); } while (0)
35#define DibReleaseLock(lock) mutex_unlock(lock)
36#define DibInitLock(lock) mutex_init(lock)
37#define DibFreeLock(lock)
38
39struct dib9000_state {
40 struct i2c_device i2c;
41
42 struct dibx000_i2c_master i2c_master;
43 struct i2c_adapter tuner_adap;
44 struct i2c_adapter component_bus;
45
46 u16 revision;
47 u8 reg_offs;
48
49 enum frontend_tune_state tune_state;
50 u32 status;
51 struct dvb_frontend_parametersContext channel_status;
52
53 u8 fe_id;
54
55#define DIB9000_GPIO_DEFAULT_DIRECTIONS 0xffff
56 u16 gpio_dir;
57#define DIB9000_GPIO_DEFAULT_VALUES 0x0000
58 u16 gpio_val;
59#define DIB9000_GPIO_DEFAULT_PWM_POS 0xffff
60 u16 gpio_pwm_pos;
61
62 union { /* common for all chips */
63 struct {
64 u8 mobile_mode:1;
65 } host;
66
67 struct {
68 struct dib9000_fe_memory_map {
69 u16 addr;
70 u16 size;
71 } fe_mm[18];
72 u8 memcmd;
73
74 DIB_LOCK mbx_if_lock; /* to protect read/write operations */
75 DIB_LOCK mbx_lock; /* to protect the whole mailbox handling */
76
77 DIB_LOCK mem_lock; /* to protect the memory accesses */
78 DIB_LOCK mem_mbx_lock; /* to protect the memory-based mailbox */
79
80#define MBX_MAX_WORDS (256 - 200 - 2)
81#define DIB9000_MSG_CACHE_SIZE 2
82 u16 message_cache[DIB9000_MSG_CACHE_SIZE][MBX_MAX_WORDS];
83 u8 fw_is_running;
84 } risc;
85 } platform;
86
87 union { /* common for all platforms */
88 struct {
89 struct dib9000_config cfg;
90 } d9;
91 } chip;
92
93 struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
94 u16 component_bus_speed;
95};
96
97u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
98 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
99 0, 0, 0
100};
101
102enum dib9000_power_mode {
103 DIB9000_POWER_ALL = 0,
104
105 DIB9000_POWER_NO,
106 DIB9000_POWER_INTERF_ANALOG_AGC,
107 DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD,
108 DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD,
109 DIB9000_POWER_INTERFACE_ONLY,
110};
111
112enum dib9000_out_messages {
113 OUT_MSG_HBM_ACK,
114 OUT_MSG_HOST_BUF_FAIL,
115 OUT_MSG_REQ_VERSION,
116 OUT_MSG_BRIDGE_I2C_W,
117 OUT_MSG_BRIDGE_I2C_R,
118 OUT_MSG_BRIDGE_APB_W,
119 OUT_MSG_BRIDGE_APB_R,
120 OUT_MSG_SCAN_CHANNEL,
121 OUT_MSG_MONIT_DEMOD,
122 OUT_MSG_CONF_GPIO,
123 OUT_MSG_DEBUG_HELP,
124 OUT_MSG_SUBBAND_SEL,
125 OUT_MSG_ENABLE_TIME_SLICE,
126 OUT_MSG_FE_FW_DL,
127 OUT_MSG_FE_CHANNEL_SEARCH,
128 OUT_MSG_FE_CHANNEL_TUNE,
129 OUT_MSG_FE_SLEEP,
130 OUT_MSG_FE_SYNC,
131 OUT_MSG_CTL_MONIT,
132
133 OUT_MSG_CONF_SVC,
134 OUT_MSG_SET_HBM,
135 OUT_MSG_INIT_DEMOD,
136 OUT_MSG_ENABLE_DIVERSITY,
137 OUT_MSG_SET_OUTPUT_MODE,
138 OUT_MSG_SET_PRIORITARY_CHANNEL,
139 OUT_MSG_ACK_FRG,
140 OUT_MSG_INIT_PMU,
141};
142
143enum dib9000_in_messages {
144 IN_MSG_DATA,
145 IN_MSG_FRAME_INFO,
146 IN_MSG_CTL_MONIT,
147 IN_MSG_ACK_FREE_ITEM,
148 IN_MSG_DEBUG_BUF,
149 IN_MSG_MPE_MONITOR,
150 IN_MSG_RAWTS_MONITOR,
151 IN_MSG_END_BRIDGE_I2C_RW,
152 IN_MSG_END_BRIDGE_APB_RW,
153 IN_MSG_VERSION,
154 IN_MSG_END_OF_SCAN,
155 IN_MSG_MONIT_DEMOD,
156 IN_MSG_ERROR,
157 IN_MSG_FE_FW_DL_DONE,
158 IN_MSG_EVENT,
159 IN_MSG_ACK_CHANGE_SVC,
160 IN_MSG_HBM_PROF,
161};
162
163/* memory_access requests */
164#define FE_MM_W_CHANNEL 0
165#define FE_MM_W_FE_INFO 1
166#define FE_MM_RW_SYNC 2
167
168#define FE_SYNC_CHANNEL 1
169#define FE_SYNC_W_GENERIC_MONIT 2
170#define FE_SYNC_COMPONENT_ACCESS 3
171
172#define FE_MM_R_CHANNEL_SEARCH_STATE 3
173#define FE_MM_R_CHANNEL_UNION_CONTEXT 4
174#define FE_MM_R_FE_INFO 5
175#define FE_MM_R_FE_MONITOR 6
176
177#define FE_MM_W_CHANNEL_HEAD 7
178#define FE_MM_W_CHANNEL_UNION 8
179#define FE_MM_W_CHANNEL_CONTEXT 9
180#define FE_MM_R_CHANNEL_UNION 10
181#define FE_MM_R_CHANNEL_CONTEXT 11
182#define FE_MM_R_CHANNEL_TUNE_STATE 12
183
184#define FE_MM_R_GENERIC_MONITORING_SIZE 13
185#define FE_MM_W_GENERIC_MONITORING 14
186#define FE_MM_R_GENERIC_MONITORING 15
187
188#define FE_MM_W_COMPONENT_ACCESS 16
189#define FE_MM_RW_COMPONENT_ACCESS_BUFFER 17
190static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen,
191 u8 * b, u32 len);
192static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len);
193
194static u16 to_fw_output_mode(u16 mode)
195{
196 switch (mode) {
197 case OUTMODE_HIGH_Z:
198 return 0;
199 case OUTMODE_MPEG2_PAR_GATED_CLK:
200 return 4;
201 case OUTMODE_MPEG2_PAR_CONT_CLK:
202 return 8;
203 case OUTMODE_MPEG2_SERIAL:
204 return 16;
205 case OUTMODE_DIVERSITY:
206 return 128;
207 case OUTMODE_MPEG2_FIFO:
208 return 2;
209 case OUTMODE_ANALOG_ADC:
210 return 1;
211 default:
212 return 0;
213 }
214}
215
216static u16 dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 * b, u32 len, u16 attribute)
217{
218 u32 chunk_size = 126;
219 u32 l;
220 int ret;
221 u8 wb[2] = { reg >> 8, reg & 0xff };
222 struct i2c_msg msg[2] = {
223 {.addr = state->i2c.i2c_addr >> 1,.flags = 0,.buf = wb,.len = 2},
224 {.addr = state->i2c.i2c_addr >> 1,.flags = I2C_M_RD,.buf = b,.len = len},
225 };
226
227 if (state->platform.risc.fw_is_running && (reg < 1024))
228 return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len);
229
230 if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
231 wb[0] |= (1 << 5);
232 if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
233 wb[0] |= (1 << 4);
234
235 do {
236 l = len < chunk_size ? len : chunk_size;
237 msg[1].len = l;
238 msg[1].buf = b;
239 ret = i2c_transfer(state->i2c.i2c_adap, msg, 2) != 2 ? -EREMOTEIO : 0;
240 if (ret != 0) {
241 dprintk("i2c read error on %d", reg);
242 return -EREMOTEIO;
243 }
244
245 b += l;
246 len -= l;
247
248 if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
249 reg += l / 2;
250 } while ((ret == 0) && len);
251
252 return 0;
253}
254
255static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg)
256{
257 u8 b[2];
258 u8 wb[2] = { reg >> 8, reg & 0xff };
259 struct i2c_msg msg[2] = {
260 {.addr = i2c->i2c_addr >> 1,.flags = 0,.buf = wb,.len = 2},
261 {.addr = i2c->i2c_addr >> 1,.flags = I2C_M_RD,.buf = b,.len = 2},
262 };
263
264 if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) {
265 dprintk("read register %x error", reg);
266 return 0;
267 }
268
269 return (b[0] << 8) | b[1];
270}
271
272static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg)
273{
274 u8 b[2];
275 if (dib9000_read16_attr(state, reg, b, 2, 0) != 0)
276 return 0;
277 return (b[0] << 8 | b[1]);
278}
279
280static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute)
281{
282 u8 b[2];
283 if (dib9000_read16_attr(state, reg, b, 2, attribute) != 0)
284 return 0;
285 return (b[0] << 8 | b[1]);
286}
287
288#define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
289
290static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * buf, u32 len, u16 attribute)
291{
292 u8 b[255];
293 u32 chunk_size = 126;
294 u32 l;
295 int ret;
296
297 struct i2c_msg msg = {
298 .addr = state->i2c.i2c_addr >> 1,.flags = 0,.buf = b,.len = len + 2
299 };
300
301 if (state->platform.risc.fw_is_running && (reg < 1024)) {
302 if (dib9000_risc_apb_access_write
303 (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0)
304 return -EINVAL;
305 return 0;
306 }
307
308 b[0] = (reg >> 8) & 0xff;
309 b[1] = (reg) & 0xff;
310
311 if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
312 b[0] |= (1 << 5);
313 if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
314 b[0] |= (1 << 4);
315
316 do {
317 l = len < chunk_size ? len : chunk_size;
318 msg.len = l + 2;
319 memcpy(&b[2], buf, l);
320
321 ret = i2c_transfer(state->i2c.i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
322
323 buf += l;
324 len -= l;
325
326 if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
327 reg += l / 2;
328 } while ((ret == 0) && len);
329
330 return ret;
331}
332
333static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
334{
335 u8 b[4] = { (reg >> 8) & 0xff, reg & 0xff, (val >> 8) & 0xff, val & 0xff };
336 struct i2c_msg msg = {
337 .addr = i2c->i2c_addr >> 1,.flags = 0,.buf = b,.len = 4
338 };
339
340 return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
341}
342
343static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val)
344{
345 u8 b[2] = { val >> 8, val & 0xff };
346 return dib9000_write16_attr(state, reg, b, 2, 0);
347}
348
349static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute)
350{
351 u8 b[2] = { val >> 8, val & 0xff };
352 return dib9000_write16_attr(state, reg, b, 2, attribute);
353}
354
355#define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0)
356#define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
357#define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute))
358
359#define dib9000_mbx_send(state, id, data, len) dib9000_mbx_send_attr(state, id, data, len, 0)
360#define dib9000_mbx_get_message(state, id, msg, len) dib9000_mbx_get_message_attr(state, id, msg, len, 0)
361
362#define MAC_IRQ (1 << 1)
363#define IRQ_POL_MSK (1 << 4)
364
365#define dib9000_risc_mem_read_chunks(state, b, len) dib9000_read16_attr(state, 1063, b, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
366#define dib9000_risc_mem_write_chunks(state, buf, len) dib9000_write16_attr(state, 1063, buf, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
367
368static void dib9000_risc_mem_setup_cmd(struct dib9000_state *state, u32 addr, u32 len, u8 reading)
369{
370 u8 b[14] = { 0 };
371
372// dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len);
373// b[0] = 0 << 7;
374 b[1] = 1;
375
376// b[2] = 0; // 1057
377// b[3] = 0;
378 b[4] = (u8) (addr >> 8); // 1058
379 b[5] = (u8) (addr & 0xff);
380
381// b[10] = 0; // 1061
382// b[11] = 0;
383 b[12] = (u8) (addr >> 8); // 1062
384 b[13] = (u8) (addr & 0xff);
385
386 addr += len;
387// b[6] = 0; // 1059
388// b[7] = 0;
389 b[8] = (u8) (addr >> 8); // 1060
390 b[9] = (u8) (addr & 0xff);
391
392 dib9000_write(state, 1056, b, 14);
393 if (reading)
394 dib9000_write_word(state, 1056, (1 << 15) | 1);
395 state->platform.risc.memcmd = -1; /* if it was called directly reset it - to force a future setup-call to set it */
396}
397
398static void dib9000_risc_mem_setup(struct dib9000_state *state, u8 cmd)
399{
400 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f];
401 /* decide whether we need to "refresh" the memory controller */
402 if (state->platform.risc.memcmd == cmd && /* same command */
403 !(cmd & 0x80 && m->size < 67)) /* and we do not want to read something with less than 67 bytes looping - working around a bug in the memory controller */
404 return;
405 dib9000_risc_mem_setup_cmd(state, m->addr, m->size, cmd & 0x80);
406 state->platform.risc.memcmd = cmd;
407}
408
409static int dib9000_risc_mem_read(struct dib9000_state *state, u8 cmd, u8 * b, u16 len)
410{
411 if (!state->platform.risc.fw_is_running)
412 return -EIO;
413
414 DibAcquireLock(&state->platform.risc.mem_lock);
415 dib9000_risc_mem_setup(state, cmd | 0x80);
416 dib9000_risc_mem_read_chunks(state, b, len);
417 DibReleaseLock(&state->platform.risc.mem_lock);
418 return 0;
419}
420
421static int dib9000_risc_mem_write(struct dib9000_state *state, u8 cmd, const u8 * b)
422{
423 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd];
424 if (!state->platform.risc.fw_is_running)
425 return -EIO;
426
427 DibAcquireLock(&state->platform.risc.mem_lock);
428 dib9000_risc_mem_setup(state, cmd);
429 dib9000_risc_mem_write_chunks(state, b, m->size);
430 DibReleaseLock(&state->platform.risc.mem_lock);
431 return 0;
432}
433
434static int dib9000_firmware_download(struct dib9000_state *state, u8 risc_id, u16 key, const u8 * code, u32 len)
435{
436 u16 offs;
437
438 if (risc_id == 1)
439 offs = 16;
440 else
441 offs = 0;
442
443 /* config crtl reg */
444 dib9000_write_word(state, 1024 + offs, 0x000f);
445 dib9000_write_word(state, 1025 + offs, 0);
446 dib9000_write_word(state, 1031 + offs, key);
447
448 dprintk("going to download %dB of microcode", len);
449 if (dib9000_write16_noinc(state, 1026 + offs, (u8 *) code, (u16) len) != 0) {
450 dprintk("error while downloading microcode for RISC %c", 'A' + risc_id);
451 return -EIO;
452 }
453
454 dprintk("Microcode for RISC %c loaded", 'A' + risc_id);
455
456 return 0;
457}
458
459static int dib9000_mbx_host_init(struct dib9000_state *state, u8 risc_id)
460{
461 u16 mbox_offs;
462 u16 reset_reg;
463 u16 tries = 1000;
464
465 if (risc_id == 1)
466 mbox_offs = 16;
467 else
468 mbox_offs = 0;
469
470 /* Reset mailbox */
471 dib9000_write_word(state, 1027 + mbox_offs, 0x8000);
472
473 /* Read reset status */
474 do {
475 reset_reg = dib9000_read_word(state, 1027 + mbox_offs);
476 msleep(100);
477 } while ((reset_reg & 0x8000) && --tries);
478
479 if (reset_reg & 0x8000) {
480 dprintk("MBX: init ERROR, no response from RISC %c", 'A' + risc_id);
481 return -EIO;
482 }
483 dprintk("MBX: initialized");
484 return 0;
485}
486
487#define MAX_MAILBOX_TRY 100
488static int dib9000_mbx_send_attr(struct dib9000_state *state, u8 id, u16 * data, u8 len, u16 attr)
489{
490 u8 ret = 0, *d, b[2];
491 u16 tmp;
492 u16 size;
493 u32 i;
494
495 if (!state->platform.risc.fw_is_running)
496 return -EINVAL;
497
498 DibAcquireLock(&state->platform.risc.mbx_if_lock);
499 tmp = MAX_MAILBOX_TRY;
500 do {
501 size = dib9000_read_word_attr(state, 1043, attr) & 0xff;
502 if ((size + len + 1) > MBX_MAX_WORDS && --tmp) {
503 dprintk("MBX: RISC mbx full, retrying");
504 msleep(100);
505 } else
506 break;
507 } while (1);
508
509 //dprintk( "MBX: size: %d", size);
510
511 if (tmp == 0) {
512 ret = -EINVAL;
513 goto out;
514 }
515#ifdef DUMP_MSG
516 dprintk("--> %02x %d ", id, len + 1);
517 for (i = 0; i < len; i++)
518 dprintk("%04x ", data[i]);
519 dprintk("\n");
520#endif
521
522 /* byte-order conversion - works on big (where it is not necessary) or little endian */
523 d = (u8 *) data;
524 for (i = 0; i < len; i++) {
525 tmp = data[i];
526 *d++ = tmp >> 8;
527 *d++ = tmp & 0xff;
528 }
529
530 /* write msg */
531 b[0] = id;
532 b[1] = len + 1;
533 if (dib9000_write16_noinc_attr(state, 1045, b, 2, attr) != 0 || dib9000_write16_noinc_attr(state, 1045, (u8 *) data, len * 2, attr) != 0) {
534 ret = -EIO;
535 goto out;
536 }
537
538 /* update register nb_mes_in_RX */
539 ret = (u8) dib9000_write_word_attr(state, 1043, 1 << 14, attr);
540
541 out:
542 DibReleaseLock(&state->platform.risc.mbx_if_lock);
543
544 return ret;
545}
546
547static u8 dib9000_mbx_read(struct dib9000_state *state, u16 * data, u8 risc_id, u16 attr)
548{
549#ifdef DUMP_MSG
550 u16 *d = data;
551#endif
552
553 u16 tmp, i;
554 u8 size;
555 u8 mc_base;
556
557 if (!state->platform.risc.fw_is_running)
558 return 0;
559
560 DibAcquireLock(&state->platform.risc.mbx_if_lock);
561 if (risc_id == 1)
562 mc_base = 16;
563 else
564 mc_base = 0;
565
566 /* Length and type in the first word */
567 *data = dib9000_read_word_attr(state, 1029 + mc_base, attr);
568
569 size = *data & 0xff;
570 if (size <= MBX_MAX_WORDS) {
571 data++;
572 size--; /* Initial word already read */
573
574 dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, size * 2, attr);
575
576 /* to word conversion */
577 for (i = 0; i < size; i++) {
578 tmp = *data;
579 *data = (tmp >> 8) | (tmp << 8);
580 data++;
581 }
582
583#ifdef DUMP_MSG
584 dprintk("<-- ");
585 for (i = 0; i < size + 1; i++)
586 dprintk("%04x ", d[i]);
587 dprintk("\n");
588#endif
589 } else {
590 dprintk("MBX: message is too big for message cache (%d), flushing message", size);
591 size--; /* Initial word already read */
592 while (size--)
593 dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, 2, attr);
594 }
595 /* Update register nb_mes_in_TX */
596 dib9000_write_word_attr(state, 1028 + mc_base, 1 << 14, attr);
597
598 DibReleaseLock(&state->platform.risc.mbx_if_lock);
599
600 return size + 1;
601}
602
603static int dib9000_risc_debug_buf(struct dib9000_state *state, u16 * data, u8 size)
604{
605 u32 ts = data[1] << 16 | data[0];
606 char *b = (char *)&data[2];
607
608 b[2 * (size - 2) - 1] = '\0'; /* Bullet proof the buffer */
609 if (*b == '~') {
610 b++;
611 dprintk(b);
612 } else
613 dprintk("RISC%d: %d.%04d %s", state->fe_id, ts / 10000, ts % 10000, *b ? b : "<emtpy>");
614 return 1;
615}
616
617static int dib9000_mbx_fetch_to_cache(struct dib9000_state *state, u16 attr)
618{
619 int i;
620 u8 size;
621 u16 *block;
622 /* find a free slot */
623 for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
624 block = state->platform.risc.message_cache[i];
625 if (*block == 0) {
626 size = dib9000_mbx_read(state, block, 1, attr);
627
628// dprintk( "MBX: fetched %04x message to cache", *block);
629
630 switch (*block >> 8) {
631 case IN_MSG_DEBUG_BUF:
632 dib9000_risc_debug_buf(state, block + 1, size); /* debug-messages are going to be printed right away */
633 *block = 0; /* free the block */
634 break;
635#if 0
636 case IN_MSG_DATA: /* FE-TRACE */
637 dib9000_risc_data_process(state, block + 1, size);
638 *block = 0;
639 break;
640#endif
641 default:
642 break;
643 }
644
645 return 1;
646 }
647 }
648 dprintk("MBX: no free cache-slot found for new message...");
649 return -1;
650}
651
652static u8 dib9000_mbx_count(struct dib9000_state *state, u8 risc_id, u16 attr)
653{
654 if (risc_id == 0)
655 return (u8) (dib9000_read_word_attr(state, 1028, attr) >> 10) & 0x1f; /* 5 bit field */
656 else
657 return (u8) (dib9000_read_word_attr(state, 1044, attr) >> 8) & 0x7f; /* 7 bit field */
658}
659
660static int dib9000_mbx_process(struct dib9000_state *state, u16 attr)
661{
662 int ret = 0;
663 u16 tmp;
664
665 if (!state->platform.risc.fw_is_running)
666 return -1;
667
668 DibAcquireLock(&state->platform.risc.mbx_lock);
669
670 if (dib9000_mbx_count(state, 1, attr)) /* 1=RiscB */
671 ret = dib9000_mbx_fetch_to_cache(state, attr);
672
673 tmp = dib9000_read_word_attr(state, 1229, attr); /* Clear the IRQ */
674// if (tmp)
675// dprintk( "cleared IRQ: %x", tmp);
676 DibReleaseLock(&state->platform.risc.mbx_lock);
677
678 return ret;
679}
680
681static int dib9000_mbx_get_message_attr(struct dib9000_state *state, u16 id, u16 * msg, u8 * size, u16 attr)
682{
683 u8 i;
684 u16 *block;
685 u16 timeout = 30;
686
687 *msg = 0;
688 do {
689 /* dib9000_mbx_get_from_cache(); */
690 for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
691 block = state->platform.risc.message_cache[i];
692 if ((*block >> 8) == id) {
693 *size = (*block & 0xff) - 1;
694 memcpy(msg, block + 1, (*size) * 2);
695 *block = 0; /* free the block */
696 i = 0; /* signal that we found a message */
697 break;
698 }
699 }
700
701 if (i == 0)
702 break;
703
704 if (dib9000_mbx_process(state, attr) == -1) /* try to fetch one message - if any */
705 return -1;
706
707 } while (--timeout);
708
709 if (timeout == 0) {
710 dprintk("waiting for message %d timed out", id);
711 return -1;
712 }
713
714 return i == 0;
715}
716
717static int dib9000_risc_check_version(struct dib9000_state *state)
718{
719 u8 r[4];
720 u8 size;
721 u16 fw_version = 0;
722
723 if (dib9000_mbx_send(state, OUT_MSG_REQ_VERSION, &fw_version, 1) != 0)
724 return -EIO;
725
726 if (dib9000_mbx_get_message(state, IN_MSG_VERSION, (u16 *) r, &size) < 0)
727 return -EIO;
728
729 fw_version = (r[0] << 8) | r[1];
730 dprintk("RISC: ver: %d.%02d (IC: %d)", fw_version >> 10, fw_version & 0x3ff, (r[2] << 8) | r[3]);
731
732 if ((fw_version >> 10) != 7)
733 return -EINVAL;
734
735 switch (fw_version & 0x3ff) {
736 case 11:
737 case 12:
738 case 14:
739 case 15:
740 case 16:
741 case 17:
742 break;
743 default:
744 dprintk("RISC: invalid firmware version");
745 return -EINVAL;
746 }
747
748 dprintk("RISC: valid firmware version");
749 return 0;
750}
751
752static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB)
753{
754 /* Reconfig pool mac ram */
755 dib9000_write_word(state, 1225, 0x02); /* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */
756 dib9000_write_word(state, 1226, 0x05);
757
758 /* Toggles IP crypto to Host APB interface. */
759 dib9000_write_word(state, 1542, 1);
760
761 /* Set jump and no jump in the dma box */
762 dib9000_write_word(state, 1074, 0);
763 dib9000_write_word(state, 1075, 0);
764
765 /* Set MAC as APB Master. */
766 dib9000_write_word(state, 1237, 0);
767
768 /* Reset the RISCs */
769 if (codeA != NULL)
770 dib9000_write_word(state, 1024, 2);
771 else
772 dib9000_write_word(state, 1024, 15);
773 if (codeB != NULL)
774 dib9000_write_word(state, 1040, 2);
775
776 if (codeA != NULL)
777 dib9000_firmware_download(state, 0, 0x1234, codeA, lenA);
778 if (codeB != NULL)
779 dib9000_firmware_download(state, 1, 0x1234, codeB, lenB);
780
781 /* Run the RISCs */
782 if (codeA != NULL)
783 dib9000_write_word(state, 1024, 0);
784 if (codeB != NULL)
785 dib9000_write_word(state, 1040, 0);
786
787 if (codeA != NULL)
788 if (dib9000_mbx_host_init(state, 0) != 0)
789 return -EIO;
790 if (codeB != NULL)
791 if (dib9000_mbx_host_init(state, 1) != 0)
792 return -EIO;
793
794 msleep(100);
795 state->platform.risc.fw_is_running = 1;
796
797 if (dib9000_risc_check_version(state) != 0)
798 return -EINVAL;
799
800 state->platform.risc.memcmd = 0xff;
801 return 0;
802}
803
804static u16 dib9000_identify(struct i2c_device *client)
805{
806 u16 value;
807
808 if ((value = dib9000_i2c_read16(client, 896)) != 0x01b3) {
809 dprintk("wrong Vendor ID (0x%x)", value);
810 return 0;
811 }
812
813 value = dib9000_i2c_read16(client, 897);
814 if (value != 0x4000 && value != 0x4001 && value != 0x4002 && value != 0x4003 && value != 0x4004 && value != 0x4005) {
815 dprintk("wrong Device ID (0x%x)", value);
816 return 0;
817 }
818
819 /* protect this driver to be used with 7000PC */
820 if (value == 0x4000 && dib9000_i2c_read16(client, 769) == 0x4000) {
821 dprintk("this driver does not work with DiB7000PC");
822 return 0;
823 }
824
825 switch (value) {
826 case 0x4000:
827 dprintk("found DiB7000MA/PA/MB/PB");
828 break;
829 case 0x4001:
830 dprintk("found DiB7000HC");
831 break;
832 case 0x4002:
833 dprintk("found DiB7000MC");
834 break;
835 case 0x4003:
836 dprintk("found DiB9000A");
837 break;
838 case 0x4004:
839 dprintk("found DiB9000H");
840 break;
841 case 0x4005:
842 dprintk("found DiB9000M");
843 break;
844 }
845
846 return value;
847}
848
849static void dib9000_set_power_mode(struct dib9000_state *state, enum dib9000_power_mode mode)
850{
851 /* by default everything is going to be powered off */
852 u16 reg_903 = 0x3fff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906;
853 u8 offset;
854
855 if (state->revision == 0x4003 || state->revision == 0x4004 || state->revision == 0x4005)
856 offset = 1;
857 else
858 offset = 0;
859
860 reg_906 = dib9000_read_word(state, 906 + offset) | 0x3; /* keep settings for RISC */
861
862 /* now, depending on the requested mode, we power on */
863 switch (mode) {
864 /* power up everything in the demod */
865 case DIB9000_POWER_ALL:
866 reg_903 = 0x0000;
867 reg_904 = 0x0000;
868 reg_905 = 0x0000;
869 reg_906 = 0x0000;
870 break;
871
872 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */
873 case DIB9000_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C or SRAM */
874 reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
875 break;
876
877 case DIB9000_POWER_INTERF_ANALOG_AGC:
878 reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
879 reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
880 reg_906 &= ~((1 << 0));
881 break;
882
883 case DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD:
884 reg_903 = 0x0000;
885 reg_904 = 0x801f;
886 reg_905 = 0x0000;
887 reg_906 &= ~((1 << 0));
888 break;
889
890 case DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD:
891 reg_903 = 0x0000;
892 reg_904 = 0x8000;
893 reg_905 = 0x010b;
894 reg_906 &= ~((1 << 0));
895 break;
896 default:
897 case DIB9000_POWER_NO:
898 break;
899 }
900
901 /* always power down unused parts */
902 if (!state->platform.host.mobile_mode)
903 reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
904
905 /* P_sdio_select_clk = 0 on MC and after */
906 if (state->revision != 0x4000)
907 reg_906 <<= 1;
908
909 dib9000_write_word(state, 903 + offset, reg_903);
910 dib9000_write_word(state, 904 + offset, reg_904);
911 dib9000_write_word(state, 905 + offset, reg_905);
912 dib9000_write_word(state, 906 + offset, reg_906);
913}
914
915static int dib9000_fw_reset(struct dvb_frontend *fe)
916{
917 struct dib9000_state *state = fe->demodulator_priv;
918
919 dib9000_write_word(state, 1817, 0x0003); // SRAM read lead in + P_host_rdy_cmos=1
920
921 dib9000_write_word(state, 1227, 1);
922 dib9000_write_word(state, 1227, 0);
923
924 switch ((state->revision = dib9000_identify(&state->i2c))) {
925 case 0x4003:
926 case 0x4004:
927 case 0x4005:
928 state->reg_offs = 1;
929 break;
930 default:
931 return -EINVAL;
932 }
933
934 /* reset the i2c-master to use the host interface */
935 dibx000_reset_i2c_master(&state->i2c_master);
936
937 dib9000_set_power_mode(state, DIB9000_POWER_ALL);
938
939 /* unforce divstr regardless whether i2c enumeration was done or not */
940 dib9000_write_word(state, 1794, dib9000_read_word(state, 1794) & ~(1 << 1));
941 dib9000_write_word(state, 1796, 0);
942 dib9000_write_word(state, 1805, 0x805);
943
944 /* restart all parts */
945 dib9000_write_word(state, 898, 0xffff);
946 dib9000_write_word(state, 899, 0xffff);
947 dib9000_write_word(state, 900, 0x0001);
948 dib9000_write_word(state, 901, 0xff19);
949 dib9000_write_word(state, 902, 0x003c);
950
951 dib9000_write_word(state, 898, 0);
952 dib9000_write_word(state, 899, 0);
953 dib9000_write_word(state, 900, 0);
954 dib9000_write_word(state, 901, 0);
955 dib9000_write_word(state, 902, 0);
956
957 dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives);
958
959 dib9000_set_power_mode(state, DIB9000_POWER_INTERFACE_ONLY);
960
961 return 0;
962}
963
964static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen,
965 u8 * b, u32 len)
966{
967 u16 mb[10];
968 u8 i, s;
969
970 if (address >= 1024 || !state->platform.risc.fw_is_running)
971 return -EINVAL;
972
973 //dprintk( "APB access thru rd fw %d %x", address, attribute);
974
975 mb[0] = (u16) address;
976 mb[1] = len / 2;
977 dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_R, mb, 2, attribute);
978 switch (dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute)) {
979 case 1:
980 s--; // address
981 for (i = 0; i < s; i++) {
982 b[i * 2] = (mb[i + 1] >> 8) & 0xff;
983 b[i * 2 + 1] = (mb[i + 1]) & 0xff;
984 }
985 return 0;
986 default:
987 return -EIO;
988 }
989 return -EIO;
990}
991
992static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len)
993{
994 u16 mb[10];
995 u8 s, i;
996
997 if (address >= 1024 || !state->platform.risc.fw_is_running)
998 return -EINVAL;
999
1000 //dprintk( "APB access thru wr fw %d %x", address, attribute);
1001
1002 mb[0] = (unsigned short)address;
1003 for (i = 0; i < len && i < 20; i += 2) // 20 bytes max
1004 mb[1 + (i / 2)] = (b[i] << 8 | b[i + 1]);
1005
1006 dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_W, mb, 1 + len / 2, attribute);
1007 return dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute) == 1 ? 0 : -EINVAL;
1008}
1009
1010static int dib9000_fw_memmbx_sync(struct dib9000_state *state, u8 i)
1011{
1012 u8 index_loop = 10;
1013
1014 if (!state->platform.risc.fw_is_running)
1015 return 0;
1016 dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i);
1017 do {
1018 dib9000_risc_mem_read(state, FE_MM_RW_SYNC, &i, 1);
1019 } while (i && index_loop--);
1020
1021 if (index_loop > 0)
1022 return 0;
1023 return -EIO;
1024}
1025
1026static int dib9000_fw_init(struct dib9000_state *state)
1027{
1028 struct dibGPIOFunction *f;
1029 u16 b[40] = { 0 };
1030 u8 i;
1031 u8 size;
1032
1033 if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0)
1034 //if (dib9000_fw_boot(state, microcode_A_buffer, microcode_A_size, microcode_B_buffer, microcode_B_size) != 0)
1035 return -EIO;
1036
1037 /* initialize the firmware */
1038 for (i = 0; i < ARRAY_SIZE(state->chip.d9.cfg.gpio_function); i++) {
1039 f = &state->chip.d9.cfg.gpio_function[i];
1040 if (f->mask) {
1041 switch (f->function) {
1042 case BOARD_GPIO_FUNCTION_COMPONENT_ON:
1043 b[0] = (u16) f->mask;
1044 b[1] = (u16) f->direction;
1045 b[2] = (u16) f->value;
1046 break;
1047 case BOARD_GPIO_FUNCTION_COMPONENT_OFF:
1048 b[3] = (u16) f->mask;
1049 b[4] = (u16) f->direction;
1050 b[5] = (u16) f->value;
1051 break;
1052 }
1053 }
1054 }
1055 if (dib9000_mbx_send(state, OUT_MSG_CONF_GPIO, b, 15) != 0)
1056 return -EIO;
1057
1058 /* subband */
1059 b[0] = state->chip.d9.cfg.subband.size; /* type == 0 -> GPIO - PWM not yet supported */
1060 for (i = 0; i < state->chip.d9.cfg.subband.size; i++) {
1061 b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz;
1062 b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask;
1063 b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction;
1064 b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value;
1065 //dprintk( "SBS: %d %d %x %x %x\n", i, b[1 + i*4], b[2 + i*4], b[3 + i*4], b[4 + i*4]);
1066 }
1067 b[1 + i * 4] = 0; /* fe_id */
1068 if (dib9000_mbx_send(state, OUT_MSG_SUBBAND_SEL, b, 2 + 4 * i) != 0)
1069 return -EIO;
1070
1071 /* 0 - id, 1 - no_of_frontends */
1072 b[0] = (0 << 8) | 1;
1073 /* 0 = i2c-address demod, 0 = tuner */
1074 b[1] = (0 << 8) | (0); //st->i2c_addr ) );
1075 b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff);
1076 b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff);
1077 b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff);
1078 b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff);
1079 b[6] = (u16) ((state->chip.d9.cfg.timing_frequency >> 16) & 0xffff);
1080 b[7] = (u16) ((state->chip.d9.cfg.timing_frequency) & 0xffff);
1081 b[29] = state->chip.d9.cfg.if_drives;
1082 if (dib9000_mbx_send(state, OUT_MSG_INIT_DEMOD, b, ARRAY_SIZE(b)) != 0)
1083 return -EIO;
1084
1085 if (dib9000_mbx_send(state, OUT_MSG_FE_FW_DL, NULL, 0) != 0)
1086 return -EIO;
1087
1088 if (dib9000_mbx_get_message(state, IN_MSG_FE_FW_DL_DONE, b, &size) < 0)
1089 return -EIO;
1090
1091 if (size > ARRAY_SIZE(b)) {
1092 dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size, (int)ARRAY_SIZE(b));
1093 return -EINVAL;
1094 }
1095
1096 for (i = 0; i < size; i += 2) {
1097 state->platform.risc.fe_mm[i / 2].addr = b[i + 0];
1098 state->platform.risc.fe_mm[i / 2].size = b[i + 1];
1099 //dprintk( "MM: %d %d %d", state->platform.risc.fe_mm[i/2].addr, state->platform.risc.fe_mm[i/2].size, ARRAY_SIZE(state->platform.risc.fe_mm));
1100 }
1101
1102 return 0;
1103}
1104
1105static void dib9000_fw_set_channel_head(struct dib9000_state *state, struct dvb_frontend_parameters *ch)
1106{
1107 u8 b[9];
1108 u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000;
1109 if (state->fe_id % 2)
1110 freq += 101;
1111
1112 b[0] = (u8) ((freq >> 0) & 0xff);
1113 b[1] = (u8) ((freq >> 8) & 0xff);
1114 b[2] = (u8) ((freq >> 16) & 0xff);
1115 b[3] = (u8) ((freq >> 24) & 0xff);
1116 b[4] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 0) & 0xff);
1117 b[5] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 8) & 0xff);
1118 b[6] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 16) & 0xff);
1119 b[7] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 24) & 0xff);
1120 b[8] = 0x80; /* do not wait for CELL ID when doing autosearch */
1121 if (state->fe[0]->dtv_property_cache.delivery_system == SYS_DVBT)
1122 b[8] |= 1;
1123 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b);
1124}
1125
1126static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel)
1127{
1128 struct dib9000_state *state = fe->demodulator_priv;
1129 struct dibDVBTChannel {
1130 s8 spectrum_inversion;
1131
1132 s8 nfft;
1133 s8 guard;
1134 s8 constellation;
1135
1136 s8 hrch;
1137 s8 alpha;
1138 s8 code_rate_hp;
1139 s8 code_rate_lp;
1140 s8 select_hp;
1141
1142 s8 intlv_native;
1143 };
1144 struct dibDVBTChannel ch;
1145 int ret = 0;
1146
1147 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
1148 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
1149 goto error;
1150 ret = -EIO;
1151 }
1152
1153 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION, (u8 *) & ch, sizeof(struct dibDVBTChannel));
1154
1155 switch (ch.spectrum_inversion&0x7) {
1156 case 1:
1157 state->fe[0]->dtv_property_cache.inversion = INVERSION_ON;
1158 break;
1159 case 0:
1160 state->fe[0]->dtv_property_cache.inversion = INVERSION_OFF;
1161 break;
1162 default:
1163 case -1:
1164 state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO;
1165 break;
1166 }
1167 switch (ch.nfft) {
1168 case 0:
1169 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
1170 break;
1171 case 2:
1172 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_4K;
1173 break;
1174 case 1:
1175 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
1176 break;
1177 default:
1178 case -1:
1179 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO;
1180 break;
1181 }
1182 switch (ch.guard) {
1183 case 0:
1184 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
1185 break;
1186 case 1:
1187 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
1188 break;
1189 case 2:
1190 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
1191 break;
1192 case 3:
1193 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
1194 break;
1195 default:
1196 case -1:
1197 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO;
1198 break;
1199 }
1200 switch (ch.constellation) {
1201 case 2:
1202 state->fe[0]->dtv_property_cache.modulation = QAM_64;
1203 break;
1204 case 1:
1205 state->fe[0]->dtv_property_cache.modulation = QAM_16;
1206 break;
1207 case 0:
1208 state->fe[0]->dtv_property_cache.modulation = QPSK;
1209 break;
1210 default:
1211 case -1:
1212 state->fe[0]->dtv_property_cache.modulation = QAM_AUTO;
1213 break;
1214 }
1215 switch (ch.hrch) {
1216 case 0:
1217 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE;
1218 break;
1219 case 1:
1220 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_1;
1221 break;
1222 default:
1223 case -1:
1224 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO;
1225 break;
1226 }
1227 switch (ch.code_rate_hp) {
1228 case 1:
1229 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2;
1230 break;
1231 case 2:
1232 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_2_3;
1233 break;
1234 case 3:
1235 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_3_4;
1236 break;
1237 case 5:
1238 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_5_6;
1239 break;
1240 case 7:
1241 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_7_8;
1242 break;
1243 default:
1244 case -1:
1245 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO;
1246 break;
1247 }
1248 switch (ch.code_rate_lp) {
1249 case 1:
1250 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2;
1251 break;
1252 case 2:
1253 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_2_3;
1254 break;
1255 case 3:
1256 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_3_4;
1257 break;
1258 case 5:
1259 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_5_6;
1260 break;
1261 case 7:
1262 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_7_8;
1263 break;
1264 default:
1265 case -1:
1266 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_AUTO;
1267 break;
1268 }
1269
1270 error:
1271 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1272 return ret;
1273}
1274
1275static int dib9000_fw_set_channel_union(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel)
1276{
1277 struct dib9000_state *state = fe->demodulator_priv;
1278 struct dibDVBTChannel {
1279 s8 spectrum_inversion;
1280
1281 s8 nfft;
1282 s8 guard;
1283 s8 constellation;
1284
1285 s8 hrch;
1286 s8 alpha;
1287 s8 code_rate_hp;
1288 s8 code_rate_lp;
1289 s8 select_hp;
1290
1291 s8 intlv_native;
1292 };
1293 struct dibDVBTChannel ch;
1294
1295 switch (state->fe[0]->dtv_property_cache.inversion) {
1296 case INVERSION_ON:
1297 ch.spectrum_inversion = 1;
1298 break;
1299 case INVERSION_OFF:
1300 ch.spectrum_inversion = 0;
1301 break;
1302 default:
1303 case INVERSION_AUTO:
1304 ch.spectrum_inversion = -1;
1305 break;
1306 }
1307 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
1308 case TRANSMISSION_MODE_2K:
1309 ch.nfft = 0;
1310 break;
1311 case TRANSMISSION_MODE_4K:
1312 ch.nfft = 2;
1313 break;
1314 case TRANSMISSION_MODE_8K:
1315 ch.nfft = 1;
1316 break;
1317 default:
1318 case TRANSMISSION_MODE_AUTO:
1319 ch.nfft = 1;
1320 break;
1321 }
1322 switch (state->fe[0]->dtv_property_cache.guard_interval) {
1323 case GUARD_INTERVAL_1_32:
1324 ch.guard = 0;
1325 break;
1326 case GUARD_INTERVAL_1_16:
1327 ch.guard = 1;
1328 break;
1329 case GUARD_INTERVAL_1_8:
1330 ch.guard = 2;
1331 break;
1332 case GUARD_INTERVAL_1_4:
1333 ch.guard = 3;
1334 break;
1335 default:
1336 case GUARD_INTERVAL_AUTO:
1337 ch.guard = -1;
1338 break;
1339 }
1340 switch (state->fe[0]->dtv_property_cache.modulation) {
1341 case QAM_64:
1342 ch.constellation = 2;
1343 break;
1344 case QAM_16:
1345 ch.constellation = 1;
1346 break;
1347 case QPSK:
1348 ch.constellation = 0;
1349 break;
1350 default:
1351 case QAM_AUTO:
1352 ch.constellation = -1;
1353 break;
1354 }
1355 switch (state->fe[0]->dtv_property_cache.hierarchy) {
1356 case HIERARCHY_NONE:
1357 ch.hrch = 0;
1358 break;
1359 case HIERARCHY_1:
1360 case HIERARCHY_2:
1361 case HIERARCHY_4:
1362 ch.hrch = 1;
1363 break;
1364 default:
1365 case HIERARCHY_AUTO:
1366 ch.hrch = -1;
1367 break;
1368 }
1369 ch.alpha = 1;
1370 switch (state->fe[0]->dtv_property_cache.code_rate_HP) {
1371 case FEC_1_2:
1372 ch.code_rate_hp = 1;
1373 break;
1374 case FEC_2_3:
1375 ch.code_rate_hp = 2;
1376 break;
1377 case FEC_3_4:
1378 ch.code_rate_hp = 3;
1379 break;
1380 case FEC_5_6:
1381 ch.code_rate_hp = 5;
1382 break;
1383 case FEC_7_8:
1384 ch.code_rate_hp = 7;
1385 break;
1386 default:
1387 case FEC_AUTO:
1388 ch.code_rate_hp = -1;
1389 break;
1390 }
1391 switch (state->fe[0]->dtv_property_cache.code_rate_LP) {
1392 case FEC_1_2:
1393 ch.code_rate_lp = 1;
1394 break;
1395 case FEC_2_3:
1396 ch.code_rate_lp = 2;
1397 break;
1398 case FEC_3_4:
1399 ch.code_rate_lp = 3;
1400 break;
1401 case FEC_5_6:
1402 ch.code_rate_lp = 5;
1403 break;
1404 case FEC_7_8:
1405 ch.code_rate_lp = 7;
1406 break;
1407 default:
1408 case FEC_AUTO:
1409 ch.code_rate_lp = -1;
1410 break;
1411 }
1412 ch.select_hp = 1;
1413 ch.intlv_native = 1;
1414
1415 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) & ch);
1416
1417 return 0;
1418}
1419
1420static int dib9000_fw_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
1421{
1422 struct dib9000_state *state = fe->demodulator_priv;
1423 int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN;
1424 s8 i;
1425
1426 switch (state->tune_state) {
1427 case CT_DEMOD_START:
1428 dib9000_fw_set_channel_head(state, ch);
1429
1430 /* write the channel context - a channel is initialized to 0, so it is OK */
1431 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info);
1432 dib9000_risc_mem_write(state, FE_MM_W_FE_INFO, (u8 *) fe_info);
1433
1434 if (search)
1435 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0);
1436 else {
1437 dib9000_fw_set_channel_union(fe, ch);
1438 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0);
1439 }
1440 state->tune_state = CT_DEMOD_STEP_1;
1441 break;
1442 case CT_DEMOD_STEP_1:
1443 if (search)
1444 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, (u8 *) & i, 1);
1445 else
1446 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, (u8 *) & i, 1);
1447 switch (i) { /* something happened */
1448 case 0:
1449 break;
1450 case -2: /* tps locks are "slower" than MPEG locks -> even in autosearch data is OK here */
1451 if (search)
1452 state->status = FE_STATUS_DEMOD_SUCCESS;
1453 else {
1454 state->tune_state = CT_DEMOD_STOP;
1455 state->status = FE_STATUS_LOCKED;
1456 }
1457 break;
1458 default:
1459 state->status = FE_STATUS_TUNE_FAILED;
1460 state->tune_state = CT_DEMOD_STOP;
1461 break;
1462 }
1463 break;
1464 default:
1465 ret = FE_CALLBACK_TIME_NEVER;
1466 break;
1467 }
1468
1469 return ret;
1470}
1471
1472static int dib9000_fw_set_diversity_in(struct dvb_frontend *fe, int onoff)
1473{
1474 struct dib9000_state *state = fe->demodulator_priv;
1475 u16 mode = (u16) onoff;
1476 return dib9000_mbx_send(state, OUT_MSG_ENABLE_DIVERSITY, &mode, 1);
1477}
1478
1479static int dib9000_fw_set_output_mode(struct dvb_frontend *fe, int mode)
1480{
1481 struct dib9000_state *state = fe->demodulator_priv;
1482 u16 outreg, smo_mode;
1483
1484 dprintk("setting output mode for demod %p to %d", fe, mode);
1485
1486 switch (mode) {
1487 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
1488 outreg = (1 << 10); /* 0x0400 */
1489 break;
1490 case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
1491 outreg = (1 << 10) | (1 << 6); /* 0x0440 */
1492 break;
1493 case OUTMODE_MPEG2_SERIAL: // STBs with serial input
1494 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
1495 break;
1496 case OUTMODE_DIVERSITY:
1497 outreg = (1 << 10) | (4 << 6); /* 0x0500 */
1498 break;
1499 case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
1500 outreg = (1 << 10) | (5 << 6);
1501 break;
1502 case OUTMODE_HIGH_Z: // disable
1503 outreg = 0;
1504 break;
1505 default:
1506 dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe[0]);
1507 return -EINVAL;
1508 }
1509
1510 dib9000_write_word(state, 1795, outreg); // has to be written from outside
1511
1512 switch (mode) {
1513 case OUTMODE_MPEG2_PAR_GATED_CLK:
1514 case OUTMODE_MPEG2_PAR_CONT_CLK:
1515 case OUTMODE_MPEG2_SERIAL:
1516 case OUTMODE_MPEG2_FIFO:
1517 smo_mode = (dib9000_read_word(state, 295) & 0x0010) | (1 << 1);
1518 if (state->chip.d9.cfg.output_mpeg2_in_188_bytes)
1519 smo_mode |= (1 << 5);
1520 dib9000_write_word(state, 295, smo_mode);
1521 break;
1522 }
1523
1524 outreg = to_fw_output_mode(mode);
1525 return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1);
1526}
1527
1528static int dib9000_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1529{
1530 struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
1531 u16 i, len, t, index_msg;
1532
1533 for (index_msg = 0; index_msg < num; index_msg++) {
1534 if (msg[index_msg].flags & I2C_M_RD) { /* read */
1535 len = msg[index_msg].len;
1536 if (len > 16)
1537 len = 16;
1538
1539 if (dib9000_read_word(state, 790) != 0)
1540 dprintk("TunerITF: read busy");
1541
1542 dib9000_write_word(state, 784, (u16) (msg[index_msg].addr));
1543 dib9000_write_word(state, 787, (len / 2) - 1);
1544 dib9000_write_word(state, 786, 1); /* start read */
1545
1546 i = 1000;
1547 while (dib9000_read_word(state, 790) != (len / 2) && i)
1548 i--;
1549
1550 if (i == 0)
1551 dprintk("TunerITF: read failed");
1552
1553 for (i = 0; i < len; i += 2) {
1554 t = dib9000_read_word(state, 785);
1555 msg[index_msg].buf[i] = (t >> 8) & 0xff;
1556 msg[index_msg].buf[i + 1] = (t) & 0xff;
1557 }
1558 if (dib9000_read_word(state, 790) != 0)
1559 dprintk("TunerITF: read more data than expected");
1560 } else {
1561 i = 1000;
1562 while (dib9000_read_word(state, 789) && i)
1563 i--;
1564 if (i == 0)
1565 dprintk("TunerITF: write busy");
1566
1567 len = msg[index_msg].len;
1568 if (len > 16)
1569 len = 16;
1570
1571 for (i = 0; i < len; i += 2)
1572 dib9000_write_word(state, 785, (msg[index_msg].buf[i] << 8) | msg[index_msg].buf[i + 1]);
1573 dib9000_write_word(state, 784, (u16) msg[index_msg].addr);
1574 dib9000_write_word(state, 787, (len / 2) - 1);
1575 dib9000_write_word(state, 786, 0); /* start write */
1576
1577 i = 1000;
1578 while (dib9000_read_word(state, 791) > 0 && i)
1579 i--;
1580 if (i == 0)
1581 dprintk("TunerITF: write failed");
1582 }
1583 }
1584 return num;
1585}
1586
1587int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed)
1588{
1589 struct dib9000_state *state = fe->demodulator_priv;
1590
1591 state->component_bus_speed = speed;
1592 return 0;
1593}
1594EXPORT_SYMBOL(dib9000_fw_set_component_bus_speed);
1595
1596static int dib9000_fw_component_bus_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1597{
1598 struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
1599 u8 type = 0; /* I2C */
1600 u8 port = DIBX000_I2C_INTERFACE_GPIO_3_4;
1601 u16 scl = state->component_bus_speed; /* SCL frequency */
1602 //u16 scl = 208; /* SCL frequency */
1603 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[FE_MM_RW_COMPONENT_ACCESS_BUFFER];
1604 u8 p[13] = { 0 };
1605
1606 p[0] = type;
1607 p[1] = port;
1608 p[2] = msg[0].addr << 1;
1609
1610 p[3] = (u8) scl & 0xff; /* scl */
1611 p[4] = (u8) (scl >> 8);
1612
1613// p[5] = 0; /* attr */
1614// p[6] = 0;
1615
1616// p[7] = (u8) (msg[0].addr << 1 );
1617// p[8] = (u8) (msg[0].addr >> 7 );
1618 p[7] = 0;
1619 p[8] = 0;
1620
1621 p[9] = (u8) (msg[0].len);
1622 p[10] = (u8) (msg[0].len >> 8);
1623 if ((num > 1) && (msg[1].flags & I2C_M_RD)) {
1624 p[11] = (u8) (msg[1].len);
1625 p[12] = (u8) (msg[1].len >> 8);
1626 } else {
1627 p[11] = 0;
1628 p[12] = 0;
1629 }
1630
1631 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
1632
1633 dib9000_risc_mem_write(state, FE_MM_W_COMPONENT_ACCESS, p);
1634
1635 { /* write-part */
1636 dib9000_risc_mem_setup_cmd(state, m->addr, msg[0].len, 0);
1637 dib9000_risc_mem_write_chunks(state, msg[0].buf, msg[0].len);
1638 }
1639
1640 /* do the transaction */
1641 if (dib9000_fw_memmbx_sync(state, FE_SYNC_COMPONENT_ACCESS) < 0) {
1642 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1643 return 0;
1644 }
1645
1646 /* read back any possible result */
1647 if ((num > 1) && (msg[1].flags & I2C_M_RD))
1648 dib9000_risc_mem_read(state, FE_MM_RW_COMPONENT_ACCESS_BUFFER, msg[1].buf, msg[1].len);
1649
1650 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1651
1652 return num;
1653}
1654
1655static u32 dib9000_i2c_func(struct i2c_adapter *adapter)
1656{
1657 return I2C_FUNC_I2C;
1658}
1659
1660static struct i2c_algorithm dib9000_tuner_algo = {
1661 .master_xfer = dib9000_tuner_xfer,
1662 .functionality = dib9000_i2c_func,
1663};
1664
1665static struct i2c_algorithm dib9000_component_bus_algo = {
1666 .master_xfer = dib9000_fw_component_bus_xfer,
1667 .functionality = dib9000_i2c_func,
1668};
1669
1670struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe)
1671{
1672 struct dib9000_state *st = fe->demodulator_priv;
1673 return &st->tuner_adap;
1674}
1675
1676EXPORT_SYMBOL(dib9000_get_tuner_interface);
1677
1678struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
1679{
1680 struct dib9000_state *st = fe->demodulator_priv;
1681 return &st->component_bus;
1682}
1683
1684EXPORT_SYMBOL(dib9000_get_component_bus_interface);
1685
1686struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
1687{
1688 struct dib9000_state *st = fe->demodulator_priv;
1689 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
1690}
1691
1692EXPORT_SYMBOL(dib9000_get_i2c_master);
1693
1694int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
1695{
1696 struct dib9000_state *st = fe->demodulator_priv;
1697
1698 st->i2c.i2c_adap = i2c;
1699 return 0;
1700}
1701
1702EXPORT_SYMBOL(dib9000_set_i2c_adapter);
1703
1704static int dib9000_cfg_gpio(struct dib9000_state *st, u8 num, u8 dir, u8 val)
1705{
1706 st->gpio_dir = dib9000_read_word(st, 773);
1707 st->gpio_dir &= ~(1 << num); /* reset the direction bit */
1708 st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
1709 dib9000_write_word(st, 773, st->gpio_dir);
1710
1711 st->gpio_val = dib9000_read_word(st, 774);
1712 st->gpio_val &= ~(1 << num); /* reset the direction bit */
1713 st->gpio_val |= (val & 0x01) << num; /* set the new value */
1714 dib9000_write_word(st, 774, st->gpio_val);
1715
1716 dprintk("gpio dir: %04x: gpio val: %04x", st->gpio_dir, st->gpio_val);
1717
1718 return 0;
1719}
1720
1721int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
1722{
1723 struct dib9000_state *state = fe->demodulator_priv;
1724 return dib9000_cfg_gpio(state, num, dir, val);
1725}
1726
1727EXPORT_SYMBOL(dib9000_set_gpio);
1728int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
1729{
1730 struct dib9000_state *state = fe->demodulator_priv;
1731 u16 val = dib9000_read_word(state, 294 + 1) & 0xffef;
1732 val |= (onoff & 0x1) << 4;
1733
1734 dprintk("PID filter enabled %d", onoff);
1735 return dib9000_write_word(state, 294 + 1, val);
1736}
1737
1738EXPORT_SYMBOL(dib9000_fw_pid_filter_ctrl);
1739int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
1740{
1741 struct dib9000_state *state = fe->demodulator_priv;
1742 dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
1743 return dib9000_write_word(state, 300 + 1 + id, onoff ? (1 << 13) | pid : 0);
1744}
1745
1746EXPORT_SYMBOL(dib9000_fw_pid_filter);
1747
1748int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
1749{
1750 struct dib9000_state *state = fe->demodulator_priv;
1751 return dib9000_fw_init(state);
1752}
1753
1754EXPORT_SYMBOL(dib9000_firmware_post_pll_init);
1755
1756static void dib9000_release(struct dvb_frontend *demod)
1757{
1758 struct dib9000_state *st = demod->demodulator_priv;
1759 u8 index_frontend;
1760
1761 for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
1762 dvb_frontend_detach(st->fe[index_frontend]);
1763
1764 DibFreeLock(&state->platform.risc.mbx_if_lock);
1765 DibFreeLock(&state->platform.risc.mbx_lock);
1766 DibFreeLock(&state->platform.risc.mem_lock);
1767 DibFreeLock(&state->platform.risc.mem_mbx_lock);
1768 dibx000_exit_i2c_master(&st->i2c_master);
1769
1770 i2c_del_adapter(&st->tuner_adap);
1771 i2c_del_adapter(&st->component_bus);
1772 kfree(st->fe[0]);
1773 kfree(st);
1774}
1775
1776static int dib9000_wakeup(struct dvb_frontend *fe)
1777{
1778 return 0;
1779}
1780
1781static int dib9000_sleep(struct dvb_frontend *fe)
1782{
1783 struct dib9000_state *state = fe->demodulator_priv;
1784 u8 index_frontend;
1785 int ret;
1786
1787 for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1788 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
1789 if (ret < 0)
1790 return ret;
1791 }
1792 return dib9000_mbx_send(state, OUT_MSG_FE_SLEEP, NULL, 0);
1793}
1794
1795static int dib9000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
1796{
1797 tune->min_delay_ms = 1000;
1798 return 0;
1799}
1800
1801static int dib9000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1802{
1803 struct dib9000_state *state = fe->demodulator_priv;
1804 u8 index_frontend, sub_index_frontend;
1805 fe_status_t stat;
1806 int ret;
1807
1808 for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1809 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
1810 if (stat & FE_HAS_SYNC) {
1811 dprintk("TPS lock on the slave%i", index_frontend);
1812
1813 /* synchronize the cache with the other frontends */
1814 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep);
1815 for (sub_index_frontend=0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
1816 if (sub_index_frontend != index_frontend) {
1817 state->fe[sub_index_frontend]->dtv_property_cache.modulation = state->fe[index_frontend]->dtv_property_cache.modulation;
1818 state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
1819 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
1820 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
1821 state->fe[sub_index_frontend]->dtv_property_cache.hierarchy = state->fe[index_frontend]->dtv_property_cache.hierarchy;
1822 state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP = state->fe[index_frontend]->dtv_property_cache.code_rate_HP;
1823 state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP = state->fe[index_frontend]->dtv_property_cache.code_rate_LP;
1824 state->fe[sub_index_frontend]->dtv_property_cache.rolloff = state->fe[index_frontend]->dtv_property_cache.rolloff;
1825 }
1826 }
1827 return 0;
1828 }
1829 }
1830
1831 /* get the channel from master chip */
1832 ret = dib9000_fw_get_channel(fe, fep);
1833 if (ret != 0)
1834 return ret;
1835
1836 /* synchronize the cache with the other frontends */
1837 for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1838 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
1839 state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
1840 state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
1841 state->fe[index_frontend]->dtv_property_cache.modulation = fe->dtv_property_cache.modulation;
1842 state->fe[index_frontend]->dtv_property_cache.hierarchy = fe->dtv_property_cache.hierarchy;
1843 state->fe[index_frontend]->dtv_property_cache.code_rate_HP = fe->dtv_property_cache.code_rate_HP;
1844 state->fe[index_frontend]->dtv_property_cache.code_rate_LP = fe->dtv_property_cache.code_rate_LP;
1845 state->fe[index_frontend]->dtv_property_cache.rolloff = fe->dtv_property_cache.rolloff;
1846 }
1847
1848 return 0;
1849}
1850
1851static int dib9000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
1852{
1853 struct dib9000_state *state = fe->demodulator_priv;
1854 state->tune_state = tune_state;
1855 if (tune_state == CT_DEMOD_START)
1856 state->status = FE_STATUS_TUNE_PENDING;
1857
1858 return 0;
1859}
1860
1861static u32 dib9000_get_status(struct dvb_frontend *fe)
1862{
1863 struct dib9000_state *state = fe->demodulator_priv;
1864 return state->status;
1865}
1866
1867static int dib9000_set_channel_status(struct dvb_frontend *fe, struct dvb_frontend_parametersContext *channel_status)
1868{
1869 struct dib9000_state *state = fe->demodulator_priv;
1870
1871 memcpy(&state->channel_status, channel_status, sizeof(struct dvb_frontend_parametersContext));
1872 return 0;
1873}
1874
1875static int dib9000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1876{
1877 struct dib9000_state *state = fe->demodulator_priv;
1878 int sleep_time, sleep_time_slave;
1879 u32 frontend_status;
1880 u8 nbr_pending, exit_condition, index_frontend, index_frontend_success;
1881 struct dvb_frontend_parametersContext channel_status;
1882
1883 /* check that the correct parameters are set */
1884 if (state->fe[0]->dtv_property_cache.frequency == 0) {
1885 dprintk("dib9000: must specify frequency ");
1886 return 0;
1887 }
1888
1889 if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
1890 dprintk("dib9000: must specify bandwidth ");
1891 return 0;
1892 }
1893 fe->dtv_property_cache.delivery_system = SYS_DVBT;
1894
1895 /* set the master status */
1896 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
1897 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
1898 /* no channel specified, autosearch the channel */
1899 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN;
1900 } else
1901 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
1902
1903 /* set mode and status for the different frontends */
1904 for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1905 dib9000_fw_set_diversity_in(state->fe[index_frontend], 1);
1906
1907 /* synchronization of the cache */
1908 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
1909
1910 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_DVBT;
1911 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z);
1912
1913 dib9000_set_channel_status(state->fe[index_frontend], &state->channel_status);
1914 dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
1915 }
1916
1917 /* actual tune */
1918 exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
1919 index_frontend_success = 0;
1920 do {
1921 sleep_time = dib9000_fw_tune(state->fe[0], NULL);
1922 for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1923 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
1924 if (sleep_time == FE_CALLBACK_TIME_NEVER)
1925 sleep_time = sleep_time_slave;
1926 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
1927 sleep_time = sleep_time_slave;
1928 }
1929 if (sleep_time != FE_CALLBACK_TIME_NEVER)
1930 msleep(sleep_time / 10);
1931 else
1932 break;
1933
1934 nbr_pending = 0;
1935 exit_condition = 0;
1936 index_frontend_success = 0;
1937 for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1938 frontend_status = -dib9000_get_status(state->fe[index_frontend]);
1939 if (frontend_status > -FE_STATUS_TUNE_PENDING) {
1940 exit_condition = 2; /* tune success */
1941 index_frontend_success = index_frontend;
1942 break;
1943 }
1944 if (frontend_status == -FE_STATUS_TUNE_PENDING)
1945 nbr_pending++; /* some frontends are still tuning */
1946 }
1947 if ((exit_condition != 2) && (nbr_pending == 0))
1948 exit_condition = 1; /* if all tune are done and no success, exit: tune failed */
1949
1950 } while (exit_condition == 0);
1951
1952 /* check the tune result */
1953 if (exit_condition == 1) { /* tune failed */
1954 dprintk("tune failed");
1955 return 0;
1956 }
1957
1958 dprintk("tune success on frontend%i", index_frontend_success);
1959
1960 /* synchronize all the channel cache */
1961 dib9000_get_frontend(state->fe[0], fep);
1962
1963 /* retune the other frontends with the found channel */
1964 channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
1965 for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1966 /* only retune the frontends which was not tuned success */
1967 if (index_frontend != index_frontend_success) {
1968 dib9000_set_channel_status(state->fe[index_frontend], &channel_status);
1969 dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
1970 }
1971 }
1972 do {
1973 sleep_time = FE_CALLBACK_TIME_NEVER;
1974 for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1975 if (index_frontend != index_frontend_success) {
1976 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
1977 if (sleep_time == FE_CALLBACK_TIME_NEVER)
1978 sleep_time = sleep_time_slave;
1979 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
1980 sleep_time = sleep_time_slave;
1981 }
1982 }
1983 if (sleep_time != FE_CALLBACK_TIME_NEVER)
1984 msleep(sleep_time / 10);
1985 else
1986 break;
1987
1988 nbr_pending = 0;
1989 for (index_frontend=0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1990 if (index_frontend != index_frontend_success) {
1991 frontend_status = -dib9000_get_status(state->fe[index_frontend]);
1992 if ((index_frontend != index_frontend_success) && (frontend_status == -FE_STATUS_TUNE_PENDING))
1993 nbr_pending++; /* some frontends are still tuning */
1994 }
1995 }
1996 } while (nbr_pending != 0);
1997
1998 /* set the output mode */
1999 dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode);
2000 for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2001 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
2002
2003 /* turn off the diversity for the last frontend */
2004 dib9000_fw_set_diversity_in(state->fe[index_frontend-1], 0);
2005
2006 return 0;
2007}
2008
2009static u16 dib9000_read_lock(struct dvb_frontend *fe)
2010{
2011 struct dib9000_state *state = fe->demodulator_priv;
2012
2013 return dib9000_read_word(state, 535);
2014}
2015
2016static int dib9000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
2017{
2018 struct dib9000_state *state = fe->demodulator_priv;
2019 u8 index_frontend;
2020 u16 lock = 0, lock_slave = 0;
2021
2022 for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2023 lock_slave |= dib9000_read_lock(state->fe[index_frontend]);
2024
2025 lock = dib9000_read_word(state, 535);
2026
2027 *stat = 0;
2028
2029 if ((lock & 0x8000) || (lock_slave & 0x8000))
2030 *stat |= FE_HAS_SIGNAL;
2031 if ((lock & 0x3000) || (lock_slave & 0x3000))
2032 *stat |= FE_HAS_CARRIER;
2033 if ((lock & 0x0100) || (lock_slave & 0x0100))
2034 *stat |= FE_HAS_VITERBI;
2035 if (((lock & 0x0038) == 0x38) || ((lock_slave & 0x0038) == 0x38))
2036 *stat |= FE_HAS_SYNC;
2037 if ((lock & 0x0008) || (lock_slave & 0x0008))
2038 *stat |= FE_HAS_LOCK;
2039
2040 return 0;
2041}
2042
2043static int dib9000_read_ber(struct dvb_frontend *fe, u32 * ber)
2044{
2045 struct dib9000_state *state = fe->demodulator_priv;
2046 u16 c[16];
2047
2048 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2049 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2050 return -EIO;
2051 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2052 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2053
2054 *ber = c[10] << 16 | c[11];
2055 return 0;
2056}
2057
2058static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2059{
2060 struct dib9000_state *state = fe->demodulator_priv;
2061 u8 index_frontend;
2062 u16 c[16];
2063 u16 val;
2064
2065 *strength = 0;
2066 for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2067 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
2068 if (val > 65535 - *strength)
2069 *strength = 65535;
2070 else
2071 *strength += val;
2072 }
2073
2074 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2075 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2076 return -EIO;
2077 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2078 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2079
2080 val = 65535 - c[4];
2081 if (val > 65535 - *strength)
2082 *strength = 65535;
2083 else
2084 *strength += val;
2085 return 0;
2086}
2087
2088static u32 dib9000_get_snr(struct dvb_frontend *fe)
2089{
2090 struct dib9000_state *state = fe->demodulator_priv;
2091 u16 c[16];
2092 u32 n, s, exp;
2093 u16 val;
2094
2095 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2096 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2097 return -EIO;
2098 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2099 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2100
2101 val = c[7];
2102 n = (val >> 4) & 0xff;
2103 exp = ((val & 0xf) << 2);
2104 val = c[8];
2105 exp += ((val >> 14) & 0x3);
2106 if ((exp & 0x20) != 0)
2107 exp -= 0x40;
2108 n <<= exp + 16;
2109
2110 s = (val >> 6) & 0xFF;
2111 exp = (val & 0x3F);
2112 if ((exp & 0x20) != 0)
2113 exp -= 0x40;
2114 s <<= exp + 16;
2115
2116 if (n > 0) {
2117 u32 t = (s / n) << 16;
2118 return t + ((s << 16) - n * t) / n;
2119 }
2120 return 0xffffffff;
2121}
2122
2123static int dib9000_read_snr(struct dvb_frontend *fe, u16 * snr)
2124{
2125 struct dib9000_state *state = fe->demodulator_priv;
2126 u8 index_frontend;
2127 u32 snr_master;
2128
2129 snr_master = dib9000_get_snr(fe);
2130 for (index_frontend=1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2131 snr_master += dib9000_get_snr(state->fe[index_frontend]);
2132
2133 if ((snr_master >> 16) != 0) {
2134 snr_master = 10 * intlog10(snr_master >> 16);
2135 *snr = snr_master / ((1 << 24) / 10);
2136 } else
2137 *snr = 0;
2138
2139 return 0;
2140}
2141
2142static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
2143{
2144 struct dib9000_state *state = fe->demodulator_priv;
2145 u16 c[16];
2146
2147 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2148 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2149 return -EIO;
2150 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2151 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2152
2153 *unc = c[12];
2154 return 0;
2155}
2156
2157int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, u8 first_addr)
2158{
2159 int k = 0;
2160 u8 new_addr = 0;
2161 struct i2c_device client = {.i2c_adap = i2c };
2162
2163 client.i2c_addr = default_addr + 16;
2164 dib9000_i2c_write16(&client, 1796, 0x0); // select DVB-T output
2165
2166 for (k = no_of_demods - 1; k >= 0; k--) {
2167 /* designated i2c address */
2168 new_addr = first_addr + (k << 1);
2169 client.i2c_addr = default_addr;
2170
2171 dib9000_i2c_write16(&client, 1817, 3);
2172 dib9000_i2c_write16(&client, 1796, 0);
2173 dib9000_i2c_write16(&client, 1227, 1);
2174 dib9000_i2c_write16(&client, 1227, 0);
2175
2176 client.i2c_addr = new_addr;
2177 dib9000_i2c_write16(&client, 1817, 3);
2178 dib9000_i2c_write16(&client, 1796, 0);
2179 dib9000_i2c_write16(&client, 1227, 1);
2180 dib9000_i2c_write16(&client, 1227, 0);
2181
2182 if (dib9000_identify(&client) == 0) {
2183 client.i2c_addr = default_addr;
2184 if (dib9000_identify(&client) == 0) {
2185 dprintk("DiB9000 #%d: not identified", k);
2186 return -EIO;
2187 }
2188 }
2189
2190 dib9000_i2c_write16(&client, 1795, (1 << 10) | (4 << 6));
2191 dib9000_i2c_write16(&client, 1794, (new_addr << 2) | 2);
2192
2193 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
2194 }
2195
2196 for (k = 0; k < no_of_demods; k++) {
2197 new_addr = first_addr | (k << 1);
2198 client.i2c_addr = new_addr;
2199
2200 dib9000_i2c_write16(&client, 1794, (new_addr << 2));
2201 dib9000_i2c_write16(&client, 1795, 0);
2202 }
2203
2204 return 0;
2205}
2206
2207EXPORT_SYMBOL(dib9000_i2c_enumeration);
2208
2209int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
2210{
2211 struct dib9000_state *state = fe->demodulator_priv;
2212 u8 index_frontend = 1;
2213
2214 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2215 index_frontend++;
2216 if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
2217 dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
2218 state->fe[index_frontend] = fe_slave;
2219 return 0;
2220 }
2221
2222 dprintk("too many slave frontend");
2223 return -ENOMEM;
2224}
2225EXPORT_SYMBOL(dib9000_set_slave_frontend);
2226
2227int dib9000_remove_slave_frontend(struct dvb_frontend *fe)
2228{
2229 struct dib9000_state *state = fe->demodulator_priv;
2230 u8 index_frontend = 1;
2231
2232 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2233 index_frontend++;
2234 if (index_frontend != 1) {
2235 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1);
2236 state->fe[index_frontend] = NULL;
2237 return 0;
2238 }
2239
2240 dprintk("no frontend to be removed");
2241 return -ENODEV;
2242}
2243EXPORT_SYMBOL(dib9000_remove_slave_frontend);
2244
2245struct dvb_frontend * dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
2246{
2247 struct dib9000_state *state = fe->demodulator_priv;
2248
2249 if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
2250 return NULL;
2251 return state->fe[slave_index];
2252}
2253EXPORT_SYMBOL(dib9000_get_slave_frontend);
2254
2255static struct dvb_frontend_ops dib9000_ops;
2256struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg)
2257{
2258 struct dvb_frontend *fe;
2259 struct dib9000_state *st;
2260 st = kzalloc(sizeof(struct dib9000_state), GFP_KERNEL);
2261 if (st == NULL)
2262 return NULL;
2263 fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
2264 if (fe == NULL)
2265 return NULL;
2266
2267 memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config));
2268 st->i2c.i2c_adap = i2c_adap;
2269 st->i2c.i2c_addr = i2c_addr;
2270
2271 st->gpio_dir = DIB9000_GPIO_DEFAULT_DIRECTIONS;
2272 st->gpio_val = DIB9000_GPIO_DEFAULT_VALUES;
2273 st->gpio_pwm_pos = DIB9000_GPIO_DEFAULT_PWM_POS;
2274
2275 DibInitLock(&st->platform.risc.mbx_if_lock);
2276 DibInitLock(&st->platform.risc.mbx_lock);
2277 DibInitLock(&st->platform.risc.mem_lock);
2278 DibInitLock(&st->platform.risc.mem_mbx_lock);
2279
2280 st->fe[0] = fe;
2281 fe->demodulator_priv = st;
2282 memcpy(&st->fe[0]->ops, &dib9000_ops, sizeof(struct dvb_frontend_ops));
2283
2284 /* Ensure the output mode remains at the previous default if it's
2285 * not specifically set by the caller.
2286 */
2287 if ((st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2288 st->chip.d9.cfg.output_mode = OUTMODE_MPEG2_FIFO;
2289
2290 if (dib9000_identify(&st->i2c) == 0)
2291 goto error;
2292
2293 dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c.i2c_adap, st->i2c.i2c_addr);
2294
2295 st->tuner_adap.dev.parent = i2c_adap->dev.parent;
2296 strncpy(st->tuner_adap.name, "DIB9000_FW TUNER ACCESS", sizeof(st->tuner_adap.name));
2297 st->tuner_adap.algo = &dib9000_tuner_algo;
2298 st->tuner_adap.algo_data = NULL;
2299 i2c_set_adapdata(&st->tuner_adap, st);
2300 if (i2c_add_adapter(&st->tuner_adap) < 0)
2301 goto error;
2302
2303 st->component_bus.dev.parent = i2c_adap->dev.parent;
2304 strncpy(st->component_bus.name, "DIB9000_FW COMPONENT BUS ACCESS", sizeof(st->component_bus.name));
2305 st->component_bus.algo = &dib9000_component_bus_algo;
2306 st->component_bus.algo_data = NULL;
2307 st->component_bus_speed = 340;
2308 i2c_set_adapdata(&st->component_bus, st);
2309 if (i2c_add_adapter(&st->component_bus) < 0)
2310 goto component_bus_add_error;
2311
2312 dib9000_fw_reset(fe);
2313
2314 return fe;
2315
2316 component_bus_add_error:
2317 i2c_del_adapter(&st->tuner_adap);
2318 error:
2319 kfree(st);
2320 return NULL;
2321}
2322
2323EXPORT_SYMBOL(dib9000_attach);
2324
2325static struct dvb_frontend_ops dib9000_ops = {
2326 .info = {
2327 .name = "DiBcom 9000",
2328 .type = FE_OFDM,
2329 .frequency_min = 44250000,
2330 .frequency_max = 867250000,
2331 .frequency_stepsize = 62500,
2332 .caps = FE_CAN_INVERSION_AUTO |
2333 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2334 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2335 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
2336 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
2337 },
2338
2339 .release = dib9000_release,
2340
2341 .init = dib9000_wakeup,
2342 .sleep = dib9000_sleep,
2343
2344 .set_frontend = dib9000_set_frontend,
2345 .get_tune_settings = dib9000_fe_get_tune_settings,
2346 .get_frontend = dib9000_get_frontend,
2347
2348 .read_status = dib9000_read_status,
2349 .read_ber = dib9000_read_ber,
2350 .read_signal_strength = dib9000_read_signal_strength,
2351 .read_snr = dib9000_read_snr,
2352 .read_ucblocks = dib9000_read_unc_blocks,
2353};
2354
2355MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
2356MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
2357MODULE_DESCRIPTION("Driver for the DiBcom 9000 COFDM demodulator");
2358MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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