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Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[deliverable/linux.git] / drivers / media / dvb / frontends / it913x-fe.c
CommitLineData
3dbbf82f
MP		 1/*
2 * Driver for it913x-fe Frontend
3 *
4 * with support for on chip it9137 integral tuner
5 *
6 * Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com)
7 * IT9137 Copyright (C) ITE Tech Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 *
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
23 */
24
25#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/slab.h>
28#include <linux/types.h>
29
30#include "dvb_frontend.h"
31#include "it913x-fe.h"
32#include "it913x-fe-priv.h"
33
34static int it913x_debug;
35
36module_param_named(debug, it913x_debug, int, 0644);
37MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
38
39#define dprintk(level, args...) do { \
40 if (level & it913x_debug) \
41 printk(KERN_DEBUG "it913x-fe: " args); \
42} while (0)
43
44#define deb_info(args...) dprintk(0x01, args)
45#define debug_data_snipet(level, name, p) \
46 dprintk(level, name" (%02x%02x%02x%02x%02x%02x%02x%02x)", \
47 *p, *(p+1), *(p+2), *(p+3), *(p+4), \
48 *(p+5), *(p+6), *(p+7));
ed942c50
MP		 49#define info(format, arg...) \
50 printk(KERN_INFO "it913x-fe: " format "\n" , ## arg)
3dbbf82f
MP		 51
52struct it913x_fe_state {
53 struct dvb_frontend frontend;
54 struct i2c_adapter *i2c_adap;
b7d425d3 55 struct ite_config *config;
3dbbf82f
MP		 56 u8 i2c_addr;
57 u32 frequency;
3339a5b1
MP		 58 fe_modulation_t constellation;
59 fe_transmit_mode_t transmission_mode;
3dbbf82f
MP		 60 u32 crystalFrequency;
61 u32 adcFrequency;
62 u8 tuner_type;
63 struct adctable *table;
64 fe_status_t it913x_status;
7c2808e2 65 u16 tun_xtal;
66 u8 tun_fdiv;
67 u8 tun_clk_mode;
68 u32 tun_fn_min;
82a05014 69 u32 ucblocks;
3dbbf82f
MP		 70};
71
72static int it913x_read_reg(struct it913x_fe_state *state,
73 u32 reg, u8 *data, u8 count)
74{
75 int ret;
76 u8 pro = PRO_DMOD; /* All reads from demodulator */
77 u8 b[4];
78 struct i2c_msg msg[2] = {
79 { .addr = state->i2c_addr + (pro << 1), .flags = 0,
80 .buf = b, .len = sizeof(b) },
81 { .addr = state->i2c_addr + (pro << 1), .flags = I2C_M_RD,
82 .buf = data, .len = count }
83 };
84 b[0] = (u8) reg >> 24;
85 b[1] = (u8)(reg >> 16) & 0xff;
86 b[2] = (u8)(reg >> 8) & 0xff;
87 b[3] = (u8) reg & 0xff;
88
89 ret = i2c_transfer(state->i2c_adap, msg, 2);
90
91 return ret;
92}
93
94static int it913x_read_reg_u8(struct it913x_fe_state *state, u32 reg)
95{
96 int ret;
97 u8 b[1];
98 ret = it913x_read_reg(state, reg, &b[0], sizeof(b));
99 return (ret < 0) ? -ENODEV : b[0];
100}
101
102static int it913x_write(struct it913x_fe_state *state,
103 u8 pro, u32 reg, u8 buf[], u8 count)
104{
105 u8 b[256];
106 struct i2c_msg msg[1] = {
107 { .addr = state->i2c_addr + (pro << 1), .flags = 0,
108 .buf = b, .len = count + 4 }
109 };
110 int ret;
111
112 b[0] = (u8) reg >> 24;
113 b[1] = (u8)(reg >> 16) & 0xff;
114 b[2] = (u8)(reg >> 8) & 0xff;
115 b[3] = (u8) reg & 0xff;
116 memcpy(&b[4], buf, count);
117
118 ret = i2c_transfer(state->i2c_adap, msg, 1);
119
120 if (ret < 0)
121 return -EIO;
122
123 return 0;
124}
125
126static int it913x_write_reg(struct it913x_fe_state *state,
127 u8 pro, u32 reg, u32 data)
128{
129 int ret;
130 u8 b[4];
131 u8 s;
132
133 b[0] = data >> 24;
134 b[1] = (data >> 16) & 0xff;
135 b[2] = (data >> 8) & 0xff;
136 b[3] = data & 0xff;
137 /* expand write as needed */
138 if (data < 0x100)
139 s = 3;
140 else if (data < 0x1000)
141 s = 2;
142 else if (data < 0x100000)
143 s = 1;
144 else
145 s = 0;
146
147 ret = it913x_write(state, pro, reg, &b[s], sizeof(b) - s);
148
149 return ret;
150}
151
152static int it913x_fe_script_loader(struct it913x_fe_state *state,
153 struct it913xset *loadscript)
154{
155 int ret, i;
156 if (loadscript == NULL)
157 return -EINVAL;
158
159 for (i = 0; i < 1000; ++i) {
160 if (loadscript[i].pro == 0xff)
161 break;
162 ret = it913x_write(state, loadscript[i].pro,
163 loadscript[i].address,
164 loadscript[i].reg, loadscript[i].count);
165 if (ret < 0)
166 return -ENODEV;
167 }
168 return 0;
169}
170
7c2808e2 171static int it913x_init_tuner(struct it913x_fe_state *state)
172{
173 int ret, i, reg;
174 u8 val, nv_val;
175 u8 nv[] = {48, 32, 24, 16, 12, 8, 6, 4, 2};
176 u8 b[2];
177
178 reg = it913x_read_reg_u8(state, 0xec86);
179 switch (reg) {
180 case 0:
181 state->tun_clk_mode = reg;
182 state->tun_xtal = 2000;
183 state->tun_fdiv = 3;
184 val = 16;
185 break;
186 case -ENODEV:
187 return -ENODEV;
188 case 1:
189 default:
190 state->tun_clk_mode = reg;
191 state->tun_xtal = 640;
192 state->tun_fdiv = 1;
193 val = 6;
194 break;
195 }
196
197 reg = it913x_read_reg_u8(state, 0xed03);
198
199 if (reg < 0)
200 return -ENODEV;
201 else if (reg < sizeof(nv))
202 nv_val = nv[reg];
203 else
204 nv_val = 2;
205
206 for (i = 0; i < 50; i++) {
207 ret = it913x_read_reg(state, 0xed23, &b[0], sizeof(b));
208 reg = (b[1] << 8) + b[0];
209 if (reg > 0)
210 break;
211 if (ret < 0)
212 return -ENODEV;
213 udelay(2000);
214 }
215 state->tun_fn_min = state->tun_xtal * reg;
216 state->tun_fn_min /= (state->tun_fdiv * nv_val);
217 deb_info("Tuner fn_min %d", state->tun_fn_min);
218
b7d425d3
MP		 219 if (state->config->chip_ver > 1)
220 msleep(50);
221 else {
222 for (i = 0; i < 50; i++) {
223 reg = it913x_read_reg_u8(state, 0xec82);
224 if (reg > 0)
225 break;
226 if (reg < 0)
227 return -ENODEV;
228 udelay(2000);
229 }
7c2808e2 230 }
231
232 return it913x_write_reg(state, PRO_DMOD, 0xed81, val);
233}
234
3dbbf82f 235static int it9137_set_tuner(struct it913x_fe_state *state,
f908cf1d 236 u32 bandwidth, u32 frequency_m)
3dbbf82f
MP		 237{
238 struct it913xset *set_tuner = set_it9137_template;
7c2808e2 239 int ret, reg;
3dbbf82f 240 u32 frequency = frequency_m / 1000;
7c2808e2 241 u32 freq, temp_f, tmp;
242 u16 iqik_m_cal;
3dbbf82f
MP		 243 u16 n_div;
244 u8 n;
245 u8 l_band;
246 u8 lna_band;
247 u8 bw;
248
990f49af
MP		 249 if (state->config->firmware_ver == 1)
250 set_tuner = set_it9135_template;
251 else
252 set_tuner = set_it9137_template;
253
3dbbf82f
MP		 254 deb_info("Tuner Frequency %d Bandwidth %d", frequency, bandwidth);
255
256 if (frequency >= 51000 && frequency <= 440000) {
257 l_band = 0;
258 lna_band = 0;
259 } else if (frequency > 440000 && frequency <= 484000) {
260 l_band = 1;
261 lna_band = 1;
262 } else if (frequency > 484000 && frequency <= 533000) {
263 l_band = 1;
264 lna_band = 2;
265 } else if (frequency > 533000 && frequency <= 587000) {
266 l_band = 1;
267 lna_band = 3;
268 } else if (frequency > 587000 && frequency <= 645000) {
269 l_band = 1;
270 lna_band = 4;
271 } else if (frequency > 645000 && frequency <= 710000) {
272 l_band = 1;
273 lna_band = 5;
274 } else if (frequency > 710000 && frequency <= 782000) {
275 l_band = 1;
276 lna_band = 6;
277 } else if (frequency > 782000 && frequency <= 860000) {
278 l_band = 1;
279 lna_band = 7;
280 } else if (frequency > 1450000 && frequency <= 1492000) {
281 l_band = 1;
282 lna_band = 0;
283 } else if (frequency > 1660000 && frequency <= 1685000) {
284 l_band = 1;
285 lna_band = 1;
286 } else
287 return -EINVAL;
288 set_tuner[0].reg[0] = lna_band;
289
f908cf1d
MCC		 290 switch (bandwidth) {
291 case 5000000:
3dbbf82f 292 bw = 0;
f908cf1d
MCC		 293 break;
294 case 6000000:
3dbbf82f 295 bw = 2;
f908cf1d
MCC		 296 break;
297 case 7000000:
3dbbf82f 298 bw = 4;
f908cf1d
MCC		 299 break;
300 default:
301 case 8000000:
3dbbf82f 302 bw = 6;
f908cf1d
MCC		 303 break;
304 }
7c2808e2 305
3dbbf82f
MP		 306 set_tuner[1].reg[0] = bw;
307 set_tuner[2].reg[0] = 0xa0 | (l_band << 3);
308
7c2808e2 309 if (frequency > 53000 && frequency <= 74000) {
3dbbf82f
MP		 310 n_div = 48;
311 n = 0;
312 } else if (frequency > 74000 && frequency <= 111000) {
313 n_div = 32;
314 n = 1;
315 } else if (frequency > 111000 && frequency <= 148000) {
316 n_div = 24;
317 n = 2;
318 } else if (frequency > 148000 && frequency <= 222000) {
319 n_div = 16;
320 n = 3;
321 } else if (frequency > 222000 && frequency <= 296000) {
322 n_div = 12;
323 n = 4;
324 } else if (frequency > 296000 && frequency <= 445000) {
325 n_div = 8;
326 n = 5;
7c2808e2 327 } else if (frequency > 445000 && frequency <= state->tun_fn_min) {
3dbbf82f
MP		 328 n_div = 6;
329 n = 6;
7c2808e2 330 } else if (frequency > state->tun_fn_min && frequency <= 950000) {
3dbbf82f
MP		 331 n_div = 4;
332 n = 7;
333 } else if (frequency > 1450000 && frequency <= 1680000) {
334 n_div = 2;
335 n = 0;
336 } else
337 return -EINVAL;
338
7c2808e2 339 reg = it913x_read_reg_u8(state, 0xed81);
340 iqik_m_cal = (u16)reg * n_div;
3dbbf82f 341
7c2808e2 342 if (reg < 0x20) {
343 if (state->tun_clk_mode == 0)
344 iqik_m_cal = (iqik_m_cal * 9) >> 5;
345 else
346 iqik_m_cal >>= 1;
347 } else {
348 iqik_m_cal = 0x40 - iqik_m_cal;
349 if (state->tun_clk_mode == 0)
350 iqik_m_cal = ~((iqik_m_cal * 9) >> 5);
351 else
352 iqik_m_cal = ~(iqik_m_cal >> 1);
353 }
354
355 temp_f = frequency * (u32)n_div * (u32)state->tun_fdiv;
356 freq = temp_f / state->tun_xtal;
357 tmp = freq * state->tun_xtal;
358
359 if ((temp_f - tmp) >= (state->tun_xtal >> 1))
360 freq++;
3dbbf82f 361
3dbbf82f 362 freq += (u32) n << 13;
7c2808e2 363 /* Frequency OMEGA_IQIK_M_CAL_MID*/
364 temp_f = freq + (u32)iqik_m_cal;
3dbbf82f 365
7c2808e2 366 set_tuner[3].reg[0] = temp_f & 0xff;
367 set_tuner[4].reg[0] = (temp_f >> 8) & 0xff;
368
369 deb_info("High Frequency = %04x", temp_f);
370
371 /* Lower frequency */
372 set_tuner[5].reg[0] = freq & 0xff;
373 set_tuner[6].reg[0] = (freq >> 8) & 0xff;
374
375 deb_info("low Frequency = %04x", freq);
3dbbf82f
MP		 376
377 ret = it913x_fe_script_loader(state, set_tuner);
378
379 return (ret < 0) ? -ENODEV : 0;
3dbbf82f
MP		 380}
381
382static int it913x_fe_select_bw(struct it913x_fe_state *state,
f908cf1d 383 u32 bandwidth, u32 adcFrequency)
3dbbf82f
MP		 384{
385 int ret, i;
386 u8 buffer[256];
387 u32 coeff[8];
388 u16 bfsfcw_fftinx_ratio;
389 u16 fftinx_bfsfcw_ratio;
390 u8 count;
391 u8 bw;
392 u8 adcmultiplier;
393
394 deb_info("Bandwidth %d Adc %d", bandwidth, adcFrequency);
395
f908cf1d
MCC		 396 switch (bandwidth) {
397 case 5000000:
3dbbf82f 398 bw = 3;
f908cf1d
MCC		 399 break;
400 case 6000000:
3dbbf82f 401 bw = 0;
f908cf1d
MCC		 402 break;
403 case 7000000:
3dbbf82f 404 bw = 1;
f908cf1d
MCC		 405 break;
406 default:
407 case 8000000:
3dbbf82f 408 bw = 2;
f908cf1d
MCC		 409 break;
410 }
3dbbf82f
MP		 411 ret = it913x_write_reg(state, PRO_DMOD, REG_BW, bw);
412
413 if (state->table == NULL)
414 return -EINVAL;
415
416 /* In write order */
417 coeff[0] = state->table[bw].coeff_1_2048;
418 coeff[1] = state->table[bw].coeff_2_2k;
419 coeff[2] = state->table[bw].coeff_1_8191;
420 coeff[3] = state->table[bw].coeff_1_8192;
421 coeff[4] = state->table[bw].coeff_1_8193;
422 coeff[5] = state->table[bw].coeff_2_8k;
423 coeff[6] = state->table[bw].coeff_1_4096;
424 coeff[7] = state->table[bw].coeff_2_4k;
425 bfsfcw_fftinx_ratio = state->table[bw].bfsfcw_fftinx_ratio;
426 fftinx_bfsfcw_ratio = state->table[bw].fftinx_bfsfcw_ratio;
427
428 /* ADC multiplier */
429 ret = it913x_read_reg_u8(state, ADC_X_2);
430 if (ret < 0)
431 return -EINVAL;
432
433 adcmultiplier = ret;
434
435 count = 0;
436
437 /* Build Buffer for COEFF Registers */
438 for (i = 0; i < 8; i++) {
439 if (adcmultiplier == 1)
440 coeff[i] /= 2;
441 buffer[count++] = (coeff[i] >> 24) & 0x3;
442 buffer[count++] = (coeff[i] >> 16) & 0xff;
443 buffer[count++] = (coeff[i] >> 8) & 0xff;
444 buffer[count++] = coeff[i] & 0xff;
445 }
446
447 /* bfsfcw_fftinx_ratio register 0x21-0x22 */
448 buffer[count++] = bfsfcw_fftinx_ratio & 0xff;
449 buffer[count++] = (bfsfcw_fftinx_ratio >> 8) & 0xff;
450 /* fftinx_bfsfcw_ratio register 0x23-0x24 */
451 buffer[count++] = fftinx_bfsfcw_ratio & 0xff;
452 buffer[count++] = (fftinx_bfsfcw_ratio >> 8) & 0xff;
453 /* start at COEFF_1_2048 and write through to fftinx_bfsfcw_ratio*/
454 ret = it913x_write(state, PRO_DMOD, COEFF_1_2048, buffer, count);
455
456 for (i = 0; i < 42; i += 8)
457 debug_data_snipet(0x1, "Buffer", &buffer[i]);
458
459 return ret;
460}
461
462
463
464static int it913x_fe_read_status(struct dvb_frontend *fe, fe_status_t *status)
465{
466 struct it913x_fe_state *state = fe->demodulator_priv;
467 int ret, i;
468 fe_status_t old_status = state->it913x_status;
469 *status = 0;
470
471 if (state->it913x_status == 0) {
472 ret = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS);
473 if (ret == 0x1) {
474 *status |= FE_HAS_SIGNAL;
475 for (i = 0; i < 40; i++) {
476 ret = it913x_read_reg_u8(state, MP2IF_SYNC_LK);
477 if (ret == 0x1)
478 break;
479 msleep(25);
480 }
481 if (ret == 0x1)
482 *status |= FE_HAS_CARRIER
483 | FE_HAS_VITERBI
484 | FE_HAS_SYNC;
485 state->it913x_status = *status;
486 }
487 }
488
489 if (state->it913x_status & FE_HAS_SYNC) {
490 ret = it913x_read_reg_u8(state, TPSD_LOCK);
491 if (ret == 0x1)
492 *status |= FE_HAS_LOCK
493 | state->it913x_status;
494 else
495 state->it913x_status = 0;
496 if (old_status != state->it913x_status)
497 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, ret);
498 }
499
500 return 0;
501}
502
503static int it913x_fe_read_signal_strength(struct dvb_frontend *fe,
504 u16 *strength)
505{
506 struct it913x_fe_state *state = fe->demodulator_priv;
507 int ret = it913x_read_reg_u8(state, SIGNAL_LEVEL);
508 /*SIGNAL_LEVEL always returns 100%! so using FE_HAS_SIGNAL as switch*/
509 if (state->it913x_status & FE_HAS_SIGNAL)
510 ret = (ret * 0xff) / 0x64;
511 else
512 ret = 0x0;
513 ret |= ret << 0x8;
514 *strength = ret;
515 return 0;
516}
517
3339a5b1 518static int it913x_fe_read_snr(struct dvb_frontend *fe, u16 *snr)
3dbbf82f
MP		 519{
520 struct it913x_fe_state *state = fe->demodulator_priv;
3339a5b1
MP		 521 int ret;
522 u8 reg[3];
523 u32 snr_val, snr_min, snr_max;
524 u32 temp;
525
526 ret = it913x_read_reg(state, 0x2c, reg, sizeof(reg));
527
9544e8a6 528 snr_val = (u32)(reg[2] << 16) | (reg[1] << 8) | reg[0];
3339a5b1
MP		 529
530 ret |= it913x_read_reg(state, 0xf78b, reg, 1);
531 if (reg[0])
532 snr_val /= reg[0];
533
534 if (state->transmission_mode == TRANSMISSION_MODE_2K)
535 snr_val *= 4;
536 else if (state->transmission_mode == TRANSMISSION_MODE_4K)
537 snr_val *= 2;
538
539 if (state->constellation == QPSK) {
540 snr_min = 0xb4711;
541 snr_max = 0x191451;
542 } else if (state->constellation == QAM_16) {
543 snr_min = 0x4f0d5;
544 snr_max = 0xc7925;
545 } else if (state->constellation == QAM_64) {
546 snr_min = 0x256d0;
547 snr_max = 0x626be;
548 } else
549 return -EINVAL;
550
551 if (snr_val < snr_min)
552 *snr = 0;
553 else if (snr_val < snr_max) {
554 temp = (snr_val - snr_min) >> 5;
555 temp *= 0xffff;
556 temp /= (snr_max - snr_min) >> 5;
557 *snr = (u16)temp;
558 } else
559 *snr = 0xffff;
560
561 return (ret < 0) ? -ENODEV : 0;
3dbbf82f
MP		 562}
563
564static int it913x_fe_read_ber(struct dvb_frontend *fe, u32 *ber)
565{
82a05014
MP		 566 struct it913x_fe_state *state = fe->demodulator_priv;
567 int ret;
568 u8 reg[5];
569 /* Read Aborted Packets and Pre-Viterbi error rate 5 bytes */
570 ret = it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg));
571 state->ucblocks += (u32)(reg[1] << 8) | reg[0];
572 *ber = (u32)(reg[4] << 16) | (reg[3] << 8) | reg[2];
3dbbf82f
MP		 573 return 0;
574}
575
576static int it913x_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
577{
82a05014
MP		 578 struct it913x_fe_state *state = fe->demodulator_priv;
579 int ret;
580 u8 reg[2];
581 /* Aborted Packets */
582 ret = it913x_read_reg(state, RSD_ABORT_PKT_LSB, reg, sizeof(reg));
583 state->ucblocks += (u32)(reg[1] << 8) | reg[0];
584 *ucblocks = state->ucblocks;
585 return ret;
3dbbf82f
MP		 586}
587
7c61d80a 588static int it913x_fe_get_frontend(struct dvb_frontend *fe)
3dbbf82f 589{
7c61d80a 590 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3dbbf82f
MP		 591 struct it913x_fe_state *state = fe->demodulator_priv;
592 int ret;
593 u8 reg[8];
594
595 ret = it913x_read_reg(state, REG_TPSD_TX_MODE, reg, sizeof(reg));
596
597 if (reg[3] < 3)
f908cf1d 598 p->modulation = fe_con[reg[3]];
3339a5b1 599
3dbbf82f 600 if (reg[0] < 3)
f908cf1d 601 p->transmission_mode = fe_mode[reg[0]];
3339a5b1 602
3dbbf82f 603 if (reg[1] < 4)
f908cf1d 604 p->guard_interval = fe_gi[reg[1]];
3dbbf82f
MP		 605
606 if (reg[2] < 4)
f908cf1d
MCC		 607 p->hierarchy = fe_hi[reg[2]];
608
609 p->code_rate_HP = (reg[6] < 6) ? fe_code[reg[6]] : FEC_NONE;
610 p->code_rate_LP = (reg[7] < 6) ? fe_code[reg[7]] : FEC_NONE;
3dbbf82f 611
f908cf1d
MCC		 612 /* Update internal state to reflect the autodetected props */
613 state->constellation = p->modulation;
614 state->transmission_mode = p->transmission_mode;
3dbbf82f
MP		 615
616 return 0;
617}
618
f908cf1d 619static int it913x_fe_set_frontend(struct dvb_frontend *fe)
3dbbf82f 620{
f908cf1d 621 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3dbbf82f
MP		 622 struct it913x_fe_state *state = fe->demodulator_priv;
623 int ret, i;
624 u8 empty_ch, last_ch;
625
626 state->it913x_status = 0;
627
628 /* Set bw*/
f908cf1d 629 ret = it913x_fe_select_bw(state, p->bandwidth_hz,
3dbbf82f
MP		 630 state->adcFrequency);
631
632 /* Training Mode Off */
633 ret = it913x_write_reg(state, PRO_LINK, TRAINING_MODE, 0x0);
634
635 /* Clear Empty Channel */
636 ret = it913x_write_reg(state, PRO_DMOD, EMPTY_CHANNEL_STATUS, 0x0);
637
638 /* Clear bits */
639 ret = it913x_write_reg(state, PRO_DMOD, MP2IF_SYNC_LK, 0x0);
640 /* LED on */
641 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1);
642 /* Select Band*/
643 if ((p->frequency >= 51000000) && (p->frequency <= 230000000))
644 i = 0;
645 else if ((p->frequency >= 350000000) && (p->frequency <= 900000000))
646 i = 1;
647 else if ((p->frequency >= 1450000000) && (p->frequency <= 1680000000))
648 i = 2;
f908cf1d
MCC		 649 else
650 return -EOPNOTSUPP;
3dbbf82f
MP		 651
652 ret = it913x_write_reg(state, PRO_DMOD, FREE_BAND, i);
653
654 deb_info("Frontend Set Tuner Type %02x", state->tuner_type);
655 switch (state->tuner_type) {
b7d425d3
MP		 656 case IT9135_38:
657 case IT9135_51:
658 case IT9135_52:
659 case IT9135_60:
660 case IT9135_61:
661 case IT9135_62:
3dbbf82f 662 ret = it9137_set_tuner(state,
f908cf1d 663 p->bandwidth_hz, p->frequency);
3dbbf82f
MP		 664 break;
665 default:
666 if (fe->ops.tuner_ops.set_params) {
14d24d14 667 fe->ops.tuner_ops.set_params(fe);
3dbbf82f
MP		 668 if (fe->ops.i2c_gate_ctrl)
669 fe->ops.i2c_gate_ctrl(fe, 0);
670 }
671 break;
672 }
673 /* LED off */
674 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0);
675 /* Trigger ofsm */
676 ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0);
677 last_ch = 2;
678 for (i = 0; i < 40; ++i) {
679 empty_ch = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS);
680 if (last_ch == 1 && empty_ch == 1)
681 break;
682 if (last_ch == 2 && empty_ch == 2)
683 return 0;
684 last_ch = empty_ch;
685 msleep(25);
686 }
687 for (i = 0; i < 40; ++i) {
688 if (it913x_read_reg_u8(state, D_TPSD_LOCK) == 1)
689 break;
690 msleep(25);
691 }
692
693 state->frequency = p->frequency;
694 return 0;
695}
696
697static int it913x_fe_suspend(struct it913x_fe_state *state)
698{
699 int ret, i;
700 u8 b;
701
702 ret = it913x_write_reg(state, PRO_DMOD, SUSPEND_FLAG, 0x1);
703
704 ret |= it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0);
705
706 for (i = 0; i < 128; i++) {
707 ret = it913x_read_reg(state, SUSPEND_FLAG, &b, 1);
708 if (ret < 0)
e3052885 709 return -ENODEV;
3dbbf82f
MP		 710 if (b == 0)
711 break;
712
713 }
714
715 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x8);
716 /* Turn LED off */
e3052885 717 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0);
3dbbf82f 718
e3052885
MP		 719 ret |= it913x_fe_script_loader(state, it9137_tuner_off);
720
721 return (ret < 0) ? -ENODEV : 0;
3dbbf82f
MP		 722}
723
e3052885
MP		 724/* Power sequence */
725/* Power Up Tuner on -> Frontend suspend off -> Tuner clk on */
726/* Power Down Frontend suspend on -> Tuner clk off -> Tuner off */
727
3dbbf82f
MP		 728static int it913x_fe_sleep(struct dvb_frontend *fe)
729{
730 struct it913x_fe_state *state = fe->demodulator_priv;
731 return it913x_fe_suspend(state);
732}
733
3dbbf82f
MP		 734static u32 compute_div(u32 a, u32 b, u32 x)
735{
736 u32 res = 0;
737 u32 c = 0;
738 u32 i = 0;
739
740 if (a > b) {
741 c = a / b;
742 a = a - c * b;
743 }
744
745 for (i = 0; i < x; i++) {
746 if (a >= b) {
747 res += 1;
748 a -= b;
749 }
750 a <<= 1;
751 res <<= 1;
752 }
753
754 res = (c << x) + res;
755
756 return res;
757}
758
759static int it913x_fe_start(struct it913x_fe_state *state)
760{
b7d425d3 761 struct it913xset *set_lna;
3dbbf82f
MP		 762 struct it913xset *set_mode;
763 int ret;
b7d425d3 764 u8 adf = (state->config->adf & 0xf);
3dbbf82f
MP		 765 u32 adc, xtal;
766 u8 b[4];
767
b7d425d3
MP		 768 if (state->config->chip_ver == 1)
769 ret = it913x_init_tuner(state);
7c2808e2 770
ed942c50
MP		 771 info("ADF table value :%02x", adf);
772
2b3c13ec 773 if (adf < 10) {
3dbbf82f
MP		 774 state->crystalFrequency = fe_clockTable[adf].xtal ;
775 state->table = fe_clockTable[adf].table;
776 state->adcFrequency = state->table->adcFrequency;
777
778 adc = compute_div(state->adcFrequency, 1000000ul, 19ul);
779 xtal = compute_div(state->crystalFrequency, 1000000ul, 19ul);
780
781 } else
782 return -EINVAL;
783
3dbbf82f
MP		 784 /* Set LED indicator on GPIOH3 */
785 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_EN, 0x1);
786 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_ON, 0x1);
787 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1);
788
3dbbf82f
MP		 789 ret |= it913x_write_reg(state, PRO_LINK, 0xf641, state->tuner_type);
790 ret |= it913x_write_reg(state, PRO_DMOD, 0xf5ca, 0x01);
791 ret |= it913x_write_reg(state, PRO_DMOD, 0xf715, 0x01);
792
793 b[0] = xtal & 0xff;
794 b[1] = (xtal >> 8) & 0xff;
795 b[2] = (xtal >> 16) & 0xff;
796 b[3] = (xtal >> 24);
797 ret |= it913x_write(state, PRO_DMOD, XTAL_CLK, b , 4);
798
799 b[0] = adc & 0xff;
800 b[1] = (adc >> 8) & 0xff;
801 b[2] = (adc >> 16) & 0xff;
802 ret |= it913x_write(state, PRO_DMOD, ADC_FREQ, b, 3);
ed942c50 803
990f49af
MP		 804 if (state->config->adc_x2)
805 ret |= it913x_write_reg(state, PRO_DMOD, ADC_X_2, 0x01);
806 b[0] = 0;
807 b[1] = 0;
808 b[2] = 0;
809 ret |= it913x_write(state, PRO_DMOD, 0x0029, b, 3);
810
811 info("Crystal Frequency :%d Adc Frequency :%d ADC X2: %02x",
812 state->crystalFrequency, state->adcFrequency,
813 state->config->adc_x2);
ed942c50
MP		 814 deb_info("Xtal value :%04x Adc value :%04x", xtal, adc);
815
b7d425d3
MP		 816 if (ret < 0)
817 return -ENODEV;
3dbbf82f 818
b7d425d3
MP		 819 /* v1 or v2 tuner script */
820 if (state->config->chip_ver > 1)
821 ret = it913x_fe_script_loader(state, it9135_v2);
822 else
823 ret = it913x_fe_script_loader(state, it9135_v1);
824 if (ret < 0)
825 return ret;
826
827 /* LNA Scripts */
3dbbf82f 828 switch (state->tuner_type) {
b7d425d3
MP		 829 case IT9135_51:
830 set_lna = it9135_51;
831 break;
832 case IT9135_52:
833 set_lna = it9135_52;
3dbbf82f 834 break;
b7d425d3
MP		 835 case IT9135_60:
836 set_lna = it9135_60;
837 break;
838 case IT9135_61:
839 set_lna = it9135_61;
840 break;
841 case IT9135_62:
842 set_lna = it9135_62;
843 break;
844 case IT9135_38:
3dbbf82f 845 default:
b7d425d3 846 set_lna = it9135_38;
3dbbf82f 847 }
ed942c50
MP		 848 info("Tuner LNA type :%02x", state->tuner_type);
849
b7d425d3
MP		 850 ret = it913x_fe_script_loader(state, set_lna);
851 if (ret < 0)
852 return ret;
853
854 if (state->config->chip_ver == 2) {
855 ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x1);
856 ret |= it913x_write_reg(state, PRO_LINK, PADODPU, 0x0);
857 ret |= it913x_write_reg(state, PRO_LINK, AGC_O_D, 0x0);
858 ret |= it913x_init_tuner(state);
859 }
860 if (ret < 0)
861 return -ENODEV;
7c2808e2 862
3dbbf82f
MP		 863 /* Always solo frontend */
864 set_mode = set_solo_fe;
865 ret |= it913x_fe_script_loader(state, set_mode);
866
867 ret |= it913x_fe_suspend(state);
b7d425d3 868 return (ret < 0) ? -ENODEV : 0;
3dbbf82f
MP		 869}
870
871static int it913x_fe_init(struct dvb_frontend *fe)
872{
873 struct it913x_fe_state *state = fe->demodulator_priv;
3dbbf82f 874 int ret = 0;
e3052885
MP		 875 /* Power Up Tuner - common all versions */
876 ret = it913x_write_reg(state, PRO_DMOD, 0xec40, 0x1);
3dbbf82f 877
3dbbf82f
MP		 878 ret |= it913x_fe_script_loader(state, init_1);
879
990f49af
MP		 880 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x0);
881
b7d425d3 882 ret |= it913x_write_reg(state, PRO_DMOD, 0xfba8, 0x0);
e3052885 883
3dbbf82f
MP		 884 return (ret < 0) ? -ENODEV : 0;
885}
886
887static void it913x_fe_release(struct dvb_frontend *fe)
888{
889 struct it913x_fe_state *state = fe->demodulator_priv;
890 kfree(state);
891}
892
893static struct dvb_frontend_ops it913x_fe_ofdm_ops;
894
895struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
b7d425d3 896 u8 i2c_addr, struct ite_config *config)
3dbbf82f
MP		 897{
898 struct it913x_fe_state *state = NULL;
899 int ret;
b7d425d3 900
3dbbf82f
MP		 901 /* allocate memory for the internal state */
902 state = kzalloc(sizeof(struct it913x_fe_state), GFP_KERNEL);
903 if (state == NULL)
b7d425d3
MP		 904 return NULL;
905 if (config == NULL)
3dbbf82f
MP		 906 goto error;
907
908 state->i2c_adap = i2c_adap;
909 state->i2c_addr = i2c_addr;
b7d425d3
MP		 910 state->config = config;
911
912 switch (state->config->tuner_id_0) {
913 case IT9135_51:
914 case IT9135_52:
915 case IT9135_60:
916 case IT9135_61:
917 case IT9135_62:
918 state->tuner_type = state->config->tuner_id_0;
919 break;
920 default:
921 case IT9135_38:
922 state->tuner_type = IT9135_38;
923 }
3dbbf82f
MP		 924
925 ret = it913x_fe_start(state);
926 if (ret < 0)
927 goto error;
928
929
930 /* create dvb_frontend */
931 memcpy(&state->frontend.ops, &it913x_fe_ofdm_ops,
932 sizeof(struct dvb_frontend_ops));
933 state->frontend.demodulator_priv = state;
934
935 return &state->frontend;
936error:
937 kfree(state);
938 return NULL;
939}
940EXPORT_SYMBOL(it913x_fe_attach);
941
942static struct dvb_frontend_ops it913x_fe_ofdm_ops = {
f908cf1d 943 .delsys = { SYS_DVBT },
3dbbf82f
MP		 944 .info = {
945 .name = "it913x-fe DVB-T",
3dbbf82f
MP		 946 .frequency_min = 51000000,
947 .frequency_max = 1680000000,
948 .frequency_stepsize = 62500,
949 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
950 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
951 FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
952 FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
953 FE_CAN_TRANSMISSION_MODE_AUTO |
954 FE_CAN_GUARD_INTERVAL_AUTO |
955 FE_CAN_HIERARCHY_AUTO,
956 },
957
958 .release = it913x_fe_release,
959
960 .init = it913x_fe_init,
961 .sleep = it913x_fe_sleep,
962
f908cf1d
MCC		 963 .set_frontend = it913x_fe_set_frontend,
964 .get_frontend = it913x_fe_get_frontend,
3dbbf82f
MP		 965
966 .read_status = it913x_fe_read_status,
967 .read_signal_strength = it913x_fe_read_signal_strength,
968 .read_snr = it913x_fe_read_snr,
969 .read_ber = it913x_fe_read_ber,
970 .read_ucblocks = it913x_fe_read_ucblocks,
971};
972
973MODULE_DESCRIPTION("it913x Frontend and it9137 tuner");
974MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
82a05014 975MODULE_VERSION("1.13");
3dbbf82f 976MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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