Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | driver for LSI L64781 COFDM demodulator | |
3 | ||
4 | Copyright (C) 2001 Holger Waechtler for Convergence Integrated Media GmbH | |
9101e622 | 5 | Marko Kohtala <marko.kohtala@luukku.com> |
1da177e4 LT |
6 | |
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | ||
21 | */ | |
22 | ||
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/string.h> | |
28 | #include <linux/slab.h> | |
29 | #include "dvb_frontend.h" | |
30 | #include "l64781.h" | |
31 | ||
32 | ||
33 | struct l64781_state { | |
34 | struct i2c_adapter* i2c; | |
1da177e4 LT |
35 | const struct l64781_config* config; |
36 | struct dvb_frontend frontend; | |
37 | ||
38 | /* private demodulator data */ | |
39 | int first:1; | |
40 | }; | |
41 | ||
42 | #define dprintk(args...) \ | |
43 | do { \ | |
44 | if (debug) printk(KERN_DEBUG "l64781: " args); \ | |
45 | } while (0) | |
46 | ||
47 | static int debug; | |
48 | ||
49 | module_param(debug, int, 0644); | |
50 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); | |
51 | ||
52 | ||
53 | static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data) | |
54 | { | |
55 | int ret; | |
56 | u8 buf [] = { reg, data }; | |
57 | struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; | |
58 | ||
59 | if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) | |
60 | dprintk ("%s: write_reg error (reg == %02x) = %02x!\n", | |
61 | __FUNCTION__, reg, ret); | |
62 | ||
63 | return (ret != 1) ? -1 : 0; | |
64 | } | |
65 | ||
66 | static int l64781_readreg (struct l64781_state* state, u8 reg) | |
67 | { | |
68 | int ret; | |
69 | u8 b0 [] = { reg }; | |
70 | u8 b1 [] = { 0 }; | |
71 | struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, | |
72 | { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; | |
73 | ||
74 | ret = i2c_transfer(state->i2c, msg, 2); | |
75 | ||
76 | if (ret != 2) return ret; | |
77 | ||
78 | return b1[0]; | |
79 | } | |
80 | ||
81 | static void apply_tps (struct l64781_state* state) | |
82 | { | |
83 | l64781_writereg (state, 0x2a, 0x00); | |
84 | l64781_writereg (state, 0x2a, 0x01); | |
85 | ||
86 | /* This here is a little bit questionable because it enables | |
87 | the automatic update of TPS registers. I think we'd need to | |
88 | handle the IRQ from FE to update some other registers as | |
89 | well, or at least implement some magic to tuning to correct | |
90 | to the TPS received from transmission. */ | |
91 | l64781_writereg (state, 0x2a, 0x02); | |
92 | } | |
93 | ||
94 | ||
95 | static void reset_afc (struct l64781_state* state) | |
96 | { | |
97 | /* Set AFC stall for the AFC_INIT_FRQ setting, TIM_STALL for | |
98 | timing offset */ | |
99 | l64781_writereg (state, 0x07, 0x9e); /* stall AFC */ | |
100 | l64781_writereg (state, 0x08, 0); /* AFC INIT FREQ */ | |
101 | l64781_writereg (state, 0x09, 0); | |
102 | l64781_writereg (state, 0x0a, 0); | |
103 | l64781_writereg (state, 0x07, 0x8e); | |
104 | l64781_writereg (state, 0x0e, 0); /* AGC gain to zero in beginning */ | |
105 | l64781_writereg (state, 0x11, 0x80); /* stall TIM */ | |
106 | l64781_writereg (state, 0x10, 0); /* TIM_OFFSET_LSB */ | |
107 | l64781_writereg (state, 0x12, 0); | |
108 | l64781_writereg (state, 0x13, 0); | |
109 | l64781_writereg (state, 0x11, 0x00); | |
110 | } | |
111 | ||
112 | static int reset_and_configure (struct l64781_state* state) | |
113 | { | |
114 | u8 buf [] = { 0x06 }; | |
115 | struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 }; | |
116 | // NOTE: this is correct in writing to address 0x00 | |
117 | ||
118 | return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV; | |
119 | } | |
120 | ||
121 | static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_parameters *param) | |
122 | { | |
b8742700 | 123 | struct l64781_state* state = fe->demodulator_priv; |
1da177e4 LT |
124 | /* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */ |
125 | static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 }; | |
126 | /* QPSK, QAM_16, QAM_64 */ | |
127 | static const u8 qam_tab [] = { 2, 4, 0, 6 }; | |
128 | static const u8 bw_tab [] = { 8, 7, 6 }; /* 8Mhz, 7MHz, 6MHz */ | |
129 | static const u8 guard_tab [] = { 1, 2, 4, 8 }; | |
130 | /* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */ | |
131 | static const u32 ppm = 8000; | |
132 | struct dvb_ofdm_parameters *p = ¶m->u.ofdm; | |
133 | u32 ddfs_offset_fixed; | |
134 | /* u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */ | |
135 | /* bw_tab[p->bandWidth]<<10)/15625; */ | |
136 | u32 init_freq; | |
137 | u32 spi_bias; | |
138 | u8 val0x04; | |
139 | u8 val0x05; | |
140 | u8 val0x06; | |
141 | int bw = p->bandwidth - BANDWIDTH_8_MHZ; | |
142 | ||
dea74869 PB |
143 | if (fe->ops.tuner_ops.set_params) { |
144 | fe->ops.tuner_ops.set_params(fe, param); | |
145 | if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); | |
b800aae3 | 146 | } |
1da177e4 LT |
147 | |
148 | if (param->inversion != INVERSION_ON && | |
149 | param->inversion != INVERSION_OFF) | |
150 | return -EINVAL; | |
151 | ||
152 | if (bw < 0 || bw > 2) | |
153 | return -EINVAL; | |
154 | ||
155 | if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 && | |
156 | p->code_rate_HP != FEC_3_4 && p->code_rate_HP != FEC_5_6 && | |
157 | p->code_rate_HP != FEC_7_8) | |
158 | return -EINVAL; | |
159 | ||
160 | if (p->hierarchy_information != HIERARCHY_NONE && | |
161 | (p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 && | |
162 | p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 && | |
163 | p->code_rate_LP != FEC_7_8)) | |
164 | return -EINVAL; | |
165 | ||
166 | if (p->constellation != QPSK && p->constellation != QAM_16 && | |
167 | p->constellation != QAM_64) | |
168 | return -EINVAL; | |
169 | ||
170 | if (p->transmission_mode != TRANSMISSION_MODE_2K && | |
171 | p->transmission_mode != TRANSMISSION_MODE_8K) | |
172 | return -EINVAL; | |
173 | ||
174 | if (p->guard_interval < GUARD_INTERVAL_1_32 || | |
175 | p->guard_interval > GUARD_INTERVAL_1_4) | |
176 | return -EINVAL; | |
177 | ||
178 | if (p->hierarchy_information < HIERARCHY_NONE || | |
179 | p->hierarchy_information > HIERARCHY_4) | |
180 | return -EINVAL; | |
181 | ||
182 | ddfs_offset_fixed = 0x4000-(ppm<<16)/bw_tab[p->bandwidth]/1000000; | |
183 | ||
184 | /* This works up to 20000 ppm, it overflows if too large ppm! */ | |
185 | init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) / | |
186 | bw_tab[p->bandwidth] & 0xFFFFFF); | |
187 | ||
188 | /* SPI bias calculation is slightly modified to fit in 32bit */ | |
189 | /* will work for high ppm only... */ | |
190 | spi_bias = 378 * (1 << 10); | |
191 | spi_bias *= 16; | |
192 | spi_bias *= bw_tab[p->bandwidth]; | |
193 | spi_bias *= qam_tab[p->constellation]; | |
194 | spi_bias /= p->code_rate_HP + 1; | |
195 | spi_bias /= (guard_tab[p->guard_interval] + 32); | |
196 | spi_bias *= 1000ULL; | |
197 | spi_bias /= 1000ULL + ppm/1000; | |
198 | spi_bias *= p->code_rate_HP; | |
199 | ||
200 | val0x04 = (p->transmission_mode << 2) | p->guard_interval; | |
201 | val0x05 = fec_tab[p->code_rate_HP]; | |
202 | ||
203 | if (p->hierarchy_information != HIERARCHY_NONE) | |
204 | val0x05 |= (p->code_rate_LP - FEC_1_2) << 3; | |
205 | ||
206 | val0x06 = (p->hierarchy_information << 2) | p->constellation; | |
207 | ||
208 | l64781_writereg (state, 0x04, val0x04); | |
209 | l64781_writereg (state, 0x05, val0x05); | |
210 | l64781_writereg (state, 0x06, val0x06); | |
211 | ||
212 | reset_afc (state); | |
213 | ||
214 | /* Technical manual section 2.6.1, TIM_IIR_GAIN optimal values */ | |
215 | l64781_writereg (state, 0x15, | |
216 | p->transmission_mode == TRANSMISSION_MODE_2K ? 1 : 3); | |
217 | l64781_writereg (state, 0x16, init_freq & 0xff); | |
218 | l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff); | |
219 | l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff); | |
220 | ||
221 | l64781_writereg (state, 0x1b, spi_bias & 0xff); | |
222 | l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff); | |
223 | l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) | | |
224 | (param->inversion == INVERSION_ON ? 0x80 : 0x00)); | |
225 | ||
226 | l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff); | |
227 | l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f); | |
228 | ||
229 | l64781_readreg (state, 0x00); /* clear interrupt registers... */ | |
230 | l64781_readreg (state, 0x01); /* dto. */ | |
231 | ||
232 | apply_tps (state); | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
237 | static int get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters* param) | |
238 | { | |
b8742700 | 239 | struct l64781_state* state = fe->demodulator_priv; |
1da177e4 LT |
240 | int tmp; |
241 | ||
242 | ||
243 | tmp = l64781_readreg(state, 0x04); | |
244 | switch(tmp & 3) { | |
245 | case 0: | |
246 | param->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; | |
247 | break; | |
248 | case 1: | |
249 | param->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; | |
250 | break; | |
251 | case 2: | |
252 | param->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; | |
253 | break; | |
254 | case 3: | |
255 | param->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; | |
256 | break; | |
257 | } | |
258 | switch((tmp >> 2) & 3) { | |
259 | case 0: | |
260 | param->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; | |
261 | break; | |
262 | case 1: | |
263 | param->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; | |
264 | break; | |
265 | default: | |
266 | printk("Unexpected value for transmission_mode\n"); | |
267 | } | |
268 | ||
269 | ||
270 | ||
271 | tmp = l64781_readreg(state, 0x05); | |
272 | switch(tmp & 7) { | |
273 | case 0: | |
274 | param->u.ofdm.code_rate_HP = FEC_1_2; | |
275 | break; | |
276 | case 1: | |
277 | param->u.ofdm.code_rate_HP = FEC_2_3; | |
278 | break; | |
279 | case 2: | |
280 | param->u.ofdm.code_rate_HP = FEC_3_4; | |
281 | break; | |
282 | case 3: | |
283 | param->u.ofdm.code_rate_HP = FEC_5_6; | |
284 | break; | |
285 | case 4: | |
286 | param->u.ofdm.code_rate_HP = FEC_7_8; | |
287 | break; | |
288 | default: | |
289 | printk("Unexpected value for code_rate_HP\n"); | |
290 | } | |
291 | switch((tmp >> 3) & 7) { | |
292 | case 0: | |
293 | param->u.ofdm.code_rate_LP = FEC_1_2; | |
294 | break; | |
295 | case 1: | |
296 | param->u.ofdm.code_rate_LP = FEC_2_3; | |
297 | break; | |
298 | case 2: | |
299 | param->u.ofdm.code_rate_LP = FEC_3_4; | |
300 | break; | |
301 | case 3: | |
302 | param->u.ofdm.code_rate_LP = FEC_5_6; | |
303 | break; | |
304 | case 4: | |
305 | param->u.ofdm.code_rate_LP = FEC_7_8; | |
306 | break; | |
307 | default: | |
308 | printk("Unexpected value for code_rate_LP\n"); | |
309 | } | |
310 | ||
311 | ||
312 | tmp = l64781_readreg(state, 0x06); | |
313 | switch(tmp & 3) { | |
314 | case 0: | |
315 | param->u.ofdm.constellation = QPSK; | |
316 | break; | |
317 | case 1: | |
318 | param->u.ofdm.constellation = QAM_16; | |
319 | break; | |
320 | case 2: | |
321 | param->u.ofdm.constellation = QAM_64; | |
322 | break; | |
323 | default: | |
324 | printk("Unexpected value for constellation\n"); | |
325 | } | |
326 | switch((tmp >> 2) & 7) { | |
327 | case 0: | |
328 | param->u.ofdm.hierarchy_information = HIERARCHY_NONE; | |
329 | break; | |
330 | case 1: | |
331 | param->u.ofdm.hierarchy_information = HIERARCHY_1; | |
332 | break; | |
333 | case 2: | |
334 | param->u.ofdm.hierarchy_information = HIERARCHY_2; | |
335 | break; | |
336 | case 3: | |
337 | param->u.ofdm.hierarchy_information = HIERARCHY_4; | |
338 | break; | |
339 | default: | |
340 | printk("Unexpected value for hierarchy\n"); | |
341 | } | |
342 | ||
343 | ||
344 | tmp = l64781_readreg (state, 0x1d); | |
345 | param->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF; | |
346 | ||
347 | tmp = (int) (l64781_readreg (state, 0x08) | | |
348 | (l64781_readreg (state, 0x09) << 8) | | |
349 | (l64781_readreg (state, 0x0a) << 16)); | |
350 | param->frequency += tmp; | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
355 | static int l64781_read_status(struct dvb_frontend* fe, fe_status_t* status) | |
356 | { | |
b8742700 | 357 | struct l64781_state* state = fe->demodulator_priv; |
1da177e4 LT |
358 | int sync = l64781_readreg (state, 0x32); |
359 | int gain = l64781_readreg (state, 0x0e); | |
360 | ||
361 | l64781_readreg (state, 0x00); /* clear interrupt registers... */ | |
362 | l64781_readreg (state, 0x01); /* dto. */ | |
363 | ||
364 | *status = 0; | |
365 | ||
366 | if (gain > 5) | |
367 | *status |= FE_HAS_SIGNAL; | |
368 | ||
369 | if (sync & 0x02) /* VCXO locked, this criteria should be ok */ | |
370 | *status |= FE_HAS_CARRIER; | |
371 | ||
372 | if (sync & 0x20) | |
373 | *status |= FE_HAS_VITERBI; | |
374 | ||
375 | if (sync & 0x40) | |
376 | *status |= FE_HAS_SYNC; | |
377 | ||
378 | if (sync == 0x7f) | |
379 | *status |= FE_HAS_LOCK; | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
384 | static int l64781_read_ber(struct dvb_frontend* fe, u32* ber) | |
385 | { | |
b8742700 | 386 | struct l64781_state* state = fe->demodulator_priv; |
1da177e4 LT |
387 | |
388 | /* XXX FIXME: set up counting period (reg 0x26...0x28) | |
389 | */ | |
390 | *ber = l64781_readreg (state, 0x39) | |
391 | | (l64781_readreg (state, 0x3a) << 8); | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | static int l64781_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength) | |
397 | { | |
b8742700 | 398 | struct l64781_state* state = fe->demodulator_priv; |
1da177e4 LT |
399 | |
400 | u8 gain = l64781_readreg (state, 0x0e); | |
401 | *signal_strength = (gain << 8) | gain; | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
406 | static int l64781_read_snr(struct dvb_frontend* fe, u16* snr) | |
407 | { | |
b8742700 | 408 | struct l64781_state* state = fe->demodulator_priv; |
1da177e4 LT |
409 | |
410 | u8 avg_quality = 0xff - l64781_readreg (state, 0x33); | |
411 | *snr = (avg_quality << 8) | avg_quality; /* not exact, but...*/ | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
416 | static int l64781_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) | |
417 | { | |
b8742700 | 418 | struct l64781_state* state = fe->demodulator_priv; |
1da177e4 LT |
419 | |
420 | *ucblocks = l64781_readreg (state, 0x37) | |
421 | | (l64781_readreg (state, 0x38) << 8); | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
426 | static int l64781_sleep(struct dvb_frontend* fe) | |
427 | { | |
b8742700 | 428 | struct l64781_state* state = fe->demodulator_priv; |
1da177e4 LT |
429 | |
430 | /* Power down */ | |
431 | return l64781_writereg (state, 0x3e, 0x5a); | |
432 | } | |
433 | ||
434 | static int l64781_init(struct dvb_frontend* fe) | |
435 | { | |
b8742700 | 436 | struct l64781_state* state = fe->demodulator_priv; |
1da177e4 | 437 | |
9101e622 | 438 | reset_and_configure (state); |
1da177e4 LT |
439 | |
440 | /* Power up */ | |
441 | l64781_writereg (state, 0x3e, 0xa5); | |
442 | ||
443 | /* Reset hard */ | |
444 | l64781_writereg (state, 0x2a, 0x04); | |
445 | l64781_writereg (state, 0x2a, 0x00); | |
446 | ||
447 | /* Set tuner specific things */ | |
448 | /* AFC_POL, set also in reset_afc */ | |
449 | l64781_writereg (state, 0x07, 0x8e); | |
450 | ||
451 | /* Use internal ADC */ | |
452 | l64781_writereg (state, 0x0b, 0x81); | |
453 | ||
454 | /* AGC loop gain, and polarity is positive */ | |
455 | l64781_writereg (state, 0x0c, 0x84); | |
456 | ||
457 | /* Internal ADC outputs two's complement */ | |
458 | l64781_writereg (state, 0x0d, 0x8c); | |
459 | ||
460 | /* With ppm=8000, it seems the DTR_SENSITIVITY will result in | |
9101e622 MCC |
461 | value of 2 with all possible bandwidths and guard |
462 | intervals, which is the initial value anyway. */ | |
463 | /*l64781_writereg (state, 0x19, 0x92);*/ | |
1da177e4 LT |
464 | |
465 | /* Everything is two's complement, soft bit and CSI_OUT too */ | |
466 | l64781_writereg (state, 0x1e, 0x09); | |
467 | ||
1da177e4 LT |
468 | /* delay a bit after first init attempt */ |
469 | if (state->first) { | |
470 | state->first = 0; | |
471 | msleep(200); | |
472 | } | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
80064b80 JS |
477 | static int l64781_get_tune_settings(struct dvb_frontend* fe, |
478 | struct dvb_frontend_tune_settings* fesettings) | |
1da177e4 | 479 | { |
9101e622 MCC |
480 | fesettings->min_delay_ms = 4000; |
481 | fesettings->step_size = 0; | |
482 | fesettings->max_drift = 0; | |
483 | return 0; | |
1da177e4 LT |
484 | } |
485 | ||
486 | static void l64781_release(struct dvb_frontend* fe) | |
487 | { | |
b8742700 | 488 | struct l64781_state* state = fe->demodulator_priv; |
1da177e4 LT |
489 | kfree(state); |
490 | } | |
491 | ||
492 | static struct dvb_frontend_ops l64781_ops; | |
493 | ||
494 | struct dvb_frontend* l64781_attach(const struct l64781_config* config, | |
495 | struct i2c_adapter* i2c) | |
496 | { | |
497 | struct l64781_state* state = NULL; | |
498 | int reg0x3e = -1; | |
499 | u8 b0 [] = { 0x1a }; | |
500 | u8 b1 [] = { 0x00 }; | |
501 | struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 }, | |
502 | { .addr = config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; | |
503 | ||
504 | /* allocate memory for the internal state */ | |
b8742700 | 505 | state = kmalloc(sizeof(struct l64781_state), GFP_KERNEL); |
1da177e4 LT |
506 | if (state == NULL) goto error; |
507 | ||
508 | /* setup the state */ | |
509 | state->config = config; | |
510 | state->i2c = i2c; | |
1da177e4 LT |
511 | state->first = 1; |
512 | ||
513 | /** | |
514 | * the L64781 won't show up before we send the reset_and_configure() | |
515 | * broadcast. If nothing responds there is no L64781 on the bus... | |
516 | */ | |
517 | if (reset_and_configure(state) < 0) { | |
518 | dprintk("No response to reset and configure broadcast...\n"); | |
519 | goto error; | |
520 | } | |
521 | ||
522 | /* The chip always responds to reads */ | |
523 | if (i2c_transfer(state->i2c, msg, 2) != 2) { | |
9101e622 | 524 | dprintk("No response to read on I2C bus\n"); |
1da177e4 LT |
525 | goto error; |
526 | } | |
527 | ||
528 | /* Save current register contents for bailout */ | |
529 | reg0x3e = l64781_readreg(state, 0x3e); | |
530 | ||
531 | /* Reading the POWER_DOWN register always returns 0 */ | |
532 | if (reg0x3e != 0) { | |
9101e622 | 533 | dprintk("Device doesn't look like L64781\n"); |
1da177e4 LT |
534 | goto error; |
535 | } | |
536 | ||
537 | /* Turn the chip off */ | |
538 | l64781_writereg (state, 0x3e, 0x5a); | |
539 | ||
540 | /* Responds to all reads with 0 */ | |
541 | if (l64781_readreg(state, 0x1a) != 0) { | |
9101e622 | 542 | dprintk("Read 1 returned unexpcted value\n"); |
1da177e4 LT |
543 | goto error; |
544 | } | |
545 | ||
546 | /* Turn the chip on */ | |
547 | l64781_writereg (state, 0x3e, 0xa5); | |
548 | ||
549 | /* Responds with register default value */ | |
550 | if (l64781_readreg(state, 0x1a) != 0xa1) { | |
9101e622 | 551 | dprintk("Read 2 returned unexpcted value\n"); |
1da177e4 LT |
552 | goto error; |
553 | } | |
554 | ||
555 | /* create dvb_frontend */ | |
dea74869 | 556 | memcpy(&state->frontend.ops, &l64781_ops, sizeof(struct dvb_frontend_ops)); |
1da177e4 LT |
557 | state->frontend.demodulator_priv = state; |
558 | return &state->frontend; | |
559 | ||
560 | error: | |
2ea75330 JJ |
561 | if (reg0x3e >= 0) |
562 | l64781_writereg (state, 0x3e, reg0x3e); /* restore reg 0x3e */ | |
1da177e4 LT |
563 | kfree(state); |
564 | return NULL; | |
565 | } | |
566 | ||
567 | static struct dvb_frontend_ops l64781_ops = { | |
568 | ||
569 | .info = { | |
570 | .name = "LSI L64781 DVB-T", | |
571 | .type = FE_OFDM, | |
572 | /* .frequency_min = ???,*/ | |
573 | /* .frequency_max = ???,*/ | |
574 | .frequency_stepsize = 166666, | |
575 | /* .frequency_tolerance = ???,*/ | |
576 | /* .symbol_rate_tolerance = ???,*/ | |
577 | .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
578 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | | |
579 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | | |
580 | FE_CAN_MUTE_TS | |
581 | }, | |
582 | ||
583 | .release = l64781_release, | |
584 | ||
585 | .init = l64781_init, | |
586 | .sleep = l64781_sleep, | |
587 | ||
588 | .set_frontend = apply_frontend_param, | |
589 | .get_frontend = get_frontend, | |
590 | .get_tune_settings = l64781_get_tune_settings, | |
591 | ||
592 | .read_status = l64781_read_status, | |
593 | .read_ber = l64781_read_ber, | |
594 | .read_signal_strength = l64781_read_signal_strength, | |
595 | .read_snr = l64781_read_snr, | |
596 | .read_ucblocks = l64781_read_ucblocks, | |
597 | }; | |
598 | ||
599 | MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver"); | |
600 | MODULE_AUTHOR("Holger Waechtler, Marko Kohtala"); | |
601 | MODULE_LICENSE("GPL"); | |
602 | ||
603 | EXPORT_SYMBOL(l64781_attach); |