[deliverable/linux.git] / drivers / media / dvb / frontends / stv0297.c

/*
    Driver for STV0297 demodulator

    Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
    Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/slab.h>

#include "dvb_frontend.h"
#include "stv0297.h"

struct stv0297_state {
	struct i2c_adapter *i2c;
	const struct stv0297_config *config;
	struct dvb_frontend frontend;

	unsigned long last_ber;
	unsigned long base_freq;
};

#if 1
#define dprintk(x...) printk(x)
#else
#define dprintk(x...)
#endif

#define STV0297_CLOCK_KHZ   28900


static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
{
	int ret;
	u8 buf[] = { reg, data };
	struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };

	ret = i2c_transfer(state->i2c, &msg, 1);

	if (ret != 1)
		dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
			"ret == %i)\n", __func__, reg, data, ret);

	return (ret != 1) ? -1 : 0;
}

static int stv0297_readreg(struct stv0297_state *state, u8 reg)
{
	int ret;
	u8 b0[] = { reg };
	u8 b1[] = { 0 };
	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
				 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
			       };

	// this device needs a STOP between the register and data
	if (state->config->stop_during_read) {
		if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
			return -1;
		}
		if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
			return -1;
		}
	} else {
		if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
			return -1;
		}
	}

	return b1[0];
}

static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
{
	int val;

	val = stv0297_readreg(state, reg);
	val &= ~mask;
	val |= (data & mask);
	stv0297_writereg(state, reg, val);

	return 0;
}

static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
{
	int ret;
	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
				  &reg1,.len = 1},
	{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
	};

	// this device needs a STOP between the register and data
	if (state->config->stop_during_read) {
		if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
			return -1;
		}
		if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
			return -1;
		}
	} else {
		if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
			dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
			return -1;
		}
	}

	return 0;
}

static u32 stv0297_get_symbolrate(struct stv0297_state *state)
{
	u64 tmp;

	tmp = stv0297_readreg(state, 0x55);
	tmp |= stv0297_readreg(state, 0x56) << 8;
	tmp |= stv0297_readreg(state, 0x57) << 16;
	tmp |= stv0297_readreg(state, 0x58) << 24;

	tmp *= STV0297_CLOCK_KHZ;
	tmp >>= 32;

	return (u32) tmp;
}

static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
{
	long tmp;

	tmp = 131072L * srate;	/* 131072 = 2^17  */
	tmp = tmp / (STV0297_CLOCK_KHZ / 4);	/* 1/4 = 2^-2 */
	tmp = tmp * 8192L;	/* 8192 = 2^13 */

	stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
	stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
	stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
	stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
}

static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
{
	long tmp;

	tmp = (long) fshift *262144L;	/* 262144 = 2*18 */
	tmp /= symrate;
	tmp *= 1024;		/* 1024 = 2*10   */

	// adjust
	if (tmp >= 0) {
		tmp += 500000;
	} else {
		tmp -= 500000;
	}
	tmp /= 1000000;

	stv0297_writereg(state, 0x60, tmp & 0xFF);
	stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
}

static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
{
	long tmp;

	/* symrate is hardcoded to 10000 */
	tmp = offset * 26844L;	/* (2**28)/10000 */
	if (tmp < 0)
		tmp += 0x10000000;
	tmp &= 0x0FFFFFFF;

	stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
	stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
	stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
	stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
}

/*
static long stv0297_get_carrieroffset(struct stv0297_state *state)
{
	s64 tmp;

	stv0297_writereg(state, 0x6B, 0x00);

	tmp = stv0297_readreg(state, 0x66);
	tmp |= (stv0297_readreg(state, 0x67) << 8);
	tmp |= (stv0297_readreg(state, 0x68) << 16);
	tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;

	tmp *= stv0297_get_symbolrate(state);
	tmp >>= 28;

	return (s32) tmp;
}
*/

static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
{
	s32 tmp;

	if (freq > 10000)
		freq -= STV0297_CLOCK_KHZ;

	tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
	tmp = (freq * 1000) / tmp;
	if (tmp > 0xffff)
		tmp = 0xffff;

	stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
	stv0297_writereg(state, 0x21, tmp >> 8);
	stv0297_writereg(state, 0x20, tmp);
}

static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation)
{
	int val = 0;

	switch (modulation) {
	case QAM_16:
		val = 0;
		break;

	case QAM_32:
		val = 1;
		break;

	case QAM_64:
		val = 4;
		break;

	case QAM_128:
		val = 2;
		break;

	case QAM_256:
		val = 3;
		break;

	default:
		return -EINVAL;
	}

	stv0297_writereg_mask(state, 0x00, 0x70, val << 4);

	return 0;
}

static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion)
{
	int val = 0;

	switch (inversion) {
	case INVERSION_OFF:
		val = 0;
		break;

	case INVERSION_ON:
		val = 1;
		break;

	default:
		return -EINVAL;
	}

	stv0297_writereg_mask(state, 0x83, 0x08, val << 3);

	return 0;
}

static int stv0297_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
	struct stv0297_state *state = fe->demodulator_priv;

	if (enable) {
		stv0297_writereg(state, 0x87, 0x78);
		stv0297_writereg(state, 0x86, 0xc8);
	}

	return 0;
}

static int stv0297_init(struct dvb_frontend *fe)
{
	struct stv0297_state *state = fe->demodulator_priv;
	int i;

	/* load init table */
	for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
		stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
	msleep(200);

	state->last_ber = 0;

	return 0;
}

static int stv0297_sleep(struct dvb_frontend *fe)
{
	struct stv0297_state *state = fe->demodulator_priv;

	stv0297_writereg_mask(state, 0x80, 1, 1);

	return 0;
}

static int stv0297_read_status(struct dvb_frontend *fe, fe_status_t * status)
{
	struct stv0297_state *state = fe->demodulator_priv;

	u8 sync = stv0297_readreg(state, 0xDF);

	*status = 0;
	if (sync & 0x80)
		*status |=
			FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
	return 0;
}

static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
{
	struct stv0297_state *state = fe->demodulator_priv;
	u8 BER[3];

	stv0297_readregs(state, 0xA0, BER, 3);
	if (!(BER[0] & 0x80)) {
		state->last_ber = BER[2] << 8 | BER[1];
		stv0297_writereg_mask(state, 0xA0, 0x80, 0x80);
	}

	*ber = state->last_ber;

	return 0;
}


static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
{
	struct stv0297_state *state = fe->demodulator_priv;
	u8 STRENGTH[3];
	u16 tmp;

	stv0297_readregs(state, 0x41, STRENGTH, 3);
	tmp = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
	if (STRENGTH[2] & 0x20) {
		if (tmp < 0x200)
			tmp = 0;
		else
			tmp = tmp - 0x200;
	} else {
		if (tmp > 0x1ff)
			tmp = 0;
		else
			tmp = 0x1ff - tmp;
	}
	*strength = (tmp << 7) | (tmp >> 2);
	return 0;
}

static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
{
	struct stv0297_state *state = fe->demodulator_priv;
	u8 SNR[2];

	stv0297_readregs(state, 0x07, SNR, 2);
	*snr = SNR[1] << 8 | SNR[0];

	return 0;
}

static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
{
	struct stv0297_state *state = fe->demodulator_priv;

	stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */

	*ucblocks = (stv0297_readreg(state, 0xD5) << 8)
		| stv0297_readreg(state, 0xD4);

	stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */
	stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */

	return 0;
}

static int stv0297_set_frontend(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
	struct stv0297_state *state = fe->demodulator_priv;
	int u_threshold;
	int initial_u;
	int blind_u;
	int delay;
	int sweeprate;
	int carrieroffset;
	unsigned long starttime;
	unsigned long timeout;
	fe_spectral_inversion_t inversion;

	switch (p->modulation) {
	case QAM_16:
	case QAM_32:
	case QAM_64:
		delay = 100;
		sweeprate = 1000;
		break;

	case QAM_128:
	case QAM_256:
		delay = 200;
		sweeprate = 500;
		break;

	default:
		return -EINVAL;
	}

	// determine inversion dependent parameters
	inversion = p->inversion;
	if (state->config->invert)
		inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
	carrieroffset = -330;
	switch (inversion) {
	case INVERSION_OFF:
		break;

	case INVERSION_ON:
		sweeprate = -sweeprate;
		carrieroffset = -carrieroffset;
		break;

	default:
		return -EINVAL;
	}

	stv0297_init(fe);
	if (fe->ops.tuner_ops.set_params) {
		fe->ops.tuner_ops.set_params(fe);
		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
	}

	/* clear software interrupts */
	stv0297_writereg(state, 0x82, 0x0);

	/* set initial demodulation frequency */
	stv0297_set_initialdemodfreq(state, 7250);

	/* setup AGC */
	stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
	stv0297_writereg(state, 0x41, 0x00);
	stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
	stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
	stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
	stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
	stv0297_writereg(state, 0x72, 0x00);
	stv0297_writereg(state, 0x73, 0x00);
	stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
	stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
	stv0297_writereg_mask(state, 0x71, 0x80, 0x00);

	/* setup STL */
	stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
	stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
	stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
	stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
	stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);

	/* disable frequency sweep */
	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);

	/* reset deinterleaver */
	stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
	stv0297_writereg_mask(state, 0x81, 0x01, 0x00);

	/* ??? */
	stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
	stv0297_writereg_mask(state, 0x83, 0x20, 0x00);

	/* reset equaliser */
	u_threshold = stv0297_readreg(state, 0x00) & 0xf;
	initial_u = stv0297_readreg(state, 0x01) >> 4;
	blind_u = stv0297_readreg(state, 0x01) & 0xf;
	stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
	stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
	stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
	stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
	stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);

	/* data comes from internal A/D */
	stv0297_writereg_mask(state, 0x87, 0x80, 0x00);

	/* clear phase registers */
	stv0297_writereg(state, 0x63, 0x00);
	stv0297_writereg(state, 0x64, 0x00);
	stv0297_writereg(state, 0x65, 0x00);
	stv0297_writereg(state, 0x66, 0x00);
	stv0297_writereg(state, 0x67, 0x00);
	stv0297_writereg(state, 0x68, 0x00);
	stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);

	/* set parameters */
	stv0297_set_qam(state, p->modulation);
	stv0297_set_symbolrate(state, p->symbol_rate / 1000);
	stv0297_set_sweeprate(state, sweeprate, p->symbol_rate / 1000);
	stv0297_set_carrieroffset(state, carrieroffset);
	stv0297_set_inversion(state, inversion);

	/* kick off lock */
	/* Disable corner detection for higher QAMs */
	if (p->modulation == QAM_128 ||
		p->modulation == QAM_256)
		stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
	else
		stv0297_writereg_mask(state, 0x88, 0x08, 0x08);

	stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
	stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
	stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
	stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
	stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
	stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
	stv0297_writereg_mask(state, 0x43, 0x10, 0x10);

	/* wait for WGAGC lock */
	starttime = jiffies;
	timeout = jiffies + msecs_to_jiffies(2000);
	while (time_before(jiffies, timeout)) {
		msleep(10);
		if (stv0297_readreg(state, 0x43) & 0x08)
			break;
	}
	if (time_after(jiffies, timeout)) {
		goto timeout;
	}
	msleep(20);

	/* wait for equaliser partial convergence */
	timeout = jiffies + msecs_to_jiffies(500);
	while (time_before(jiffies, timeout)) {
		msleep(10);

		if (stv0297_readreg(state, 0x82) & 0x04) {
			break;
		}
	}
	if (time_after(jiffies, timeout)) {
		goto timeout;
	}

	/* wait for equaliser full convergence */
	timeout = jiffies + msecs_to_jiffies(delay);
	while (time_before(jiffies, timeout)) {
		msleep(10);

		if (stv0297_readreg(state, 0x82) & 0x08) {
			break;
		}
	}
	if (time_after(jiffies, timeout)) {
		goto timeout;
	}

	/* disable sweep */
	stv0297_writereg_mask(state, 0x6a, 1, 0);
	stv0297_writereg_mask(state, 0x88, 8, 0);

	/* wait for main lock */
	timeout = jiffies + msecs_to_jiffies(20);
	while (time_before(jiffies, timeout)) {
		msleep(10);

		if (stv0297_readreg(state, 0xDF) & 0x80) {
			break;
		}
	}
	if (time_after(jiffies, timeout)) {
		goto timeout;
	}
	msleep(100);

	/* is it still locked after that delay? */
	if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
		goto timeout;
	}

	/* success!! */
	stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
	state->base_freq = p->frequency;
	return 0;

timeout:
	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
	return 0;
}

static int stv0297_get_frontend(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
	struct stv0297_state *state = fe->demodulator_priv;
	int reg_00, reg_83;

	reg_00 = stv0297_readreg(state, 0x00);
	reg_83 = stv0297_readreg(state, 0x83);

	p->frequency = state->base_freq;
	p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
	if (state->config->invert)
		p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
	p->symbol_rate = stv0297_get_symbolrate(state) * 1000;
	p->fec_inner = FEC_NONE;

	switch ((reg_00 >> 4) & 0x7) {
	case 0:
		p->modulation = QAM_16;
		break;
	case 1:
		p->modulation = QAM_32;
		break;
	case 2:
		p->modulation = QAM_128;
		break;
	case 3:
		p->modulation = QAM_256;
		break;
	case 4:
		p->modulation = QAM_64;
		break;
	}

	return 0;
}

static void stv0297_release(struct dvb_frontend *fe)
{
	struct stv0297_state *state = fe->demodulator_priv;
	kfree(state);
}

static struct dvb_frontend_ops stv0297_ops;

struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
				    struct i2c_adapter *i2c)
{
	struct stv0297_state *state = NULL;

	/* allocate memory for the internal state */
	state = kzalloc(sizeof(struct stv0297_state), GFP_KERNEL);
	if (state == NULL)
		goto error;

	/* setup the state */
	state->config = config;
	state->i2c = i2c;
	state->last_ber = 0;
	state->base_freq = 0;

	/* check if the demod is there */
	if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
		goto error;

	/* create dvb_frontend */
	memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
	state->frontend.demodulator_priv = state;
	return &state->frontend;

error:
	kfree(state);
	return NULL;
}

static struct dvb_frontend_ops stv0297_ops = {
	.delsys = { SYS_DVBC_ANNEX_A },
	.info = {
		 .name = "ST STV0297 DVB-C",
		 .frequency_min = 47000000,
		 .frequency_max = 862000000,
		 .frequency_stepsize = 62500,
		 .symbol_rate_min = 870000,
		 .symbol_rate_max = 11700000,
		 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
		 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},

	.release = stv0297_release,

	.init = stv0297_init,
	.sleep = stv0297_sleep,
	.i2c_gate_ctrl = stv0297_i2c_gate_ctrl,

	.set_frontend = stv0297_set_frontend,
	.get_frontend = stv0297_get_frontend,

	.read_status = stv0297_read_status,
	.read_ber = stv0297_read_ber,
	.read_signal_strength = stv0297_read_signal_strength,
	.read_snr = stv0297_read_snr,
	.read_ucblocks = stv0297_read_ucblocks,
};

MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(stv0297_attach);
Commit	Line	Data
1da177e4 LT	1	/*
	2	Driver for STV0297 demodulator
	3
	4	Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
	5	Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software
	19	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	20	*/
	21
	22	#include <linux/init.h>
	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/string.h>
	26	#include <linux/delay.h>
4e57b681 TS	27	#include <linux/jiffies.h>
4e57b681 TS	28	#include <linux/slab.h>
1da177e4 LT	29
	30	#include "dvb_frontend.h"
	31	#include "stv0297.h"
	32
	33	struct stv0297_state {
	34	struct i2c_adapter *i2c;
1da177e4 LT	35	const struct stv0297_config *config;
	36	struct dvb_frontend frontend;
	37
90e3bd4b	38	unsigned long last_ber;
1da177e4	39	unsigned long base_freq;
1da177e4 LT	40	};
	41
	42	#if 1
	43	#define dprintk(x...) printk(x)
	44	#else
	45	#define dprintk(x...)
	46	#endif
	47
	48	#define STV0297_CLOCK_KHZ 28900
	49
1da177e4 LT	50
	51	static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
	52	{
	53	int ret;
	54	u8 buf[] = { reg, data };
	55	struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
	56
	57	ret = i2c_transfer(state->i2c, &msg, 1);
	58
	59	if (ret != 1)
	60	dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
271ddbf7	61	"ret == %i)\n", __func__, reg, data, ret);
1da177e4 LT	62
	63	return (ret != 1) ? -1 : 0;
	64	}
	65
	66	static int stv0297_readreg(struct stv0297_state *state, u8 reg)
	67	{
	68	int ret;
	69	u8 b0[] = { reg };
	70	u8 b1[] = { 0 };
b8d4c235 TK	71	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
	72	{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
	73	};
1da177e4 LT	74
1da177e4 LT	75	// this device needs a STOP between the register and data
b8d4c235 TK	76	if (state->config->stop_during_read) {
b8d4c235 TK	77	if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
271ddbf7	78	dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
b8d4c235 TK	79	return -1;
	80	}
	81	if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
271ddbf7	82	dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
b8d4c235 TK	83	return -1;
	84	}
	85	} else {
	86	if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
271ddbf7	87	dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
b8d4c235 TK	88	return -1;
b8d4c235 TK	89	}
1da177e4 LT	90	}
	91
	92	return b1[0];
	93	}
	94
	95	static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
	96	{
	97	int val;
	98
	99	val = stv0297_readreg(state, reg);
	100	val &= ~mask;
	101	val \|= (data & mask);
	102	stv0297_writereg(state, reg, val);
	103
	104	return 0;
	105	}
	106
	107	static int stv0297_readregs(struct stv0297_state state, u8 reg1, u8 b, u8 len)
	108	{
	109	int ret;
	110	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
	111	&reg1,.len = 1},
	112	{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
	113	};
	114
	115	// this device needs a STOP between the register and data
b8d4c235 TK	116	if (state->config->stop_during_read) {
b8d4c235 TK	117	if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
271ddbf7	118	dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
b8d4c235 TK	119	return -1;
	120	}
	121	if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
271ddbf7	122	dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
b8d4c235 TK	123	return -1;
	124	}
	125	} else {
	126	if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
271ddbf7	127	dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
b8d4c235 TK	128	return -1;
b8d4c235 TK	129	}
1da177e4 LT	130	}
	131
	132	return 0;
	133	}
	134
	135	static u32 stv0297_get_symbolrate(struct stv0297_state *state)
	136	{
	137	u64 tmp;
	138
	139	tmp = stv0297_readreg(state, 0x55);
	140	tmp \|= stv0297_readreg(state, 0x56) << 8;
	141	tmp \|= stv0297_readreg(state, 0x57) << 16;
	142	tmp \|= stv0297_readreg(state, 0x58) << 24;
	143
	144	tmp *= STV0297_CLOCK_KHZ;
	145	tmp >>= 32;
	146
	147	return (u32) tmp;
	148	}
	149
	150	static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
	151	{
	152	long tmp;
	153
	154	tmp = 131072L * srate; /* 131072 = 2^17 */
	155	tmp = tmp / (STV0297_CLOCK_KHZ / 4); /* 1/4 = 2^-2 */
	156	tmp = tmp * 8192L; /* 8192 = 2^13 */
	157
	158	stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
	159	stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
	160	stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
	161	stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
	162	}
	163
	164	static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
	165	{
	166	long tmp;
	167
	168	tmp = (long) fshift 262144L; / 262144 = 218 /
	169	tmp /= symrate;
	170	tmp = 1024; / 1024 = 210 /
	171
	172	// adjust
	173	if (tmp >= 0) {
	174	tmp += 500000;
	175	} else {
	176	tmp -= 500000;
	177	}
	178	tmp /= 1000000;
	179
	180	stv0297_writereg(state, 0x60, tmp & 0xFF);
	181	stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
	182	}
	183
	184	static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
	185	{
	186	long tmp;
	187
	188	/* symrate is hardcoded to 10000 */
	189	tmp = offset * 26844L; /* (2*28)/10000 /
	190	if (tmp < 0)
	191	tmp += 0x10000000;
	192	tmp &= 0x0FFFFFFF;
	193
194	stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
195	stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
196	stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
197	stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
198	}
199
200	/*
201	static long stv0297_get_carrieroffset(struct stv0297_state *state)
202	{
203	s64 tmp;
204
205	stv0297_writereg(state, 0x6B, 0x00);
206
207	tmp = stv0297_readreg(state, 0x66);
208	tmp \|= (stv0297_readreg(state, 0x67) << 8);
209	tmp \|= (stv0297_readreg(state, 0x68) << 16);
210	tmp \|= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
211
212	tmp *= stv0297_get_symbolrate(state);
213	tmp >>= 28;
214
215	return (s32) tmp;
216	}
217	*/
218
219	static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
220	{
221	s32 tmp;
222
223	if (freq > 10000)
224	freq -= STV0297_CLOCK_KHZ;
225
226	tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
227	tmp = (freq * 1000) / tmp;
228	if (tmp > 0xffff)
229	tmp = 0xffff;
230
231	stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
232	stv0297_writereg(state, 0x21, tmp >> 8);
233	stv0297_writereg(state, 0x20, tmp);
234	}
235
236	static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation)
237	{
238	int val = 0;
239
240	switch (modulation) {
241	case QAM_16:
242	val = 0;
243	break;
244
245	case QAM_32:
246	val = 1;
247	break;
248
249	case QAM_64:
250	val = 4;
251	break;
252
253	case QAM_128:
254	val = 2;
255	break;
256
257	case QAM_256:
258	val = 3;
259	break;
260
261	default:
262	return -EINVAL;
263	}
264
265	stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
266
267	return 0;
268	}
269
270	static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion)
271	{
272	int val = 0;
273
274	switch (inversion) {
275	case INVERSION_OFF:
276	val = 0;
277	break;
278
279	case INVERSION_ON:
280	val = 1;
281	break;
282
283	default:
284	return -EINVAL;
285	}
286
287	stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
288
289	return 0;
290	}
291
58ac7d36	292	static int stv0297_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
1da177e4	293	{
b8742700	294	struct stv0297_state *state = fe->demodulator_priv;
1da177e4	295
58ac7d36 AQ	296	if (enable) {
	297	stv0297_writereg(state, 0x87, 0x78);
	298	stv0297_writereg(state, 0x86, 0xc8);
	299	}
1da177e4 LT	300
	301	return 0;
	302	}
	303
	304	static int stv0297_init(struct dvb_frontend *fe)
	305	{
b8742700	306	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	307	int i;
1da177e4 LT	308
1da177e4	309	/* load init table */
dc27a169 AQ	310	for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
dc27a169 AQ	311	stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
1da177e4 LT	312	msleep(200);
1da177e4 LT	313
90e3bd4b HB	314	state->last_ber = 0;
90e3bd4b HB	315
1da177e4 LT	316	return 0;
	317	}
	318
	319	static int stv0297_sleep(struct dvb_frontend *fe)
	320	{
b8742700	321	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	322
	323	stv0297_writereg_mask(state, 0x80, 1, 1);
	324
	325	return 0;
	326	}
	327
	328	static int stv0297_read_status(struct dvb_frontend fe, fe_status_t status)
	329	{
b8742700	330	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	331
	332	u8 sync = stv0297_readreg(state, 0xDF);
	333
	334	*status = 0;
	335	if (sync & 0x80)
	336	*status \|=
	337	FE_HAS_SYNC \| FE_HAS_SIGNAL \| FE_HAS_CARRIER \| FE_HAS_VITERBI \| FE_HAS_LOCK;
	338	return 0;
	339	}
	340
	341	static int stv0297_read_ber(struct dvb_frontend fe, u32 ber)
	342	{
b8742700	343	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	344	u8 BER[3];
1da177e4 LT	345
1da177e4	346	stv0297_readregs(state, 0xA0, BER, 3);
90e3bd4b HB	347	if (!(BER[0] & 0x80)) {
	348	state->last_ber = BER[2] << 8 \| BER[1];
	349	stv0297_writereg_mask(state, 0xA0, 0x80, 0x80);
	350	}
	351
	352	*ber = state->last_ber;
1da177e4 LT	353
	354	return 0;
	355	}
	356
	357
	358	static int stv0297_read_signal_strength(struct dvb_frontend fe, u16 strength)
	359	{
b8742700	360	struct stv0297_state *state = fe->demodulator_priv;
85085ad7 HB	361	u8 STRENGTH[3];
	362	u16 tmp;
	363
	364	stv0297_readregs(state, 0x41, STRENGTH, 3);
	365	tmp = (STRENGTH[1] & 0x03) << 8 \| STRENGTH[0];
	366	if (STRENGTH[2] & 0x20) {
	367	if (tmp < 0x200)
	368	tmp = 0;
	369	else
	370	tmp = tmp - 0x200;
	371	} else {
	372	if (tmp > 0x1ff)
	373	tmp = 0;
	374	else
	375	tmp = 0x1ff - tmp;
	376	}
	377	*strength = (tmp << 7) \| (tmp >> 2);
1da177e4 LT	378	return 0;
	379	}
	380
	381	static int stv0297_read_snr(struct dvb_frontend fe, u16 snr)
	382	{
b8742700	383	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	384	u8 SNR[2];
	385
	386	stv0297_readregs(state, 0x07, SNR, 2);
	387	*snr = SNR[1] << 8 \| SNR[0];
	388
	389	return 0;
	390	}
	391
	392	static int stv0297_read_ucblocks(struct dvb_frontend fe, u32 ucblocks)
	393	{
b8742700	394	struct stv0297_state *state = fe->demodulator_priv;
1da177e4	395
90e3bd4b HB	396	stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */
90e3bd4b HB	397
1da177e4 LT	398	*ucblocks = (stv0297_readreg(state, 0xD5) << 8)
	399	\| stv0297_readreg(state, 0xD4);
	400
90e3bd4b HB	401	stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */
	402	stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */
	403
1da177e4 LT	404	return 0;
	405	}
	406
35aa48e7	407	static int stv0297_set_frontend(struct dvb_frontend *fe)
1da177e4	408	{
35aa48e7	409	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
b8742700	410	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	411	int u_threshold;
	412	int initial_u;
	413	int blind_u;
	414	int delay;
	415	int sweeprate;
	416	int carrieroffset;
	417	unsigned long starttime;
	418	unsigned long timeout;
	419	fe_spectral_inversion_t inversion;
	420
35aa48e7	421	switch (p->modulation) {
1da177e4 LT	422	case QAM_16:
	423	case QAM_32:
	424	case QAM_64:
	425	delay = 100;
19b7ad31	426	sweeprate = 1000;
1da177e4 LT	427	break;
	428
	429	case QAM_128:
1da177e4 LT	430	case QAM_256:
	431	delay = 200;
	432	sweeprate = 500;
	433	break;
	434
	435	default:
	436	return -EINVAL;
	437	}
	438
25985edc	439	// determine inversion dependent parameters
1da177e4 LT	440	inversion = p->inversion;
	441	if (state->config->invert)
	442	inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
	443	carrieroffset = -330;
	444	switch (inversion) {
	445	case INVERSION_OFF:
	446	break;
	447
	448	case INVERSION_ON:
	449	sweeprate = -sweeprate;
	450	carrieroffset = -carrieroffset;
	451	break;
	452
	453	default:
	454	return -EINVAL;
	455	}
	456
	457	stv0297_init(fe);
dea74869	458	if (fe->ops.tuner_ops.set_params) {
14d24d14	459	fe->ops.tuner_ops.set_params(fe);
dea74869	460	if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
58ac7d36	461	}
1da177e4 LT	462
	463	/* clear software interrupts */
	464	stv0297_writereg(state, 0x82, 0x0);
	465
	466	/* set initial demodulation frequency */
	467	stv0297_set_initialdemodfreq(state, 7250);
	468
	469	/* setup AGC */
	470	stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
	471	stv0297_writereg(state, 0x41, 0x00);
	472	stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
	473	stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
	474	stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
	475	stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
	476	stv0297_writereg(state, 0x72, 0x00);
	477	stv0297_writereg(state, 0x73, 0x00);
	478	stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
	479	stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
	480	stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
	481
	482	/* setup STL */
	483	stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
	484	stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
	485	stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
	486	stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
	487	stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
	488
	489	/* disable frequency sweep */
	490	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
	491
	492	/* reset deinterleaver */
	493	stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
	494	stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
	495
	496	/* ??? */
	497	stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
	498	stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
	499
	500	/* reset equaliser */
	501	u_threshold = stv0297_readreg(state, 0x00) & 0xf;
	502	initial_u = stv0297_readreg(state, 0x01) >> 4;
	503	blind_u = stv0297_readreg(state, 0x01) & 0xf;
	504	stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
	505	stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
	506	stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
	507	stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
	508	stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
	509
	510	/* data comes from internal A/D */
	511	stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
	512
	513	/* clear phase registers */
	514	stv0297_writereg(state, 0x63, 0x00);
	515	stv0297_writereg(state, 0x64, 0x00);
	516	stv0297_writereg(state, 0x65, 0x00);
	517	stv0297_writereg(state, 0x66, 0x00);
	518	stv0297_writereg(state, 0x67, 0x00);
	519	stv0297_writereg(state, 0x68, 0x00);
	520	stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
	521
	522	/* set parameters */
35aa48e7 MCC	523	stv0297_set_qam(state, p->modulation);
	524	stv0297_set_symbolrate(state, p->symbol_rate / 1000);
	525	stv0297_set_sweeprate(state, sweeprate, p->symbol_rate / 1000);
1da177e4 LT	526	stv0297_set_carrieroffset(state, carrieroffset);
	527	stv0297_set_inversion(state, inversion);
	528
	529	/* kick off lock */
593cbf3d	530	/* Disable corner detection for higher QAMs */
35aa48e7 MCC	531	if (p->modulation == QAM_128 \|\|
35aa48e7 MCC	532	p->modulation == QAM_256)
593cbf3d PB	533	stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
	534	else
	535	stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
	536
1da177e4 LT	537	stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
	538	stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
	539	stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
	540	stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
	541	stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
	542	stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
	543	stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
	544
	545	/* wait for WGAGC lock */
	546	starttime = jiffies;
48e4cc2d	547	timeout = jiffies + msecs_to_jiffies(2000);
1da177e4 LT	548	while (time_before(jiffies, timeout)) {
	549	msleep(10);
	550	if (stv0297_readreg(state, 0x43) & 0x08)
	551	break;
	552	}
	553	if (time_after(jiffies, timeout)) {
	554	goto timeout;
	555	}
	556	msleep(20);
	557
	558	/* wait for equaliser partial convergence */
48e4cc2d	559	timeout = jiffies + msecs_to_jiffies(500);
1da177e4 LT	560	while (time_before(jiffies, timeout)) {
	561	msleep(10);
	562
	563	if (stv0297_readreg(state, 0x82) & 0x04) {
	564	break;
	565	}
	566	}
	567	if (time_after(jiffies, timeout)) {
	568	goto timeout;
	569	}
	570
	571	/* wait for equaliser full convergence */
48e4cc2d	572	timeout = jiffies + msecs_to_jiffies(delay);
1da177e4 LT	573	while (time_before(jiffies, timeout)) {
	574	msleep(10);
	575
	576	if (stv0297_readreg(state, 0x82) & 0x08) {
	577	break;
	578	}
	579	}
	580	if (time_after(jiffies, timeout)) {
	581	goto timeout;
	582	}
	583
	584	/* disable sweep */
	585	stv0297_writereg_mask(state, 0x6a, 1, 0);
	586	stv0297_writereg_mask(state, 0x88, 8, 0);
	587
	588	/* wait for main lock */
48e4cc2d	589	timeout = jiffies + msecs_to_jiffies(20);
1da177e4 LT	590	while (time_before(jiffies, timeout)) {
	591	msleep(10);
	592
	593	if (stv0297_readreg(state, 0xDF) & 0x80) {
	594	break;
	595	}
	596	}
	597	if (time_after(jiffies, timeout)) {
	598	goto timeout;
	599	}
	600	msleep(100);
	601
	602	/* is it still locked after that delay? */
	603	if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
	604	goto timeout;
	605	}
	606
	607	/* success!! */
	608	stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
	609	state->base_freq = p->frequency;
	610	return 0;
	611
	612	timeout:
	613	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
	614	return 0;
	615	}
	616
7c61d80a	617	static int stv0297_get_frontend(struct dvb_frontend *fe)
1da177e4	618	{
7c61d80a	619	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
b8742700	620	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	621	int reg_00, reg_83;
	622
	623	reg_00 = stv0297_readreg(state, 0x00);
	624	reg_83 = stv0297_readreg(state, 0x83);
	625
	626	p->frequency = state->base_freq;
	627	p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
	628	if (state->config->invert)
	629	p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
35aa48e7 MCC	630	p->symbol_rate = stv0297_get_symbolrate(state) * 1000;
35aa48e7 MCC	631	p->fec_inner = FEC_NONE;
1da177e4 LT	632
	633	switch ((reg_00 >> 4) & 0x7) {
	634	case 0:
35aa48e7	635	p->modulation = QAM_16;
1da177e4 LT	636	break;
1da177e4 LT	637	case 1:
35aa48e7	638	p->modulation = QAM_32;
1da177e4 LT	639	break;
1da177e4 LT	640	case 2:
35aa48e7	641	p->modulation = QAM_128;
1da177e4 LT	642	break;
1da177e4 LT	643	case 3:
35aa48e7	644	p->modulation = QAM_256;
1da177e4 LT	645	break;
1da177e4 LT	646	case 4:
35aa48e7	647	p->modulation = QAM_64;
1da177e4 LT	648	break;
	649	}
	650
	651	return 0;
	652	}
	653
	654	static void stv0297_release(struct dvb_frontend *fe)
	655	{
b8742700	656	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	657	kfree(state);
	658	}
	659
	660	static struct dvb_frontend_ops stv0297_ops;
	661
	662	struct dvb_frontend stv0297_attach(const struct stv0297_config config,
dc27a169	663	struct i2c_adapter *i2c)
1da177e4 LT	664	{
	665	struct stv0297_state *state = NULL;
	666
	667	/* allocate memory for the internal state */
084e24ac	668	state = kzalloc(sizeof(struct stv0297_state), GFP_KERNEL);
1da177e4 LT	669	if (state == NULL)
	670	goto error;
	671
	672	/* setup the state */
	673	state->config = config;
	674	state->i2c = i2c;
90e3bd4b	675	state->last_ber = 0;
1da177e4	676	state->base_freq = 0;
1da177e4 LT	677
	678	/* check if the demod is there */
	679	if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
	680	goto error;
	681
	682	/* create dvb_frontend */
dea74869	683	memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
1da177e4 LT	684	state->frontend.demodulator_priv = state;
	685	return &state->frontend;
	686
	687	error:
	688	kfree(state);
	689	return NULL;
	690	}
	691
	692	static struct dvb_frontend_ops stv0297_ops = {
a95c471e	693	.delsys = { SYS_DVBC_ANNEX_A },
1da177e4 LT	694	.info = {
1da177e4 LT	695	.name = "ST STV0297 DVB-C",
a18255be HB	696	.frequency_min = 47000000,
a18255be HB	697	.frequency_max = 862000000,
1da177e4 LT	698	.frequency_stepsize = 62500,
	699	.symbol_rate_min = 870000,
	700	.symbol_rate_max = 11700000,
	701	.caps = FE_CAN_QAM_16 \| FE_CAN_QAM_32 \| FE_CAN_QAM_64 \|
	702	FE_CAN_QAM_128 \| FE_CAN_QAM_256 \| FE_CAN_FEC_AUTO},
	703
	704	.release = stv0297_release,
	705
	706	.init = stv0297_init,
	707	.sleep = stv0297_sleep,
58ac7d36	708	.i2c_gate_ctrl = stv0297_i2c_gate_ctrl,
1da177e4	709
35aa48e7 MCC	710	.set_frontend = stv0297_set_frontend,
35aa48e7 MCC	711	.get_frontend = stv0297_get_frontend,
1da177e4 LT	712
	713	.read_status = stv0297_read_status,
	714	.read_ber = stv0297_read_ber,
	715	.read_signal_strength = stv0297_read_signal_strength,
	716	.read_snr = stv0297_read_snr,
	717	.read_ucblocks = stv0297_read_ucblocks,
	718	};
	719
	720	MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
	721	MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
	722	MODULE_LICENSE("GPL");
	723
	724	EXPORT_SYMBOL(stv0297_attach);