projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] dvb: frontend: tda1004x update
[deliverable/linux.git] / drivers / media / dvb / frontends / tda1004x.c
CommitLineData
1da177e4
LT		 1 /*
2 Driver for Philips tda1004xh OFDM Demodulator
3
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 */
22/*
23 * This driver needs external firmware. Please use the commands
24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware.
27 */
28#define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
29#define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
30
31#include <linux/init.h>
32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/device.h>
35#include "dvb_frontend.h"
36#include "tda1004x.h"
37
7f5e02db
JS		 38enum tda1004x_demod {
39 TDA1004X_DEMOD_TDA10045,
40 TDA1004X_DEMOD_TDA10046,
41};
1da177e4
LT		 42
43struct tda1004x_state {
44 struct i2c_adapter* i2c;
45 struct dvb_frontend_ops ops;
46 const struct tda1004x_config* config;
47 struct dvb_frontend frontend;
48
49 /* private demod data */
7f5e02db
JS		 50 u8 initialised;
51 enum tda1004x_demod demod_type;
1da177e4
LT		 52};
53
1da177e4
LT		 54static int debug;
55#define dprintk(args...) \
56 do { \
57 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
58 } while (0)
59
60#define TDA1004X_CHIPID 0x00
61#define TDA1004X_AUTO 0x01
62#define TDA1004X_IN_CONF1 0x02
63#define TDA1004X_IN_CONF2 0x03
64#define TDA1004X_OUT_CONF1 0x04
65#define TDA1004X_OUT_CONF2 0x05
66#define TDA1004X_STATUS_CD 0x06
67#define TDA1004X_CONFC4 0x07
68#define TDA1004X_DSSPARE2 0x0C
69#define TDA10045H_CODE_IN 0x0D
70#define TDA10045H_FWPAGE 0x0E
71#define TDA1004X_SCAN_CPT 0x10
72#define TDA1004X_DSP_CMD 0x11
73#define TDA1004X_DSP_ARG 0x12
74#define TDA1004X_DSP_DATA1 0x13
75#define TDA1004X_DSP_DATA2 0x14
76#define TDA1004X_CONFADC1 0x15
77#define TDA1004X_CONFC1 0x16
78#define TDA10045H_S_AGC 0x1a
79#define TDA10046H_AGC_TUN_LEVEL 0x1a
80#define TDA1004X_SNR 0x1c
81#define TDA1004X_CONF_TS1 0x1e
82#define TDA1004X_CONF_TS2 0x1f
83#define TDA1004X_CBER_RESET 0x20
84#define TDA1004X_CBER_MSB 0x21
85#define TDA1004X_CBER_LSB 0x22
86#define TDA1004X_CVBER_LUT 0x23
87#define TDA1004X_VBER_MSB 0x24
88#define TDA1004X_VBER_MID 0x25
89#define TDA1004X_VBER_LSB 0x26
90#define TDA1004X_UNCOR 0x27
91
92#define TDA10045H_CONFPLL_P 0x2D
93#define TDA10045H_CONFPLL_M_MSB 0x2E
94#define TDA10045H_CONFPLL_M_LSB 0x2F
95#define TDA10045H_CONFPLL_N 0x30
96
97#define TDA10046H_CONFPLL1 0x2D
98#define TDA10046H_CONFPLL2 0x2F
99#define TDA10046H_CONFPLL3 0x30
100#define TDA10046H_TIME_WREF1 0x31
101#define TDA10046H_TIME_WREF2 0x32
102#define TDA10046H_TIME_WREF3 0x33
103#define TDA10046H_TIME_WREF4 0x34
104#define TDA10046H_TIME_WREF5 0x35
105
106#define TDA10045H_UNSURW_MSB 0x31
107#define TDA10045H_UNSURW_LSB 0x32
108#define TDA10045H_WREF_MSB 0x33
109#define TDA10045H_WREF_MID 0x34
110#define TDA10045H_WREF_LSB 0x35
111#define TDA10045H_MUXOUT 0x36
112#define TDA1004X_CONFADC2 0x37
113
114#define TDA10045H_IOFFSET 0x38
115
116#define TDA10046H_CONF_TRISTATE1 0x3B
117#define TDA10046H_CONF_TRISTATE2 0x3C
118#define TDA10046H_CONF_POLARITY 0x3D
119#define TDA10046H_FREQ_OFFSET 0x3E
120#define TDA10046H_GPIO_OUT_SEL 0x41
121#define TDA10046H_GPIO_SELECT 0x42
122#define TDA10046H_AGC_CONF 0x43
123#define TDA10046H_AGC_GAINS 0x46
124#define TDA10046H_AGC_TUN_MIN 0x47
125#define TDA10046H_AGC_TUN_MAX 0x48
126#define TDA10046H_AGC_IF_MIN 0x49
127#define TDA10046H_AGC_IF_MAX 0x4A
128
129#define TDA10046H_FREQ_PHY2_MSB 0x4D
130#define TDA10046H_FREQ_PHY2_LSB 0x4E
131
132#define TDA10046H_CVBER_CTRL 0x4F
133#define TDA10046H_AGC_IF_LEVEL 0x52
134#define TDA10046H_CODE_CPT 0x57
135#define TDA10046H_CODE_IN 0x58
136
137
138static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
139{
140 int ret;
141 u8 buf[] = { reg, data };
7f5e02db 142 struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
1da177e4
LT		 143
144 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
145
146 msg.addr = state->config->demod_address;
147 ret = i2c_transfer(state->i2c, &msg, 1);
148
149 if (ret != 1)
150 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
151 __FUNCTION__, reg, data, ret);
152
153 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
154 reg, data, ret);
155 return (ret != 1) ? -1 : 0;
156}
157
158static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
159{
160 int ret;
161 u8 b0[] = { reg };
162 u8 b1[] = { 0 };
7f5e02db
JS		 163 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
164 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
1da177e4
LT		 165
166 dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
167
168 msg[0].addr = state->config->demod_address;
169 msg[1].addr = state->config->demod_address;
170 ret = i2c_transfer(state->i2c, msg, 2);
171
172 if (ret != 2) {
173 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
174 ret);
175 return -1;
176 }
177
178 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
179 reg, b1[0], ret);
180 return b1[0];
181}
182
183static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
184{
185 int val;
186 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
187 mask, data);
188
189 // read a byte and check
190 val = tda1004x_read_byte(state, reg);
191 if (val < 0)
192 return val;
193
194 // mask if off
195 val = val & ~mask;
196 val |= data & 0xff;
197
198 // write it out again
199 return tda1004x_write_byteI(state, reg, val);
200}
201
202static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
203{
204 int i;
205 int result;
206
207 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
208
209 result = 0;
210 for (i = 0; i < len; i++) {
211 result = tda1004x_write_byteI(state, reg + i, buf[i]);
212 if (result != 0)
213 break;
214 }
215
216 return result;
217}
218
219static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
220{
221 int result;
222 dprintk("%s\n", __FUNCTION__);
223
224 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
225 msleep(1);
226 return result;
227}
228
229static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
230{
231 dprintk("%s\n", __FUNCTION__);
232
233 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
234}
235
236static int tda10045h_set_bandwidth(struct tda1004x_state *state,
237 fe_bandwidth_t bandwidth)
238{
239 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
240 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
241 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
242
243 switch (bandwidth) {
244 case BANDWIDTH_6_MHZ:
245 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
246 break;
247
248 case BANDWIDTH_7_MHZ:
249 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
250 break;
251
252 case BANDWIDTH_8_MHZ:
253 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
254 break;
255
256 default:
257 return -EINVAL;
258 }
259
260 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
261
262 return 0;
263}
264
265static int tda10046h_set_bandwidth(struct tda1004x_state *state,
266 fe_bandwidth_t bandwidth)
267{
268 static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
269 static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
270 static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
271
272 switch (bandwidth) {
273 case BANDWIDTH_6_MHZ:
274 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
275 break;
276
277 case BANDWIDTH_7_MHZ:
278 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
279 break;
280
281 case BANDWIDTH_8_MHZ:
282 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
283 break;
284
285 default:
286 return -EINVAL;
287 }
288
289 return 0;
290}
291
292static int tda1004x_do_upload(struct tda1004x_state *state,
293 unsigned char *mem, unsigned int len,
294 u8 dspCodeCounterReg, u8 dspCodeInReg)
295{
296 u8 buf[65];
7f5e02db 297 struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
1da177e4
LT		 298 int tx_size;
299 int pos = 0;
300
301 /* clear code counter */
302 tda1004x_write_byteI(state, dspCodeCounterReg, 0);
303 fw_msg.addr = state->config->demod_address;
304
305 buf[0] = dspCodeInReg;
306 while (pos != len) {
1da177e4
LT		 307 // work out how much to send this time
308 tx_size = len - pos;
7f5e02db 309 if (tx_size > 0x10)
1da177e4 310 tx_size = 0x10;
1da177e4
LT		 311
312 // send the chunk
313 memcpy(buf + 1, mem + pos, tx_size);
314 fw_msg.len = tx_size + 1;
315 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
ecb60deb 316 printk(KERN_ERR "tda1004x: Error during firmware upload\n");
1da177e4
LT		 317 return -EIO;
318 }
319 pos += tx_size;
320
321 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
322 }
ecb60deb
HH		 323 // give the DSP a chance to settle 03/10/05 Hac
324 msleep(100);
7f5e02db 325
1da177e4
LT		 326 return 0;
327}
328
ecb60deb 329static int tda1004x_check_upload_ok(struct tda1004x_state *state)
1da177e4
LT		 330{
331 u8 data1, data2;
ecb60deb
HH		 332 unsigned long timeout;
333
334 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
335 timeout = jiffies + 2 * HZ;
336 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
337 if (time_after(jiffies, timeout)) {
338 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
339 break;
340 }
341 msleep(1);
342 }
343 } else
344 msleep(100);
1da177e4
LT		 345
346 // check upload was OK
347 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
348 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
349
350 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
351 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
ecb60deb
HH		 352 if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2a) {
353 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
1da177e4 354 return -EIO;
ecb60deb
HH		 355 }
356 printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
1da177e4
LT		 357 return 0;
358}
359
360static int tda10045_fwupload(struct dvb_frontend* fe)
361{
362 struct tda1004x_state* state = fe->demodulator_priv;
363 int ret;
364 const struct firmware *fw;
365
1da177e4 366 /* don't re-upload unless necessary */
ecb60deb 367 if (tda1004x_check_upload_ok(state) == 0)
7f5e02db 368 return 0;
1da177e4
LT		 369
370 /* request the firmware, this will block until someone uploads it */
ecb60deb 371 printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
1da177e4
LT		 372 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
373 if (ret) {
ecb60deb 374 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
1da177e4
LT		 375 return ret;
376 }
377
378 /* reset chip */
379 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
380 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
381 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
382 msleep(10);
383
384 /* set parameters */
385 tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
386
387 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
388 if (ret)
389 return ret;
ecb60deb 390 printk(KERN_INFO "tda1004x: firmware upload complete\n");
1da177e4
LT		 391
392 /* wait for DSP to initialise */
393 /* DSPREADY doesn't seem to work on the TDA10045H */
394 msleep(100);
395
ecb60deb 396 return tda1004x_check_upload_ok(state);
1da177e4
LT		 397}
398
ecb60deb 399static void tda10046_init_plls(struct dvb_frontend* fe)
71e34201 400{
ecb60deb 401 struct tda1004x_state* state = fe->demodulator_priv;
71e34201 402
ecb60deb
HH		 403 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
404 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10
405 if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
406 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
407 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
408 } else {
409 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
410 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
411 }
412 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);
413 switch (state->config->if_freq) {
414 case TDA10046_FREQ_3617:
415 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
416 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
417 break;
418 case TDA10046_FREQ_3613:
419 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
420 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x13);
421 break;
422 }
423 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
71e34201
JS		 424}
425
1da177e4
LT		 426static int tda10046_fwupload(struct dvb_frontend* fe)
427{
428 struct tda1004x_state* state = fe->demodulator_priv;
1da177e4
LT		 429 int ret;
430 const struct firmware *fw;
431
432 /* reset + wake up chip */
ecb60deb 433 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
1da177e4 434 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
ecb60deb
HH		 435 /* let the clocks recover from sleep */
436 msleep(5);
1da177e4
LT		 437
438 /* don't re-upload unless necessary */
ecb60deb 439 if (tda1004x_check_upload_ok(state) == 0)
7f5e02db 440 return 0;
1da177e4 441
1da177e4 442 /* set parameters */
ecb60deb
HH		 443 tda10046_init_plls(fe);
444
445 if (state->config->request_firmware != NULL) {
446 /* request the firmware, this will block until someone uploads it */
447 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
448 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
449 if (ret) {
450 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
451 return ret;
1da177e4 452 }
ecb60deb
HH		 453 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
454 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
455 if (ret)
456 return ret;
457 } else {
458 /* boot from firmware eeprom */
459 /* Hac Note: we might need to do some GPIO Magic here */
460 printk(KERN_INFO "tda1004x: booting from eeprom\n");
461 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
462 msleep(300);
1da177e4 463 }
ecb60deb 464 return tda1004x_check_upload_ok(state);
1da177e4
LT		 465}
466
467static int tda1004x_encode_fec(int fec)
468{
469 // convert known FEC values
470 switch (fec) {
471 case FEC_1_2:
472 return 0;
473 case FEC_2_3:
474 return 1;
475 case FEC_3_4:
476 return 2;
477 case FEC_5_6:
478 return 3;
479 case FEC_7_8:
480 return 4;
481 }
482
483 // unsupported
484 return -EINVAL;
485}
486
487static int tda1004x_decode_fec(int tdafec)
488{
489 // convert known FEC values
490 switch (tdafec) {
491 case 0:
492 return FEC_1_2;
493 case 1:
494 return FEC_2_3;
495 case 2:
496 return FEC_3_4;
497 case 3:
498 return FEC_5_6;
499 case 4:
500 return FEC_7_8;
501 }
502
503 // unsupported
504 return -1;
505}
506
507int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
508{
509 struct tda1004x_state* state = fe->demodulator_priv;
510
511 return tda1004x_write_byteI(state, reg, data);
512}
513
514static int tda10045_init(struct dvb_frontend* fe)
515{
516 struct tda1004x_state* state = fe->demodulator_priv;
517
518 dprintk("%s\n", __FUNCTION__);
519
7f5e02db
JS		 520 if (state->initialised)
521 return 0;
1da177e4
LT		 522
523 if (tda10045_fwupload(fe)) {
524 printk("tda1004x: firmware upload failed\n");
525 return -EIO;
526 }
527
528 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
529
530 // Init the PLL
531 if (state->config->pll_init) {
532 tda1004x_enable_tuner_i2c(state);
533 state->config->pll_init(fe);
534 tda1004x_disable_tuner_i2c(state);
535 }
536
537 // tda setup
538 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
539 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
540 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
541 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
542 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
543 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
544 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
545 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
546 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
547 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
548 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
549
550 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
551
552 state->initialised = 1;
553 return 0;
554}
555
556static int tda10046_init(struct dvb_frontend* fe)
557{
558 struct tda1004x_state* state = fe->demodulator_priv;
559 dprintk("%s\n", __FUNCTION__);
560
7f5e02db
JS		 561 if (state->initialised)
562 return 0;
1da177e4
LT		 563
564 if (tda10046_fwupload(fe)) {
565 printk("tda1004x: firmware upload failed\n");
ecb60deb 566 return -EIO;
1da177e4
LT		 567 }
568
ecb60deb 569 // Init the tuner PLL
1da177e4
LT		 570 if (state->config->pll_init) {
571 tda1004x_enable_tuner_i2c(state);
572 state->config->pll_init(fe);
573 tda1004x_disable_tuner_i2c(state);
574 }
575
576 // tda setup
577 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
ecb60deb
HH		 578 tda1004x_write_byteI(state, TDA1004X_AUTO, 7); // select HP stream
579 tda1004x_write_byteI(state, TDA1004X_CONFC1, 8); // disable pulse killer
580
581 tda10046_init_plls(fe);
582 switch (state->config->agc_config) {
583 case TDA10046_AGC_DEFAULT:
584 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
585 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
586 break;
587 case TDA10046_AGC_IFO_AUTO_NEG:
588 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
589 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
590 break;
591 }
592 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
1da177e4
LT		 593 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
594 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
595 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
596 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
1da177e4 597 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
ecb60deb 598 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
1da177e4 599 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
ecb60deb
HH		 600 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
601 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
602
1da177e4
LT		 603 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
604 tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
ecb60deb 605 tda1004x_write_byteI(state, TDA10046H_GPIO_SELECT, 8); // GPIO select
1da177e4
LT		 606
607 state->initialised = 1;
608 return 0;
609}
610
611static int tda1004x_set_fe(struct dvb_frontend* fe,
612 struct dvb_frontend_parameters *fe_params)
613{
614 struct tda1004x_state* state = fe->demodulator_priv;
615 int tmp;
616 int inversion;
617
618 dprintk("%s\n", __FUNCTION__);
619
620 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
621 // setup auto offset
622 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
623 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
624 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
625
626 // disable agc_conf[2]
627 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
628 }
629
630 // set frequency
631 tda1004x_enable_tuner_i2c(state);
632 state->config->pll_set(fe, fe_params);
633 tda1004x_disable_tuner_i2c(state);
634
1da177e4
LT		 635 // Hardcoded to use auto as much as possible on the TDA10045 as it
636 // is very unreliable if AUTO mode is _not_ used.
637 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
638 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
639 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
640 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
641 }
642
643 // Set standard params.. or put them to auto
644 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
645 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
646 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
647 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
648 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
649 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
650 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
651 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
652 } else {
653 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
654
655 // set HP FEC
656 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
7f5e02db
JS		 657 if (tmp < 0)
658 return tmp;
1da177e4
LT		 659 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
660
661 // set LP FEC
662 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
7f5e02db
JS		 663 if (tmp < 0)
664 return tmp;
1da177e4
LT		 665 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
666
667 // set constellation
668 switch (fe_params->u.ofdm.constellation) {
669 case QPSK:
670 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
671 break;
672
673 case QAM_16:
674 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
675 break;
676
677 case QAM_64:
678 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
679 break;
680
681 default:
682 return -EINVAL;
683 }
684
685 // set hierarchy
686 switch (fe_params->u.ofdm.hierarchy_information) {
687 case HIERARCHY_NONE:
688 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
689 break;
690
691 case HIERARCHY_1:
692 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
693 break;
694
695 case HIERARCHY_2:
696 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
697 break;
698
699 case HIERARCHY_4:
700 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
701 break;
702
703 default:
704 return -EINVAL;
705 }
706 }
707
708 // set bandwidth
7f5e02db 709 switch (state->demod_type) {
1da177e4
LT		 710 case TDA1004X_DEMOD_TDA10045:
711 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
712 break;
713
714 case TDA1004X_DEMOD_TDA10046:
715 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
716 break;
717 }
718
719 // set inversion
720 inversion = fe_params->inversion;
7f5e02db
JS		 721 if (state->config->invert)
722 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
1da177e4
LT		 723 switch (inversion) {
724 case INVERSION_OFF:
725 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
726 break;
727
728 case INVERSION_ON:
729 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
730 break;
731
732 default:
733 return -EINVAL;
734 }
735
736 // set guard interval
737 switch (fe_params->u.ofdm.guard_interval) {
738 case GUARD_INTERVAL_1_32:
739 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
740 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
741 break;
742
743 case GUARD_INTERVAL_1_16:
744 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
745 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
746 break;
747
748 case GUARD_INTERVAL_1_8:
749 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
750 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
751 break;
752
753 case GUARD_INTERVAL_1_4:
754 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
755 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
756 break;
757
758 case GUARD_INTERVAL_AUTO:
759 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
760 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
761 break;
762
763 default:
764 return -EINVAL;
765 }
766
767 // set transmission mode
768 switch (fe_params->u.ofdm.transmission_mode) {
769 case TRANSMISSION_MODE_2K:
770 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
771 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
772 break;
773
774 case TRANSMISSION_MODE_8K:
775 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
776 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
777 break;
778
779 case TRANSMISSION_MODE_AUTO:
780 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
781 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
782 break;
783
784 default:
785 return -EINVAL;
786 }
787
788 // start the lock
7f5e02db 789 switch (state->demod_type) {
1da177e4
LT		 790 case TDA1004X_DEMOD_TDA10045:
791 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
792 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
1da177e4
LT		 793 break;
794
795 case TDA1004X_DEMOD_TDA10046:
796 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
1da177e4
LT		 797 break;
798 }
799
7f5e02db
JS		 800 msleep(10);
801
1da177e4
LT		 802 return 0;
803}
804
805static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
806{
807 struct tda1004x_state* state = fe->demodulator_priv;
808 dprintk("%s\n", __FUNCTION__);
809
810 // inversion status
811 fe_params->inversion = INVERSION_OFF;
7f5e02db 812 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
1da177e4 813 fe_params->inversion = INVERSION_ON;
7f5e02db
JS		 814 if (state->config->invert)
815 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
1da177e4
LT		 816
817 // bandwidth
7f5e02db 818 switch (state->demod_type) {
1da177e4
LT		 819 case TDA1004X_DEMOD_TDA10045:
820 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
821 case 0x14:
822 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
823 break;
824 case 0xdb:
825 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
826 break;
827 case 0x4f:
828 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
829 break;
830 }
831 break;
832
833 case TDA1004X_DEMOD_TDA10046:
834 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
835 case 0x60:
836 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
837 break;
838 case 0x6e:
839 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
840 break;
841 case 0x80:
842 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
843 break;
844 }
845 break;
846 }
847
848 // FEC
849 fe_params->u.ofdm.code_rate_HP =
850 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
851 fe_params->u.ofdm.code_rate_LP =
852 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
853
854 // constellation
855 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
856 case 0:
857 fe_params->u.ofdm.constellation = QPSK;
858 break;
859 case 1:
860 fe_params->u.ofdm.constellation = QAM_16;
861 break;
862 case 2:
863 fe_params->u.ofdm.constellation = QAM_64;
864 break;
865 }
866
867 // transmission mode
868 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
7f5e02db 869 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
1da177e4 870 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1da177e4
LT		 871
872 // guard interval
873 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
874 case 0:
875 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
876 break;
877 case 1:
878 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
879 break;
880 case 2:
881 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
882 break;
883 case 3:
884 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
885 break;
886 }
887
888 // hierarchy
889 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
890 case 0:
891 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
892 break;
893 case 1:
894 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
895 break;
896 case 2:
897 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
898 break;
899 case 3:
900 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
901 break;
902 }
903
904 return 0;
905}
906
907static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
908{
909 struct tda1004x_state* state = fe->demodulator_priv;
910 int status;
911 int cber;
912 int vber;
913
914 dprintk("%s\n", __FUNCTION__);
915
916 // read status
917 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
7f5e02db 918 if (status == -1)
1da177e4 919 return -EIO;
1da177e4
LT		 920
921 // decode
922 *fe_status = 0;
7f5e02db
JS		 923 if (status & 4)
924 *fe_status |= FE_HAS_SIGNAL;
925 if (status & 2)
926 *fe_status |= FE_HAS_CARRIER;
927 if (status & 8)
928 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1da177e4
LT		 929
930 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
931 // is getting anything valid
932 if (!(*fe_status & FE_HAS_VITERBI)) {
933 // read the CBER
934 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
7f5e02db
JS		 935 if (cber == -1)
936 return -EIO;
1da177e4 937 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
7f5e02db
JS		 938 if (status == -1)
939 return -EIO;
1da177e4
LT		 940 cber |= (status << 8);
941 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
942
7f5e02db 943 if (cber != 65535)
1da177e4 944 *fe_status |= FE_HAS_VITERBI;
1da177e4
LT		 945 }
946
947 // if we DO have some valid VITERBI output, but don't already have SYNC
948 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
949 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
950 // read the VBER
951 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
7f5e02db
JS		 952 if (vber == -1)
953 return -EIO;
1da177e4 954 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
7f5e02db
JS		 955 if (status == -1)
956 return -EIO;
1da177e4
LT		 957 vber |= (status << 8);
958 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
7f5e02db
JS		 959 if (status == -1)
960 return -EIO;
1da177e4
LT		 961 vber |= ((status << 16) & 0x0f);
962 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
963
964 // if RS has passed some valid TS packets, then we must be
965 // getting some SYNC bytes
7f5e02db 966 if (vber < 16632)
1da177e4 967 *fe_status |= FE_HAS_SYNC;
1da177e4
LT		 968 }
969
970 // success
971 dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
972 return 0;
973}
974
975static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
976{
977 struct tda1004x_state* state = fe->demodulator_priv;
978 int tmp;
979 int reg = 0;
980
981 dprintk("%s\n", __FUNCTION__);
982
983 // determine the register to use
7f5e02db 984 switch (state->demod_type) {
1da177e4
LT		 985 case TDA1004X_DEMOD_TDA10045:
986 reg = TDA10045H_S_AGC;
987 break;
988
989 case TDA1004X_DEMOD_TDA10046:
990 reg = TDA10046H_AGC_IF_LEVEL;
991 break;
992 }
993
994 // read it
995 tmp = tda1004x_read_byte(state, reg);
996 if (tmp < 0)
997 return -EIO;
998
999 *signal = (tmp << 8) | tmp;
1000 dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1001 return 0;
1002}
1003
1004static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1005{
1006 struct tda1004x_state* state = fe->demodulator_priv;
1007 int tmp;
1008
1009 dprintk("%s\n", __FUNCTION__);
1010
1011 // read it
1012 tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1013 if (tmp < 0)
1014 return -EIO;
7f5e02db 1015 if (tmp)
1da177e4 1016 tmp = 255 - tmp;
1da177e4
LT		 1017
1018 *snr = ((tmp << 8) | tmp);
1019 dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1020 return 0;
1021}
1022
1023static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1024{
1025 struct tda1004x_state* state = fe->demodulator_priv;
1026 int tmp;
1027 int tmp2;
1028 int counter;
1029
1030 dprintk("%s\n", __FUNCTION__);
1031
1032 // read the UCBLOCKS and reset
1033 counter = 0;
1034 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1035 if (tmp < 0)
1036 return -EIO;
1037 tmp &= 0x7f;
1038 while (counter++ < 5) {
1039 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1040 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1041 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1042
1043 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1044 if (tmp2 < 0)
1045 return -EIO;
1046 tmp2 &= 0x7f;
1047 if ((tmp2 < tmp) || (tmp2 == 0))
1048 break;
1049 }
1050
7f5e02db 1051 if (tmp != 0x7f)
1da177e4 1052 *ucblocks = tmp;
7f5e02db 1053 else
1da177e4 1054 *ucblocks = 0xffffffff;
7f5e02db 1055
1da177e4
LT		 1056 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1057 return 0;
1058}
1059
1060static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1061{
1062 struct tda1004x_state* state = fe->demodulator_priv;
1063 int tmp;
1064
1065 dprintk("%s\n", __FUNCTION__);
1066
1067 // read it in
1068 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
7f5e02db
JS		 1069 if (tmp < 0)
1070 return -EIO;
1da177e4
LT		 1071 *ber = tmp << 1;
1072 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
7f5e02db
JS		 1073 if (tmp < 0)
1074 return -EIO;
1da177e4
LT		 1075 *ber |= (tmp << 9);
1076 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1077
1078 dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1079 return 0;
1080}
1081
1082static int tda1004x_sleep(struct dvb_frontend* fe)
1083{
1084 struct tda1004x_state* state = fe->demodulator_priv;
1085
7f5e02db 1086 switch (state->demod_type) {
1da177e4
LT		 1087 case TDA1004X_DEMOD_TDA10045:
1088 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1089 break;
1090
1091 case TDA1004X_DEMOD_TDA10046:
1092 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
ecb60deb
HH		 1093 if (state->config->pll_sleep != NULL)
1094 state->config->pll_sleep(fe);
1da177e4
LT		 1095 break;
1096 }
1097 state->initialised = 0;
1098
1099 return 0;
1100}
1101
1102static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1103{
1104 fesettings->min_delay_ms = 800;
1105 fesettings->step_size = 166667;
1106 fesettings->max_drift = 166667*2;
1107 return 0;
1108}
1109
1110static void tda1004x_release(struct dvb_frontend* fe)
1111{
7f5e02db 1112 struct tda1004x_state *state = fe->demodulator_priv;
1da177e4
LT		 1113 kfree(state);
1114}
1115
1da177e4 1116static struct dvb_frontend_ops tda10045_ops = {
1da177e4
LT		 1117 .info = {
1118 .name = "Philips TDA10045H DVB-T",
1119 .type = FE_OFDM,
1120 .frequency_min = 51000000,
1121 .frequency_max = 858000000,
1122 .frequency_stepsize = 166667,
1123 .caps =
1124 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1125 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1126 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1127 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1128 },
1129
1130 .release = tda1004x_release,
1131
1132 .init = tda10045_init,
1133 .sleep = tda1004x_sleep,
1134
1135 .set_frontend = tda1004x_set_fe,
1136 .get_frontend = tda1004x_get_fe,
1137 .get_tune_settings = tda1004x_get_tune_settings,
1138
1139 .read_status = tda1004x_read_status,
1140 .read_ber = tda1004x_read_ber,
1141 .read_signal_strength = tda1004x_read_signal_strength,
1142 .read_snr = tda1004x_read_snr,
1143 .read_ucblocks = tda1004x_read_ucblocks,
1144};
1145
7f5e02db
JS		 1146struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1147 struct i2c_adapter* i2c)
1148{
1149 struct tda1004x_state *state;
1150
1151 /* allocate memory for the internal state */
1152 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1153 if (!state)
1154 return NULL;
1155
1156 /* setup the state */
1157 state->config = config;
1158 state->i2c = i2c;
1159 memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1160 state->initialised = 0;
1161 state->demod_type = TDA1004X_DEMOD_TDA10045;
1162
1163 /* check if the demod is there */
1164 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1165 kfree(state);
1166 return NULL;
1167 }
1168
1169 /* create dvb_frontend */
1170 state->frontend.ops = &state->ops;
1171 state->frontend.demodulator_priv = state;
1172 return &state->frontend;
1173}
1da177e4 1174
7f5e02db 1175static struct dvb_frontend_ops tda10046_ops = {
1da177e4
LT		 1176 .info = {
1177 .name = "Philips TDA10046H DVB-T",
1178 .type = FE_OFDM,
1179 .frequency_min = 51000000,
1180 .frequency_max = 858000000,
1181 .frequency_stepsize = 166667,
1182 .caps =
1183 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1184 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1185 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1186 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1187 },
1188
1189 .release = tda1004x_release,
1190
1191 .init = tda10046_init,
1192 .sleep = tda1004x_sleep,
1193
1194 .set_frontend = tda1004x_set_fe,
1195 .get_frontend = tda1004x_get_fe,
1196 .get_tune_settings = tda1004x_get_tune_settings,
1197
1198 .read_status = tda1004x_read_status,
1199 .read_ber = tda1004x_read_ber,
1200 .read_signal_strength = tda1004x_read_signal_strength,
1201 .read_snr = tda1004x_read_snr,
1202 .read_ucblocks = tda1004x_read_ucblocks,
1203};
1204
7f5e02db
JS		 1205struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1206 struct i2c_adapter* i2c)
1207{
1208 struct tda1004x_state *state;
1209
1210 /* allocate memory for the internal state */
1211 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1212 if (!state)
1213 return NULL;
1214
1215 /* setup the state */
1216 state->config = config;
1217 state->i2c = i2c;
1218 memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1219 state->initialised = 0;
1220 state->demod_type = TDA1004X_DEMOD_TDA10046;
1221
1222 /* check if the demod is there */
1223 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1224 kfree(state);
1225 return NULL;
1226 }
1227
1228 /* create dvb_frontend */
1229 state->frontend.ops = &state->ops;
1230 state->frontend.demodulator_priv = state;
1231 return &state->frontend;
1232}
1233
1da177e4
LT		 1234module_param(debug, int, 0644);
1235MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1236
1237MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1238MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1239MODULE_LICENSE("GPL");
1240
1241EXPORT_SYMBOL(tda10045_attach);
1242EXPORT_SYMBOL(tda10046_attach);
1243EXPORT_SYMBOL(tda1004x_write_byte);
Linux kernel - Deliverables
This page took 0.097101 seconds and 5 git commands to generate.