Commit | Line | Data |
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27cfc85e AP |
1 | /* |
2 | * Sony CXD2820R demodulator driver | |
3 | * | |
4 | * Copyright (C) 2010 Antti Palosaari <crope@iki.fi> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | ||
22 | #include "cxd2820r_priv.h" | |
23 | ||
37ebaf68 MCC |
24 | /* Max transfer size done by I2C transfer functions */ |
25 | #define MAX_XFER_SIZE 64 | |
26 | ||
27cfc85e AP |
27 | /* write multiple registers */ |
28 | static int cxd2820r_wr_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg, | |
29 | u8 *val, int len) | |
30 | { | |
31 | int ret; | |
37ebaf68 | 32 | u8 buf[MAX_XFER_SIZE]; |
27cfc85e AP |
33 | struct i2c_msg msg[1] = { |
34 | { | |
35 | .addr = i2c, | |
36 | .flags = 0, | |
0db3fa27 | 37 | .len = len + 1, |
27cfc85e AP |
38 | .buf = buf, |
39 | } | |
40 | }; | |
41 | ||
37ebaf68 MCC |
42 | if (1 + len > sizeof(buf)) { |
43 | dev_warn(&priv->i2c->dev, | |
44 | "%s: i2c wr reg=%04x: len=%d is too big!\n", | |
45 | KBUILD_MODNAME, reg, len); | |
46 | return -EINVAL; | |
47 | } | |
48 | ||
27cfc85e AP |
49 | buf[0] = reg; |
50 | memcpy(&buf[1], val, len); | |
51 | ||
52 | ret = i2c_transfer(priv->i2c, msg, 1); | |
53 | if (ret == 1) { | |
54 | ret = 0; | |
55 | } else { | |
75aeafc9 AP |
56 | dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \ |
57 | "len=%d\n", KBUILD_MODNAME, ret, reg, len); | |
27cfc85e AP |
58 | ret = -EREMOTEIO; |
59 | } | |
60 | return ret; | |
61 | } | |
62 | ||
63 | /* read multiple registers */ | |
64 | static int cxd2820r_rd_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg, | |
65 | u8 *val, int len) | |
66 | { | |
67 | int ret; | |
37ebaf68 | 68 | u8 buf[MAX_XFER_SIZE]; |
27cfc85e AP |
69 | struct i2c_msg msg[2] = { |
70 | { | |
71 | .addr = i2c, | |
72 | .flags = 0, | |
73 | .len = 1, | |
74 | .buf = ®, | |
75 | }, { | |
76 | .addr = i2c, | |
77 | .flags = I2C_M_RD, | |
0db3fa27 | 78 | .len = len, |
27cfc85e AP |
79 | .buf = buf, |
80 | } | |
81 | }; | |
82 | ||
37ebaf68 MCC |
83 | if (len > sizeof(buf)) { |
84 | dev_warn(&priv->i2c->dev, | |
85 | "%s: i2c wr reg=%04x: len=%d is too big!\n", | |
86 | KBUILD_MODNAME, reg, len); | |
87 | return -EINVAL; | |
88 | } | |
89 | ||
27cfc85e AP |
90 | ret = i2c_transfer(priv->i2c, msg, 2); |
91 | if (ret == 2) { | |
92 | memcpy(val, buf, len); | |
93 | ret = 0; | |
94 | } else { | |
75aeafc9 AP |
95 | dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \ |
96 | "len=%d\n", KBUILD_MODNAME, ret, reg, len); | |
27cfc85e AP |
97 | ret = -EREMOTEIO; |
98 | } | |
99 | ||
100 | return ret; | |
101 | } | |
102 | ||
103 | /* write multiple registers */ | |
9ac51c5e | 104 | int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, |
27cfc85e AP |
105 | int len) |
106 | { | |
107 | int ret; | |
108 | u8 i2c_addr; | |
109 | u8 reg = (reginfo >> 0) & 0xff; | |
110 | u8 bank = (reginfo >> 8) & 0xff; | |
111 | u8 i2c = (reginfo >> 16) & 0x01; | |
112 | ||
113 | /* select I2C */ | |
114 | if (i2c) | |
115 | i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */ | |
116 | else | |
117 | i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */ | |
118 | ||
119 | /* switch bank if needed */ | |
120 | if (bank != priv->bank[i2c]) { | |
121 | ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1); | |
122 | if (ret) | |
123 | return ret; | |
124 | priv->bank[i2c] = bank; | |
125 | } | |
126 | return cxd2820r_wr_regs_i2c(priv, i2c_addr, reg, val, len); | |
127 | } | |
128 | ||
129 | /* read multiple registers */ | |
9ac51c5e | 130 | int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, |
27cfc85e AP |
131 | int len) |
132 | { | |
133 | int ret; | |
134 | u8 i2c_addr; | |
135 | u8 reg = (reginfo >> 0) & 0xff; | |
136 | u8 bank = (reginfo >> 8) & 0xff; | |
137 | u8 i2c = (reginfo >> 16) & 0x01; | |
138 | ||
139 | /* select I2C */ | |
140 | if (i2c) | |
141 | i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */ | |
142 | else | |
143 | i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */ | |
144 | ||
145 | /* switch bank if needed */ | |
146 | if (bank != priv->bank[i2c]) { | |
147 | ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1); | |
148 | if (ret) | |
149 | return ret; | |
150 | priv->bank[i2c] = bank; | |
151 | } | |
152 | return cxd2820r_rd_regs_i2c(priv, i2c_addr, reg, val, len); | |
153 | } | |
154 | ||
155 | /* write single register */ | |
9ac51c5e | 156 | int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val) |
27cfc85e AP |
157 | { |
158 | return cxd2820r_wr_regs(priv, reg, &val, 1); | |
159 | } | |
160 | ||
161 | /* read single register */ | |
9ac51c5e | 162 | int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val) |
27cfc85e AP |
163 | { |
164 | return cxd2820r_rd_regs(priv, reg, val, 1); | |
165 | } | |
166 | ||
167 | /* write single register with mask */ | |
9ac51c5e | 168 | int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val, |
27cfc85e AP |
169 | u8 mask) |
170 | { | |
171 | int ret; | |
172 | u8 tmp; | |
173 | ||
174 | /* no need for read if whole reg is written */ | |
175 | if (mask != 0xff) { | |
176 | ret = cxd2820r_rd_reg(priv, reg, &tmp); | |
177 | if (ret) | |
178 | return ret; | |
179 | ||
180 | val &= mask; | |
181 | tmp &= ~mask; | |
182 | val |= tmp; | |
183 | } | |
184 | ||
185 | return cxd2820r_wr_reg(priv, reg, val); | |
186 | } | |
187 | ||
1e8f31f3 | 188 | int cxd2820r_gpio(struct dvb_frontend *fe, u8 *gpio) |
27cfc85e AP |
189 | { |
190 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
191 | int ret, i; | |
1e8f31f3 | 192 | u8 tmp0, tmp1; |
75aeafc9 AP |
193 | |
194 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, | |
195 | fe->dtv_property_cache.delivery_system); | |
27cfc85e | 196 | |
27cfc85e AP |
197 | /* update GPIOs only when needed */ |
198 | if (!memcmp(gpio, priv->gpio, sizeof(priv->gpio))) | |
199 | return 0; | |
200 | ||
201 | tmp0 = 0x00; | |
202 | tmp1 = 0x00; | |
203 | for (i = 0; i < sizeof(priv->gpio); i++) { | |
204 | /* enable / disable */ | |
205 | if (gpio[i] & CXD2820R_GPIO_E) | |
206 | tmp0 |= (2 << 6) >> (2 * i); | |
207 | else | |
208 | tmp0 |= (1 << 6) >> (2 * i); | |
209 | ||
210 | /* input / output */ | |
211 | if (gpio[i] & CXD2820R_GPIO_I) | |
212 | tmp1 |= (1 << (3 + i)); | |
213 | else | |
214 | tmp1 |= (0 << (3 + i)); | |
215 | ||
216 | /* high / low */ | |
217 | if (gpio[i] & CXD2820R_GPIO_H) | |
218 | tmp1 |= (1 << (0 + i)); | |
219 | else | |
220 | tmp1 |= (0 << (0 + i)); | |
221 | ||
75aeafc9 AP |
222 | dev_dbg(&priv->i2c->dev, "%s: gpio i=%d %02x %02x\n", __func__, |
223 | i, tmp0, tmp1); | |
27cfc85e AP |
224 | } |
225 | ||
75aeafc9 AP |
226 | dev_dbg(&priv->i2c->dev, "%s: wr gpio=%02x %02x\n", __func__, tmp0, |
227 | tmp1); | |
27cfc85e AP |
228 | |
229 | /* write bits [7:2] */ | |
230 | ret = cxd2820r_wr_reg_mask(priv, 0x00089, tmp0, 0xfc); | |
231 | if (ret) | |
232 | goto error; | |
233 | ||
234 | /* write bits [5:0] */ | |
235 | ret = cxd2820r_wr_reg_mask(priv, 0x0008e, tmp1, 0x3f); | |
236 | if (ret) | |
237 | goto error; | |
238 | ||
239 | memcpy(priv->gpio, gpio, sizeof(priv->gpio)); | |
240 | ||
241 | return ret; | |
242 | error: | |
75aeafc9 | 243 | dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); |
27cfc85e AP |
244 | return ret; |
245 | } | |
246 | ||
f311f68a | 247 | static int cxd2820r_set_frontend(struct dvb_frontend *fe) |
27cfc85e | 248 | { |
75aeafc9 | 249 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e AP |
250 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
251 | int ret; | |
27cfc85e | 252 | |
75aeafc9 AP |
253 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
254 | fe->dtv_property_cache.delivery_system); | |
255 | ||
14c03862 MA |
256 | switch (c->delivery_system) { |
257 | case SYS_DVBT: | |
258 | ret = cxd2820r_init_t(fe); | |
259 | if (ret < 0) | |
260 | goto err; | |
f311f68a | 261 | ret = cxd2820r_set_frontend_t(fe); |
14c03862 MA |
262 | if (ret < 0) |
263 | goto err; | |
264 | break; | |
265 | case SYS_DVBT2: | |
266 | ret = cxd2820r_init_t(fe); | |
267 | if (ret < 0) | |
268 | goto err; | |
f311f68a | 269 | ret = cxd2820r_set_frontend_t2(fe); |
14c03862 MA |
270 | if (ret < 0) |
271 | goto err; | |
272 | break; | |
f311f68a | 273 | case SYS_DVBC_ANNEX_A: |
14c03862 MA |
274 | ret = cxd2820r_init_c(fe); |
275 | if (ret < 0) | |
276 | goto err; | |
f311f68a | 277 | ret = cxd2820r_set_frontend_c(fe); |
14c03862 MA |
278 | if (ret < 0) |
279 | goto err; | |
280 | break; | |
281 | default: | |
75aeafc9 AP |
282 | dev_dbg(&priv->i2c->dev, "%s: error state=%d\n", __func__, |
283 | fe->dtv_property_cache.delivery_system); | |
14c03862 MA |
284 | ret = -EINVAL; |
285 | break; | |
27cfc85e | 286 | } |
14c03862 | 287 | err: |
27cfc85e AP |
288 | return ret; |
289 | } | |
0df289a2 MCC |
290 | |
291 | static int cxd2820r_read_status(struct dvb_frontend *fe, enum fe_status *status) | |
27cfc85e | 292 | { |
75aeafc9 | 293 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 294 | int ret; |
27cfc85e | 295 | |
75aeafc9 AP |
296 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
297 | fe->dtv_property_cache.delivery_system); | |
298 | ||
14c03862 MA |
299 | switch (fe->dtv_property_cache.delivery_system) { |
300 | case SYS_DVBT: | |
301 | ret = cxd2820r_read_status_t(fe, status); | |
302 | break; | |
303 | case SYS_DVBT2: | |
304 | ret = cxd2820r_read_status_t2(fe, status); | |
305 | break; | |
f311f68a | 306 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 307 | ret = cxd2820r_read_status_c(fe, status); |
14c03862 MA |
308 | break; |
309 | default: | |
310 | ret = -EINVAL; | |
311 | break; | |
27cfc85e | 312 | } |
27cfc85e AP |
313 | return ret; |
314 | } | |
315 | ||
7c61d80a | 316 | static int cxd2820r_get_frontend(struct dvb_frontend *fe) |
27cfc85e | 317 | { |
3b6a567a | 318 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 319 | int ret; |
27cfc85e | 320 | |
75aeafc9 AP |
321 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
322 | fe->dtv_property_cache.delivery_system); | |
3b6a567a AP |
323 | |
324 | if (priv->delivery_system == SYS_UNDEFINED) | |
325 | return 0; | |
326 | ||
14c03862 MA |
327 | switch (fe->dtv_property_cache.delivery_system) { |
328 | case SYS_DVBT: | |
f311f68a | 329 | ret = cxd2820r_get_frontend_t(fe); |
14c03862 MA |
330 | break; |
331 | case SYS_DVBT2: | |
f311f68a | 332 | ret = cxd2820r_get_frontend_t2(fe); |
14c03862 | 333 | break; |
f311f68a MCC |
334 | case SYS_DVBC_ANNEX_A: |
335 | ret = cxd2820r_get_frontend_c(fe); | |
14c03862 MA |
336 | break; |
337 | default: | |
338 | ret = -EINVAL; | |
339 | break; | |
27cfc85e | 340 | } |
27cfc85e AP |
341 | return ret; |
342 | } | |
343 | ||
344 | static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber) | |
345 | { | |
75aeafc9 | 346 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 347 | int ret; |
27cfc85e | 348 | |
75aeafc9 AP |
349 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
350 | fe->dtv_property_cache.delivery_system); | |
351 | ||
14c03862 MA |
352 | switch (fe->dtv_property_cache.delivery_system) { |
353 | case SYS_DVBT: | |
354 | ret = cxd2820r_read_ber_t(fe, ber); | |
355 | break; | |
356 | case SYS_DVBT2: | |
357 | ret = cxd2820r_read_ber_t2(fe, ber); | |
358 | break; | |
f311f68a | 359 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 360 | ret = cxd2820r_read_ber_c(fe, ber); |
14c03862 MA |
361 | break; |
362 | default: | |
363 | ret = -EINVAL; | |
364 | break; | |
27cfc85e | 365 | } |
27cfc85e AP |
366 | return ret; |
367 | } | |
368 | ||
369 | static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength) | |
370 | { | |
75aeafc9 | 371 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 372 | int ret; |
27cfc85e | 373 | |
75aeafc9 AP |
374 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
375 | fe->dtv_property_cache.delivery_system); | |
376 | ||
14c03862 MA |
377 | switch (fe->dtv_property_cache.delivery_system) { |
378 | case SYS_DVBT: | |
379 | ret = cxd2820r_read_signal_strength_t(fe, strength); | |
380 | break; | |
381 | case SYS_DVBT2: | |
382 | ret = cxd2820r_read_signal_strength_t2(fe, strength); | |
383 | break; | |
f311f68a | 384 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 385 | ret = cxd2820r_read_signal_strength_c(fe, strength); |
14c03862 MA |
386 | break; |
387 | default: | |
388 | ret = -EINVAL; | |
389 | break; | |
27cfc85e | 390 | } |
27cfc85e AP |
391 | return ret; |
392 | } | |
393 | ||
394 | static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr) | |
395 | { | |
75aeafc9 | 396 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 397 | int ret; |
27cfc85e | 398 | |
75aeafc9 AP |
399 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
400 | fe->dtv_property_cache.delivery_system); | |
401 | ||
14c03862 MA |
402 | switch (fe->dtv_property_cache.delivery_system) { |
403 | case SYS_DVBT: | |
404 | ret = cxd2820r_read_snr_t(fe, snr); | |
405 | break; | |
406 | case SYS_DVBT2: | |
407 | ret = cxd2820r_read_snr_t2(fe, snr); | |
408 | break; | |
f311f68a | 409 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 410 | ret = cxd2820r_read_snr_c(fe, snr); |
14c03862 MA |
411 | break; |
412 | default: | |
413 | ret = -EINVAL; | |
414 | break; | |
27cfc85e | 415 | } |
27cfc85e AP |
416 | return ret; |
417 | } | |
418 | ||
419 | static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |
420 | { | |
75aeafc9 | 421 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 422 | int ret; |
27cfc85e | 423 | |
75aeafc9 AP |
424 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
425 | fe->dtv_property_cache.delivery_system); | |
426 | ||
14c03862 MA |
427 | switch (fe->dtv_property_cache.delivery_system) { |
428 | case SYS_DVBT: | |
429 | ret = cxd2820r_read_ucblocks_t(fe, ucblocks); | |
430 | break; | |
431 | case SYS_DVBT2: | |
432 | ret = cxd2820r_read_ucblocks_t2(fe, ucblocks); | |
433 | break; | |
f311f68a | 434 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 435 | ret = cxd2820r_read_ucblocks_c(fe, ucblocks); |
14c03862 MA |
436 | break; |
437 | default: | |
438 | ret = -EINVAL; | |
439 | break; | |
27cfc85e | 440 | } |
27cfc85e AP |
441 | return ret; |
442 | } | |
443 | ||
444 | static int cxd2820r_init(struct dvb_frontend *fe) | |
445 | { | |
14c03862 | 446 | return 0; |
27cfc85e AP |
447 | } |
448 | ||
449 | static int cxd2820r_sleep(struct dvb_frontend *fe) | |
450 | { | |
75aeafc9 | 451 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
27cfc85e | 452 | int ret; |
27cfc85e | 453 | |
75aeafc9 AP |
454 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
455 | fe->dtv_property_cache.delivery_system); | |
456 | ||
14c03862 MA |
457 | switch (fe->dtv_property_cache.delivery_system) { |
458 | case SYS_DVBT: | |
459 | ret = cxd2820r_sleep_t(fe); | |
460 | break; | |
461 | case SYS_DVBT2: | |
462 | ret = cxd2820r_sleep_t2(fe); | |
463 | break; | |
f311f68a | 464 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 465 | ret = cxd2820r_sleep_c(fe); |
14c03862 MA |
466 | break; |
467 | default: | |
468 | ret = -EINVAL; | |
469 | break; | |
27cfc85e | 470 | } |
27cfc85e AP |
471 | return ret; |
472 | } | |
473 | ||
474 | static int cxd2820r_get_tune_settings(struct dvb_frontend *fe, | |
14c03862 | 475 | struct dvb_frontend_tune_settings *s) |
27cfc85e | 476 | { |
75aeafc9 | 477 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
e47b78f0 | 478 | int ret; |
27cfc85e | 479 | |
75aeafc9 AP |
480 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, |
481 | fe->dtv_property_cache.delivery_system); | |
482 | ||
14c03862 MA |
483 | switch (fe->dtv_property_cache.delivery_system) { |
484 | case SYS_DVBT: | |
485 | ret = cxd2820r_get_tune_settings_t(fe, s); | |
486 | break; | |
487 | case SYS_DVBT2: | |
488 | ret = cxd2820r_get_tune_settings_t2(fe, s); | |
489 | break; | |
f311f68a | 490 | case SYS_DVBC_ANNEX_A: |
27cfc85e | 491 | ret = cxd2820r_get_tune_settings_c(fe, s); |
14c03862 MA |
492 | break; |
493 | default: | |
494 | ret = -EINVAL; | |
495 | break; | |
27cfc85e | 496 | } |
27cfc85e AP |
497 | return ret; |
498 | } | |
499 | ||
41da5320 | 500 | static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe) |
e47b78f0 AP |
501 | { |
502 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
503 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
504 | int ret, i; | |
0df289a2 | 505 | enum fe_status status = 0; |
75aeafc9 AP |
506 | |
507 | dev_dbg(&priv->i2c->dev, "%s: delsys=%d\n", __func__, | |
508 | fe->dtv_property_cache.delivery_system); | |
e47b78f0 AP |
509 | |
510 | /* switch between DVB-T and DVB-T2 when tune fails */ | |
d04ca8df | 511 | if (priv->last_tune_failed) { |
72565224 AP |
512 | if (priv->delivery_system == SYS_DVBT) { |
513 | ret = cxd2820r_sleep_t(fe); | |
514 | if (ret) | |
515 | goto error; | |
516 | ||
e47b78f0 | 517 | c->delivery_system = SYS_DVBT2; |
72565224 AP |
518 | } else if (priv->delivery_system == SYS_DVBT2) { |
519 | ret = cxd2820r_sleep_t2(fe); | |
520 | if (ret) | |
521 | goto error; | |
522 | ||
e47b78f0 | 523 | c->delivery_system = SYS_DVBT; |
72565224 | 524 | } |
e47b78f0 AP |
525 | } |
526 | ||
527 | /* set frontend */ | |
f311f68a | 528 | ret = cxd2820r_set_frontend(fe); |
e47b78f0 AP |
529 | if (ret) |
530 | goto error; | |
531 | ||
532 | ||
533 | /* frontend lock wait loop count */ | |
534 | switch (priv->delivery_system) { | |
535 | case SYS_DVBT: | |
1f649729 | 536 | case SYS_DVBC_ANNEX_A: |
e47b78f0 AP |
537 | i = 20; |
538 | break; | |
539 | case SYS_DVBT2: | |
540 | i = 40; | |
541 | break; | |
542 | case SYS_UNDEFINED: | |
543 | default: | |
544 | i = 0; | |
545 | break; | |
546 | } | |
547 | ||
548 | /* wait frontend lock */ | |
549 | for (; i > 0; i--) { | |
75aeafc9 | 550 | dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i); |
e47b78f0 AP |
551 | msleep(50); |
552 | ret = cxd2820r_read_status(fe, &status); | |
553 | if (ret) | |
554 | goto error; | |
555 | ||
b115f400 | 556 | if (status & FE_HAS_LOCK) |
e47b78f0 AP |
557 | break; |
558 | } | |
559 | ||
560 | /* check if we have a valid signal */ | |
b115f400 | 561 | if (status & FE_HAS_LOCK) { |
285c0b00 | 562 | priv->last_tune_failed = false; |
e47b78f0 AP |
563 | return DVBFE_ALGO_SEARCH_SUCCESS; |
564 | } else { | |
285c0b00 | 565 | priv->last_tune_failed = true; |
e47b78f0 AP |
566 | return DVBFE_ALGO_SEARCH_AGAIN; |
567 | } | |
568 | ||
569 | error: | |
75aeafc9 | 570 | dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); |
e47b78f0 AP |
571 | return DVBFE_ALGO_SEARCH_ERROR; |
572 | } | |
573 | ||
574 | static int cxd2820r_get_frontend_algo(struct dvb_frontend *fe) | |
575 | { | |
576 | return DVBFE_ALGO_CUSTOM; | |
577 | } | |
578 | ||
27cfc85e AP |
579 | static void cxd2820r_release(struct dvb_frontend *fe) |
580 | { | |
581 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
75aeafc9 AP |
582 | |
583 | dev_dbg(&priv->i2c->dev, "%s\n", __func__); | |
27cfc85e | 584 | |
1e8f31f3 AP |
585 | #ifdef CONFIG_GPIOLIB |
586 | /* remove GPIOs */ | |
88d5e520 | 587 | if (priv->gpio_chip.label) |
588 | gpiochip_remove(&priv->gpio_chip); | |
589 | ||
1e8f31f3 | 590 | #endif |
14c03862 | 591 | kfree(priv); |
27cfc85e AP |
592 | return; |
593 | } | |
594 | ||
0db4bf42 | 595 | static int cxd2820r_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) |
27cfc85e AP |
596 | { |
597 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
75aeafc9 AP |
598 | |
599 | dev_dbg(&priv->i2c->dev, "%s: %d\n", __func__, enable); | |
0db4bf42 SK |
600 | |
601 | /* Bit 0 of reg 0xdb in bank 0x00 controls I2C repeater */ | |
602 | return cxd2820r_wr_reg_mask(priv, 0xdb, enable ? 1 : 0, 0x1); | |
27cfc85e | 603 | } |
27cfc85e | 604 | |
1e8f31f3 AP |
605 | #ifdef CONFIG_GPIOLIB |
606 | static int cxd2820r_gpio_direction_output(struct gpio_chip *chip, unsigned nr, | |
607 | int val) | |
608 | { | |
609 | struct cxd2820r_priv *priv = | |
610 | container_of(chip, struct cxd2820r_priv, gpio_chip); | |
611 | u8 gpio[GPIO_COUNT]; | |
612 | ||
613 | dev_dbg(&priv->i2c->dev, "%s: nr=%d val=%d\n", __func__, nr, val); | |
614 | ||
615 | memcpy(gpio, priv->gpio, sizeof(gpio)); | |
616 | gpio[nr] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | (val << 2); | |
617 | ||
618 | return cxd2820r_gpio(&priv->fe, gpio); | |
619 | } | |
620 | ||
621 | static void cxd2820r_gpio_set(struct gpio_chip *chip, unsigned nr, int val) | |
622 | { | |
623 | struct cxd2820r_priv *priv = | |
624 | container_of(chip, struct cxd2820r_priv, gpio_chip); | |
625 | u8 gpio[GPIO_COUNT]; | |
626 | ||
627 | dev_dbg(&priv->i2c->dev, "%s: nr=%d val=%d\n", __func__, nr, val); | |
628 | ||
629 | memcpy(gpio, priv->gpio, sizeof(gpio)); | |
630 | gpio[nr] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | (val << 2); | |
631 | ||
632 | (void) cxd2820r_gpio(&priv->fe, gpio); | |
633 | ||
634 | return; | |
635 | } | |
636 | ||
637 | static int cxd2820r_gpio_get(struct gpio_chip *chip, unsigned nr) | |
638 | { | |
639 | struct cxd2820r_priv *priv = | |
640 | container_of(chip, struct cxd2820r_priv, gpio_chip); | |
641 | ||
642 | dev_dbg(&priv->i2c->dev, "%s: nr=%d\n", __func__, nr); | |
643 | ||
644 | return (priv->gpio[nr] >> 2) & 0x01; | |
645 | } | |
646 | #endif | |
647 | ||
14c03862 | 648 | static const struct dvb_frontend_ops cxd2820r_ops = { |
f311f68a | 649 | .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A }, |
14c03862 MA |
650 | /* default: DVB-T/T2 */ |
651 | .info = { | |
9bf31efa | 652 | .name = "Sony CXD2820R", |
14c03862 MA |
653 | |
654 | .caps = FE_CAN_FEC_1_2 | | |
655 | FE_CAN_FEC_2_3 | | |
656 | FE_CAN_FEC_3_4 | | |
657 | FE_CAN_FEC_5_6 | | |
658 | FE_CAN_FEC_7_8 | | |
659 | FE_CAN_FEC_AUTO | | |
660 | FE_CAN_QPSK | | |
661 | FE_CAN_QAM_16 | | |
9bf31efa | 662 | FE_CAN_QAM_32 | |
14c03862 | 663 | FE_CAN_QAM_64 | |
9bf31efa | 664 | FE_CAN_QAM_128 | |
14c03862 MA |
665 | FE_CAN_QAM_256 | |
666 | FE_CAN_QAM_AUTO | | |
667 | FE_CAN_TRANSMISSION_MODE_AUTO | | |
668 | FE_CAN_GUARD_INTERVAL_AUTO | | |
669 | FE_CAN_HIERARCHY_AUTO | | |
670 | FE_CAN_MUTE_TS | | |
4a74772e EP |
671 | FE_CAN_2G_MODULATION | |
672 | FE_CAN_MULTISTREAM | |
14c03862 | 673 | }, |
27cfc85e | 674 | |
14c03862 MA |
675 | .release = cxd2820r_release, |
676 | .init = cxd2820r_init, | |
677 | .sleep = cxd2820r_sleep, | |
27cfc85e | 678 | |
14c03862 MA |
679 | .get_tune_settings = cxd2820r_get_tune_settings, |
680 | .i2c_gate_ctrl = cxd2820r_i2c_gate_ctrl, | |
27cfc85e | 681 | |
f311f68a | 682 | .get_frontend = cxd2820r_get_frontend, |
27cfc85e | 683 | |
14c03862 MA |
684 | .get_frontend_algo = cxd2820r_get_frontend_algo, |
685 | .search = cxd2820r_search, | |
27cfc85e | 686 | |
14c03862 MA |
687 | .read_status = cxd2820r_read_status, |
688 | .read_snr = cxd2820r_read_snr, | |
689 | .read_ber = cxd2820r_read_ber, | |
690 | .read_ucblocks = cxd2820r_read_ucblocks, | |
691 | .read_signal_strength = cxd2820r_read_signal_strength, | |
14c03862 | 692 | }; |
27cfc85e | 693 | |
14c03862 | 694 | struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg, |
1e8f31f3 AP |
695 | struct i2c_adapter *i2c, int *gpio_chip_base |
696 | ) | |
14c03862 | 697 | { |
1e8f31f3 | 698 | struct cxd2820r_priv *priv; |
14c03862 | 699 | int ret; |
44e0d7de | 700 | u8 tmp; |
14c03862 | 701 | |
a36a66d7 | 702 | priv = kzalloc(sizeof(struct cxd2820r_priv), GFP_KERNEL); |
1e8f31f3 AP |
703 | if (!priv) { |
704 | ret = -ENOMEM; | |
705 | dev_err(&i2c->dev, "%s: kzalloc() failed\n", | |
706 | KBUILD_MODNAME); | |
14c03862 | 707 | goto error; |
1e8f31f3 | 708 | } |
27cfc85e | 709 | |
14c03862 | 710 | priv->i2c = i2c; |
a36a66d7 AP |
711 | memcpy(&priv->cfg, cfg, sizeof(struct cxd2820r_config)); |
712 | memcpy(&priv->fe.ops, &cxd2820r_ops, sizeof(struct dvb_frontend_ops)); | |
713 | priv->fe.demodulator_priv = priv; | |
14c03862 MA |
714 | |
715 | priv->bank[0] = priv->bank[1] = 0xff; | |
716 | ret = cxd2820r_rd_reg(priv, 0x000fd, &tmp); | |
75aeafc9 | 717 | dev_dbg(&priv->i2c->dev, "%s: chip id=%02x\n", __func__, tmp); |
14c03862 MA |
718 | if (ret || tmp != 0xe1) |
719 | goto error; | |
720 | ||
1e8f31f3 | 721 | if (gpio_chip_base) { |
a36a66d7 AP |
722 | #ifdef CONFIG_GPIOLIB |
723 | /* add GPIOs */ | |
1e8f31f3 AP |
724 | priv->gpio_chip.label = KBUILD_MODNAME; |
725 | priv->gpio_chip.dev = &priv->i2c->dev; | |
726 | priv->gpio_chip.owner = THIS_MODULE; | |
727 | priv->gpio_chip.direction_output = | |
728 | cxd2820r_gpio_direction_output; | |
729 | priv->gpio_chip.set = cxd2820r_gpio_set; | |
730 | priv->gpio_chip.get = cxd2820r_gpio_get; | |
731 | priv->gpio_chip.base = -1; /* dynamic allocation */ | |
732 | priv->gpio_chip.ngpio = GPIO_COUNT; | |
733 | priv->gpio_chip.can_sleep = 1; | |
734 | ret = gpiochip_add(&priv->gpio_chip); | |
735 | if (ret) | |
736 | goto error; | |
737 | ||
738 | dev_dbg(&priv->i2c->dev, "%s: gpio_chip.base=%d\n", __func__, | |
739 | priv->gpio_chip.base); | |
740 | ||
741 | *gpio_chip_base = priv->gpio_chip.base; | |
a36a66d7 AP |
742 | #else |
743 | /* | |
744 | * Use static GPIO configuration if GPIOLIB is undefined. | |
745 | * This is fallback condition. | |
746 | */ | |
44e0d7de | 747 | u8 gpio[GPIO_COUNT]; |
a36a66d7 AP |
748 | gpio[0] = (*gpio_chip_base >> 0) & 0x07; |
749 | gpio[1] = (*gpio_chip_base >> 3) & 0x07; | |
750 | gpio[2] = 0; | |
751 | ret = cxd2820r_gpio(&priv->fe, gpio); | |
752 | if (ret) | |
753 | goto error; | |
1e8f31f3 | 754 | #endif |
a36a66d7 | 755 | } |
1e8f31f3 | 756 | |
14c03862 | 757 | return &priv->fe; |
27cfc85e | 758 | error: |
1e8f31f3 | 759 | dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret); |
27cfc85e AP |
760 | kfree(priv); |
761 | return NULL; | |
762 | } | |
763 | EXPORT_SYMBOL(cxd2820r_attach); | |
764 | ||
27cfc85e AP |
765 | MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); |
766 | MODULE_DESCRIPTION("Sony CXD2820R demodulator driver"); | |
767 | MODULE_LICENSE("GPL"); |