Commit | Line | Data |
---|---|---|
27cfc85e AP |
1 | /* |
2 | * Sony CXD2820R demodulator driver | |
3 | * | |
4 | * Copyright (C) 2010 Antti Palosaari <crope@iki.fi> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | ||
9ac51c5e SK |
22 | #include "cxd2820r_priv.h" |
23 | ||
f311f68a | 24 | int cxd2820r_set_frontend_t2(struct dvb_frontend *fe) |
27cfc85e | 25 | { |
27cfc85e | 26 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
7e3e68bc | 27 | struct cxd2820r_priv *priv = fe->demodulator_priv; |
13d723ba | 28 | int ret, i, bw_i; |
fda23faa | 29 | u32 if_freq, if_ctl; |
27cfc85e AP |
30 | u64 num; |
31 | u8 buf[3], bw_param; | |
32 | u8 bw_params1[][5] = { | |
33 | { 0x1c, 0xb3, 0x33, 0x33, 0x33 }, /* 5 MHz */ | |
34 | { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */ | |
35 | { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */ | |
36 | { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */ | |
37 | }; | |
38 | struct reg_val_mask tab[] = { | |
39 | { 0x00080, 0x02, 0xff }, | |
40 | { 0x00081, 0x20, 0xff }, | |
41 | { 0x00085, 0x07, 0xff }, | |
42 | { 0x00088, 0x01, 0xff }, | |
43 | { 0x02069, 0x01, 0xff }, | |
44 | ||
45 | { 0x0207f, 0x2a, 0xff }, | |
46 | { 0x02082, 0x0a, 0xff }, | |
47 | { 0x02083, 0x0a, 0xff }, | |
48 | { 0x020cb, priv->cfg.if_agc_polarity << 6, 0x40 }, | |
49 | { 0x02070, priv->cfg.ts_mode, 0xff }, | |
4d1ab185 | 50 | { 0x02071, !priv->cfg.ts_clock_inv << 6, 0x40 }, |
27cfc85e AP |
51 | { 0x020b5, priv->cfg.spec_inv << 4, 0x10 }, |
52 | { 0x02567, 0x07, 0x0f }, | |
53 | { 0x02569, 0x03, 0x03 }, | |
54 | { 0x02595, 0x1a, 0xff }, | |
55 | { 0x02596, 0x50, 0xff }, | |
56 | { 0x02a8c, 0x00, 0xff }, | |
57 | { 0x02a8d, 0x34, 0xff }, | |
58 | { 0x02a45, 0x06, 0x07 }, | |
59 | { 0x03f10, 0x0d, 0xff }, | |
60 | { 0x03f11, 0x02, 0xff }, | |
61 | { 0x03f12, 0x01, 0xff }, | |
62 | { 0x03f23, 0x2c, 0xff }, | |
63 | { 0x03f51, 0x13, 0xff }, | |
64 | { 0x03f52, 0x01, 0xff }, | |
65 | { 0x03f53, 0x00, 0xff }, | |
66 | { 0x027e6, 0x14, 0xff }, | |
67 | { 0x02786, 0x02, 0x07 }, | |
68 | { 0x02787, 0x40, 0xe0 }, | |
69 | { 0x027ef, 0x10, 0x18 }, | |
70 | }; | |
71 | ||
75aeafc9 AP |
72 | dev_dbg(&priv->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", __func__, |
73 | c->frequency, c->bandwidth_hz); | |
27cfc85e | 74 | |
13d723ba AP |
75 | switch (c->bandwidth_hz) { |
76 | case 5000000: | |
77 | bw_i = 0; | |
78 | bw_param = 3; | |
79 | break; | |
80 | case 6000000: | |
81 | bw_i = 1; | |
82 | bw_param = 2; | |
83 | break; | |
84 | case 7000000: | |
85 | bw_i = 2; | |
86 | bw_param = 1; | |
87 | break; | |
88 | case 8000000: | |
89 | bw_i = 3; | |
90 | bw_param = 0; | |
91 | break; | |
92 | default: | |
93 | return -EINVAL; | |
94 | } | |
95 | ||
27cfc85e AP |
96 | /* program tuner */ |
97 | if (fe->ops.tuner_ops.set_params) | |
14d24d14 | 98 | fe->ops.tuner_ops.set_params(fe); |
27cfc85e AP |
99 | |
100 | if (priv->delivery_system != SYS_DVBT2) { | |
101 | for (i = 0; i < ARRAY_SIZE(tab); i++) { | |
102 | ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, | |
103 | tab[i].val, tab[i].mask); | |
104 | if (ret) | |
105 | goto error; | |
106 | } | |
107 | } | |
108 | ||
109 | priv->delivery_system = SYS_DVBT2; | |
110 | ||
fda23faa AP |
111 | /* program IF frequency */ |
112 | if (fe->ops.tuner_ops.get_if_frequency) { | |
113 | ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq); | |
114 | if (ret) | |
115 | goto error; | |
116 | } else | |
117 | if_freq = 0; | |
118 | ||
75aeafc9 | 119 | dev_dbg(&priv->i2c->dev, "%s: if_freq=%d\n", __func__, if_freq); |
fda23faa AP |
120 | |
121 | num = if_freq / 1000; /* Hz => kHz */ | |
27cfc85e | 122 | num *= 0x1000000; |
512eb720 | 123 | if_ctl = DIV_ROUND_CLOSEST_ULL(num, 41000); |
27cfc85e AP |
124 | buf[0] = ((if_ctl >> 16) & 0xff); |
125 | buf[1] = ((if_ctl >> 8) & 0xff); | |
126 | buf[2] = ((if_ctl >> 0) & 0xff); | |
127 | ||
4a74772e | 128 | /* PLP filtering */ |
a9af5392 | 129 | if (c->stream_id > 255) { |
4a74772e EP |
130 | dev_dbg(&priv->i2c->dev, "%s: Disable PLP filtering\n", __func__); |
131 | ret = cxd2820r_wr_reg(priv, 0x023ad , 0); | |
132 | if (ret) | |
133 | goto error; | |
134 | } else { | |
135 | dev_dbg(&priv->i2c->dev, "%s: Enable PLP filtering = %d\n", __func__, | |
136 | c->stream_id); | |
137 | ret = cxd2820r_wr_reg(priv, 0x023af , c->stream_id & 0xFF); | |
138 | if (ret) | |
139 | goto error; | |
140 | ret = cxd2820r_wr_reg(priv, 0x023ad , 1); | |
141 | if (ret) | |
142 | goto error; | |
143 | } | |
144 | ||
27cfc85e AP |
145 | ret = cxd2820r_wr_regs(priv, 0x020b6, buf, 3); |
146 | if (ret) | |
147 | goto error; | |
148 | ||
13d723ba | 149 | ret = cxd2820r_wr_regs(priv, 0x0209f, bw_params1[bw_i], 5); |
27cfc85e AP |
150 | if (ret) |
151 | goto error; | |
152 | ||
153 | ret = cxd2820r_wr_reg_mask(priv, 0x020d7, bw_param << 6, 0xc0); | |
154 | if (ret) | |
155 | goto error; | |
156 | ||
157 | ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08); | |
158 | if (ret) | |
159 | goto error; | |
160 | ||
161 | ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01); | |
162 | if (ret) | |
163 | goto error; | |
164 | ||
165 | return ret; | |
166 | error: | |
75aeafc9 | 167 | dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); |
27cfc85e AP |
168 | return ret; |
169 | ||
170 | } | |
171 | ||
7e3e68bc MCC |
172 | int cxd2820r_get_frontend_t2(struct dvb_frontend *fe, |
173 | struct dtv_frontend_properties *c) | |
27cfc85e AP |
174 | { |
175 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
27cfc85e AP |
176 | int ret; |
177 | u8 buf[2]; | |
178 | ||
179 | ret = cxd2820r_rd_regs(priv, 0x0205c, buf, 2); | |
180 | if (ret) | |
181 | goto error; | |
182 | ||
183 | switch ((buf[0] >> 0) & 0x07) { | |
184 | case 0: | |
185 | c->transmission_mode = TRANSMISSION_MODE_2K; | |
186 | break; | |
187 | case 1: | |
188 | c->transmission_mode = TRANSMISSION_MODE_8K; | |
189 | break; | |
190 | case 2: | |
191 | c->transmission_mode = TRANSMISSION_MODE_4K; | |
192 | break; | |
193 | case 3: | |
194 | c->transmission_mode = TRANSMISSION_MODE_1K; | |
195 | break; | |
196 | case 4: | |
197 | c->transmission_mode = TRANSMISSION_MODE_16K; | |
198 | break; | |
199 | case 5: | |
200 | c->transmission_mode = TRANSMISSION_MODE_32K; | |
201 | break; | |
202 | } | |
203 | ||
204 | switch ((buf[1] >> 4) & 0x07) { | |
205 | case 0: | |
206 | c->guard_interval = GUARD_INTERVAL_1_32; | |
207 | break; | |
208 | case 1: | |
209 | c->guard_interval = GUARD_INTERVAL_1_16; | |
210 | break; | |
211 | case 2: | |
212 | c->guard_interval = GUARD_INTERVAL_1_8; | |
213 | break; | |
214 | case 3: | |
215 | c->guard_interval = GUARD_INTERVAL_1_4; | |
216 | break; | |
217 | case 4: | |
218 | c->guard_interval = GUARD_INTERVAL_1_128; | |
219 | break; | |
220 | case 5: | |
221 | c->guard_interval = GUARD_INTERVAL_19_128; | |
222 | break; | |
223 | case 6: | |
224 | c->guard_interval = GUARD_INTERVAL_19_256; | |
225 | break; | |
226 | } | |
227 | ||
228 | ret = cxd2820r_rd_regs(priv, 0x0225b, buf, 2); | |
229 | if (ret) | |
230 | goto error; | |
231 | ||
232 | switch ((buf[0] >> 0) & 0x07) { | |
233 | case 0: | |
234 | c->fec_inner = FEC_1_2; | |
235 | break; | |
236 | case 1: | |
237 | c->fec_inner = FEC_3_5; | |
238 | break; | |
239 | case 2: | |
240 | c->fec_inner = FEC_2_3; | |
241 | break; | |
242 | case 3: | |
243 | c->fec_inner = FEC_3_4; | |
244 | break; | |
245 | case 4: | |
246 | c->fec_inner = FEC_4_5; | |
247 | break; | |
248 | case 5: | |
249 | c->fec_inner = FEC_5_6; | |
250 | break; | |
251 | } | |
252 | ||
253 | switch ((buf[1] >> 0) & 0x07) { | |
254 | case 0: | |
255 | c->modulation = QPSK; | |
256 | break; | |
257 | case 1: | |
258 | c->modulation = QAM_16; | |
259 | break; | |
260 | case 2: | |
261 | c->modulation = QAM_64; | |
262 | break; | |
263 | case 3: | |
264 | c->modulation = QAM_256; | |
265 | break; | |
266 | } | |
267 | ||
268 | ret = cxd2820r_rd_reg(priv, 0x020b5, &buf[0]); | |
269 | if (ret) | |
270 | goto error; | |
271 | ||
272 | switch ((buf[0] >> 4) & 0x01) { | |
273 | case 0: | |
274 | c->inversion = INVERSION_OFF; | |
275 | break; | |
276 | case 1: | |
277 | c->inversion = INVERSION_ON; | |
278 | break; | |
279 | } | |
280 | ||
281 | return ret; | |
282 | error: | |
75aeafc9 | 283 | dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); |
27cfc85e AP |
284 | return ret; |
285 | } | |
286 | ||
0df289a2 | 287 | int cxd2820r_read_status_t2(struct dvb_frontend *fe, enum fe_status *status) |
27cfc85e AP |
288 | { |
289 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
290 | int ret; | |
291 | u8 buf[1]; | |
292 | *status = 0; | |
293 | ||
294 | ret = cxd2820r_rd_reg(priv, 0x02010 , &buf[0]); | |
295 | if (ret) | |
296 | goto error; | |
297 | ||
298 | if ((buf[0] & 0x07) == 6) { | |
299 | if (((buf[0] >> 5) & 0x01) == 1) { | |
300 | *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | | |
301 | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; | |
302 | } else { | |
303 | *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | | |
304 | FE_HAS_VITERBI | FE_HAS_SYNC; | |
305 | } | |
306 | } | |
307 | ||
75aeafc9 | 308 | dev_dbg(&priv->i2c->dev, "%s: lock=%02x\n", __func__, buf[0]); |
27cfc85e AP |
309 | |
310 | return ret; | |
311 | error: | |
75aeafc9 | 312 | dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); |
27cfc85e AP |
313 | return ret; |
314 | } | |
315 | ||
9ac51c5e | 316 | int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber) |
27cfc85e AP |
317 | { |
318 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
319 | int ret; | |
320 | u8 buf[4]; | |
321 | unsigned int errbits; | |
322 | *ber = 0; | |
323 | /* FIXME: correct calculation */ | |
324 | ||
325 | ret = cxd2820r_rd_regs(priv, 0x02039, buf, sizeof(buf)); | |
326 | if (ret) | |
327 | goto error; | |
328 | ||
329 | if ((buf[0] >> 4) & 0x01) { | |
330 | errbits = (buf[0] & 0x0f) << 24 | buf[1] << 16 | | |
331 | buf[2] << 8 | buf[3]; | |
332 | ||
333 | if (errbits) | |
334 | *ber = errbits * 64 / 16588800; | |
335 | } | |
336 | ||
337 | return ret; | |
338 | error: | |
75aeafc9 | 339 | dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); |
27cfc85e AP |
340 | return ret; |
341 | } | |
342 | ||
9ac51c5e | 343 | int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe, |
27cfc85e AP |
344 | u16 *strength) |
345 | { | |
346 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
347 | int ret; | |
348 | u8 buf[2]; | |
349 | u16 tmp; | |
350 | ||
351 | ret = cxd2820r_rd_regs(priv, 0x02026, buf, sizeof(buf)); | |
352 | if (ret) | |
353 | goto error; | |
354 | ||
355 | tmp = (buf[0] & 0x0f) << 8 | buf[1]; | |
356 | tmp = ~tmp & 0x0fff; | |
357 | ||
358 | /* scale value to 0x0000-0xffff from 0x0000-0x0fff */ | |
359 | *strength = tmp * 0xffff / 0x0fff; | |
360 | ||
361 | return ret; | |
362 | error: | |
75aeafc9 | 363 | dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); |
27cfc85e AP |
364 | return ret; |
365 | } | |
366 | ||
9ac51c5e | 367 | int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr) |
27cfc85e AP |
368 | { |
369 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
370 | int ret; | |
371 | u8 buf[2]; | |
372 | u16 tmp; | |
373 | /* report SNR in dB * 10 */ | |
374 | ||
375 | ret = cxd2820r_rd_regs(priv, 0x02028, buf, sizeof(buf)); | |
376 | if (ret) | |
377 | goto error; | |
378 | ||
379 | tmp = (buf[0] & 0x0f) << 8 | buf[1]; | |
380 | #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */ | |
381 | if (tmp) | |
382 | *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24) | |
383 | / 100); | |
384 | else | |
385 | *snr = 0; | |
386 | ||
75aeafc9 AP |
387 | dev_dbg(&priv->i2c->dev, "%s: dBx10=%d val=%04x\n", __func__, *snr, |
388 | tmp); | |
27cfc85e AP |
389 | |
390 | return ret; | |
391 | error: | |
75aeafc9 | 392 | dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); |
27cfc85e AP |
393 | return ret; |
394 | } | |
395 | ||
9ac51c5e | 396 | int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks) |
27cfc85e AP |
397 | { |
398 | *ucblocks = 0; | |
399 | /* no way to read ? */ | |
400 | return 0; | |
401 | } | |
402 | ||
9ac51c5e | 403 | int cxd2820r_sleep_t2(struct dvb_frontend *fe) |
27cfc85e AP |
404 | { |
405 | struct cxd2820r_priv *priv = fe->demodulator_priv; | |
406 | int ret, i; | |
407 | struct reg_val_mask tab[] = { | |
408 | { 0x000ff, 0x1f, 0xff }, | |
409 | { 0x00085, 0x00, 0xff }, | |
410 | { 0x00088, 0x01, 0xff }, | |
411 | { 0x02069, 0x00, 0xff }, | |
412 | { 0x00081, 0x00, 0xff }, | |
413 | { 0x00080, 0x00, 0xff }, | |
414 | }; | |
415 | ||
75aeafc9 | 416 | dev_dbg(&priv->i2c->dev, "%s\n", __func__); |
27cfc85e AP |
417 | |
418 | for (i = 0; i < ARRAY_SIZE(tab); i++) { | |
419 | ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val, | |
420 | tab[i].mask); | |
421 | if (ret) | |
422 | goto error; | |
423 | } | |
424 | ||
425 | priv->delivery_system = SYS_UNDEFINED; | |
426 | ||
427 | return ret; | |
428 | error: | |
75aeafc9 | 429 | dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); |
27cfc85e AP |
430 | return ret; |
431 | } | |
432 | ||
9ac51c5e | 433 | int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe, |
27cfc85e AP |
434 | struct dvb_frontend_tune_settings *s) |
435 | { | |
436 | s->min_delay_ms = 1500; | |
437 | s->step_size = fe->ops.info.frequency_stepsize * 2; | |
438 | s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1; | |
439 | ||
440 | return 0; | |
441 | } |