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1da177e4 LT |
1 | /* |
2 | * dib3000mb_priv.h | |
3 | * | |
99e44da7 | 4 | * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@posteo.de) |
1da177e4 LT |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation, version 2. | |
9 | * | |
10 | * for more information see dib3000mb.c . | |
11 | */ | |
12 | ||
13 | #ifndef __DIB3000MB_PRIV_H_INCLUDED__ | |
14 | #define __DIB3000MB_PRIV_H_INCLUDED__ | |
15 | ||
74340b0a PB |
16 | /* info and err, taken from usb.h, if there is anything available like by default. */ |
17 | #define err(format, arg...) printk(KERN_ERR "dib3000: " format "\n" , ## arg) | |
18 | #define info(format, arg...) printk(KERN_INFO "dib3000: " format "\n" , ## arg) | |
19 | #define warn(format, arg...) printk(KERN_WARNING "dib3000: " format "\n" , ## arg) | |
20 | ||
21 | /* handy shortcuts */ | |
22 | #define rd(reg) dib3000_read_reg(state,reg) | |
23 | ||
24 | #define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \ | |
25 | { err("while sending 0x%04x to 0x%04x.",val,reg); return -EREMOTEIO; } | |
26 | ||
27 | #define wr_foreach(a,v) { int i; \ | |
28 | if (sizeof(a) != sizeof(v)) \ | |
29 | err("sizeof: %zu %zu is different",sizeof(a),sizeof(v));\ | |
30 | for (i=0; i < sizeof(a)/sizeof(u16); i++) \ | |
31 | wr(a[i],v[i]); \ | |
32 | } | |
33 | ||
34 | #define set_or(reg,val) wr(reg,rd(reg) | val) | |
35 | ||
36 | #define set_and(reg,val) wr(reg,rd(reg) & val) | |
37 | ||
38 | /* debug */ | |
39 | ||
74340b0a PB |
40 | #define dprintk(level,args...) \ |
41 | do { if ((debug & level)) { printk(args); } } while (0) | |
74340b0a PB |
42 | |
43 | /* mask for enabling a specific pid for the pid_filter */ | |
44 | #define DIB3000_ACTIVATE_PID_FILTERING (0x2000) | |
45 | ||
46 | /* common values for tuning */ | |
47 | #define DIB3000_ALPHA_0 ( 0) | |
48 | #define DIB3000_ALPHA_1 ( 1) | |
49 | #define DIB3000_ALPHA_2 ( 2) | |
50 | #define DIB3000_ALPHA_4 ( 4) | |
51 | ||
52 | #define DIB3000_CONSTELLATION_QPSK ( 0) | |
53 | #define DIB3000_CONSTELLATION_16QAM ( 1) | |
54 | #define DIB3000_CONSTELLATION_64QAM ( 2) | |
55 | ||
56 | #define DIB3000_GUARD_TIME_1_32 ( 0) | |
57 | #define DIB3000_GUARD_TIME_1_16 ( 1) | |
58 | #define DIB3000_GUARD_TIME_1_8 ( 2) | |
59 | #define DIB3000_GUARD_TIME_1_4 ( 3) | |
60 | ||
61 | #define DIB3000_TRANSMISSION_MODE_2K ( 0) | |
62 | #define DIB3000_TRANSMISSION_MODE_8K ( 1) | |
63 | ||
64 | #define DIB3000_SELECT_LP ( 0) | |
65 | #define DIB3000_SELECT_HP ( 1) | |
66 | ||
67 | #define DIB3000_FEC_1_2 ( 1) | |
68 | #define DIB3000_FEC_2_3 ( 2) | |
69 | #define DIB3000_FEC_3_4 ( 3) | |
70 | #define DIB3000_FEC_5_6 ( 5) | |
71 | #define DIB3000_FEC_7_8 ( 7) | |
72 | ||
73 | #define DIB3000_HRCH_OFF ( 0) | |
74 | #define DIB3000_HRCH_ON ( 1) | |
75 | ||
76 | #define DIB3000_DDS_INVERSION_OFF ( 0) | |
77 | #define DIB3000_DDS_INVERSION_ON ( 1) | |
78 | ||
79 | #define DIB3000_TUNER_WRITE_ENABLE(a) (0xffff & (a << 8)) | |
80 | #define DIB3000_TUNER_WRITE_DISABLE(a) (0xffff & ((a << 8) | (1 << 7))) | |
81 | ||
74340b0a PB |
82 | #define DIB3000_REG_MANUFACTOR_ID ( 1025) |
83 | #define DIB3000_I2C_ID_DIBCOM (0x01b3) | |
84 | ||
85 | #define DIB3000_REG_DEVICE_ID ( 1026) | |
86 | #define DIB3000MB_DEVICE_ID (0x3000) | |
87 | #define DIB3000MC_DEVICE_ID (0x3001) | |
88 | #define DIB3000P_DEVICE_ID (0x3002) | |
89 | ||
90 | /* frontend state */ | |
91 | struct dib3000_state { | |
92 | struct i2c_adapter* i2c; | |
93 | ||
94 | /* configuration settings */ | |
95 | struct dib3000_config config; | |
96 | ||
97 | struct dvb_frontend frontend; | |
98 | int timing_offset; | |
99 | int timing_offset_comp_done; | |
100 | ||
c6f56e7d | 101 | u32 last_tuned_bw; |
74340b0a PB |
102 | u32 last_tuned_freq; |
103 | }; | |
104 | ||
1da177e4 LT |
105 | /* register addresses and some of their default values */ |
106 | ||
107 | /* restart subsystems */ | |
108 | #define DIB3000MB_REG_RESTART ( 0) | |
109 | ||
110 | #define DIB3000MB_RESTART_OFF ( 0) | |
111 | #define DIB3000MB_RESTART_AUTO_SEARCH (1 << 1) | |
112 | #define DIB3000MB_RESTART_CTRL (1 << 2) | |
113 | #define DIB3000MB_RESTART_AGC (1 << 3) | |
114 | ||
115 | /* FFT size */ | |
116 | #define DIB3000MB_REG_FFT ( 1) | |
117 | ||
118 | /* Guard time */ | |
119 | #define DIB3000MB_REG_GUARD_TIME ( 2) | |
120 | ||
121 | /* QAM */ | |
122 | #define DIB3000MB_REG_QAM ( 3) | |
123 | ||
124 | /* Alpha coefficient high priority Viterbi algorithm */ | |
125 | #define DIB3000MB_REG_VIT_ALPHA ( 4) | |
126 | ||
127 | /* spectrum inversion */ | |
128 | #define DIB3000MB_REG_DDS_INV ( 5) | |
129 | ||
130 | /* DDS frequency value (IF position) ad ? values don't match reg_3000mb.txt */ | |
131 | #define DIB3000MB_REG_DDS_FREQ_MSB ( 6) | |
132 | #define DIB3000MB_REG_DDS_FREQ_LSB ( 7) | |
133 | #define DIB3000MB_DDS_FREQ_MSB ( 178) | |
134 | #define DIB3000MB_DDS_FREQ_LSB ( 8990) | |
135 | ||
136 | /* timing frequency (carrier spacing) */ | |
137 | static u16 dib3000mb_reg_timing_freq[] = { 8,9 }; | |
138 | static u16 dib3000mb_timing_freq[][2] = { | |
139 | { 126 , 48873 }, /* 6 MHz */ | |
140 | { 147 , 57019 }, /* 7 MHz */ | |
141 | { 168 , 65164 }, /* 8 MHz */ | |
142 | }; | |
143 | ||
144 | /* impulse noise parameter */ | |
145 | /* 36 ??? */ | |
146 | ||
147 | static u16 dib3000mb_reg_impulse_noise[] = { 10,11,12,15,36 }; | |
148 | ||
149 | enum dib3000mb_impulse_noise_type { | |
150 | DIB3000MB_IMPNOISE_OFF, | |
151 | DIB3000MB_IMPNOISE_MOBILE, | |
152 | DIB3000MB_IMPNOISE_FIXED, | |
153 | DIB3000MB_IMPNOISE_DEFAULT | |
154 | }; | |
155 | ||
156 | static u16 dib3000mb_impulse_noise_values[][5] = { | |
157 | { 0x0000, 0x0004, 0x0014, 0x01ff, 0x0399 }, /* off */ | |
158 | { 0x0001, 0x0004, 0x0014, 0x01ff, 0x037b }, /* mobile */ | |
159 | { 0x0001, 0x0004, 0x0020, 0x01bd, 0x0399 }, /* fixed */ | |
160 | { 0x0000, 0x0002, 0x000a, 0x01ff, 0x0399 }, /* default */ | |
161 | }; | |
162 | ||
163 | /* | |
164 | * Dual Automatic-Gain-Control | |
165 | * - gains RF in tuner (AGC1) | |
166 | * - gains IF after filtering (AGC2) | |
167 | */ | |
168 | ||
169 | /* also from 16 to 18 */ | |
170 | static u16 dib3000mb_reg_agc_gain[] = { | |
171 | 19,20,21,22,23,24,25,26,27,28,29,30,31,32 | |
172 | }; | |
173 | ||
174 | static u16 dib3000mb_default_agc_gain[] = | |
175 | { 0x0001, 52429, 623, 128, 166, 195, 61, /* RF ??? */ | |
176 | 0x0001, 53766, 38011, 0, 90, 33, 23 }; /* IF ??? */ | |
177 | ||
178 | /* phase noise */ | |
179 | /* 36 is set when setting the impulse noise */ | |
180 | static u16 dib3000mb_reg_phase_noise[] = { 33,34,35,37,38 }; | |
181 | ||
182 | static u16 dib3000mb_default_noise_phase[] = { 2, 544, 0, 5, 4 }; | |
183 | ||
184 | /* lock duration */ | |
185 | static u16 dib3000mb_reg_lock_duration[] = { 39,40 }; | |
186 | static u16 dib3000mb_default_lock_duration[] = { 135, 135 }; | |
187 | ||
188 | /* AGC loop bandwidth */ | |
189 | static u16 dib3000mb_reg_agc_bandwidth[] = { 43,44,45,46,47,48,49,50 }; | |
190 | ||
191 | static u16 dib3000mb_agc_bandwidth_low[] = | |
192 | { 2088, 10, 2088, 10, 3448, 5, 3448, 5 }; | |
193 | static u16 dib3000mb_agc_bandwidth_high[] = | |
194 | { 2349, 5, 2349, 5, 2586, 2, 2586, 2 }; | |
195 | ||
196 | /* | |
197 | * lock0 definition (coff_lock) | |
198 | */ | |
199 | #define DIB3000MB_REG_LOCK0_MASK ( 51) | |
200 | #define DIB3000MB_LOCK0_DEFAULT ( 4) | |
201 | ||
202 | /* | |
203 | * lock1 definition (cpil_lock) | |
204 | * for auto search | |
205 | * which values hide behind the lock masks | |
206 | */ | |
207 | #define DIB3000MB_REG_LOCK1_MASK ( 52) | |
208 | #define DIB3000MB_LOCK1_SEARCH_4 (0x0004) | |
209 | #define DIB3000MB_LOCK1_SEARCH_2048 (0x0800) | |
210 | #define DIB3000MB_LOCK1_DEFAULT (0x0001) | |
211 | ||
212 | /* | |
213 | * lock2 definition (fec_lock) */ | |
214 | #define DIB3000MB_REG_LOCK2_MASK ( 53) | |
215 | #define DIB3000MB_LOCK2_DEFAULT (0x0080) | |
216 | ||
217 | /* | |
218 | * SEQ ? what was that again ... :) | |
219 | * changes when, inversion, guard time and fft is | |
220 | * either automatically detected or not | |
221 | */ | |
222 | #define DIB3000MB_REG_SEQ ( 54) | |
223 | ||
224 | /* bandwidth */ | |
225 | static u16 dib3000mb_reg_bandwidth[] = { 55,56,57,58,59,60,61,62,63,64,65,66,67 }; | |
226 | static u16 dib3000mb_bandwidth_6mhz[] = | |
227 | { 0, 33, 53312, 112, 46635, 563, 36565, 0, 1000, 0, 1010, 1, 45264 }; | |
228 | ||
229 | static u16 dib3000mb_bandwidth_7mhz[] = | |
230 | { 0, 28, 64421, 96, 39973, 483, 3255, 0, 1000, 0, 1010, 1, 45264 }; | |
231 | ||
232 | static u16 dib3000mb_bandwidth_8mhz[] = | |
233 | { 0, 25, 23600, 84, 34976, 422, 43808, 0, 1000, 0, 1010, 1, 45264 }; | |
234 | ||
235 | #define DIB3000MB_REG_UNK_68 ( 68) | |
236 | #define DIB3000MB_UNK_68 ( 0) | |
237 | ||
238 | #define DIB3000MB_REG_UNK_69 ( 69) | |
239 | #define DIB3000MB_UNK_69 ( 0) | |
240 | ||
241 | #define DIB3000MB_REG_UNK_71 ( 71) | |
242 | #define DIB3000MB_UNK_71 ( 0) | |
243 | ||
244 | #define DIB3000MB_REG_UNK_77 ( 77) | |
245 | #define DIB3000MB_UNK_77 ( 6) | |
246 | ||
247 | #define DIB3000MB_REG_UNK_78 ( 78) | |
248 | #define DIB3000MB_UNK_78 (0x0080) | |
249 | ||
250 | /* isi */ | |
251 | #define DIB3000MB_REG_ISI ( 79) | |
252 | #define DIB3000MB_ISI_ACTIVATE ( 0) | |
253 | #define DIB3000MB_ISI_INHIBIT ( 1) | |
254 | ||
255 | /* sync impovement */ | |
256 | #define DIB3000MB_REG_SYNC_IMPROVEMENT ( 84) | |
257 | #define DIB3000MB_SYNC_IMPROVE_2K_1_8 ( 3) | |
258 | #define DIB3000MB_SYNC_IMPROVE_DEFAULT ( 0) | |
259 | ||
260 | /* phase noise compensation inhibition */ | |
261 | #define DIB3000MB_REG_PHASE_NOISE ( 87) | |
262 | #define DIB3000MB_PHASE_NOISE_DEFAULT ( 0) | |
263 | ||
264 | #define DIB3000MB_REG_UNK_92 ( 92) | |
265 | #define DIB3000MB_UNK_92 (0x0080) | |
266 | ||
267 | #define DIB3000MB_REG_UNK_96 ( 96) | |
268 | #define DIB3000MB_UNK_96 (0x0010) | |
269 | ||
270 | #define DIB3000MB_REG_UNK_97 ( 97) | |
271 | #define DIB3000MB_UNK_97 (0x0009) | |
272 | ||
273 | /* mobile mode ??? */ | |
274 | #define DIB3000MB_REG_MOBILE_MODE ( 101) | |
275 | #define DIB3000MB_MOBILE_MODE_ON ( 1) | |
276 | #define DIB3000MB_MOBILE_MODE_OFF ( 0) | |
277 | ||
278 | #define DIB3000MB_REG_UNK_106 ( 106) | |
279 | #define DIB3000MB_UNK_106 (0x0080) | |
280 | ||
281 | #define DIB3000MB_REG_UNK_107 ( 107) | |
282 | #define DIB3000MB_UNK_107 (0x0080) | |
283 | ||
284 | #define DIB3000MB_REG_UNK_108 ( 108) | |
285 | #define DIB3000MB_UNK_108 (0x0080) | |
286 | ||
287 | /* fft */ | |
288 | #define DIB3000MB_REG_UNK_121 ( 121) | |
289 | #define DIB3000MB_UNK_121_2K ( 7) | |
290 | #define DIB3000MB_UNK_121_DEFAULT ( 5) | |
291 | ||
292 | #define DIB3000MB_REG_UNK_122 ( 122) | |
293 | #define DIB3000MB_UNK_122 ( 2867) | |
294 | ||
295 | /* QAM for mobile mode */ | |
296 | #define DIB3000MB_REG_MOBILE_MODE_QAM ( 126) | |
297 | #define DIB3000MB_MOBILE_MODE_QAM_64 ( 3) | |
298 | #define DIB3000MB_MOBILE_MODE_QAM_QPSK_16 ( 1) | |
299 | #define DIB3000MB_MOBILE_MODE_QAM_OFF ( 0) | |
300 | ||
301 | /* | |
302 | * data diversity when having more than one chip on-board | |
303 | * see also DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY | |
304 | */ | |
305 | #define DIB3000MB_REG_DATA_IN_DIVERSITY ( 127) | |
306 | #define DIB3000MB_DATA_DIVERSITY_IN_OFF ( 0) | |
307 | #define DIB3000MB_DATA_DIVERSITY_IN_ON ( 2) | |
308 | ||
309 | /* vit hrch */ | |
310 | #define DIB3000MB_REG_VIT_HRCH ( 128) | |
311 | ||
312 | /* vit code rate */ | |
313 | #define DIB3000MB_REG_VIT_CODE_RATE ( 129) | |
314 | ||
315 | /* vit select hp */ | |
316 | #define DIB3000MB_REG_VIT_HP ( 130) | |
317 | ||
318 | /* time frame for Bit-Error-Rate calculation */ | |
319 | #define DIB3000MB_REG_BERLEN ( 135) | |
320 | #define DIB3000MB_BERLEN_LONG ( 0) | |
321 | #define DIB3000MB_BERLEN_DEFAULT ( 1) | |
322 | #define DIB3000MB_BERLEN_MEDIUM ( 2) | |
323 | #define DIB3000MB_BERLEN_SHORT ( 3) | |
324 | ||
325 | /* 142 - 152 FIFO parameters | |
326 | * which is what ? | |
327 | */ | |
328 | ||
329 | #define DIB3000MB_REG_FIFO_142 ( 142) | |
330 | #define DIB3000MB_FIFO_142 ( 0) | |
331 | ||
332 | /* MPEG2 TS output mode */ | |
333 | #define DIB3000MB_REG_MPEG2_OUT_MODE ( 143) | |
334 | #define DIB3000MB_MPEG2_OUT_MODE_204 ( 0) | |
335 | #define DIB3000MB_MPEG2_OUT_MODE_188 ( 1) | |
336 | ||
337 | #define DIB3000MB_REG_PID_PARSE ( 144) | |
338 | #define DIB3000MB_PID_PARSE_INHIBIT ( 0) | |
339 | #define DIB3000MB_PID_PARSE_ACTIVATE ( 1) | |
340 | ||
341 | #define DIB3000MB_REG_FIFO ( 145) | |
342 | #define DIB3000MB_FIFO_INHIBIT ( 1) | |
343 | #define DIB3000MB_FIFO_ACTIVATE ( 0) | |
344 | ||
345 | #define DIB3000MB_REG_FIFO_146 ( 146) | |
346 | #define DIB3000MB_FIFO_146 ( 3) | |
347 | ||
348 | #define DIB3000MB_REG_FIFO_147 ( 147) | |
349 | #define DIB3000MB_FIFO_147 (0x0100) | |
350 | ||
351 | /* | |
352 | * pidfilter | |
353 | * it is not a hardware pidfilter but a filter which drops all pids | |
354 | * except the ones set. Necessary because of the limited USB1.1 bandwidth. | |
355 | * regs 153-168 | |
356 | */ | |
357 | ||
358 | #define DIB3000MB_REG_FIRST_PID ( 153) | |
359 | #define DIB3000MB_NUM_PIDS ( 16) | |
360 | ||
361 | /* | |
362 | * output mode | |
363 | * USB devices have to use 'slave'-mode | |
364 | * see also DIB3000MB_REG_ELECT_OUT_MODE | |
365 | */ | |
366 | #define DIB3000MB_REG_OUTPUT_MODE ( 169) | |
367 | #define DIB3000MB_OUTPUT_MODE_GATED_CLK ( 0) | |
368 | #define DIB3000MB_OUTPUT_MODE_CONT_CLK ( 1) | |
369 | #define DIB3000MB_OUTPUT_MODE_SERIAL ( 2) | |
370 | #define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY ( 5) | |
371 | #define DIB3000MB_OUTPUT_MODE_SLAVE ( 6) | |
372 | ||
373 | /* irq event mask */ | |
374 | #define DIB3000MB_REG_IRQ_EVENT_MASK ( 170) | |
375 | #define DIB3000MB_IRQ_EVENT_MASK ( 0) | |
376 | ||
377 | /* filter coefficients */ | |
378 | static u16 dib3000mb_reg_filter_coeffs[] = { | |
379 | 171, 172, 173, 174, 175, 176, 177, 178, | |
380 | 179, 180, 181, 182, 183, 184, 185, 186, | |
381 | 188, 189, 190, 191, 192, 194 | |
382 | }; | |
383 | ||
384 | static u16 dib3000mb_filter_coeffs[] = { | |
385 | 226, 160, 29, | |
776338e1 | 386 | 979, 998, 19, |
1da177e4 LT |
387 | 22, 1019, 1006, |
388 | 1022, 12, 6, | |
389 | 1017, 1017, 3, | |
390 | 6, 1019, | |
391 | 1021, 2, 3, | |
392 | 1, 0, | |
393 | }; | |
394 | ||
395 | /* | |
396 | * mobile algorithm (when you are moving with your device) | |
397 | * but not faster than 90 km/h | |
398 | */ | |
399 | #define DIB3000MB_REG_MOBILE_ALGO ( 195) | |
400 | #define DIB3000MB_MOBILE_ALGO_ON ( 0) | |
401 | #define DIB3000MB_MOBILE_ALGO_OFF ( 1) | |
402 | ||
403 | /* multiple demodulators algorithm */ | |
404 | #define DIB3000MB_REG_MULTI_DEMOD_MSB ( 206) | |
405 | #define DIB3000MB_REG_MULTI_DEMOD_LSB ( 207) | |
406 | ||
407 | /* terminator, no more demods */ | |
408 | #define DIB3000MB_MULTI_DEMOD_MSB ( 32767) | |
409 | #define DIB3000MB_MULTI_DEMOD_LSB ( 4095) | |
410 | ||
411 | /* bring the device into a known */ | |
412 | #define DIB3000MB_REG_RESET_DEVICE ( 1024) | |
413 | #define DIB3000MB_RESET_DEVICE (0x812c) | |
414 | #define DIB3000MB_RESET_DEVICE_RST ( 0) | |
415 | ||
416 | /* hardware clock configuration */ | |
417 | #define DIB3000MB_REG_CLOCK ( 1027) | |
418 | #define DIB3000MB_CLOCK_DEFAULT (0x9000) | |
419 | #define DIB3000MB_CLOCK_DIVERSITY (0x92b0) | |
420 | ||
421 | /* power down config */ | |
422 | #define DIB3000MB_REG_POWER_CONTROL ( 1028) | |
423 | #define DIB3000MB_POWER_DOWN ( 1) | |
424 | #define DIB3000MB_POWER_UP ( 0) | |
425 | ||
426 | /* electrical output mode */ | |
427 | #define DIB3000MB_REG_ELECT_OUT_MODE ( 1029) | |
428 | #define DIB3000MB_ELECT_OUT_MODE_OFF ( 0) | |
429 | #define DIB3000MB_ELECT_OUT_MODE_ON ( 1) | |
430 | ||
431 | /* set the tuner i2c address */ | |
432 | #define DIB3000MB_REG_TUNER ( 1089) | |
433 | ||
434 | /* monitoring registers (read only) */ | |
435 | ||
436 | /* agc loop locked (size: 1) */ | |
437 | #define DIB3000MB_REG_AGC_LOCK ( 324) | |
438 | ||
439 | /* agc power (size: 16) */ | |
440 | #define DIB3000MB_REG_AGC_POWER ( 325) | |
441 | ||
442 | /* agc1 value (16) */ | |
443 | #define DIB3000MB_REG_AGC1_VALUE ( 326) | |
444 | ||
445 | /* agc2 value (16) */ | |
446 | #define DIB3000MB_REG_AGC2_VALUE ( 327) | |
447 | ||
448 | /* total RF power (16), can be used for signal strength */ | |
449 | #define DIB3000MB_REG_RF_POWER ( 328) | |
450 | ||
451 | /* dds_frequency with offset (24) */ | |
452 | #define DIB3000MB_REG_DDS_VALUE_MSB ( 339) | |
453 | #define DIB3000MB_REG_DDS_VALUE_LSB ( 340) | |
454 | ||
455 | /* timing offset signed (24) */ | |
456 | #define DIB3000MB_REG_TIMING_OFFSET_MSB ( 341) | |
457 | #define DIB3000MB_REG_TIMING_OFFSET_LSB ( 342) | |
458 | ||
459 | /* fft start position (13) */ | |
460 | #define DIB3000MB_REG_FFT_WINDOW_POS ( 353) | |
461 | ||
462 | /* carriers locked (1) */ | |
463 | #define DIB3000MB_REG_CARRIER_LOCK ( 355) | |
464 | ||
465 | /* noise power (24) */ | |
466 | #define DIB3000MB_REG_NOISE_POWER_MSB ( 372) | |
467 | #define DIB3000MB_REG_NOISE_POWER_LSB ( 373) | |
468 | ||
469 | #define DIB3000MB_REG_MOBILE_NOISE_MSB ( 374) | |
470 | #define DIB3000MB_REG_MOBILE_NOISE_LSB ( 375) | |
471 | ||
472 | /* | |
473 | * signal power (16), this and the above can be | |
474 | * used to calculate the signal/noise - ratio | |
475 | */ | |
476 | #define DIB3000MB_REG_SIGNAL_POWER ( 380) | |
477 | ||
478 | /* mer (24) */ | |
479 | #define DIB3000MB_REG_MER_MSB ( 381) | |
480 | #define DIB3000MB_REG_MER_LSB ( 382) | |
481 | ||
482 | /* | |
483 | * Transmission Parameter Signalling (TPS) | |
484 | * the following registers can be used to get TPS-information. | |
485 | * The values are according to the DVB-T standard. | |
486 | */ | |
487 | ||
488 | /* TPS locked (1) */ | |
489 | #define DIB3000MB_REG_TPS_LOCK ( 394) | |
490 | ||
491 | /* QAM from TPS (2) (values according to DIB3000MB_REG_QAM) */ | |
492 | #define DIB3000MB_REG_TPS_QAM ( 398) | |
493 | ||
494 | /* hierarchy from TPS (1) */ | |
495 | #define DIB3000MB_REG_TPS_HRCH ( 399) | |
496 | ||
497 | /* alpha from TPS (3) (values according to DIB3000MB_REG_VIT_ALPHA) */ | |
498 | #define DIB3000MB_REG_TPS_VIT_ALPHA ( 400) | |
499 | ||
500 | /* code rate high priority from TPS (3) (values according to DIB3000MB_FEC_*) */ | |
501 | #define DIB3000MB_REG_TPS_CODE_RATE_HP ( 401) | |
502 | ||
503 | /* code rate low priority from TPS (3) if DIB3000MB_REG_TPS_VIT_ALPHA */ | |
504 | #define DIB3000MB_REG_TPS_CODE_RATE_LP ( 402) | |
505 | ||
506 | /* guard time from TPS (2) (values according to DIB3000MB_REG_GUARD_TIME */ | |
507 | #define DIB3000MB_REG_TPS_GUARD_TIME ( 403) | |
508 | ||
509 | /* fft size from TPS (2) (values according to DIB3000MB_REG_FFT) */ | |
510 | #define DIB3000MB_REG_TPS_FFT ( 404) | |
511 | ||
512 | /* cell id from TPS (16) */ | |
513 | #define DIB3000MB_REG_TPS_CELL_ID ( 406) | |
514 | ||
515 | /* TPS (68) */ | |
516 | #define DIB3000MB_REG_TPS_1 ( 408) | |
517 | #define DIB3000MB_REG_TPS_2 ( 409) | |
518 | #define DIB3000MB_REG_TPS_3 ( 410) | |
519 | #define DIB3000MB_REG_TPS_4 ( 411) | |
520 | #define DIB3000MB_REG_TPS_5 ( 412) | |
521 | ||
522 | /* bit error rate (before RS correction) (21) */ | |
523 | #define DIB3000MB_REG_BER_MSB ( 414) | |
524 | #define DIB3000MB_REG_BER_LSB ( 415) | |
525 | ||
526 | /* packet error rate (uncorrected TS packets) (16) */ | |
527 | #define DIB3000MB_REG_PACKET_ERROR_RATE ( 417) | |
528 | ||
529 | /* uncorrected packet count (16) */ | |
530 | #define DIB3000MB_REG_UNC ( 420) | |
531 | ||
532 | /* viterbi locked (1) */ | |
533 | #define DIB3000MB_REG_VIT_LCK ( 421) | |
534 | ||
535 | /* viterbi inidcator (16) */ | |
536 | #define DIB3000MB_REG_VIT_INDICATOR ( 422) | |
537 | ||
538 | /* transport stream sync lock (1) */ | |
539 | #define DIB3000MB_REG_TS_SYNC_LOCK ( 423) | |
540 | ||
541 | /* transport stream RS lock (1) */ | |
542 | #define DIB3000MB_REG_TS_RS_LOCK ( 424) | |
543 | ||
544 | /* lock mask 0 value (1) */ | |
545 | #define DIB3000MB_REG_LOCK0_VALUE ( 425) | |
546 | ||
547 | /* lock mask 1 value (1) */ | |
548 | #define DIB3000MB_REG_LOCK1_VALUE ( 426) | |
549 | ||
550 | /* lock mask 2 value (1) */ | |
551 | #define DIB3000MB_REG_LOCK2_VALUE ( 427) | |
552 | ||
553 | /* interrupt pending for auto search */ | |
554 | #define DIB3000MB_REG_AS_IRQ_PENDING ( 434) | |
555 | ||
556 | #endif |