[media] drx-j: Don't use CamelCase
[deliverable/linux.git] / drivers / media / dvb-frontends / drx39xyj / drx39xxj_dummy.c
CommitLineData
38b2df95
DH
1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/module.h>
4#include <linux/string.h>
5#include <linux/slab.h>
6#include <linux/delay.h>
7#include <linux/jiffies.h>
8#include <linux/types.h>
9
10#include "drx_driver.h"
38b2df95
DH
11#include "drx39xxj.h"
12
13/* Dummy function to satisfy drxj.c */
57afe2f0 14int drxbsp_tuner_open(struct tuner_instance *tuner)
38b2df95
DH
15{
16 return DRX_STS_OK;
17}
18
57afe2f0 19int drxbsp_tuner_close(struct tuner_instance *tuner)
38b2df95
DH
20{
21 return DRX_STS_OK;
22}
23
57afe2f0 24int drxbsp_tuner_set_frequency(struct tuner_instance *tuner,
61263c75 25 u32 mode,
57afe2f0 26 s32 center_frequency)
38b2df95
DH
27{
28 return DRX_STS_OK;
29}
30
61263c75 31int
57afe2f0 32drxbsp_tuner_get_frequency(struct tuner_instance *tuner,
61263c75 33 u32 mode,
57afe2f0
MCC
34 s32 *r_ffrequency,
35 s32 *i_ffrequency)
38b2df95
DH
36{
37 return DRX_STS_OK;
38}
39
57afe2f0 40int drxbsp_hst_sleep(u32 n)
38b2df95
DH
41{
42 msleep(n);
43 return DRX_STS_OK;
44}
45
57afe2f0 46u32 drxbsp_hst_clock(void)
38b2df95
DH
47{
48 return jiffies_to_msecs(jiffies);
49}
50
57afe2f0 51int drxbsp_hst_memcmp(void *s1, void *s2, u32 n)
38b2df95 52{
443f18d0 53 return (memcmp(s1, s2, (size_t) n));
38b2df95
DH
54}
55
57afe2f0 56void *drxbsp_hst_memcpy(void *to, void *from, u32 n)
38b2df95 57{
443f18d0 58 return (memcpy(to, from, (size_t) n));
38b2df95
DH
59}
60
57afe2f0
MCC
61int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
62 u16 w_count,
43a431e4 63 u8 *wData,
57afe2f0
MCC
64 struct i2c_device_addr *r_dev_addr,
65 u16 r_count, u8 *r_data)
38b2df95
DH
66{
67 struct drx39xxj_state *state;
68 struct i2c_msg msg[2];
69 unsigned int num_msgs;
70
57afe2f0 71 if (w_dev_addr == NULL) {
38b2df95 72 /* Read only */
57afe2f0
MCC
73 state = r_dev_addr->user_data;
74 msg[0].addr = r_dev_addr->i2c_addr >> 1;
38b2df95 75 msg[0].flags = I2C_M_RD;
57afe2f0
MCC
76 msg[0].buf = r_data;
77 msg[0].len = r_count;
38b2df95 78 num_msgs = 1;
57afe2f0 79 } else if (r_dev_addr == NULL) {
38b2df95 80 /* Write only */
57afe2f0
MCC
81 state = w_dev_addr->user_data;
82 msg[0].addr = w_dev_addr->i2c_addr >> 1;
38b2df95
DH
83 msg[0].flags = 0;
84 msg[0].buf = wData;
57afe2f0 85 msg[0].len = w_count;
38b2df95
DH
86 num_msgs = 1;
87 } else {
88 /* Both write and read */
57afe2f0
MCC
89 state = w_dev_addr->user_data;
90 msg[0].addr = w_dev_addr->i2c_addr >> 1;
38b2df95
DH
91 msg[0].flags = 0;
92 msg[0].buf = wData;
57afe2f0
MCC
93 msg[0].len = w_count;
94 msg[1].addr = r_dev_addr->i2c_addr >> 1;
38b2df95 95 msg[1].flags = I2C_M_RD;
57afe2f0
MCC
96 msg[1].buf = r_data;
97 msg[1].len = r_count;
38b2df95
DH
98 num_msgs = 2;
99 }
100
101 if (state->i2c == NULL) {
443f18d0
MCC
102 printk("i2c was zero, aborting\n");
103 return 0;
38b2df95
DH
104 }
105 if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
106 printk(KERN_WARNING "drx3933: I2C write/read failed\n");
107 return -EREMOTEIO;
108 }
109
110 return DRX_STS_OK;
111
112#ifdef DJH_DEBUG
57afe2f0 113 struct drx39xxj_state *state = w_dev_addr->user_data;
38b2df95
DH
114
115 struct i2c_msg msg[2] = {
57afe2f0
MCC
116 {.addr = w_dev_addr->i2c_addr,
117 .flags = 0, .buf = wData, .len = w_count},
118 {.addr = r_dev_addr->i2c_addr,
119 .flags = I2C_M_RD, .buf = r_data, .len = r_count},
38b2df95
DH
120 };
121
122 printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
57afe2f0 123 w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
38b2df95
DH
124
125 if (i2c_transfer(state->i2c, msg, 2) != 2) {
126 printk(KERN_WARNING "drx3933: I2C write/read failed\n");
127 return -EREMOTEIO;
128 }
129#endif
130 return 0;
131}
This page took 0.034392 seconds and 5 git commands to generate.