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ca3355a9 DH |
1 | /* |
2 | Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. | |
3 | All rights reserved. | |
4 | ||
5 | Redistribution and use in source and binary forms, with or without | |
6 | modification, are permitted provided that the following conditions are met: | |
7 | ||
8 | * Redistributions of source code must retain the above copyright notice, | |
9 | this list of conditions and the following disclaimer. | |
10 | * Redistributions in binary form must reproduce the above copyright notice, | |
11 | this list of conditions and the following disclaimer in the documentation | |
12 | and/or other materials provided with the distribution. | |
13 | * Neither the name of Trident Microsystems nor Hauppauge Computer Works | |
14 | nor the names of its contributors may be used to endorse or promote | |
15 | products derived from this software without specific prior written | |
16 | permission. | |
17 | ||
18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
19 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
20 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
21 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE | |
22 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
23 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
24 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
25 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
26 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
27 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
28 | POSSIBILITY OF SUCH DAMAGE. | |
29 | */ | |
30 | ||
38b2df95 DH |
31 | #ifndef __DRXDRIVER_H__ |
32 | #define __DRXDRIVER_H__ | |
6c1d56c5 MCC |
33 | |
34 | #include <linux/kernel.h> | |
9482354f | 35 | #include <linux/errno.h> |
b48293db MCC |
36 | #include <linux/firmware.h> |
37 | #include <linux/i2c.h> | |
6c1d56c5 MCC |
38 | |
39 | /* | |
57afe2f0 MCC |
40 | * This structure contains the I2C address, the device ID and a user_data pointer. |
41 | * The user_data pointer can be used for application specific purposes. | |
6c1d56c5 MCC |
42 | */ |
43 | struct i2c_device_addr { | |
57afe2f0 MCC |
44 | u16 i2c_addr; /* The I2C address of the device. */ |
45 | u16 i2c_dev_id; /* The device identifier. */ | |
46 | void *user_data; /* User data pointer */ | |
6c1d56c5 MCC |
47 | }; |
48 | ||
49 | /** | |
50 | * \def IS_I2C_10BIT( addr ) | |
51 | * \brief Determine if I2C address 'addr' is a 10 bits address or not. | |
52 | * \param addr The I2C address. | |
53 | * \return int. | |
54 | * \retval 0 if address is not a 10 bits I2C address. | |
55 | * \retval 1 if address is a 10 bits I2C address. | |
56 | */ | |
57 | #define IS_I2C_10BIT(addr) \ | |
58 | (((addr) & 0xF8) == 0xF0) | |
59 | ||
60 | /*------------------------------------------------------------------------------ | |
61 | Exported FUNCTIONS | |
62 | ------------------------------------------------------------------------------*/ | |
63 | ||
64 | /** | |
57afe2f0 | 65 | * \fn drxbsp_i2c_init() |
6c1d56c5 | 66 | * \brief Initialize I2C communication module. |
61263c75 | 67 | * \return int Return status. |
9482354f MCC |
68 | * \retval 0 Initialization successful. |
69 | * \retval -EIO Initialization failed. | |
6c1d56c5 | 70 | */ |
57afe2f0 | 71 | int drxbsp_i2c_init(void); |
6c1d56c5 MCC |
72 | |
73 | /** | |
57afe2f0 | 74 | * \fn drxbsp_i2c_term() |
6c1d56c5 | 75 | * \brief Terminate I2C communication module. |
61263c75 | 76 | * \return int Return status. |
9482354f MCC |
77 | * \retval 0 Termination successful. |
78 | * \retval -EIO Termination failed. | |
6c1d56c5 | 79 | */ |
57afe2f0 | 80 | int drxbsp_i2c_term(void); |
6c1d56c5 MCC |
81 | |
82 | /** | |
57afe2f0 MCC |
83 | * \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, |
84 | * u16 w_count, | |
6c1d56c5 | 85 | * u8 * wData, |
57afe2f0 MCC |
86 | * struct i2c_device_addr *r_dev_addr, |
87 | * u16 r_count, | |
88 | * u8 * r_data) | |
6c1d56c5 | 89 | * \brief Read and/or write count bytes from I2C bus, store them in data[]. |
57afe2f0 MCC |
90 | * \param w_dev_addr The device i2c address and the device ID to write to |
91 | * \param w_count The number of bytes to write | |
6c1d56c5 | 92 | * \param wData The array to write the data to |
57afe2f0 MCC |
93 | * \param r_dev_addr The device i2c address and the device ID to read from |
94 | * \param r_count The number of bytes to read | |
95 | * \param r_data The array to read the data from | |
61263c75 | 96 | * \return int Return status. |
9482354f MCC |
97 | * \retval 0 Succes. |
98 | * \retval -EIO Failure. | |
99 | * \retval -EINVAL Parameter 'wcount' is not zero but parameter | |
6c1d56c5 MCC |
100 | * 'wdata' contains NULL. |
101 | * Idem for 'rcount' and 'rdata'. | |
57afe2f0 | 102 | * Both w_dev_addr and r_dev_addr are NULL. |
6c1d56c5 MCC |
103 | * |
104 | * This function must implement an atomic write and/or read action on the I2C bus | |
105 | * No other process may use the I2C bus when this function is executing. | |
106 | * The critical section of this function runs from and including the I2C | |
107 | * write, up to and including the I2C read action. | |
108 | * | |
109 | * The device ID can be useful if several devices share an I2C address. | |
110 | * It can be used to control a "switch" on the I2C bus to the correct device. | |
111 | */ | |
57afe2f0 MCC |
112 | int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, |
113 | u16 w_count, | |
7ef66759 | 114 | u8 *wData, |
57afe2f0 MCC |
115 | struct i2c_device_addr *r_dev_addr, |
116 | u16 r_count, u8 *r_data); | |
6c1d56c5 MCC |
117 | |
118 | /** | |
57afe2f0 | 119 | * \fn drxbsp_i2c_error_text() |
6c1d56c5 | 120 | * \brief Returns a human readable error. |
57afe2f0 | 121 | * Counter part of numerical drx_i2c_error_g. |
6c1d56c5 MCC |
122 | * |
123 | * \return char* Pointer to human readable error text. | |
124 | */ | |
57afe2f0 | 125 | char *drxbsp_i2c_error_text(void); |
6c1d56c5 MCC |
126 | |
127 | /** | |
57afe2f0 | 128 | * \var drx_i2c_error_g; |
6c1d56c5 MCC |
129 | * \brief I2C specific error codes, platform dependent. |
130 | */ | |
57afe2f0 | 131 | extern int drx_i2c_error_g; |
6c1d56c5 MCC |
132 | |
133 | #define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ | |
134 | #define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ | |
135 | #define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ | |
136 | #define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ | |
137 | #define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ | |
138 | #define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ | |
139 | #define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ | |
140 | #define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ | |
141 | ||
142 | #define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ | |
143 | #define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ | |
144 | #define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ | |
145 | #define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ | |
146 | #define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ | |
147 | #define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ | |
148 | #define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ | |
149 | ||
150 | #define TUNER_MODE_SUB_MAX 8 | |
7ef66759 | 151 | #define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ |
6c1d56c5 MCC |
152 | TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ |
153 | TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ | |
7ef66759 | 154 | TUNER_MODE_SUB6 | TUNER_MODE_SUB7) |
6c1d56c5 | 155 | |
6c1d56c5 | 156 | |
61263c75 | 157 | enum tuner_lock_status { |
6c1d56c5 MCC |
158 | TUNER_LOCKED, |
159 | TUNER_NOT_LOCKED | |
61263c75 | 160 | }; |
6c1d56c5 | 161 | |
61263c75 | 162 | struct tuner_common { |
6c1d56c5 | 163 | char *name; /* Tuner brand & type name */ |
57afe2f0 MCC |
164 | s32 min_freq_rf; /* Lowest RF input frequency, in kHz */ |
165 | s32 max_freq_rf; /* Highest RF input frequency, in kHz */ | |
6c1d56c5 | 166 | |
57afe2f0 | 167 | u8 sub_mode; /* Index to sub-mode in use */ |
e33f2193 | 168 | char ***sub_mode_descriptions; /* Pointer to description of sub-modes */ |
57afe2f0 | 169 | u8 sub_modes; /* Number of available sub-modes */ |
6c1d56c5 MCC |
170 | |
171 | /* The following fields will be either 0, NULL or false and do not need | |
172 | initialisation */ | |
57afe2f0 MCC |
173 | void *self_check; /* gives proof of initialization */ |
174 | bool programmed; /* only valid if self_check is OK */ | |
175 | s32 r_ffrequency; /* only valid if programmed */ | |
176 | s32 i_ffrequency; /* only valid if programmed */ | |
6c1d56c5 | 177 | |
e33f2193 | 178 | void *my_user_data; /* pointer to associated demod instance */ |
57afe2f0 | 179 | u16 my_capabilities; /* value for storing application flags */ |
61263c75 | 180 | }; |
6c1d56c5 | 181 | |
61263c75 | 182 | struct tuner_instance; |
6c1d56c5 | 183 | |
57afe2f0 MCC |
184 | typedef int(*tuner_open_func_t) (struct tuner_instance *tuner); |
185 | typedef int(*tuner_close_func_t) (struct tuner_instance *tuner); | |
6c1d56c5 | 186 | |
57afe2f0 | 187 | typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner, |
61263c75 | 188 | u32 mode, |
6c1d56c5 MCC |
189 | s32 |
190 | frequency); | |
191 | ||
57afe2f0 | 192 | typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner, |
61263c75 | 193 | u32 mode, |
6c1d56c5 | 194 | s32 * |
57afe2f0 | 195 | r_ffrequency, |
6c1d56c5 | 196 | s32 * |
57afe2f0 | 197 | i_ffrequency); |
6c1d56c5 | 198 | |
57afe2f0 | 199 | typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner, |
61263c75 | 200 | enum tuner_lock_status * |
57afe2f0 | 201 | lock_stat); |
6c1d56c5 | 202 | |
57afe2f0 | 203 | typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner, |
6c1d56c5 | 204 | struct i2c_device_addr * |
57afe2f0 | 205 | w_dev_addr, u16 w_count, |
7ef66759 | 206 | u8 *wData, |
6c1d56c5 | 207 | struct i2c_device_addr * |
57afe2f0 MCC |
208 | r_dev_addr, u16 r_count, |
209 | u8 *r_data); | |
6c1d56c5 | 210 | |
61263c75 | 211 | struct tuner_ops { |
57afe2f0 MCC |
212 | tuner_open_func_t open_func; |
213 | tuner_close_func_t close_func; | |
214 | tuner_set_frequency_func_t set_frequency_func; | |
215 | tuner_get_frequency_func_t get_frequency_func; | |
e33f2193 | 216 | tuner_lock_status_func_t lock_status_func; |
57afe2f0 | 217 | tune_ri2c_write_read_func_t i2c_write_read_func; |
6c1d56c5 | 218 | |
61263c75 | 219 | }; |
6c1d56c5 | 220 | |
61263c75 | 221 | struct tuner_instance { |
57afe2f0 MCC |
222 | struct i2c_device_addr my_i2c_dev_addr; |
223 | struct tuner_common *my_common_attr; | |
224 | void *my_ext_attr; | |
225 | struct tuner_ops *my_funct; | |
61263c75 | 226 | }; |
6c1d56c5 | 227 | |
57afe2f0 | 228 | int drxbsp_tuner_open(struct tuner_instance *tuner); |
6c1d56c5 | 229 | |
57afe2f0 | 230 | int drxbsp_tuner_close(struct tuner_instance *tuner); |
6c1d56c5 | 231 | |
57afe2f0 | 232 | int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, |
61263c75 | 233 | u32 mode, |
6c1d56c5 MCC |
234 | s32 frequency); |
235 | ||
57afe2f0 | 236 | int drxbsp_tuner_get_frequency(struct tuner_instance *tuner, |
61263c75 | 237 | u32 mode, |
57afe2f0 MCC |
238 | s32 *r_ffrequency, |
239 | s32 *i_ffrequency); | |
6c1d56c5 | 240 | |
57afe2f0 MCC |
241 | int drxbsp_tuner_lock_status(struct tuner_instance *tuner, |
242 | enum tuner_lock_status *lock_stat); | |
6c1d56c5 | 243 | |
57afe2f0 MCC |
244 | int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, |
245 | struct i2c_device_addr *w_dev_addr, | |
246 | u16 w_count, | |
7ef66759 | 247 | u8 *wData, |
57afe2f0 MCC |
248 | struct i2c_device_addr *r_dev_addr, |
249 | u16 r_count, u8 *r_data); | |
6c1d56c5 | 250 | |
57afe2f0 | 251 | int drxbsp_hst_init(void); |
6c1d56c5 | 252 | |
57afe2f0 | 253 | int drxbsp_hst_term(void); |
6c1d56c5 | 254 | |
57afe2f0 | 255 | void *drxbsp_hst_memcpy(void *to, void *from, u32 n); |
6c1d56c5 | 256 | |
57afe2f0 | 257 | int drxbsp_hst_memcmp(void *s1, void *s2, u32 n); |
6c1d56c5 | 258 | |
57afe2f0 | 259 | u32 drxbsp_hst_clock(void); |
6c1d56c5 | 260 | |
57afe2f0 | 261 | int drxbsp_hst_sleep(u32 n); |
6c1d56c5 | 262 | |
38b2df95 | 263 | |
38b2df95 DH |
264 | |
265 | /************** | |
266 | * | |
267 | * This section configures the DRX Data Access Protocols (DAPs). | |
268 | * | |
269 | **************/ | |
270 | ||
271 | /** | |
272 | * \def DRXDAP_SINGLE_MASTER | |
273 | * \brief Enable I2C single or I2C multimaster mode on host. | |
274 | * | |
275 | * Set to 1 to enable single master mode | |
276 | * Set to 0 to enable multi master mode | |
277 | * | |
278 | * The actual DAP implementation may be restricted to only one of the modes. | |
279 | * A compiler warning or error will be generated if the DAP implementation | |
280 | * overides or cannot handle the mode defined below. | |
281 | * | |
282 | */ | |
283 | #ifndef DRXDAP_SINGLE_MASTER | |
284 | #define DRXDAP_SINGLE_MASTER 0 | |
285 | #endif | |
286 | ||
287 | /** | |
288 | * \def DRXDAP_MAX_WCHUNKSIZE | |
289 | * \brief Defines maximum chunksize of an i2c write action by host. | |
290 | * | |
291 | * This indicates the maximum size of data the I2C device driver is able to | |
292 | * write at a time. This includes I2C device address and register addressing. | |
293 | * | |
294 | * This maximum size may be restricted by the actual DAP implementation. | |
295 | * A compiler warning or error will be generated if the DAP implementation | |
296 | * overides or cannot handle the chunksize defined below. | |
297 | * | |
298 | * Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data | |
299 | * buffer. Do not undefine or choose too large, unless your system is able to | |
300 | * handle a stack buffer of that size. | |
301 | * | |
302 | */ | |
303 | #ifndef DRXDAP_MAX_WCHUNKSIZE | |
304 | #define DRXDAP_MAX_WCHUNKSIZE 60 | |
305 | #endif | |
306 | ||
307 | /** | |
308 | * \def DRXDAP_MAX_RCHUNKSIZE | |
309 | * \brief Defines maximum chunksize of an i2c read action by host. | |
310 | * | |
311 | * This indicates the maximum size of data the I2C device driver is able to read | |
312 | * at a time. Minimum value is 2. Also, the read chunk size must be even. | |
313 | * | |
314 | * This maximum size may be restricted by the actual DAP implementation. | |
315 | * A compiler warning or error will be generated if the DAP implementation | |
316 | * overides or cannot handle the chunksize defined below. | |
317 | * | |
318 | */ | |
319 | #ifndef DRXDAP_MAX_RCHUNKSIZE | |
320 | #define DRXDAP_MAX_RCHUNKSIZE 60 | |
321 | #endif | |
322 | ||
323 | /************** | |
324 | * | |
325 | * This section describes drxdriver defines. | |
326 | * | |
327 | **************/ | |
328 | ||
329 | /** | |
330 | * \def DRX_UNKNOWN | |
331 | * \brief Generic UNKNOWN value for DRX enumerated types. | |
332 | * | |
333 | * Used to indicate that the parameter value is unknown or not yet initalized. | |
334 | */ | |
335 | #ifndef DRX_UNKNOWN | |
336 | #define DRX_UNKNOWN (254) | |
337 | #endif | |
338 | ||
339 | /** | |
340 | * \def DRX_AUTO | |
341 | * \brief Generic AUTO value for DRX enumerated types. | |
342 | * | |
343 | * Used to instruct the driver to automatically determine the value of the | |
344 | * parameter. | |
345 | */ | |
346 | #ifndef DRX_AUTO | |
347 | #define DRX_AUTO (255) | |
348 | #endif | |
349 | ||
38b2df95 DH |
350 | /************** |
351 | * | |
352 | * This section describes flag definitions for the device capbilities. | |
353 | * | |
354 | **************/ | |
355 | ||
356 | /** | |
357 | * \brief LNA capability flag | |
358 | * | |
359 | * Device has a Low Noise Amplifier | |
360 | * | |
361 | */ | |
362 | #define DRX_CAPABILITY_HAS_LNA (1UL << 0) | |
363 | /** | |
364 | * \brief OOB-RX capability flag | |
365 | * | |
366 | * Device has OOB-RX | |
367 | * | |
368 | */ | |
369 | #define DRX_CAPABILITY_HAS_OOBRX (1UL << 1) | |
370 | /** | |
371 | * \brief ATV capability flag | |
372 | * | |
373 | * Device has ATV | |
374 | * | |
375 | */ | |
376 | #define DRX_CAPABILITY_HAS_ATV (1UL << 2) | |
377 | /** | |
378 | * \brief DVB-T capability flag | |
379 | * | |
380 | * Device has DVB-T | |
381 | * | |
382 | */ | |
383 | #define DRX_CAPABILITY_HAS_DVBT (1UL << 3) | |
384 | /** | |
385 | * \brief ITU-B capability flag | |
386 | * | |
387 | * Device has ITU-B | |
388 | * | |
389 | */ | |
390 | #define DRX_CAPABILITY_HAS_ITUB (1UL << 4) | |
391 | /** | |
392 | * \brief Audio capability flag | |
393 | * | |
394 | * Device has Audio | |
395 | * | |
396 | */ | |
397 | #define DRX_CAPABILITY_HAS_AUD (1UL << 5) | |
398 | /** | |
399 | * \brief SAW switch capability flag | |
400 | * | |
401 | * Device has SAW switch | |
402 | * | |
403 | */ | |
404 | #define DRX_CAPABILITY_HAS_SAWSW (1UL << 6) | |
405 | /** | |
406 | * \brief GPIO1 capability flag | |
407 | * | |
408 | * Device has GPIO1 | |
409 | * | |
410 | */ | |
411 | #define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7) | |
412 | /** | |
413 | * \brief GPIO2 capability flag | |
414 | * | |
415 | * Device has GPIO2 | |
416 | * | |
417 | */ | |
418 | #define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8) | |
419 | /** | |
420 | * \brief IRQN capability flag | |
421 | * | |
422 | * Device has IRQN | |
423 | * | |
424 | */ | |
425 | #define DRX_CAPABILITY_HAS_IRQN (1UL << 9) | |
426 | /** | |
427 | * \brief 8VSB capability flag | |
428 | * | |
429 | * Device has 8VSB | |
430 | * | |
431 | */ | |
432 | #define DRX_CAPABILITY_HAS_8VSB (1UL << 10) | |
433 | /** | |
434 | * \brief SMA-TX capability flag | |
435 | * | |
436 | * Device has SMATX | |
437 | * | |
438 | */ | |
439 | #define DRX_CAPABILITY_HAS_SMATX (1UL << 11) | |
440 | /** | |
441 | * \brief SMA-RX capability flag | |
442 | * | |
443 | * Device has SMARX | |
444 | * | |
445 | */ | |
446 | #define DRX_CAPABILITY_HAS_SMARX (1UL << 12) | |
447 | /** | |
448 | * \brief ITU-A/C capability flag | |
449 | * | |
450 | * Device has ITU-A/C | |
451 | * | |
452 | */ | |
453 | #define DRX_CAPABILITY_HAS_ITUAC (1UL << 13) | |
454 | ||
455 | /*------------------------------------------------------------------------- | |
456 | MACROS | |
457 | -------------------------------------------------------------------------*/ | |
458 | /* Macros to stringify the version number */ | |
7ef66759 | 459 | #define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \ |
38b2df95 DH |
460 | DRX_VERSIONSTRING_HELP(MAJOR)"." \ |
461 | DRX_VERSIONSTRING_HELP(MINOR)"." \ | |
462 | DRX_VERSIONSTRING_HELP(PATCH) | |
7ef66759 | 463 | #define DRX_VERSIONSTRING_HELP(NUM) #NUM |
38b2df95 DH |
464 | |
465 | /** | |
466 | * \brief Macro to create byte array elements from 16 bit integers. | |
467 | * This macro is used to create byte arrays for block writes. | |
468 | * Block writes speed up I2C traffic between host and demod. | |
469 | * The macro takes care of the required byte order in a 16 bits word. | |
470 | * x->lowbyte(x), highbyte(x) | |
471 | */ | |
7ef66759 | 472 | #define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ |
43a431e4 | 473 | ((u8)((((u16)x)>>8)&0xFF)) |
38b2df95 DH |
474 | |
475 | /** | |
476 | * \brief Macro to sign extend signed 9 bit value to signed 16 bit value | |
477 | */ | |
22892268 | 478 | #define DRX_S9TOS16(x) ((((u16)x)&0x100) ? ((s16)((u16)(x)|0xFF00)) : (x)) |
38b2df95 DH |
479 | |
480 | /** | |
481 | * \brief Macro to sign extend signed 9 bit value to signed 16 bit value | |
482 | */ | |
1bfc9e15 | 483 | #define DRX_S24TODRXFREQ(x) ((((u32) x) & 0x00800000UL) ? \ |
7ef66759 | 484 | ((s32) \ |
1bfc9e15 | 485 | (((u32) x) | 0xFF000000)) : \ |
22892268 | 486 | ((s32) x)) |
38b2df95 DH |
487 | |
488 | /** | |
73f7065b | 489 | * \brief Macro to convert 16 bit register value to a s32 |
38b2df95 | 490 | */ |
22892268 | 491 | #define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \ |
7ef66759 | 492 | ((s32) \ |
1bfc9e15 | 493 | (((u32) x) | 0xFFFF0000)) : \ |
22892268 | 494 | ((s32) x)) |
38b2df95 DH |
495 | |
496 | /*------------------------------------------------------------------------- | |
497 | ENUM | |
498 | -------------------------------------------------------------------------*/ | |
499 | ||
500 | /** | |
61263c75 | 501 | * \enum enum drx_standard |
38b2df95 DH |
502 | * \brief Modulation standards. |
503 | */ | |
61263c75 MCC |
504 | enum drx_standard { |
505 | DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ | |
506 | DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ | |
507 | DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ | |
508 | DRX_STANDARD_PAL_SECAM_BG, | |
509 | /**< Terrestrial analog PAL/SECAM B/G */ | |
510 | DRX_STANDARD_PAL_SECAM_DK, | |
511 | /**< Terrestrial analog PAL/SECAM D/K */ | |
512 | DRX_STANDARD_PAL_SECAM_I, | |
513 | /**< Terrestrial analog PAL/SECAM I */ | |
514 | DRX_STANDARD_PAL_SECAM_L, | |
515 | /**< Terrestrial analog PAL/SECAM L | |
516 | with negative modulation */ | |
517 | DRX_STANDARD_PAL_SECAM_LP, | |
518 | /**< Terrestrial analog PAL/SECAM L | |
519 | with positive modulation */ | |
520 | DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ | |
521 | DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ | |
522 | DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ | |
523 | DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ | |
524 | DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ | |
525 | DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ | |
526 | DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, | |
527 | /**< Standard unknown. */ | |
528 | DRX_STANDARD_AUTO = DRX_AUTO | |
529 | /**< Autodetect standard. */ | |
530 | }; | |
531 | ||
532 | /** | |
533 | * \enum enum drx_standard | |
38b2df95 DH |
534 | * \brief Modulation sub-standards. |
535 | */ | |
61263c75 MCC |
536 | enum drx_substandard { |
537 | DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ | |
538 | DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, | |
539 | DRX_SUBSTANDARD_ATV_DK_POLAND, | |
540 | DRX_SUBSTANDARD_ATV_DK_CHINA, | |
541 | DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, | |
542 | /**< Sub-standard unknown. */ | |
543 | DRX_SUBSTANDARD_AUTO = DRX_AUTO | |
544 | /**< Auto (default) sub-standard */ | |
545 | }; | |
546 | ||
547 | /** | |
548 | * \enum enum drx_bandwidth | |
38b2df95 DH |
549 | * \brief Channel bandwidth or channel spacing. |
550 | */ | |
61263c75 MCC |
551 | enum drx_bandwidth { |
552 | DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ | |
553 | DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ | |
554 | DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ | |
555 | DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, | |
556 | /**< Bandwidth unknown. */ | |
557 | DRX_BANDWIDTH_AUTO = DRX_AUTO | |
558 | /**< Auto Set Bandwidth */ | |
559 | }; | |
38b2df95 DH |
560 | |
561 | /** | |
61263c75 | 562 | * \enum enum drx_mirror |
38b2df95 DH |
563 | * \brief Indicate if channel spectrum is mirrored or not. |
564 | */ | |
7ef66759 | 565 | enum drx_mirror { |
61263c75 MCC |
566 | DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ |
567 | DRX_MIRROR_YES, /**< Spectrum is mirrored. */ | |
568 | DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, | |
569 | /**< Unknown if spectrum is mirrored. */ | |
570 | DRX_MIRROR_AUTO = DRX_AUTO | |
571 | /**< Autodetect if spectrum is mirrored. */ | |
572 | }; | |
38b2df95 DH |
573 | |
574 | /** | |
61263c75 | 575 | * \enum enum drx_modulation |
38b2df95 DH |
576 | * \brief Constellation type of the channel. |
577 | */ | |
61263c75 MCC |
578 | enum drx_modulation { |
579 | DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ | |
580 | DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ | |
581 | DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ | |
582 | DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ | |
583 | DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ | |
584 | DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ | |
585 | DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ | |
586 | DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ | |
587 | DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ | |
588 | DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ | |
589 | DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ | |
590 | DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, | |
591 | /**< Constellation unknown. */ | |
592 | DRX_CONSTELLATION_AUTO = DRX_AUTO | |
593 | /**< Autodetect constellation. */ | |
594 | }; | |
595 | ||
596 | /** | |
597 | * \enum enum drx_hierarchy | |
38b2df95 DH |
598 | * \brief Hierarchy of the channel. |
599 | */ | |
61263c75 MCC |
600 | enum drx_hierarchy { |
601 | DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ | |
602 | DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ | |
603 | DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ | |
604 | DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ | |
605 | DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, | |
606 | /**< Hierarchy unknown. */ | |
607 | DRX_HIERARCHY_AUTO = DRX_AUTO | |
608 | /**< Autodetect hierarchy. */ | |
609 | }; | |
610 | ||
611 | /** | |
612 | * \enum enum drx_priority | |
38b2df95 DH |
613 | * \brief Channel priority in case of hierarchical transmission. |
614 | */ | |
61263c75 MCC |
615 | enum drx_priority { |
616 | DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ | |
617 | DRX_PRIORITY_HIGH, /**< High priority channel. */ | |
618 | DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN | |
619 | /**< Priority unknown. */ | |
620 | }; | |
38b2df95 DH |
621 | |
622 | /** | |
61263c75 | 623 | * \enum enum drx_coderate |
38b2df95 DH |
624 | * \brief Channel priority in case of hierarchical transmission. |
625 | */ | |
7ef66759 | 626 | enum drx_coderate { |
443f18d0 MCC |
627 | DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ |
628 | DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ | |
629 | DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ | |
630 | DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */ | |
631 | DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */ | |
632 | DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, | |
633 | /**< Code rate unknown. */ | |
634 | DRX_CODERATE_AUTO = DRX_AUTO | |
635 | /**< Autodetect code rate. */ | |
61263c75 | 636 | }; |
38b2df95 DH |
637 | |
638 | /** | |
61263c75 | 639 | * \enum enum drx_guard |
38b2df95 DH |
640 | * \brief Guard interval of a channel. |
641 | */ | |
61263c75 MCC |
642 | enum drx_guard { |
643 | DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ | |
644 | DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ | |
645 | DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ | |
646 | DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ | |
647 | DRX_GUARD_UNKNOWN = DRX_UNKNOWN, | |
648 | /**< Guard interval unknown. */ | |
649 | DRX_GUARD_AUTO = DRX_AUTO | |
650 | /**< Autodetect guard interval. */ | |
651 | }; | |
652 | ||
653 | /** | |
654 | * \enum enum drx_fft_mode | |
38b2df95 DH |
655 | * \brief FFT mode. |
656 | */ | |
61263c75 MCC |
657 | enum drx_fft_mode { |
658 | DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ | |
659 | DRX_FFTMODE_4K, /**< 4K FFT mode. */ | |
660 | DRX_FFTMODE_8K, /**< 8K FFT mode. */ | |
661 | DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, | |
662 | /**< FFT mode unknown. */ | |
663 | DRX_FFTMODE_AUTO = DRX_AUTO | |
664 | /**< Autodetect FFT mode. */ | |
665 | }; | |
38b2df95 DH |
666 | |
667 | /** | |
61263c75 | 668 | * \enum enum drx_classification |
38b2df95 DH |
669 | * \brief Channel classification. |
670 | */ | |
61263c75 MCC |
671 | enum drx_classification { |
672 | DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ | |
673 | DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ | |
674 | DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ | |
675 | DRX_CLASSIFICATION_STATIC, /**< Static echo. */ | |
676 | DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ | |
677 | DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ | |
678 | DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, | |
679 | /**< Unknown classification */ | |
680 | DRX_CLASSIFICATION_AUTO = DRX_AUTO | |
681 | /**< Autodetect classification. */ | |
682 | }; | |
683 | ||
684 | /** | |
685 | * /enum enum drx_interleave_mode | |
38b2df95 DH |
686 | * /brief Interleave modes |
687 | */ | |
61263c75 MCC |
688 | enum drx_interleave_mode { |
689 | DRX_INTERLEAVEMODE_I128_J1 = 0, | |
690 | DRX_INTERLEAVEMODE_I128_J1_V2, | |
691 | DRX_INTERLEAVEMODE_I128_J2, | |
692 | DRX_INTERLEAVEMODE_I64_J2, | |
693 | DRX_INTERLEAVEMODE_I128_J3, | |
694 | DRX_INTERLEAVEMODE_I32_J4, | |
695 | DRX_INTERLEAVEMODE_I128_J4, | |
696 | DRX_INTERLEAVEMODE_I16_J8, | |
697 | DRX_INTERLEAVEMODE_I128_J5, | |
698 | DRX_INTERLEAVEMODE_I8_J16, | |
699 | DRX_INTERLEAVEMODE_I128_J6, | |
700 | DRX_INTERLEAVEMODE_RESERVED_11, | |
701 | DRX_INTERLEAVEMODE_I128_J7, | |
702 | DRX_INTERLEAVEMODE_RESERVED_13, | |
703 | DRX_INTERLEAVEMODE_I128_J8, | |
704 | DRX_INTERLEAVEMODE_RESERVED_15, | |
705 | DRX_INTERLEAVEMODE_I12_J17, | |
706 | DRX_INTERLEAVEMODE_I5_J4, | |
707 | DRX_INTERLEAVEMODE_B52_M240, | |
708 | DRX_INTERLEAVEMODE_B52_M720, | |
709 | DRX_INTERLEAVEMODE_B52_M48, | |
710 | DRX_INTERLEAVEMODE_B52_M0, | |
711 | DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, | |
712 | /**< Unknown interleave mode */ | |
713 | DRX_INTERLEAVEMODE_AUTO = DRX_AUTO | |
714 | /**< Autodetect interleave mode */ | |
715 | }; | |
716 | ||
717 | /** | |
718 | * \enum enum drx_carrier_mode | |
38b2df95 DH |
719 | * \brief Channel Carrier Mode. |
720 | */ | |
7ef66759 | 721 | enum drx_carrier_mode { |
61263c75 MCC |
722 | DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ |
723 | DRX_CARRIER_SINGLE, /**< Single carrier mode */ | |
724 | DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, | |
725 | /**< Carrier mode unknown. */ | |
726 | DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ | |
727 | }; | |
38b2df95 DH |
728 | |
729 | /** | |
61263c75 | 730 | * \enum enum drx_frame_mode |
38b2df95 DH |
731 | * \brief Channel Frame Mode. |
732 | */ | |
7ef66759 | 733 | enum drx_frame_mode { |
61263c75 MCC |
734 | DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ |
735 | DRX_FRAMEMODE_595, /**< 595 */ | |
736 | DRX_FRAMEMODE_945, /**< 945 with variable PN */ | |
737 | DRX_FRAMEMODE_420_FIXED_PN, | |
738 | /**< 420 with fixed PN */ | |
739 | DRX_FRAMEMODE_945_FIXED_PN, | |
740 | /**< 945 with fixed PN */ | |
741 | DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, | |
742 | /**< Frame mode unknown. */ | |
743 | DRX_FRAMEMODE_AUTO = DRX_AUTO | |
744 | /**< Autodetect frame mode */ | |
745 | }; | |
746 | ||
747 | /** | |
748 | * \enum enum drx_tps_frame | |
38b2df95 DH |
749 | * \brief Frame number in current super-frame. |
750 | */ | |
7ef66759 | 751 | enum drx_tps_frame { |
61263c75 MCC |
752 | DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ |
753 | DRX_TPS_FRAME2, /**< TPS frame 2. */ | |
754 | DRX_TPS_FRAME3, /**< TPS frame 3. */ | |
755 | DRX_TPS_FRAME4, /**< TPS frame 4. */ | |
756 | DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN | |
757 | /**< TPS frame unknown. */ | |
758 | }; | |
38b2df95 DH |
759 | |
760 | /** | |
61263c75 | 761 | * \enum enum drx_ldpc |
38b2df95 DH |
762 | * \brief TPS LDPC . |
763 | */ | |
7ef66759 | 764 | enum drx_ldpc { |
61263c75 MCC |
765 | DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ |
766 | DRX_LDPC_0_6, /**< LDPC 0.6 */ | |
767 | DRX_LDPC_0_8, /**< LDPC 0.8 */ | |
768 | DRX_LDPC_UNKNOWN = DRX_UNKNOWN, | |
769 | /**< LDPC unknown. */ | |
770 | DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ | |
771 | }; | |
38b2df95 DH |
772 | |
773 | /** | |
61263c75 | 774 | * \enum enum drx_pilot_mode |
38b2df95 DH |
775 | * \brief Pilot modes in DTMB. |
776 | */ | |
7ef66759 | 777 | enum drx_pilot_mode { |
61263c75 MCC |
778 | DRX_PILOT_ON = 0, /**< Pilot On */ |
779 | DRX_PILOT_OFF, /**< Pilot Off */ | |
780 | DRX_PILOT_UNKNOWN = DRX_UNKNOWN, | |
781 | /**< Pilot unknown. */ | |
782 | DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ | |
783 | }; | |
38b2df95 | 784 | |
38b2df95 | 785 | /** |
1bfc9e15 MCC |
786 | * enum drxu_code_action - indicate if firmware has to be uploaded or verified. |
787 | * @UCODE_UPLOAD: Upload the microcode image to device | |
788 | * @UCODE_VERIFY: Compare microcode image with code on device | |
789 | */ | |
790 | enum drxu_code_action { | |
791 | UCODE_UPLOAD, | |
792 | UCODE_VERIFY | |
793 | }; | |
38b2df95 DH |
794 | |
795 | /** | |
1bfc9e15 | 796 | * \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator. |
38b2df95 DH |
797 | * |
798 | * The generic lock states have device dependent semantics. | |
1bfc9e15 | 799 | |
443f18d0 | 800 | DRX_NEVER_LOCK = 0, |
1bfc9e15 | 801 | **< Device will never lock on this signal * |
443f18d0 | 802 | DRX_NOT_LOCKED, |
1bfc9e15 | 803 | **< Device has no lock at all * |
443f18d0 | 804 | DRX_LOCK_STATE_1, |
1bfc9e15 | 805 | **< Generic lock state * |
443f18d0 | 806 | DRX_LOCK_STATE_2, |
1bfc9e15 | 807 | **< Generic lock state * |
443f18d0 | 808 | DRX_LOCK_STATE_3, |
1bfc9e15 | 809 | **< Generic lock state * |
443f18d0 | 810 | DRX_LOCK_STATE_4, |
1bfc9e15 | 811 | **< Generic lock state * |
443f18d0 | 812 | DRX_LOCK_STATE_5, |
1bfc9e15 | 813 | **< Generic lock state * |
443f18d0 | 814 | DRX_LOCK_STATE_6, |
1bfc9e15 | 815 | **< Generic lock state * |
443f18d0 | 816 | DRX_LOCK_STATE_7, |
1bfc9e15 | 817 | **< Generic lock state * |
443f18d0 | 818 | DRX_LOCK_STATE_8, |
1bfc9e15 | 819 | **< Generic lock state * |
443f18d0 | 820 | DRX_LOCK_STATE_9, |
1bfc9e15 MCC |
821 | **< Generic lock state * |
822 | DRX_LOCKED **< Device is in lock * | |
823 | */ | |
824 | ||
825 | enum drx_lock_status { | |
826 | DRX_NEVER_LOCK = 0, | |
827 | DRX_NOT_LOCKED, | |
828 | DRX_LOCK_STATE_1, | |
829 | DRX_LOCK_STATE_2, | |
830 | DRX_LOCK_STATE_3, | |
831 | DRX_LOCK_STATE_4, | |
832 | DRX_LOCK_STATE_5, | |
833 | DRX_LOCK_STATE_6, | |
834 | DRX_LOCK_STATE_7, | |
835 | DRX_LOCK_STATE_8, | |
836 | DRX_LOCK_STATE_9, | |
837 | DRX_LOCKED | |
838 | }; | |
839 | ||
840 | /** | |
841 | * \enum enum drx_uio* \brief Used to address a User IO (UIO). | |
842 | */ | |
843 | enum drx_uio { | |
844 | DRX_UIO1, | |
845 | DRX_UIO2, | |
846 | DRX_UIO3, | |
847 | DRX_UIO4, | |
848 | DRX_UIO5, | |
849 | DRX_UIO6, | |
850 | DRX_UIO7, | |
851 | DRX_UIO8, | |
852 | DRX_UIO9, | |
853 | DRX_UIO10, | |
854 | DRX_UIO11, | |
855 | DRX_UIO12, | |
856 | DRX_UIO13, | |
857 | DRX_UIO14, | |
858 | DRX_UIO15, | |
859 | DRX_UIO16, | |
860 | DRX_UIO17, | |
861 | DRX_UIO18, | |
862 | DRX_UIO19, | |
863 | DRX_UIO20, | |
864 | DRX_UIO21, | |
865 | DRX_UIO22, | |
866 | DRX_UIO23, | |
867 | DRX_UIO24, | |
868 | DRX_UIO25, | |
869 | DRX_UIO26, | |
870 | DRX_UIO27, | |
871 | DRX_UIO28, | |
872 | DRX_UIO29, | |
873 | DRX_UIO30, | |
874 | DRX_UIO31, | |
875 | DRX_UIO32, | |
876 | DRX_UIO_MAX = DRX_UIO32 | |
877 | }; | |
878 | ||
879 | /** | |
880 | * \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO. | |
38b2df95 DH |
881 | * |
882 | * DRX_UIO_MODE_FIRMWARE is an old uio mode. | |
883 | * It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9. | |
884 | * To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to | |
885 | * DRX_UIO_MODE_FIRMWARE0. | |
886 | */ | |
1bfc9e15 MCC |
887 | enum drxuio_mode { |
888 | DRX_UIO_MODE_DISABLE = 0x01, | |
889 | /**< not used, pin is configured as input */ | |
890 | DRX_UIO_MODE_READWRITE = 0x02, | |
891 | /**< used for read/write by application */ | |
892 | DRX_UIO_MODE_FIRMWARE = 0x04, | |
893 | /**< controlled by firmware, function 0 */ | |
894 | DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, | |
895 | /**< same as above */ | |
896 | DRX_UIO_MODE_FIRMWARE1 = 0x08, | |
897 | /**< controlled by firmware, function 1 */ | |
898 | DRX_UIO_MODE_FIRMWARE2 = 0x10, | |
899 | /**< controlled by firmware, function 2 */ | |
900 | DRX_UIO_MODE_FIRMWARE3 = 0x20, | |
901 | /**< controlled by firmware, function 3 */ | |
902 | DRX_UIO_MODE_FIRMWARE4 = 0x40, | |
903 | /**< controlled by firmware, function 4 */ | |
904 | DRX_UIO_MODE_FIRMWARE5 = 0x80 | |
905 | /**< controlled by firmware, function 5 */ | |
906 | }; | |
907 | ||
908 | /** | |
909 | * \enum enum drxoob_downstream_standard * \brief Used to select OOB standard. | |
38b2df95 DH |
910 | * |
911 | * Based on ANSI 55-1 and 55-2 | |
912 | */ | |
1bfc9e15 MCC |
913 | enum drxoob_downstream_standard { |
914 | DRX_OOB_MODE_A = 0, | |
915 | /**< ANSI 55-1 */ | |
916 | DRX_OOB_MODE_B_GRADE_A, | |
917 | /**< ANSI 55-2 A */ | |
918 | DRX_OOB_MODE_B_GRADE_B | |
919 | /**< ANSI 55-2 B */ | |
920 | }; | |
38b2df95 DH |
921 | |
922 | /*------------------------------------------------------------------------- | |
923 | STRUCTS | |
924 | -------------------------------------------------------------------------*/ | |
925 | ||
926 | /*============================================================================*/ | |
927 | /*============================================================================*/ | |
928 | /*== CTRL CFG related data structures ========================================*/ | |
929 | /*============================================================================*/ | |
930 | /*============================================================================*/ | |
931 | ||
38b2df95 | 932 | #ifndef DRX_CFG_BASE |
1bfc9e15 | 933 | #define DRX_CFG_BASE 0 |
38b2df95 DH |
934 | #endif |
935 | ||
7ef66759 MCC |
936 | #define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */ |
937 | #define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */ | |
938 | #define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */ | |
939 | #define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */ | |
940 | #define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */ | |
941 | #define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */ | |
942 | #define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */ | |
943 | #define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */ | |
944 | #define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8) /* ASS & ASC */ | |
945 | #define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9) /* ASS Thresholds */ | |
946 | #define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10) /* Deviation */ | |
947 | #define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11) /* Prescale */ | |
948 | #define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12) /* Mixer */ | |
949 | #define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13) /* AVSync */ | |
950 | #define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14) /* Audio carriers */ | |
951 | #define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15) /* I2S output */ | |
952 | #define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16) /* ATV standard */ | |
953 | #define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17) /* SQI speed */ | |
954 | #define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18) /* never to be used */ | |
38b2df95 DH |
955 | |
956 | #define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE | |
957 | /*============================================================================*/ | |
958 | /*============================================================================*/ | |
959 | /*== CTRL related data structures ============================================*/ | |
960 | /*============================================================================*/ | |
961 | /*============================================================================*/ | |
962 | ||
963 | /** | |
b48293db MCC |
964 | * struct drxu_code_info Parameters for microcode upload and verfiy. |
965 | * | |
966 | * @mc_file: microcode file name | |
967 | * | |
968 | * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE | |
969 | */ | |
1bfc9e15 | 970 | struct drxu_code_info { |
b48293db | 971 | char *mc_file; |
1bfc9e15 | 972 | }; |
38b2df95 DH |
973 | |
974 | /** | |
57afe2f0 | 975 | * \struct drx_mc_version_rec_t |
38b2df95 DH |
976 | * \brief Microcode version record |
977 | * Version numbers are stored in BCD format, as usual: | |
978 | * o major number = bits 31-20 (first three nibbles of MSW) | |
979 | * o minor number = bits 19-16 (fourth nibble of MSW) | |
980 | * o patch number = bits 15-0 (remaining nibbles in LSW) | |
981 | * | |
982 | * The device type indicates for which the device is meant. It is based on the | |
983 | * JTAG ID, using everything except the bond ID and the metal fix. | |
984 | * | |
985 | * Special values: | |
57afe2f0 MCC |
986 | * - mc_dev_type == 0 => any device allowed |
987 | * - mc_base_version == 0.0.0 => full microcode (mc_version is the version) | |
988 | * - mc_base_version != 0.0.0 => patch microcode, the base microcode version | |
989 | * (mc_version is the version) | |
38b2df95 DH |
990 | */ |
991 | #define AUX_VER_RECORD 0x8000 | |
992 | ||
1bfc9e15 MCC |
993 | struct drx_mc_version_rec { |
994 | u16 aux_type; /* type of aux data - 0x8000 for version record */ | |
995 | u32 mc_dev_type; /* device type, based on JTAG ID */ | |
996 | u32 mc_version; /* version of microcode */ | |
997 | u32 mc_base_version; /* in case of patch: the original microcode version */ | |
998 | }; | |
38b2df95 DH |
999 | |
1000 | /*========================================*/ | |
1001 | ||
1002 | /** | |
57afe2f0 | 1003 | * \struct drx_filter_info_t |
38b2df95 DH |
1004 | * \brief Parameters for loading filter coefficients |
1005 | * | |
1006 | * Used by DRX_CTRL_LOAD_FILTER | |
1007 | */ | |
1bfc9e15 MCC |
1008 | struct drx_filter_info { |
1009 | u8 *data_re; | |
1010 | /**< pointer to coefficients for RE */ | |
1011 | u8 *data_im; | |
1012 | /**< pointer to coefficients for IM */ | |
1013 | u16 size_re; | |
1014 | /**< size of coefficients for RE */ | |
1015 | u16 size_im; | |
1016 | /**< size of coefficients for IM */ | |
1017 | }; | |
38b2df95 DH |
1018 | |
1019 | /*========================================*/ | |
1020 | ||
1021 | /** | |
1bfc9e15 | 1022 | * \struct struct drx_channel * \brief The set of parameters describing a single channel. |
38b2df95 DH |
1023 | * |
1024 | * Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. | |
1025 | * Only certain fields need to be used for a specfic standard. | |
1026 | * | |
1027 | */ | |
1bfc9e15 MCC |
1028 | struct drx_channel { |
1029 | s32 frequency; | |
1030 | /**< frequency in kHz */ | |
1031 | enum drx_bandwidth bandwidth; | |
1032 | /**< bandwidth */ | |
1033 | enum drx_mirror mirror; /**< mirrored or not on RF */ | |
1034 | enum drx_modulation constellation; | |
1035 | /**< constellation */ | |
1036 | enum drx_hierarchy hierarchy; | |
1037 | /**< hierarchy */ | |
1038 | enum drx_priority priority; /**< priority */ | |
1039 | enum drx_coderate coderate; /**< coderate */ | |
1040 | enum drx_guard guard; /**< guard interval */ | |
1041 | enum drx_fft_mode fftmode; /**< fftmode */ | |
1042 | enum drx_classification classification; | |
1043 | /**< classification */ | |
1044 | u32 symbolrate; | |
1045 | /**< symbolrate in symbols/sec */ | |
1046 | enum drx_interleave_mode interleavemode; | |
1047 | /**< interleaveMode QAM */ | |
1048 | enum drx_ldpc ldpc; /**< ldpc */ | |
1049 | enum drx_carrier_mode carrier; /**< carrier */ | |
1050 | enum drx_frame_mode framemode; | |
1051 | /**< frame mode */ | |
1052 | enum drx_pilot_mode pilot; /**< pilot mode */ | |
1053 | }; | |
38b2df95 DH |
1054 | |
1055 | /*========================================*/ | |
1056 | ||
1057 | /** | |
1bfc9e15 | 1058 | * \struct struct drx_sig_quality * Signal quality metrics. |
38b2df95 DH |
1059 | * |
1060 | * Used by DRX_CTRL_SIG_QUALITY. | |
1061 | */ | |
1bfc9e15 MCC |
1062 | struct drx_sig_quality { |
1063 | u16 MER; /**< in steps of 0.1 dB */ | |
1064 | u32 pre_viterbi_ber; | |
1065 | /**< in steps of 1/scale_factor_ber */ | |
1066 | u32 post_viterbi_ber; | |
1067 | /**< in steps of 1/scale_factor_ber */ | |
1068 | u32 scale_factor_ber; | |
1069 | /**< scale factor for BER */ | |
1070 | u16 packet_error; | |
1071 | /**< number of packet errors */ | |
1072 | u32 post_reed_solomon_ber; | |
1073 | /**< in steps of 1/scale_factor_ber */ | |
1074 | u32 pre_ldpc_ber; | |
1075 | /**< in steps of 1/scale_factor_ber */ | |
1076 | u32 aver_iter;/**< in steps of 0.01 */ | |
1077 | u16 indicator; | |
1078 | /**< indicative signal quality low=0..100=high */ | |
1079 | }; | |
1080 | ||
1081 | enum drx_cfg_sqi_speed { | |
1082 | DRX_SQI_SPEED_FAST = 0, | |
1083 | DRX_SQI_SPEED_MEDIUM, | |
1084 | DRX_SQI_SPEED_SLOW, | |
1085 | DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN | |
1086 | }; | |
38b2df95 DH |
1087 | |
1088 | /*========================================*/ | |
1089 | ||
1090 | /** | |
1bfc9e15 | 1091 | * \struct struct drx_complex * A complex number. |
38b2df95 DH |
1092 | * |
1093 | * Used by DRX_CTRL_CONSTEL. | |
1094 | */ | |
1bfc9e15 MCC |
1095 | struct drx_complex { |
1096 | s16 im; | |
1097 | /**< Imaginary part. */ | |
1098 | s16 re; | |
1099 | /**< Real part. */ | |
1100 | }; | |
38b2df95 DH |
1101 | |
1102 | /*========================================*/ | |
1103 | ||
1104 | /** | |
1bfc9e15 | 1105 | * \struct struct drx_frequency_plan * Array element of a frequency plan. |
38b2df95 DH |
1106 | * |
1107 | * Used by DRX_CTRL_SCAN_INIT. | |
1108 | */ | |
1bfc9e15 MCC |
1109 | struct drx_frequency_plan { |
1110 | s32 first; | |
1111 | /**< First centre frequency in this band */ | |
1112 | s32 last; | |
1113 | /**< Last centre frequency in this band */ | |
1114 | s32 step; | |
1115 | /**< Stepping frequency in this band */ | |
1116 | enum drx_bandwidth bandwidth; | |
1117 | /**< Bandwidth within this frequency band */ | |
1118 | u16 ch_number; | |
1119 | /**< First channel number in this band, or first | |
1120 | index in ch_names */ | |
1121 | char **ch_names; | |
1122 | /**< Optional list of channel names in this | |
1123 | band */ | |
1124 | }; | |
38b2df95 DH |
1125 | |
1126 | /*========================================*/ | |
1127 | ||
1128 | /** | |
1bfc9e15 | 1129 | * \struct struct drx_scan_param * Parameters for channel scan. |
38b2df95 DH |
1130 | * |
1131 | * Used by DRX_CTRL_SCAN_INIT. | |
1132 | */ | |
1bfc9e15 MCC |
1133 | struct drx_scan_param { |
1134 | struct drx_frequency_plan *frequency_plan; | |
1135 | /**< Frequency plan (array)*/ | |
1136 | u16 frequency_plan_size; /**< Number of bands */ | |
1137 | u32 num_tries; /**< Max channels tried */ | |
1138 | s32 skip; /**< Minimum frequency step to take | |
1139 | after a channel is found */ | |
1140 | void *ext_params; /**< Standard specific params */ | |
1141 | }; | |
38b2df95 DH |
1142 | |
1143 | /*========================================*/ | |
1144 | ||
1145 | /** | |
1146 | * \brief Scan commands. | |
1147 | * Used by scanning algorithms. | |
1148 | */ | |
1bfc9e15 | 1149 | enum drx_scan_command { |
443f18d0 MCC |
1150 | DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */ |
1151 | DRX_SCAN_COMMAND_NEXT, /**< Next scan */ | |
1152 | DRX_SCAN_COMMAND_STOP /**< Stop scanning */ | |
1bfc9e15 | 1153 | }; |
38b2df95 DH |
1154 | |
1155 | /*========================================*/ | |
1156 | ||
1157 | /** | |
1158 | * \brief Inner scan function prototype. | |
1159 | */ | |
1bfc9e15 MCC |
1160 | typedef int(*drx_scan_func_t) (void *scan_context, |
1161 | enum drx_scan_command scan_command, | |
1162 | struct drx_channel *scan_channel, | |
1163 | bool *get_next_channel); | |
38b2df95 DH |
1164 | |
1165 | /*========================================*/ | |
1166 | ||
1167 | /** | |
1bfc9e15 | 1168 | * \struct struct drxtps_info * TPS information, DVB-T specific. |
38b2df95 DH |
1169 | * |
1170 | * Used by DRX_CTRL_TPS_INFO. | |
1171 | */ | |
1bfc9e15 | 1172 | struct drxtps_info { |
61263c75 MCC |
1173 | enum drx_fft_mode fftmode; /**< Fft mode */ |
1174 | enum drx_guard guard; /**< Guard interval */ | |
1175 | enum drx_modulation constellation; | |
443f18d0 | 1176 | /**< Constellation */ |
61263c75 | 1177 | enum drx_hierarchy hierarchy; |
443f18d0 | 1178 | /**< Hierarchy */ |
57afe2f0 | 1179 | enum drx_coderate high_coderate; |
443f18d0 | 1180 | /**< High code rate */ |
57afe2f0 | 1181 | enum drx_coderate low_coderate; |
443f18d0 | 1182 | /**< Low cod rate */ |
61263c75 | 1183 | enum drx_tps_frame frame; /**< Tps frame */ |
43a431e4 | 1184 | u8 length; /**< Length */ |
57afe2f0 | 1185 | u16 cell_id; /**< Cell id */ |
1bfc9e15 | 1186 | }; |
38b2df95 DH |
1187 | |
1188 | /*========================================*/ | |
1189 | ||
1190 | /** | |
1191 | * \brief Power mode of device. | |
1192 | * | |
1193 | * Used by DRX_CTRL_SET_POWER_MODE. | |
1194 | */ | |
1bfc9e15 | 1195 | enum drx_power_mode { |
443f18d0 MCC |
1196 | DRX_POWER_UP = 0, |
1197 | /**< Generic , Power Up Mode */ | |
1198 | DRX_POWER_MODE_1, | |
1199 | /**< Device specific , Power Up Mode */ | |
1200 | DRX_POWER_MODE_2, | |
1201 | /**< Device specific , Power Up Mode */ | |
1202 | DRX_POWER_MODE_3, | |
1203 | /**< Device specific , Power Up Mode */ | |
1204 | DRX_POWER_MODE_4, | |
1205 | /**< Device specific , Power Up Mode */ | |
1206 | DRX_POWER_MODE_5, | |
1207 | /**< Device specific , Power Up Mode */ | |
1208 | DRX_POWER_MODE_6, | |
1209 | /**< Device specific , Power Up Mode */ | |
1210 | DRX_POWER_MODE_7, | |
1211 | /**< Device specific , Power Up Mode */ | |
1212 | DRX_POWER_MODE_8, | |
1213 | /**< Device specific , Power Up Mode */ | |
1214 | ||
1215 | DRX_POWER_MODE_9, | |
1216 | /**< Device specific , Power Down Mode */ | |
1217 | DRX_POWER_MODE_10, | |
1218 | /**< Device specific , Power Down Mode */ | |
1219 | DRX_POWER_MODE_11, | |
1220 | /**< Device specific , Power Down Mode */ | |
1221 | DRX_POWER_MODE_12, | |
1222 | /**< Device specific , Power Down Mode */ | |
1223 | DRX_POWER_MODE_13, | |
1224 | /**< Device specific , Power Down Mode */ | |
1225 | DRX_POWER_MODE_14, | |
1226 | /**< Device specific , Power Down Mode */ | |
1227 | DRX_POWER_MODE_15, | |
1228 | /**< Device specific , Power Down Mode */ | |
1229 | DRX_POWER_MODE_16, | |
1230 | /**< Device specific , Power Down Mode */ | |
1231 | DRX_POWER_DOWN = 255 | |
1232 | /**< Generic , Power Down Mode */ | |
1bfc9e15 | 1233 | }; |
38b2df95 DH |
1234 | |
1235 | /*========================================*/ | |
1236 | ||
1237 | /** | |
1bfc9e15 | 1238 | * \enum enum drx_module * \brief Software module identification. |
38b2df95 DH |
1239 | * |
1240 | * Used by DRX_CTRL_VERSION. | |
1241 | */ | |
1bfc9e15 | 1242 | enum drx_module { |
443f18d0 MCC |
1243 | DRX_MODULE_DEVICE, |
1244 | DRX_MODULE_MICROCODE, | |
1245 | DRX_MODULE_DRIVERCORE, | |
1246 | DRX_MODULE_DEVICEDRIVER, | |
1247 | DRX_MODULE_DAP, | |
1248 | DRX_MODULE_BSP_I2C, | |
1249 | DRX_MODULE_BSP_TUNER, | |
1250 | DRX_MODULE_BSP_HOST, | |
1251 | DRX_MODULE_UNKNOWN | |
1bfc9e15 | 1252 | }; |
38b2df95 DH |
1253 | |
1254 | /** | |
1bfc9e15 | 1255 | * \enum struct drx_version * \brief Version information of one software module. |
38b2df95 DH |
1256 | * |
1257 | * Used by DRX_CTRL_VERSION. | |
1258 | */ | |
1bfc9e15 MCC |
1259 | struct drx_version { |
1260 | enum drx_module module_type; | |
443f18d0 | 1261 | /**< Type identifier of the module */ |
57afe2f0 | 1262 | char *module_name; |
443f18d0 | 1263 | /**< Name or description of module */ |
57afe2f0 MCC |
1264 | u16 v_major; /**< Major version number */ |
1265 | u16 v_minor; /**< Minor version number */ | |
1266 | u16 v_patch; /**< Patch version number */ | |
1267 | char *v_string; /**< Version as text string */ | |
1bfc9e15 | 1268 | }; |
38b2df95 DH |
1269 | |
1270 | /** | |
1bfc9e15 | 1271 | * \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information. |
38b2df95 DH |
1272 | * |
1273 | * Used by DRX_CTRL_VERSION. | |
1274 | */ | |
1bfc9e15 MCC |
1275 | struct drx_version_list { |
1276 | struct drx_version *version;/**< Version information */ | |
1277 | struct drx_version_list *next; | |
1278 | /**< Next list element */ | |
1279 | }; | |
38b2df95 DH |
1280 | |
1281 | /*========================================*/ | |
1282 | ||
1283 | /** | |
1284 | * \brief Parameters needed to confiugure a UIO. | |
1285 | * | |
1286 | * Used by DRX_CTRL_UIO_CFG. | |
1287 | */ | |
1bfc9e15 MCC |
1288 | struct drxuio_cfg { |
1289 | enum drx_uio uio; | |
443f18d0 | 1290 | /**< UIO identifier */ |
1bfc9e15 | 1291 | enum drxuio_mode mode; |
443f18d0 | 1292 | /**< UIO operational mode */ |
1bfc9e15 | 1293 | }; |
38b2df95 DH |
1294 | |
1295 | /*========================================*/ | |
1296 | ||
1297 | /** | |
1298 | * \brief Parameters needed to read from or write to a UIO. | |
1299 | * | |
1300 | * Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. | |
1301 | */ | |
1bfc9e15 MCC |
1302 | struct drxuio_data { |
1303 | enum drx_uio uio; | |
443f18d0 | 1304 | /**< UIO identifier */ |
73f7065b MCC |
1305 | bool value; |
1306 | /**< UIO value (true=1, false=0) */ | |
1bfc9e15 | 1307 | }; |
38b2df95 DH |
1308 | |
1309 | /*========================================*/ | |
1310 | ||
1311 | /** | |
1312 | * \brief Parameters needed to configure OOB. | |
1313 | * | |
1314 | * Used by DRX_CTRL_SET_OOB. | |
1315 | */ | |
1bfc9e15 | 1316 | struct drxoob { |
73f7065b | 1317 | s32 frequency; /**< Frequency in kHz */ |
1bfc9e15 | 1318 | enum drxoob_downstream_standard standard; |
443f18d0 | 1319 | /**< OOB standard */ |
57afe2f0 | 1320 | bool spectrum_inverted; /**< If true, then spectrum |
38b2df95 | 1321 | is inverted */ |
1bfc9e15 | 1322 | }; |
38b2df95 DH |
1323 | |
1324 | /*========================================*/ | |
1325 | ||
1326 | /** | |
1327 | * \brief Metrics from OOB. | |
1328 | * | |
1329 | * Used by DRX_CTRL_GET_OOB. | |
1330 | */ | |
1bfc9e15 | 1331 | struct drxoob_status { |
73f7065b | 1332 | s32 frequency; /**< Frequency in Khz */ |
1bfc9e15 | 1333 | enum drx_lock_status lock; /**< Lock status */ |
43a431e4 | 1334 | u32 mer; /**< MER */ |
57afe2f0 | 1335 | s32 symbol_rate_offset; /**< Symbolrate offset in ppm */ |
1bfc9e15 | 1336 | }; |
38b2df95 DH |
1337 | |
1338 | /*========================================*/ | |
1339 | ||
1340 | /** | |
1341 | * \brief Device dependent configuration data. | |
1342 | * | |
1343 | * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. | |
57afe2f0 | 1344 | * A sort of nested drx_ctrl() functionality for device specific controls. |
38b2df95 | 1345 | */ |
1bfc9e15 MCC |
1346 | struct drx_cfg { |
1347 | u32 cfg_type; | |
443f18d0 | 1348 | /**< Function identifier */ |
57afe2f0 | 1349 | void *cfg_data; |
443f18d0 | 1350 | /**< Function data */ |
1bfc9e15 | 1351 | }; |
38b2df95 DH |
1352 | |
1353 | /*========================================*/ | |
1354 | ||
1355 | /** | |
1356 | * /struct DRXMpegStartWidth_t | |
1357 | * MStart width [nr MCLK cycles] for serial MPEG output. | |
1358 | */ | |
1359 | ||
1bfc9e15 | 1360 | enum drxmpeg_str_width { |
443f18d0 MCC |
1361 | DRX_MPEG_STR_WIDTH_1, |
1362 | DRX_MPEG_STR_WIDTH_8 | |
1bfc9e15 | 1363 | }; |
38b2df95 DH |
1364 | |
1365 | /* CTRL CFG MPEG ouput */ | |
1366 | /** | |
1bfc9e15 | 1367 | * \struct struct drx_cfg_mpeg_output * \brief Configuartion parameters for MPEG output control. |
38b2df95 DH |
1368 | * |
1369 | * Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and | |
1370 | * DRX_CTRL_GET_CFG. | |
1371 | */ | |
1372 | ||
1bfc9e15 | 1373 | struct drx_cfg_mpeg_output { |
57afe2f0 MCC |
1374 | bool enable_mpeg_output;/**< If true, enable MPEG output */ |
1375 | bool insert_rs_byte; /**< If true, insert RS byte */ | |
1376 | bool enable_parallel; /**< If true, parallel out otherwise | |
38b2df95 | 1377 | serial */ |
57afe2f0 MCC |
1378 | bool invert_data; /**< If true, invert DATA signals */ |
1379 | bool invert_err; /**< If true, invert ERR signal */ | |
1380 | bool invert_str; /**< If true, invert STR signals */ | |
1381 | bool invert_val; /**< If true, invert VAL signals */ | |
1382 | bool invert_clk; /**< If true, invert CLK signals */ | |
1383 | bool static_clk; /**< If true, static MPEG clockrate | |
38b2df95 DH |
1384 | will be used, otherwise clockrate |
1385 | will adapt to the bitrate of the | |
1386 | TS */ | |
43a431e4 | 1387 | u32 bitrate; /**< Maximum bitrate in b/s in case |
38b2df95 | 1388 | static clockrate is selected */ |
1bfc9e15 | 1389 | enum drxmpeg_str_width width_str; |
443f18d0 | 1390 | /**< MPEG start width */ |
1bfc9e15 | 1391 | }; |
38b2df95 | 1392 | |
38b2df95 DH |
1393 | |
1394 | /*========================================*/ | |
1395 | ||
1396 | /** | |
1bfc9e15 | 1397 | * \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port. |
38b2df95 DH |
1398 | * |
1399 | * Used by DRX_CTRL_I2C_READWRITE. | |
57afe2f0 | 1400 | * If port_nr is equal to primairy port_nr BSPI2C will be used. |
38b2df95 DH |
1401 | * |
1402 | */ | |
1bfc9e15 | 1403 | struct drxi2c_data { |
57afe2f0 MCC |
1404 | u16 port_nr; /**< I2C port number */ |
1405 | struct i2c_device_addr *w_dev_addr; | |
443f18d0 | 1406 | /**< Write device address */ |
57afe2f0 | 1407 | u16 w_count; /**< Size of write data in bytes */ |
43a431e4 | 1408 | u8 *wData; /**< Pointer to write data */ |
57afe2f0 | 1409 | struct i2c_device_addr *r_dev_addr; |
443f18d0 | 1410 | /**< Read device address */ |
57afe2f0 MCC |
1411 | u16 r_count; /**< Size of data to read in bytes */ |
1412 | u8 *r_data; /**< Pointer to read buffer */ | |
1bfc9e15 | 1413 | }; |
38b2df95 DH |
1414 | |
1415 | /*========================================*/ | |
1416 | ||
1417 | /** | |
1bfc9e15 | 1418 | * \enum enum drx_aud_standard * \brief Audio standard identifier. |
38b2df95 DH |
1419 | * |
1420 | * Used by DRX_CTRL_SET_AUD. | |
1421 | */ | |
1bfc9e15 | 1422 | enum drx_aud_standard { |
443f18d0 MCC |
1423 | DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */ |
1424 | DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */ | |
1425 | DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */ | |
1426 | DRX_AUD_STANDARD_FM_STEREO,/**< set to FM-Stereo Radio */ | |
1427 | DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */ | |
1428 | DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */ | |
1429 | DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */ | |
1430 | DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */ | |
1431 | DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */ | |
1432 | DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */ | |
1433 | DRX_AUD_STANDARD_BG_NICAM_FM, | |
1434 | /**< set BG_NICAM_FM standard */ | |
1435 | DRX_AUD_STANDARD_L_NICAM_AM, | |
1436 | /**< set L_NICAM_AM standard */ | |
1437 | DRX_AUD_STANDARD_I_NICAM_FM, | |
1438 | /**< set I_NICAM_FM standard */ | |
1439 | DRX_AUD_STANDARD_D_K_NICAM_FM, | |
1440 | /**< set D_K_NICAM_FM standard */ | |
1441 | DRX_AUD_STANDARD_NOT_READY,/**< used to detect audio standard */ | |
1442 | DRX_AUD_STANDARD_AUTO = DRX_AUTO, | |
1443 | /**< Automatic Standard Detection */ | |
1444 | DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN | |
1445 | /**< used as auto and for readback */ | |
1bfc9e15 | 1446 | }; |
38b2df95 | 1447 | |
1bfc9e15 | 1448 | /* CTRL_AUD_GET_STATUS - struct drx_aud_status */ |
38b2df95 | 1449 | /** |
1bfc9e15 | 1450 | * \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier. |
38b2df95 | 1451 | */ |
1bfc9e15 | 1452 | enum drx_aud_nicam_status { |
443f18d0 MCC |
1453 | DRX_AUD_NICAM_DETECTED = 0, |
1454 | /**< NICAM carrier detected */ | |
1455 | DRX_AUD_NICAM_NOT_DETECTED, | |
1456 | /**< NICAM carrier not detected */ | |
1457 | DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ | |
1bfc9e15 | 1458 | }; |
38b2df95 DH |
1459 | |
1460 | /** | |
1bfc9e15 | 1461 | * \struct struct drx_aud_status * \brief Audio status characteristics. |
38b2df95 | 1462 | */ |
1bfc9e15 | 1463 | struct drx_aud_status { |
73f7065b | 1464 | bool stereo; /**< stereo detection */ |
57afe2f0 MCC |
1465 | bool carrier_a; /**< carrier A detected */ |
1466 | bool carrier_b; /**< carrier B detected */ | |
73f7065b MCC |
1467 | bool sap; /**< sap / bilingual detection */ |
1468 | bool rds; /**< RDS data array present */ | |
1bfc9e15 | 1469 | enum drx_aud_nicam_status nicam_status; |
443f18d0 | 1470 | /**< status of NICAM carrier */ |
57afe2f0 | 1471 | s8 fm_ident; /**< FM Identification value */ |
1bfc9e15 | 1472 | }; |
38b2df95 DH |
1473 | |
1474 | /* CTRL_AUD_READ_RDS - DRXRDSdata_t */ | |
1475 | ||
1476 | /** | |
1477 | * \struct DRXRDSdata_t | |
1478 | * \brief Raw RDS data array. | |
1479 | */ | |
1bfc9e15 | 1480 | struct drx_cfg_aud_rds { |
73f7065b | 1481 | bool valid; /**< RDS data validation */ |
43a431e4 | 1482 | u16 data[18]; /**< data from one RDS data array */ |
1bfc9e15 | 1483 | }; |
38b2df95 | 1484 | |
1bfc9e15 | 1485 | /* DRX_CFG_AUD_VOLUME - struct drx_cfg_aud_volume - set/get */ |
38b2df95 DH |
1486 | /** |
1487 | * \enum DRXAudAVCDecayTime_t | |
1488 | * \brief Automatic volume control configuration. | |
1489 | */ | |
1bfc9e15 | 1490 | enum drx_aud_avc_mode { |
443f18d0 MCC |
1491 | DRX_AUD_AVC_OFF, /**< Automatic volume control off */ |
1492 | DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */ | |
1493 | DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ | |
1494 | DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ | |
1495 | DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */ | |
1bfc9e15 | 1496 | }; |
38b2df95 DH |
1497 | |
1498 | /** | |
1499 | * /enum DRXAudMaxAVCGain_t | |
1500 | * /brief Automatic volume control max gain in audio baseband. | |
1501 | */ | |
1bfc9e15 | 1502 | enum drx_aud_avc_max_gain { |
443f18d0 MCC |
1503 | DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ |
1504 | DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ | |
1505 | DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ | |
1bfc9e15 | 1506 | }; |
38b2df95 DH |
1507 | |
1508 | /** | |
1509 | * /enum DRXAudMaxAVCAtten_t | |
1510 | * /brief Automatic volume control max attenuation in audio baseband. | |
1511 | */ | |
1bfc9e15 | 1512 | enum drx_aud_avc_max_atten { |
443f18d0 MCC |
1513 | DRX_AUD_AVC_MAX_ATTEN_12DB, |
1514 | /**< maximum AVC attenuation 12 dB */ | |
1515 | DRX_AUD_AVC_MAX_ATTEN_18DB, | |
1516 | /**< maximum AVC attenuation 18 dB */ | |
1517 | DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */ | |
1bfc9e15 | 1518 | }; |
38b2df95 | 1519 | /** |
1bfc9e15 | 1520 | * \struct struct drx_cfg_aud_volume * \brief Audio volume configuration. |
38b2df95 | 1521 | */ |
1bfc9e15 | 1522 | struct drx_cfg_aud_volume { |
73f7065b | 1523 | bool mute; /**< mute overrides volume setting */ |
43a431e4 | 1524 | s16 volume; /**< volume, range -114 to 12 dB */ |
1bfc9e15 | 1525 | enum drx_aud_avc_mode avc_mode; /**< AVC auto volume control mode */ |
57afe2f0 | 1526 | u16 avc_ref_level; /**< AVC reference level */ |
1bfc9e15 | 1527 | enum drx_aud_avc_max_gain avc_max_gain; |
443f18d0 | 1528 | /**< AVC max gain selection */ |
1bfc9e15 | 1529 | enum drx_aud_avc_max_atten avc_max_atten; |
443f18d0 | 1530 | /**< AVC max attenuation selection */ |
57afe2f0 MCC |
1531 | s16 strength_left; /**< quasi-peak, left speaker */ |
1532 | s16 strength_right; /**< quasi-peak, right speaker */ | |
1bfc9e15 | 1533 | }; |
38b2df95 | 1534 | |
1bfc9e15 | 1535 | /* DRX_CFG_I2S_OUTPUT - struct drx_cfg_i2s_output - set/get */ |
38b2df95 | 1536 | /** |
1bfc9e15 | 1537 | * \enum enum drxi2s_mode * \brief I2S output mode. |
38b2df95 | 1538 | */ |
1bfc9e15 | 1539 | enum drxi2s_mode { |
443f18d0 MCC |
1540 | DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ |
1541 | DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ | |
1bfc9e15 | 1542 | }; |
38b2df95 DH |
1543 | |
1544 | /** | |
1bfc9e15 | 1545 | * \enum enum drxi2s_word_length * \brief Width of I2S data. |
38b2df95 | 1546 | */ |
1bfc9e15 | 1547 | enum drxi2s_word_length { |
443f18d0 MCC |
1548 | DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */ |
1549 | DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ | |
1bfc9e15 | 1550 | }; |
38b2df95 DH |
1551 | |
1552 | /** | |
1bfc9e15 | 1553 | * \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S. |
38b2df95 | 1554 | */ |
1bfc9e15 | 1555 | enum drxi2s_format { |
443f18d0 MCC |
1556 | DRX_I2S_FORMAT_WS_WITH_DATA, |
1557 | /**< I2S data and wordstrobe are aligned */ | |
1558 | DRX_I2S_FORMAT_WS_ADVANCED | |
1559 | /**< I2S data one cycle after wordstrobe */ | |
1bfc9e15 | 1560 | }; |
38b2df95 DH |
1561 | |
1562 | /** | |
1bfc9e15 | 1563 | * \enum enum drxi2s_polarity * \brief Polarity of I2S data. |
38b2df95 | 1564 | */ |
1bfc9e15 | 1565 | enum drxi2s_polarity { |
443f18d0 MCC |
1566 | DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */ |
1567 | DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ | |
1bfc9e15 | 1568 | }; |
38b2df95 DH |
1569 | |
1570 | /** | |
1bfc9e15 | 1571 | * \struct struct drx_cfg_i2s_output * \brief I2S output configuration. |
38b2df95 | 1572 | */ |
1bfc9e15 | 1573 | struct drx_cfg_i2s_output { |
57afe2f0 | 1574 | bool output_enable; /**< I2S output enable */ |
43a431e4 | 1575 | u32 frequency; /**< range from 8000-48000 Hz */ |
1bfc9e15 MCC |
1576 | enum drxi2s_mode mode; /**< I2S mode, master or slave */ |
1577 | enum drxi2s_word_length word_length; | |
443f18d0 | 1578 | /**< I2S wordlength, 16 or 32 bits */ |
1bfc9e15 MCC |
1579 | enum drxi2s_polarity polarity;/**< I2S wordstrobe polarity */ |
1580 | enum drxi2s_format format; /**< I2S wordstrobe delay to data */ | |
1581 | }; | |
38b2df95 DH |
1582 | |
1583 | /* ------------------------------expert interface-----------------------------*/ | |
1584 | /** | |
1bfc9e15 | 1585 | * /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator. |
38b2df95 DH |
1586 | * |
1587 | */ | |
1bfc9e15 | 1588 | enum drx_aud_fm_deemphasis { |
443f18d0 MCC |
1589 | DRX_AUD_FM_DEEMPH_50US, |
1590 | DRX_AUD_FM_DEEMPH_75US, | |
1591 | DRX_AUD_FM_DEEMPH_OFF | |
1bfc9e15 | 1592 | }; |
38b2df95 DH |
1593 | |
1594 | /** | |
1595 | * /enum DRXAudDeviation_t | |
1596 | * setting for deviation mode in audio demodulator. | |
1597 | * | |
1598 | */ | |
1bfc9e15 | 1599 | enum drx_cfg_aud_deviation { |
443f18d0 MCC |
1600 | DRX_AUD_DEVIATION_NORMAL, |
1601 | DRX_AUD_DEVIATION_HIGH | |
1bfc9e15 | 1602 | }; |
38b2df95 DH |
1603 | |
1604 | /** | |
1bfc9e15 | 1605 | * /enum enum drx_no_carrier_option * setting for carrier, mute/noise. |
38b2df95 DH |
1606 | * |
1607 | */ | |
1bfc9e15 | 1608 | enum drx_no_carrier_option { |
443f18d0 MCC |
1609 | DRX_NO_CARRIER_MUTE, |
1610 | DRX_NO_CARRIER_NOISE | |
1bfc9e15 | 1611 | }; |
38b2df95 DH |
1612 | |
1613 | /** | |
1614 | * \enum DRXAudAutoSound_t | |
1615 | * \brief Automatic Sound | |
1616 | */ | |
1bfc9e15 | 1617 | enum drx_cfg_aud_auto_sound { |
443f18d0 MCC |
1618 | DRX_AUD_AUTO_SOUND_OFF = 0, |
1619 | DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, | |
1620 | DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF | |
1bfc9e15 | 1621 | }; |
38b2df95 DH |
1622 | |
1623 | /** | |
1624 | * \enum DRXAudASSThres_t | |
1625 | * \brief Automatic Sound Select Thresholds | |
1626 | */ | |
1bfc9e15 | 1627 | struct drx_cfg_aud_ass_thres { |
43a431e4 MCC |
1628 | u16 a2; /* A2 Threshold for ASS configuration */ |
1629 | u16 btsc; /* BTSC Threshold for ASS configuration */ | |
1630 | u16 nicam; /* Nicam Threshold for ASS configuration */ | |
1bfc9e15 | 1631 | }; |
38b2df95 DH |
1632 | |
1633 | /** | |
1bfc9e15 | 1634 | * \struct struct drx_aud_carrier * \brief Carrier detection related parameters |
38b2df95 | 1635 | */ |
1bfc9e15 | 1636 | struct drx_aud_carrier { |
43a431e4 | 1637 | u16 thres; /* carrier detetcion threshold for primary carrier (A) */ |
1bfc9e15 | 1638 | enum drx_no_carrier_option opt; /* Mute or noise at no carrier detection (A) */ |
73f7065b MCC |
1639 | s32 shift; /* DC level of incoming signal (A) */ |
1640 | s32 dco; /* frequency adjustment (A) */ | |
1bfc9e15 | 1641 | }; |
38b2df95 DH |
1642 | |
1643 | /** | |
1bfc9e15 | 1644 | * \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct |
38b2df95 | 1645 | */ |
1bfc9e15 MCC |
1646 | struct drx_cfg_aud_carriers { |
1647 | struct drx_aud_carrier a; | |
1648 | struct drx_aud_carrier b; | |
1649 | }; | |
38b2df95 DH |
1650 | |
1651 | /** | |
1bfc9e15 | 1652 | * /enum enum drx_aud_i2s_src * Selection of audio source |
38b2df95 | 1653 | */ |
1bfc9e15 | 1654 | enum drx_aud_i2s_src { |
443f18d0 MCC |
1655 | DRX_AUD_SRC_MONO, |
1656 | DRX_AUD_SRC_STEREO_OR_AB, | |
1657 | DRX_AUD_SRC_STEREO_OR_A, | |
1bfc9e15 | 1658 | DRX_AUD_SRC_STEREO_OR_B}; |
38b2df95 DH |
1659 | |
1660 | /** | |
1bfc9e15 | 1661 | * \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output. |
38b2df95 | 1662 | */ |
1bfc9e15 | 1663 | enum drx_aud_i2s_matrix { |
443f18d0 MCC |
1664 | DRX_AUD_I2S_MATRIX_A_MONO, |
1665 | /**< A sound only, stereo or mono */ | |
1666 | DRX_AUD_I2S_MATRIX_B_MONO, | |
1667 | /**< B sound only, stereo or mono */ | |
1668 | DRX_AUD_I2S_MATRIX_STEREO, | |
1669 | /**< A+B sound, transparant */ | |
1bfc9e15 | 1670 | DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */}; |
38b2df95 DH |
1671 | |
1672 | /** | |
1bfc9e15 | 1673 | * /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator. |
38b2df95 DH |
1674 | * |
1675 | */ | |
1bfc9e15 | 1676 | enum drx_aud_fm_matrix { |
443f18d0 MCC |
1677 | DRX_AUD_FM_MATRIX_NO_MATRIX, |
1678 | DRX_AUD_FM_MATRIX_GERMAN, | |
1679 | DRX_AUD_FM_MATRIX_KOREAN, | |
1680 | DRX_AUD_FM_MATRIX_SOUND_A, | |
1bfc9e15 | 1681 | DRX_AUD_FM_MATRIX_SOUND_B}; |
38b2df95 DH |
1682 | |
1683 | /** | |
1684 | * \struct DRXAudMatrices_t | |
1685 | * \brief Mixer settings | |
1686 | */ | |
1bfc9e15 MCC |
1687 | struct drx_cfg_aud_mixer { |
1688 | enum drx_aud_i2s_src source_i2s; | |
1689 | enum drx_aud_i2s_matrix matrix_i2s; | |
1690 | enum drx_aud_fm_matrix matrix_fm; | |
1691 | }; | |
38b2df95 DH |
1692 | |
1693 | /** | |
1694 | * \enum DRXI2SVidSync_t | |
1695 | * \brief Audio/video synchronization, interacts with I2S mode. | |
1696 | * AUTO_1 and AUTO_2 are for automatic video standard detection with preference | |
1697 | * for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) | |
1698 | */ | |
1bfc9e15 | 1699 | enum drx_cfg_aud_av_sync { |
443f18d0 MCC |
1700 | DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */ |
1701 | DRX_AUD_AVSYNC_NTSC, | |
1702 | /**< it is an NTSC system */ | |
1703 | DRX_AUD_AVSYNC_MONOCHROME, | |
1704 | /**< it is a MONOCHROME system */ | |
1705 | DRX_AUD_AVSYNC_PAL_SECAM | |
1bfc9e15 | 1706 | /**< it is a PAL/SECAM system */}; |
38b2df95 DH |
1707 | |
1708 | /** | |
1bfc9e15 | 1709 | * \struct struct drx_cfg_aud_prescale * \brief Prescalers |
38b2df95 | 1710 | */ |
1bfc9e15 MCC |
1711 | struct drx_cfg_aud_prescale { |
1712 | u16 fm_deviation; | |
1713 | s16 nicam_gain; | |
1714 | }; | |
38b2df95 DH |
1715 | |
1716 | /** | |
1bfc9e15 | 1717 | * \struct struct drx_aud_beep * \brief Beep |
38b2df95 | 1718 | */ |
1bfc9e15 MCC |
1719 | struct drx_aud_beep { |
1720 | s16 volume; /* dB */ | |
1721 | u16 frequency; /* Hz */ | |
1722 | bool mute; | |
1723 | }; | |
38b2df95 DH |
1724 | |
1725 | /** | |
1bfc9e15 | 1726 | * \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode |
38b2df95 | 1727 | */ |
1bfc9e15 | 1728 | enum drx_aud_btsc_detect { |
443f18d0 | 1729 | DRX_BTSC_STEREO, |
1bfc9e15 MCC |
1730 | DRX_BTSC_MONO_AND_SAP}; |
1731 | ||
1732 | /** | |
1733 | * \struct struct drx_aud_data * \brief Audio data structure | |
1734 | */ | |
1735 | struct drx_aud_data { | |
1736 | /* audio storage */ | |
1737 | bool audio_is_active; | |
1738 | enum drx_aud_standard audio_standard; | |
1739 | struct drx_cfg_i2s_output i2sdata; | |
1740 | struct drx_cfg_aud_volume volume; | |
1741 | enum drx_cfg_aud_auto_sound auto_sound; | |
1742 | struct drx_cfg_aud_ass_thres ass_thresholds; | |
1743 | struct drx_cfg_aud_carriers carriers; | |
1744 | struct drx_cfg_aud_mixer mixer; | |
1745 | enum drx_cfg_aud_deviation deviation; | |
1746 | enum drx_cfg_aud_av_sync av_sync; | |
1747 | struct drx_cfg_aud_prescale prescale; | |
1748 | enum drx_aud_fm_deemphasis deemph; | |
1749 | enum drx_aud_btsc_detect btsc_detect; | |
1750 | /* rds */ | |
1751 | u16 rds_data_counter; | |
1752 | bool rds_data_present; | |
1753 | }; | |
1754 | ||
1755 | /** | |
1756 | * \enum enum drx_qam_lock_range * \brief QAM lock range mode | |
1757 | */ | |
1758 | enum drx_qam_lock_range { | |
443f18d0 | 1759 | DRX_QAM_LOCKRANGE_NORMAL, |
1bfc9e15 | 1760 | DRX_QAM_LOCKRANGE_EXTENDED}; |
38b2df95 DH |
1761 | |
1762 | /*============================================================================*/ | |
1763 | /*============================================================================*/ | |
1764 | /*== Data access structures ==================================================*/ | |
1765 | /*============================================================================*/ | |
1766 | /*============================================================================*/ | |
1767 | ||
1768 | /* Address on device */ | |
57afe2f0 | 1769 | typedef u32 dr_xaddr_t, *pdr_xaddr_t; |
38b2df95 DH |
1770 | |
1771 | /* Protocol specific flags */ | |
57afe2f0 | 1772 | typedef u32 dr_xflags_t, *pdr_xflags_t; |
38b2df95 DH |
1773 | |
1774 | /* Write block of data to device */ | |
57afe2f0 | 1775 | typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1776 | u32 addr, /* address of register/memory */ |
43a431e4 MCC |
1777 | u16 datasize, /* size of data in bytes */ |
1778 | u8 *data, /* data to send */ | |
1bfc9e15 | 1779 | u32 flags); |
38b2df95 DH |
1780 | |
1781 | /* Read block of data from device */ | |
57afe2f0 | 1782 | typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1783 | u32 addr, /* address of register/memory */ |
43a431e4 MCC |
1784 | u16 datasize, /* size of data in bytes */ |
1785 | u8 *data, /* receive buffer */ | |
1bfc9e15 | 1786 | u32 flags); |
38b2df95 DH |
1787 | |
1788 | /* Write 8-bits value to device */ | |
57afe2f0 | 1789 | typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1790 | u32 addr, /* address of register/memory */ |
43a431e4 | 1791 | u8 data, /* data to send */ |
1bfc9e15 | 1792 | u32 flags); |
38b2df95 DH |
1793 | |
1794 | /* Read 8-bits value to device */ | |
57afe2f0 | 1795 | typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1796 | u32 addr, /* address of register/memory */ |
43a431e4 | 1797 | u8 *data, /* receive buffer */ |
1bfc9e15 | 1798 | u32 flags); |
38b2df95 DH |
1799 | |
1800 | /* Read modify write 8-bits value to device */ | |
57afe2f0 | 1801 | typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 MCC |
1802 | u32 waddr, /* write address of register */ |
1803 | u32 raddr, /* read address of register */ | |
43a431e4 MCC |
1804 | u8 wdata, /* data to write */ |
1805 | u8 *rdata); /* data to read */ | |
38b2df95 DH |
1806 | |
1807 | /* Write 16-bits value to device */ | |
57afe2f0 | 1808 | typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1809 | u32 addr, /* address of register/memory */ |
43a431e4 | 1810 | u16 data, /* data to send */ |
1bfc9e15 | 1811 | u32 flags); |
38b2df95 DH |
1812 | |
1813 | /* Read 16-bits value to device */ | |
57afe2f0 | 1814 | typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1815 | u32 addr, /* address of register/memory */ |
43a431e4 | 1816 | u16 *data, /* receive buffer */ |
1bfc9e15 | 1817 | u32 flags); |
38b2df95 DH |
1818 | |
1819 | /* Read modify write 16-bits value to device */ | |
57afe2f0 | 1820 | typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 MCC |
1821 | u32 waddr, /* write address of register */ |
1822 | u32 raddr, /* read address of register */ | |
43a431e4 MCC |
1823 | u16 wdata, /* data to write */ |
1824 | u16 *rdata); /* data to read */ | |
38b2df95 DH |
1825 | |
1826 | /* Write 32-bits value to device */ | |
57afe2f0 | 1827 | typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1828 | u32 addr, /* address of register/memory */ |
43a431e4 | 1829 | u32 data, /* data to send */ |
1bfc9e15 | 1830 | u32 flags); |
38b2df95 DH |
1831 | |
1832 | /* Read 32-bits value to device */ | |
57afe2f0 | 1833 | typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1834 | u32 addr, /* address of register/memory */ |
43a431e4 | 1835 | u32 *data, /* receive buffer */ |
1bfc9e15 | 1836 | u32 flags); |
38b2df95 DH |
1837 | |
1838 | /* Read modify write 32-bits value to device */ | |
57afe2f0 | 1839 | typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 MCC |
1840 | u32 waddr, /* write address of register */ |
1841 | u32 raddr, /* read address of register */ | |
43a431e4 MCC |
1842 | u32 wdata, /* data to write */ |
1843 | u32 *rdata); /* data to read */ | |
38b2df95 DH |
1844 | |
1845 | /** | |
1bfc9e15 MCC |
1846 | * \struct struct drx_access_func * \brief Interface to an access protocol. |
1847 | */ | |
1848 | struct drx_access_func { | |
1849 | struct drx_version *protocolVersion; | |
1850 | drx_write_block_func_t write_block_func; | |
1851 | drx_read_block_func_t read_block_func; | |
1852 | drx_write_reg8func_t write_reg8func; | |
1853 | drx_read_reg8func_t read_reg8func; | |
1854 | drx_read_modify_write_reg8func_t read_modify_write_reg8func; | |
1855 | drx_write_reg16func_t write_reg16func; | |
1856 | drx_read_reg16func_t read_reg16func; | |
1857 | drx_read_modify_write_reg16func_t read_modify_write_reg16func; | |
1858 | drx_write_reg32func_t write_reg32func; | |
1859 | drx_read_reg32func_t read_reg32func; | |
1860 | drx_read_modify_write_reg32func_t read_modify_write_reg32func; | |
1861 | }; | |
38b2df95 DH |
1862 | |
1863 | /* Register address and data for register dump function */ | |
1bfc9e15 MCC |
1864 | struct drx_reg_dump { |
1865 | u32 address; | |
1866 | u32 data; | |
1867 | }; | |
38b2df95 DH |
1868 | |
1869 | /*============================================================================*/ | |
1870 | /*============================================================================*/ | |
1871 | /*== Demod instance data structures ==========================================*/ | |
1872 | /*============================================================================*/ | |
1873 | /*============================================================================*/ | |
1874 | ||
1875 | /** | |
1bfc9e15 | 1876 | * \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices. |
38b2df95 | 1877 | */ |
1bfc9e15 | 1878 | struct drx_common_attr { |
443f18d0 | 1879 | /* Microcode (firmware) attributes */ |
b48293db | 1880 | char *microcode_file; /**< microcode filename */ |
57afe2f0 | 1881 | bool verify_microcode; |
443f18d0 | 1882 | /**< Use microcode verify or not. */ |
1bfc9e15 | 1883 | struct drx_mc_version_rec mcversion; |
443f18d0 MCC |
1884 | /**< Version record of microcode from file */ |
1885 | ||
1886 | /* Clocks and tuner attributes */ | |
57afe2f0 | 1887 | s32 intermediate_freq; |
443f18d0 | 1888 | /**< IF,if tuner instance not used. (kHz)*/ |
57afe2f0 | 1889 | s32 sys_clock_freq; |
443f18d0 | 1890 | /**< Systemclock frequency. (kHz) */ |
57afe2f0 | 1891 | s32 osc_clock_freq; |
443f18d0 | 1892 | /**< Oscillator clock frequency. (kHz) */ |
57afe2f0 | 1893 | s16 osc_clock_deviation; |
443f18d0 | 1894 | /**< Oscillator clock deviation. (ppm) */ |
57afe2f0 | 1895 | bool mirror_freq_spect; |
443f18d0 MCC |
1896 | /**< Mirror IF frequency spectrum or not.*/ |
1897 | ||
1898 | /* Initial MPEG output attributes */ | |
1bfc9e15 | 1899 | struct drx_cfg_mpeg_output mpeg_cfg; |
443f18d0 MCC |
1900 | /**< MPEG configuration */ |
1901 | ||
57afe2f0 | 1902 | bool is_opened; /**< if true instance is already opened. */ |
443f18d0 MCC |
1903 | |
1904 | /* Channel scan */ | |
1bfc9e15 | 1905 | struct drx_scan_param *scan_param; |
443f18d0 | 1906 | /**< scan parameters */ |
57afe2f0 | 1907 | u16 scan_freq_plan_index; |
443f18d0 | 1908 | /**< next index in freq plan */ |
57afe2f0 | 1909 | s32 scan_next_frequency; |
443f18d0 | 1910 | /**< next freq to scan */ |
57afe2f0 MCC |
1911 | bool scan_ready; /**< scan ready flag */ |
1912 | u32 scan_max_channels;/**< number of channels in freqplan */ | |
e33f2193 | 1913 | u32 scan_channels_scanned; |
443f18d0 MCC |
1914 | /**< number of channels scanned */ |
1915 | /* Channel scan - inner loop: demod related */ | |
57afe2f0 | 1916 | drx_scan_func_t scan_function; |
443f18d0 MCC |
1917 | /**< function to check channel */ |
1918 | /* Channel scan - inner loop: SYSObj related */ | |
57afe2f0 | 1919 | void *scan_context; /**< Context Pointer of SYSObj */ |
443f18d0 | 1920 | /* Channel scan - parameters for default DTV scan function in core driver */ |
57afe2f0 | 1921 | u16 scan_demod_lock_timeout; |
443f18d0 | 1922 | /**< millisecs to wait for lock */ |
1bfc9e15 | 1923 | enum drx_lock_status scan_desired_lock; |
443f18d0 | 1924 | /**< lock requirement for channel found */ |
57afe2f0 | 1925 | /* scan_active can be used by SetChannel to decide how to program the tuner, |
443f18d0 | 1926 | fast or slow (but stable). Usually fast during scan. */ |
57afe2f0 | 1927 | bool scan_active; /**< true when scan routines are active */ |
443f18d0 MCC |
1928 | |
1929 | /* Power management */ | |
1bfc9e15 | 1930 | enum drx_power_mode current_power_mode; |
443f18d0 MCC |
1931 | /**< current power management mode */ |
1932 | ||
1933 | /* Tuner */ | |
57afe2f0 MCC |
1934 | u8 tuner_port_nr; /**< nr of I2C port to wich tuner is */ |
1935 | s32 tuner_min_freq_rf; | |
443f18d0 | 1936 | /**< minimum RF input frequency, in kHz */ |
57afe2f0 | 1937 | s32 tuner_max_freq_rf; |
443f18d0 | 1938 | /**< maximum RF input frequency, in kHz */ |
57afe2f0 MCC |
1939 | bool tuner_rf_agc_pol; /**< if true invert RF AGC polarity */ |
1940 | bool tuner_if_agc_pol; /**< if true invert IF AGC polarity */ | |
1941 | bool tuner_slow_mode; /**< if true invert IF AGC polarity */ | |
443f18d0 | 1942 | |
1bfc9e15 | 1943 | struct drx_channel current_channel; |
443f18d0 | 1944 | /**< current channel parameters */ |
57afe2f0 | 1945 | enum drx_standard current_standard; |
443f18d0 | 1946 | /**< current standard selection */ |
57afe2f0 | 1947 | enum drx_standard prev_standard; |
443f18d0 | 1948 | /**< previous standard selection */ |
57afe2f0 | 1949 | enum drx_standard di_cache_standard; |
443f18d0 | 1950 | /**< standard in DI cache if available */ |
57afe2f0 | 1951 | bool use_bootloader; /**< use bootloader in open */ |
43a431e4 | 1952 | u32 capabilities; /**< capabilities flags */ |
1bfc9e15 | 1953 | u32 product_id; /**< product ID inc. metal fix number */}; |
38b2df95 DH |
1954 | |
1955 | /* | |
1956 | * Generic functions for DRX devices. | |
1957 | */ | |
38b2df95 | 1958 | |
1bfc9e15 MCC |
1959 | struct drx_demod_instance; |
1960 | ||
38b2df95 | 1961 | /** |
1bfc9e15 | 1962 | * \struct struct drx_demod_instance * \brief Top structure of demodulator instance. |
38b2df95 | 1963 | */ |
b48293db MCC |
1964 | struct drx_demod_instance { |
1965 | /* type specific demodulator data */ | |
b48293db MCC |
1966 | struct drx_access_func *my_access_funct; |
1967 | /**< data access protocol functions */ | |
1968 | struct tuner_instance *my_tuner; | |
1969 | /**< tuner instance,if NULL then baseband */ | |
1970 | struct i2c_device_addr *my_i2c_dev_addr; | |
1971 | /**< i2c address and device identifier */ | |
1972 | struct drx_common_attr *my_common_attr; | |
1973 | /**< common DRX attributes */ | |
1974 | void *my_ext_attr; /**< device specific attributes */ | |
1975 | /* generic demodulator data */ | |
1976 | ||
1977 | struct i2c_adapter *i2c; | |
1978 | const struct firmware *firmware; | |
1979 | }; | |
38b2df95 DH |
1980 | |
1981 | /*------------------------------------------------------------------------- | |
1982 | MACROS | |
1983 | Conversion from enum values to human readable form. | |
1984 | -------------------------------------------------------------------------*/ | |
1985 | ||
1986 | /* standard */ | |
1987 | ||
1988 | #define DRX_STR_STANDARD(x) ( \ | |
2f1f7333 MCC |
1989 | (x == DRX_STANDARD_DVBT) ? "DVB-T" : \ |
1990 | (x == DRX_STANDARD_8VSB) ? "8VSB" : \ | |
1991 | (x == DRX_STANDARD_NTSC) ? "NTSC" : \ | |
1992 | (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \ | |
1993 | (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \ | |
1994 | (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \ | |
1995 | (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \ | |
1996 | (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \ | |
1997 | (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \ | |
1998 | (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \ | |
1999 | (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \ | |
2000 | (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \ | |
2001 | (x == DRX_STANDARD_FM) ? "FM" : \ | |
2002 | (x == DRX_STANDARD_DTMB) ? "DTMB" : \ | |
2003 | (x == DRX_STANDARD_AUTO) ? "Auto" : \ | |
2004 | (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \ | |
2005 | "(Invalid)") | |
38b2df95 DH |
2006 | |
2007 | /* channel */ | |
2008 | ||
2009 | #define DRX_STR_BANDWIDTH(x) ( \ | |
2f1f7333 MCC |
2010 | (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \ |
2011 | (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \ | |
2012 | (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \ | |
2013 | (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \ | |
2014 | (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \ | |
2015 | "(Invalid)") | |
38b2df95 | 2016 | #define DRX_STR_FFTMODE(x) ( \ |
2f1f7333 MCC |
2017 | (x == DRX_FFTMODE_2K) ? "2k" : \ |
2018 | (x == DRX_FFTMODE_4K) ? "4k" : \ | |
2019 | (x == DRX_FFTMODE_8K) ? "8k" : \ | |
2020 | (x == DRX_FFTMODE_AUTO) ? "Auto" : \ | |
2021 | (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \ | |
2022 | "(Invalid)") | |
38b2df95 | 2023 | #define DRX_STR_GUARD(x) ( \ |
2f1f7333 MCC |
2024 | (x == DRX_GUARD_1DIV32) ? "1/32nd" : \ |
2025 | (x == DRX_GUARD_1DIV16) ? "1/16th" : \ | |
2026 | (x == DRX_GUARD_1DIV8) ? "1/8th" : \ | |
2027 | (x == DRX_GUARD_1DIV4) ? "1/4th" : \ | |
2028 | (x == DRX_GUARD_AUTO) ? "Auto" : \ | |
2029 | (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \ | |
2030 | "(Invalid)") | |
38b2df95 | 2031 | #define DRX_STR_CONSTELLATION(x) ( \ |
2f1f7333 MCC |
2032 | (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \ |
2033 | (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \ | |
2034 | (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \ | |
2035 | (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \ | |
2036 | (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \ | |
2037 | (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \ | |
2038 | (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \ | |
2039 | (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \ | |
2040 | (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \ | |
2041 | (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \ | |
2042 | (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \ | |
2043 | (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \ | |
2044 | (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \ | |
2045 | "(Invalid)") | |
38b2df95 | 2046 | #define DRX_STR_CODERATE(x) ( \ |
2f1f7333 MCC |
2047 | (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \ |
2048 | (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \ | |
2049 | (x == DRX_CODERATE_3DIV4) ? "3/4th" : \ | |
2050 | (x == DRX_CODERATE_5DIV6) ? "5/6th" : \ | |
2051 | (x == DRX_CODERATE_7DIV8) ? "7/8th" : \ | |
2052 | (x == DRX_CODERATE_AUTO) ? "Auto" : \ | |
2053 | (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \ | |
2054 | "(Invalid)") | |
38b2df95 | 2055 | #define DRX_STR_HIERARCHY(x) ( \ |
2f1f7333 MCC |
2056 | (x == DRX_HIERARCHY_NONE) ? "None" : \ |
2057 | (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \ | |
2058 | (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \ | |
2059 | (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \ | |
2060 | (x == DRX_HIERARCHY_AUTO) ? "Auto" : \ | |
2061 | (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \ | |
2062 | "(Invalid)") | |
38b2df95 | 2063 | #define DRX_STR_PRIORITY(x) ( \ |
2f1f7333 MCC |
2064 | (x == DRX_PRIORITY_LOW) ? "Low" : \ |
2065 | (x == DRX_PRIORITY_HIGH) ? "High" : \ | |
2066 | (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \ | |
2067 | "(Invalid)") | |
38b2df95 | 2068 | #define DRX_STR_MIRROR(x) ( \ |
2f1f7333 MCC |
2069 | (x == DRX_MIRROR_NO) ? "Normal" : \ |
2070 | (x == DRX_MIRROR_YES) ? "Mirrored" : \ | |
2071 | (x == DRX_MIRROR_AUTO) ? "Auto" : \ | |
2072 | (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \ | |
2073 | "(Invalid)") | |
38b2df95 | 2074 | #define DRX_STR_CLASSIFICATION(x) ( \ |
2f1f7333 MCC |
2075 | (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \ |
2076 | (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \ | |
2077 | (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \ | |
2078 | (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \ | |
2079 | (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \ | |
2080 | (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \ | |
2081 | (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \ | |
2082 | (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \ | |
2083 | "(Invalid)") | |
38b2df95 DH |
2084 | |
2085 | #define DRX_STR_INTERLEAVEMODE(x) ( \ | |
2f1f7333 MCC |
2086 | (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \ |
2087 | (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \ | |
2088 | (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \ | |
2089 | (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \ | |
2090 | (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \ | |
2091 | (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \ | |
2092 | (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \ | |
2093 | (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \ | |
2094 | (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \ | |
2095 | (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \ | |
2096 | (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \ | |
2097 | (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \ | |
2098 | (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \ | |
2099 | (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \ | |
2100 | (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \ | |
2101 | (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \ | |
2102 | (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \ | |
2103 | (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \ | |
2104 | (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \ | |
2105 | (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \ | |
2106 | (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \ | |
2107 | (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \ | |
2108 | (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \ | |
2109 | (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \ | |
2110 | "(Invalid)") | |
38b2df95 DH |
2111 | |
2112 | #define DRX_STR_LDPC(x) ( \ | |
2f1f7333 MCC |
2113 | (x == DRX_LDPC_0_4) ? "0.4" : \ |
2114 | (x == DRX_LDPC_0_6) ? "0.6" : \ | |
2115 | (x == DRX_LDPC_0_8) ? "0.8" : \ | |
2116 | (x == DRX_LDPC_AUTO) ? "Auto" : \ | |
2117 | (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \ | |
2118 | "(Invalid)") | |
38b2df95 DH |
2119 | |
2120 | #define DRX_STR_CARRIER(x) ( \ | |
2f1f7333 MCC |
2121 | (x == DRX_CARRIER_MULTI) ? "Multi" : \ |
2122 | (x == DRX_CARRIER_SINGLE) ? "Single" : \ | |
2123 | (x == DRX_CARRIER_AUTO) ? "Auto" : \ | |
2124 | (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \ | |
2125 | "(Invalid)") | |
38b2df95 DH |
2126 | |
2127 | #define DRX_STR_FRAMEMODE(x) ( \ | |
2f1f7333 MCC |
2128 | (x == DRX_FRAMEMODE_420) ? "420" : \ |
2129 | (x == DRX_FRAMEMODE_595) ? "595" : \ | |
2130 | (x == DRX_FRAMEMODE_945) ? "945" : \ | |
2131 | (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \ | |
2132 | (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \ | |
2133 | (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \ | |
2134 | (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \ | |
2135 | "(Invalid)") | |
38b2df95 DH |
2136 | |
2137 | #define DRX_STR_PILOT(x) ( \ | |
2f1f7333 MCC |
2138 | (x == DRX_PILOT_ON) ? "On" : \ |
2139 | (x == DRX_PILOT_OFF) ? "Off" : \ | |
2140 | (x == DRX_PILOT_AUTO) ? "Auto" : \ | |
2141 | (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \ | |
2142 | "(Invalid)") | |
38b2df95 DH |
2143 | /* TPS */ |
2144 | ||
2145 | #define DRX_STR_TPS_FRAME(x) ( \ | |
2f1f7333 MCC |
2146 | (x == DRX_TPS_FRAME1) ? "Frame1" : \ |
2147 | (x == DRX_TPS_FRAME2) ? "Frame2" : \ | |
2148 | (x == DRX_TPS_FRAME3) ? "Frame3" : \ | |
2149 | (x == DRX_TPS_FRAME4) ? "Frame4" : \ | |
2150 | (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \ | |
2151 | "(Invalid)") | |
38b2df95 DH |
2152 | |
2153 | /* lock status */ | |
2154 | ||
2155 | #define DRX_STR_LOCKSTATUS(x) ( \ | |
2f1f7333 MCC |
2156 | (x == DRX_NEVER_LOCK) ? "Never" : \ |
2157 | (x == DRX_NOT_LOCKED) ? "No" : \ | |
2158 | (x == DRX_LOCKED) ? "Locked" : \ | |
2159 | (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \ | |
2160 | (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \ | |
2161 | (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \ | |
2162 | (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \ | |
2163 | (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \ | |
2164 | (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \ | |
2165 | (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \ | |
2166 | (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \ | |
2167 | (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \ | |
2168 | "(Invalid)") | |
38b2df95 DH |
2169 | |
2170 | /* version information , modules */ | |
2171 | #define DRX_STR_MODULE(x) ( \ | |
2f1f7333 MCC |
2172 | (x == DRX_MODULE_DEVICE) ? "Device" : \ |
2173 | (x == DRX_MODULE_MICROCODE) ? "Microcode" : \ | |
2174 | (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \ | |
2175 | (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \ | |
2176 | (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \ | |
2177 | (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \ | |
2178 | (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \ | |
2179 | (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \ | |
2180 | (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \ | |
2181 | "(Invalid)") | |
38b2df95 DH |
2182 | |
2183 | #define DRX_STR_POWER_MODE(x) ( \ | |
2f1f7333 MCC |
2184 | (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \ |
2185 | (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \ | |
2186 | (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \ | |
2187 | (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \ | |
2188 | (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \ | |
2189 | (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \ | |
2190 | (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \ | |
2191 | (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \ | |
2192 | (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \ | |
2193 | (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \ | |
2194 | (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \ | |
2195 | (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \ | |
2196 | (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \ | |
2197 | (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \ | |
2198 | (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \ | |
2199 | (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \ | |
2200 | (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \ | |
2201 | (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \ | |
2202 | "(Invalid)") | |
38b2df95 DH |
2203 | |
2204 | #define DRX_STR_OOB_STANDARD(x) ( \ | |
2f1f7333 MCC |
2205 | (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \ |
2206 | (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \ | |
2207 | (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \ | |
2208 | "(Invalid)") | |
38b2df95 DH |
2209 | |
2210 | #define DRX_STR_AUD_STANDARD(x) ( \ | |
2f1f7333 MCC |
2211 | (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \ |
2212 | (x == DRX_AUD_STANDARD_A2) ? "A2" : \ | |
2213 | (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \ | |
2214 | (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \ | |
2215 | (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \ | |
2216 | (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \ | |
2217 | (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \ | |
2218 | (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \ | |
2219 | (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \ | |
2220 | (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \ | |
2221 | (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \ | |
2222 | (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \ | |
2223 | (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \ | |
2224 | (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \ | |
2225 | (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \ | |
2226 | (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \ | |
2227 | "(Invalid)") | |
38b2df95 | 2228 | #define DRX_STR_AUD_STEREO(x) ( \ |
2f1f7333 MCC |
2229 | (x == true) ? "Stereo" : \ |
2230 | (x == false) ? "Mono" : \ | |
2231 | "(Invalid)") | |
38b2df95 DH |
2232 | |
2233 | #define DRX_STR_AUD_SAP(x) ( \ | |
2f1f7333 MCC |
2234 | (x == true) ? "Present" : \ |
2235 | (x == false) ? "Not present" : \ | |
2236 | "(Invalid)") | |
38b2df95 DH |
2237 | |
2238 | #define DRX_STR_AUD_CARRIER(x) ( \ | |
2f1f7333 MCC |
2239 | (x == true) ? "Present" : \ |
2240 | (x == false) ? "Not present" : \ | |
2241 | "(Invalid)") | |
38b2df95 DH |
2242 | |
2243 | #define DRX_STR_AUD_RDS(x) ( \ | |
2f1f7333 MCC |
2244 | (x == true) ? "Available" : \ |
2245 | (x == false) ? "Not Available" : \ | |
2246 | "(Invalid)") | |
38b2df95 DH |
2247 | |
2248 | #define DRX_STR_AUD_NICAM_STATUS(x) ( \ | |
2f1f7333 MCC |
2249 | (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \ |
2250 | (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \ | |
2251 | (x == DRX_AUD_NICAM_BAD) ? "Bad" : \ | |
2252 | "(Invalid)") | |
38b2df95 DH |
2253 | |
2254 | #define DRX_STR_RDS_VALID(x) ( \ | |
2f1f7333 MCC |
2255 | (x == true) ? "Valid" : \ |
2256 | (x == false) ? "Not Valid" : \ | |
2257 | "(Invalid)") | |
38b2df95 DH |
2258 | |
2259 | /*------------------------------------------------------------------------- | |
2260 | Access macros | |
2261 | -------------------------------------------------------------------------*/ | |
2262 | ||
38b2df95 DH |
2263 | /** |
2264 | * \brief Create a compilable reference to the microcode attribute | |
2265 | * \param d pointer to demod instance | |
2266 | * | |
2267 | * Used as main reference to an attribute field. | |
2268 | * Used by both macro implementation and function implementation. | |
2269 | * These macros are defined to avoid duplication of code in macro and function | |
2270 | * definitions that handle access of demod common or extended attributes. | |
2271 | * | |
2272 | */ | |
2273 | ||
57afe2f0 MCC |
2274 | #define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion) |
2275 | #define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect) | |
2276 | #define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode) | |
2277 | #define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened) | |
2278 | #define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader) | |
2279 | #define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard) | |
2280 | #define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard) | |
2281 | #define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard) | |
2282 | #define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel) | |
2283 | #define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode) | |
57afe2f0 MCC |
2284 | #define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode) |
2285 | #define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities) | |
2286 | #define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id) | |
2287 | #define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq) | |
2288 | #define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq) | |
2289 | #define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol) | |
2290 | #define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol) | |
2291 | #define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode) | |
2292 | #define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr) | |
2293 | #define DRX_ATTR_TUNER(d) ((d)->my_tuner) | |
2294 | #define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr) | |
2295 | #define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) | |
38b2df95 DH |
2296 | #define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) |
2297 | ||
2298 | /**************************/ | |
2299 | ||
38b2df95 DH |
2300 | /* Macros with device-specific handling are converted to CFG functions */ |
2301 | ||
57afe2f0 | 2302 | #define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \ |
2f1f7333 MCC |
2303 | do { \ |
2304 | struct drx_cfg config; \ | |
2305 | data_type cfg_data; \ | |
2306 | config.cfg_type = cfg_name; \ | |
2307 | config.cfg_data = &cfg_data; \ | |
2308 | cfg_data = value; \ | |
2309 | drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \ | |
2310 | } while (0) | |
38b2df95 | 2311 | |
57afe2f0 | 2312 | #define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \ |
2f1f7333 MCC |
2313 | do { \ |
2314 | int cfg_status; \ | |
2315 | struct drx_cfg config; \ | |
2316 | data_type cfg_data; \ | |
2317 | config.cfg_type = cfg_name; \ | |
2318 | config.cfg_data = &cfg_data; \ | |
2319 | cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \ | |
2320 | if (cfg_status == 0) { \ | |
2321 | value = cfg_data; \ | |
2322 | } else { \ | |
2323 | value = (data_type)error_value; \ | |
2324 | } \ | |
2325 | } while (0) | |
38b2df95 | 2326 | |
38b2df95 DH |
2327 | /* Configuration functions for usage by Access (XS) Macros */ |
2328 | ||
2329 | #ifndef DRX_XS_CFG_BASE | |
2330 | #define DRX_XS_CFG_BASE (500) | |
2331 | #endif | |
2332 | ||
7ef66759 MCC |
2333 | #define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0) |
2334 | #define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1) | |
2335 | #define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2) | |
38b2df95 DH |
2336 | |
2337 | /* Access Macros with device-specific handling */ | |
2338 | ||
7ef66759 | 2339 | #define DRX_SET_PRESET(d, x) \ |
2f1f7333 | 2340 | DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*) |
7ef66759 | 2341 | #define DRX_GET_PRESET(d, x) \ |
2f1f7333 | 2342 | DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") |
38b2df95 | 2343 | |
22892268 | 2344 | #define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \ |
1bfc9e15 | 2345 | DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect) |
22892268 | 2346 | #define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \ |
1bfc9e15 | 2347 | DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect, DRX_UNKNOWN) |
38b2df95 | 2348 | |
22892268 | 2349 | #define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \ |
1bfc9e15 | 2350 | DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range) |
22892268 | 2351 | #define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \ |
1bfc9e15 | 2352 | DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN) |
38b2df95 | 2353 | |
38b2df95 DH |
2354 | /** |
2355 | * \brief Macro to check if std is an ATV standard | |
73f7065b MCC |
2356 | * \retval true std is an ATV standard |
2357 | * \retval false std is an ATV standard | |
38b2df95 | 2358 | */ |
1bfc9e15 | 2359 | #define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \ |
7ef66759 MCC |
2360 | ((std) == DRX_STANDARD_PAL_SECAM_DK) || \ |
2361 | ((std) == DRX_STANDARD_PAL_SECAM_I) || \ | |
2362 | ((std) == DRX_STANDARD_PAL_SECAM_L) || \ | |
2363 | ((std) == DRX_STANDARD_PAL_SECAM_LP) || \ | |
2364 | ((std) == DRX_STANDARD_NTSC) || \ | |
22892268 | 2365 | ((std) == DRX_STANDARD_FM)) |
38b2df95 DH |
2366 | |
2367 | /** | |
2368 | * \brief Macro to check if std is an QAM standard | |
73f7065b MCC |
2369 | * \retval true std is an QAM standards |
2370 | * \retval false std is an QAM standards | |
38b2df95 | 2371 | */ |
1bfc9e15 | 2372 | #define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \ |
7ef66759 MCC |
2373 | ((std) == DRX_STANDARD_ITU_B) || \ |
2374 | ((std) == DRX_STANDARD_ITU_C) || \ | |
2375 | ((std) == DRX_STANDARD_ITU_D)) | |
38b2df95 DH |
2376 | |
2377 | /** | |
2378 | * \brief Macro to check if std is VSB standard | |
73f7065b MCC |
2379 | * \retval true std is VSB standard |
2380 | * \retval false std is not VSB standard | |
38b2df95 | 2381 | */ |
22892268 | 2382 | #define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB) |
38b2df95 DH |
2383 | |
2384 | /** | |
2385 | * \brief Macro to check if std is DVBT standard | |
73f7065b MCC |
2386 | * \retval true std is DVBT standard |
2387 | * \retval false std is not DVBT standard | |
38b2df95 | 2388 | */ |
22892268 | 2389 | #define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT) |
38b2df95 | 2390 | |
38b2df95 DH |
2391 | /*------------------------------------------------------------------------- |
2392 | THE END | |
2393 | -------------------------------------------------------------------------*/ | |
443f18d0 | 2394 | #endif /* __DRXDRIVER_H__ */ |