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[media] drx-j: put under 3-clause BSD license
[deliverable/linux.git] / drivers / media / dvb-frontends / drx39xyj / drx_driver.h
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ca3355a9
DH		 1/*
2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright notice,
9 this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice,
11 this list of conditions and the following disclaimer in the documentation
12 and/or other materials provided with the distribution.
13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works
14 nor the names of its contributors may be used to endorse or promote
15 products derived from this software without specific prior written
16 permission.
17
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 POSSIBILITY OF SUCH DAMAGE.
29*/
30
38b2df95
DH		 31/**
32* \file $Id: drx_driver.h,v 1.84 2010/01/14 22:47:50 dingtao Exp $
33*
34* \brief DRX driver API
35*
38b2df95
DH		 36*/
37#ifndef __DRXDRIVER_H__
38#define __DRXDRIVER_H__
39/*-------------------------------------------------------------------------
40INCLUDES
41-------------------------------------------------------------------------*/
42#include "bsp_types.h"
43#include "bsp_i2c.h"
44#include "bsp_tuner.h"
45#include "bsp_host.h"
46
47#ifdef __cplusplus
48extern "C" {
49#endif
50/*-------------------------------------------------------------------------
51TYPEDEFS
52-------------------------------------------------------------------------*/
53
54/*-------------------------------------------------------------------------
55DEFINES
56-------------------------------------------------------------------------*/
57
58/**************
59*
60* This section configures the DRX Data Access Protocols (DAPs).
61*
62**************/
63
64/**
65* \def DRXDAP_SINGLE_MASTER
66* \brief Enable I2C single or I2C multimaster mode on host.
67*
68* Set to 1 to enable single master mode
69* Set to 0 to enable multi master mode
70*
71* The actual DAP implementation may be restricted to only one of the modes.
72* A compiler warning or error will be generated if the DAP implementation
73* overides or cannot handle the mode defined below.
74*
75*/
76#ifndef DRXDAP_SINGLE_MASTER
77#define DRXDAP_SINGLE_MASTER 0
78#endif
79
80/**
81* \def DRXDAP_MAX_WCHUNKSIZE
82* \brief Defines maximum chunksize of an i2c write action by host.
83*
84* This indicates the maximum size of data the I2C device driver is able to
85* write at a time. This includes I2C device address and register addressing.
86*
87* This maximum size may be restricted by the actual DAP implementation.
88* A compiler warning or error will be generated if the DAP implementation
89* overides or cannot handle the chunksize defined below.
90*
91* Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data
92* buffer. Do not undefine or choose too large, unless your system is able to
93* handle a stack buffer of that size.
94*
95*/
96#ifndef DRXDAP_MAX_WCHUNKSIZE
97#define DRXDAP_MAX_WCHUNKSIZE 60
98#endif
99
100/**
101* \def DRXDAP_MAX_RCHUNKSIZE
102* \brief Defines maximum chunksize of an i2c read action by host.
103*
104* This indicates the maximum size of data the I2C device driver is able to read
105* at a time. Minimum value is 2. Also, the read chunk size must be even.
106*
107* This maximum size may be restricted by the actual DAP implementation.
108* A compiler warning or error will be generated if the DAP implementation
109* overides or cannot handle the chunksize defined below.
110*
111*/
112#ifndef DRXDAP_MAX_RCHUNKSIZE
113#define DRXDAP_MAX_RCHUNKSIZE 60
114#endif
115
116/**************
117*
118* This section describes drxdriver defines.
119*
120**************/
121
122/**
123* \def DRX_UNKNOWN
124* \brief Generic UNKNOWN value for DRX enumerated types.
125*
126* Used to indicate that the parameter value is unknown or not yet initalized.
127*/
128#ifndef DRX_UNKNOWN
129#define DRX_UNKNOWN (254)
130#endif
131
132/**
133* \def DRX_AUTO
134* \brief Generic AUTO value for DRX enumerated types.
135*
136* Used to instruct the driver to automatically determine the value of the
137* parameter.
138*/
139#ifndef DRX_AUTO
140#define DRX_AUTO (255)
141#endif
142
143
144/**************
145*
146* This section describes flag definitions for the device capbilities.
147*
148**************/
149
150/**
151* \brief LNA capability flag
152*
153* Device has a Low Noise Amplifier
154*
155*/
156#define DRX_CAPABILITY_HAS_LNA (1UL << 0)
157/**
158* \brief OOB-RX capability flag
159*
160* Device has OOB-RX
161*
162*/
163#define DRX_CAPABILITY_HAS_OOBRX (1UL << 1)
164/**
165* \brief ATV capability flag
166*
167* Device has ATV
168*
169*/
170#define DRX_CAPABILITY_HAS_ATV (1UL << 2)
171/**
172* \brief DVB-T capability flag
173*
174* Device has DVB-T
175*
176*/
177#define DRX_CAPABILITY_HAS_DVBT (1UL << 3)
178/**
179* \brief ITU-B capability flag
180*
181* Device has ITU-B
182*
183*/
184#define DRX_CAPABILITY_HAS_ITUB (1UL << 4)
185/**
186* \brief Audio capability flag
187*
188* Device has Audio
189*
190*/
191#define DRX_CAPABILITY_HAS_AUD (1UL << 5)
192/**
193* \brief SAW switch capability flag
194*
195* Device has SAW switch
196*
197*/
198#define DRX_CAPABILITY_HAS_SAWSW (1UL << 6)
199/**
200* \brief GPIO1 capability flag
201*
202* Device has GPIO1
203*
204*/
205#define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7)
206/**
207* \brief GPIO2 capability flag
208*
209* Device has GPIO2
210*
211*/
212#define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8)
213/**
214* \brief IRQN capability flag
215*
216* Device has IRQN
217*
218*/
219#define DRX_CAPABILITY_HAS_IRQN (1UL << 9)
220/**
221* \brief 8VSB capability flag
222*
223* Device has 8VSB
224*
225*/
226#define DRX_CAPABILITY_HAS_8VSB (1UL << 10)
227/**
228* \brief SMA-TX capability flag
229*
230* Device has SMATX
231*
232*/
233#define DRX_CAPABILITY_HAS_SMATX (1UL << 11)
234/**
235* \brief SMA-RX capability flag
236*
237* Device has SMARX
238*
239*/
240#define DRX_CAPABILITY_HAS_SMARX (1UL << 12)
241/**
242* \brief ITU-A/C capability flag
243*
244* Device has ITU-A/C
245*
246*/
247#define DRX_CAPABILITY_HAS_ITUAC (1UL << 13)
248
249/*-------------------------------------------------------------------------
250MACROS
251-------------------------------------------------------------------------*/
252/* Macros to stringify the version number */
253#define DRX_VERSIONSTRING( MAJOR, MINOR, PATCH ) \
254 DRX_VERSIONSTRING_HELP(MAJOR)"." \
255 DRX_VERSIONSTRING_HELP(MINOR)"." \
256 DRX_VERSIONSTRING_HELP(PATCH)
257#define DRX_VERSIONSTRING_HELP( NUM ) #NUM
258
259/**
260* \brief Macro to create byte array elements from 16 bit integers.
261* This macro is used to create byte arrays for block writes.
262* Block writes speed up I2C traffic between host and demod.
263* The macro takes care of the required byte order in a 16 bits word.
264* x->lowbyte(x), highbyte(x)
265*/
266#define DRX_16TO8( x ) ((u8_t) (((u16_t)x) &0xFF)), \
267 ((u8_t)((((u16_t)x)>>8)&0xFF))
268
269/**
270* \brief Macro to sign extend signed 9 bit value to signed 16 bit value
271*/
272#define DRX_S9TOS16(x) ((((u16_t)x)&0x100 )?((s16_t)((u16_t)(x)|0xFF00)):(x))
273
274/**
275* \brief Macro to sign extend signed 9 bit value to signed 16 bit value
276*/
277#define DRX_S24TODRXFREQ(x) ( ( ( (u32_t) x ) & 0x00800000UL ) ? \
278 ( (DRXFrequency_t) \
279 ( ( (u32_t) x ) | 0xFF000000 ) ) : \
280 ( (DRXFrequency_t) x ) )
281
282/**
283* \brief Macro to convert 16 bit register value to a DRXFrequency_t
284*/
285#define DRX_U16TODRXFREQ(x) ( ( x & 0x8000 ) ? \
286 ( (DRXFrequency_t) \
287 ( ( (u32_t) x ) | 0xFFFF0000 ) ) : \
288 ( (DRXFrequency_t) x ) )
289
290/*-------------------------------------------------------------------------
291ENUM
292-------------------------------------------------------------------------*/
293
294/**
295* \enum DRXStandard_t
296* \brief Modulation standards.
297*/
298typedef enum {
299 DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */
300 DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */
301 DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */
302 DRX_STANDARD_PAL_SECAM_BG, /**< Terrestrial analog PAL/SECAM B/G */
303 DRX_STANDARD_PAL_SECAM_DK, /**< Terrestrial analog PAL/SECAM D/K */
304 DRX_STANDARD_PAL_SECAM_I, /**< Terrestrial analog PAL/SECAM I */
305 DRX_STANDARD_PAL_SECAM_L, /**< Terrestrial analog PAL/SECAM L
306 with negative modulation */
307 DRX_STANDARD_PAL_SECAM_LP, /**< Terrestrial analog PAL/SECAM L
308 with positive modulation */
309 DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */
310 DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */
311 DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */
312 DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */
313 DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */
314 DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/
315 DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, /**< Standard unknown. */
316 DRX_STANDARD_AUTO = DRX_AUTO /**< Autodetect standard. */
317} DRXStandard_t, *pDRXStandard_t;
318
319/**
320* \enum DRXStandard_t
321* \brief Modulation sub-standards.
322*/
323typedef enum {
324 DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */
325 DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA,
326 DRX_SUBSTANDARD_ATV_DK_POLAND,
327 DRX_SUBSTANDARD_ATV_DK_CHINA,
328 DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, /**< Sub-standard unknown. */
329 DRX_SUBSTANDARD_AUTO = DRX_AUTO /**< Auto (default) sub-standard */
330} DRXSubstandard_t, *pDRXSubstandard_t;
331
332/**
333* \enum DRXBandwidth_t
334* \brief Channel bandwidth or channel spacing.
335*/
336typedef enum {
337 DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */
338 DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */
339 DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */
340 DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, /**< Bandwidth unknown. */
341 DRX_BANDWIDTH_AUTO = DRX_AUTO /**< Auto Set Bandwidth */
342} DRXBandwidth_t, *pDRXBandwidth_t;
343
344/**
345* \enum DRXMirror_t
346* \brief Indicate if channel spectrum is mirrored or not.
347*/
348typedef enum {
349 DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */
350 DRX_MIRROR_YES, /**< Spectrum is mirrored. */
351 DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, /**< Unknown if spectrum is mirrored. */
352 DRX_MIRROR_AUTO = DRX_AUTO /**< Autodetect if spectrum is mirrored. */
353} DRXMirror_t, *pDRXMirror_t;
354
355/**
356* \enum DRXConstellation_t
357* \brief Constellation type of the channel.
358*/
359typedef enum {
360 DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */
361 DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */
362 DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */
363 DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */
364 DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */
365 DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */
366 DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */
367 DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */
368 DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */
369 DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */
370 DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */
371 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, /**< Constellation unknown. */
372 DRX_CONSTELLATION_AUTO = DRX_AUTO /**< Autodetect constellation. */
373} DRXConstellation_t, *pDRXConstellation_t;
374
375/**
376* \enum DRXHierarchy_t
377* \brief Hierarchy of the channel.
378*/
379typedef enum {
380 DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */
381 DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */
382 DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */
383 DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */
384 DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, /**< Hierarchy unknown. */
385 DRX_HIERARCHY_AUTO = DRX_AUTO /**< Autodetect hierarchy. */
386} DRXHierarchy_t, *pDRXHierarchy_t;
387
388/**
389* \enum DRXPriority_t
390* \brief Channel priority in case of hierarchical transmission.
391*/
392typedef enum {
393 DRX_PRIORITY_LOW = 0, /**< Low priority channel. */
394 DRX_PRIORITY_HIGH, /**< High priority channel. */
395 DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN /**< Priority unknown. */
396} DRXPriority_t, *pDRXPriority_t;
397
398/**
399* \enum DRXCoderate_t
400* \brief Channel priority in case of hierarchical transmission.
401*/
402typedef enum {
403 DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */
404 DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */
405 DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */
406 DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */
407 DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */
408 DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, /**< Code rate unknown. */
409 DRX_CODERATE_AUTO = DRX_AUTO /**< Autodetect code rate. */
410} DRXCoderate_t, *pDRXCoderate_t;
411
412/**
413* \enum DRXGuard_t
414* \brief Guard interval of a channel.
415*/
416typedef enum {
417 DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */
418 DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */
419 DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */
420 DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */
421 DRX_GUARD_UNKNOWN = DRX_UNKNOWN, /**< Guard interval unknown. */
422 DRX_GUARD_AUTO = DRX_AUTO /**< Autodetect guard interval. */
423} DRXGuard_t, *pDRXGuard_t;
424
425/**
426* \enum DRXFftmode_t
427* \brief FFT mode.
428*/
429typedef enum {
430 DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */
431 DRX_FFTMODE_4K, /**< 4K FFT mode. */
432 DRX_FFTMODE_8K, /**< 8K FFT mode. */
433 DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, /**< FFT mode unknown. */
434 DRX_FFTMODE_AUTO = DRX_AUTO /**< Autodetect FFT mode. */
435} DRXFftmode_t, *pDRXFftmode_t;
436
437/**
438* \enum DRXClassification_t
439* \brief Channel classification.
440*/
441typedef enum {
442 DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */
443 DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */
444 DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */
445 DRX_CLASSIFICATION_STATIC, /**< Static echo. */
446 DRX_CLASSIFICATION_MOVING, /**< Moving echo. */
447 DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */
448 DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, /**< Unknown classification */
449 DRX_CLASSIFICATION_AUTO = DRX_AUTO /**< Autodetect classification. */
450} DRXClassification_t, *pDRXClassification_t;
451
452/**
453* /enum DRXInterleaveModes_t
454* /brief Interleave modes
455*/
456typedef enum {
457 DRX_INTERLEAVEMODE_I128_J1 = 0,
458 DRX_INTERLEAVEMODE_I128_J1_V2,
459 DRX_INTERLEAVEMODE_I128_J2,
460 DRX_INTERLEAVEMODE_I64_J2,
461 DRX_INTERLEAVEMODE_I128_J3,
462 DRX_INTERLEAVEMODE_I32_J4,
463 DRX_INTERLEAVEMODE_I128_J4,
464 DRX_INTERLEAVEMODE_I16_J8,
465 DRX_INTERLEAVEMODE_I128_J5,
466 DRX_INTERLEAVEMODE_I8_J16,
467 DRX_INTERLEAVEMODE_I128_J6,
468 DRX_INTERLEAVEMODE_RESERVED_11,
469 DRX_INTERLEAVEMODE_I128_J7,
470 DRX_INTERLEAVEMODE_RESERVED_13,
471 DRX_INTERLEAVEMODE_I128_J8,
472 DRX_INTERLEAVEMODE_RESERVED_15,
473 DRX_INTERLEAVEMODE_I12_J17,
474 DRX_INTERLEAVEMODE_I5_J4,
475 DRX_INTERLEAVEMODE_B52_M240,
476 DRX_INTERLEAVEMODE_B52_M720,
477 DRX_INTERLEAVEMODE_B52_M48,
478 DRX_INTERLEAVEMODE_B52_M0,
479 DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, /**< Unknown interleave mode */
480 DRX_INTERLEAVEMODE_AUTO = DRX_AUTO /**< Autodetect interleave mode */
481} DRXInterleaveModes_t, *pDRXInterleaveModes_t;
482
483/**
484* \enum DRXCarrier_t
485* \brief Channel Carrier Mode.
486*/
487typedef enum {
488 DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */
489 DRX_CARRIER_SINGLE, /**< Single carrier mode */
490 DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, /**< Carrier mode unknown. */
491 DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */
492} DRXCarrier_t, *pDRXCarrier_t;
493
494/**
495* \enum DRXFramemode_t
496* \brief Channel Frame Mode.
497*/
498typedef enum {
499 DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */
500 DRX_FRAMEMODE_595, /**< 595 */
501 DRX_FRAMEMODE_945, /**< 945 with variable PN */
502 DRX_FRAMEMODE_420_FIXED_PN, /**< 420 with fixed PN */
503 DRX_FRAMEMODE_945_FIXED_PN, /**< 945 with fixed PN */
504 DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, /**< Frame mode unknown. */
505 DRX_FRAMEMODE_AUTO = DRX_AUTO /**< Autodetect frame mode */
506} DRXFramemode_t, *pDRXFramemode_t;
507
508/**
509* \enum DRXTPSFrame_t
510* \brief Frame number in current super-frame.
511*/
512typedef enum {
513 DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */
514 DRX_TPS_FRAME2, /**< TPS frame 2. */
515 DRX_TPS_FRAME3, /**< TPS frame 3. */
516 DRX_TPS_FRAME4, /**< TPS frame 4. */
517 DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN /**< TPS frame unknown. */
518} DRXTPSFrame_t, *pDRXTPSFrame_t;
519
520/**
521* \enum DRXLDPC_t
522* \brief TPS LDPC .
523*/
524typedef enum {
525 DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */
526 DRX_LDPC_0_6, /**< LDPC 0.6 */
527 DRX_LDPC_0_8, /**< LDPC 0.8 */
528 DRX_LDPC_UNKNOWN = DRX_UNKNOWN, /**< LDPC unknown. */
529 DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */
530} DRXLDPC_t, *pDRXLDPC_t;
531
532/**
533* \enum DRXPilotMode_t
534* \brief Pilot modes in DTMB.
535*/
536typedef enum {
537 DRX_PILOT_ON = 0, /**< Pilot On */
538 DRX_PILOT_OFF, /**< Pilot Off */
539 DRX_PILOT_UNKNOWN = DRX_UNKNOWN, /**< Pilot unknown. */
540 DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */
541} DRXPilotMode_t, *pDRXPilotMode_t;
542
543
544
545/**
546* \enum DRXCtrlIndex_t
547* \brief Indices of the control functions.
548*/
549typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t;
550
551#ifndef DRX_CTRL_BASE
552#define DRX_CTRL_BASE ((DRXCtrlIndex_t)0)
553#endif
554
555#define DRX_CTRL_NOP ( DRX_CTRL_BASE + 0)/**< No Operation */
556#define DRX_CTRL_PROBE_DEVICE ( DRX_CTRL_BASE + 1)/**< Probe device */
557
558#define DRX_CTRL_LOAD_UCODE ( DRX_CTRL_BASE + 2)/**< Load microcode */
559#define DRX_CTRL_VERIFY_UCODE ( DRX_CTRL_BASE + 3)/**< Verify microcode */
560#define DRX_CTRL_SET_CHANNEL ( DRX_CTRL_BASE + 4)/**< Set channel */
561#define DRX_CTRL_GET_CHANNEL ( DRX_CTRL_BASE + 5)/**< Get channel */
562#define DRX_CTRL_LOCK_STATUS ( DRX_CTRL_BASE + 6)/**< Get lock status */
563#define DRX_CTRL_SIG_QUALITY ( DRX_CTRL_BASE + 7)/**< Get signal quality */
564#define DRX_CTRL_SIG_STRENGTH ( DRX_CTRL_BASE + 8)/**< Get signal strength*/
565#define DRX_CTRL_RF_POWER ( DRX_CTRL_BASE + 9)/**< Get RF power */
566#define DRX_CTRL_CONSTEL ( DRX_CTRL_BASE + 10)/**< Get constel point */
567#define DRX_CTRL_SCAN_INIT ( DRX_CTRL_BASE + 11)/**< Initialize scan */
568#define DRX_CTRL_SCAN_NEXT ( DRX_CTRL_BASE + 12)/**< Scan for next */
569#define DRX_CTRL_SCAN_STOP ( DRX_CTRL_BASE + 13)/**< Stop scan */
570#define DRX_CTRL_TPS_INFO ( DRX_CTRL_BASE + 14)/**< Get TPS info */
571#define DRX_CTRL_SET_CFG ( DRX_CTRL_BASE + 15)/**< Set configuration */
572#define DRX_CTRL_GET_CFG ( DRX_CTRL_BASE + 16)/**< Get configuration */
573#define DRX_CTRL_VERSION ( DRX_CTRL_BASE + 17)/**< Get version info */
574#define DRX_CTRL_I2C_BRIDGE ( DRX_CTRL_BASE + 18)/**< Open/close bridge */
575#define DRX_CTRL_SET_STANDARD ( DRX_CTRL_BASE + 19)/**< Set demod std */
576#define DRX_CTRL_GET_STANDARD ( DRX_CTRL_BASE + 20)/**< Get demod std */
577#define DRX_CTRL_SET_OOB ( DRX_CTRL_BASE + 21)/**< Set OOB param */
578#define DRX_CTRL_GET_OOB ( DRX_CTRL_BASE + 22)/**< Get OOB param */
579#define DRX_CTRL_AUD_SET_STANDARD (DRX_CTRL_BASE + 23)/**< Set audio param */
580#define DRX_CTRL_AUD_GET_STANDARD (DRX_CTRL_BASE + 24)/**< Get audio param */
581#define DRX_CTRL_AUD_GET_STATUS ( DRX_CTRL_BASE + 25)/**< Read RDS */
582#define DRX_CTRL_AUD_BEEP ( DRX_CTRL_BASE + 26)/**< Read RDS */
583#define DRX_CTRL_I2C_READWRITE ( DRX_CTRL_BASE + 27)/**< Read/write I2C */
584#define DRX_CTRL_PROGRAM_TUNER ( DRX_CTRL_BASE + 28)/**< Program tuner */
585
586 /* Professional */
587#define DRX_CTRL_MB_CFG ( DRX_CTRL_BASE + 29) /**< */
588#define DRX_CTRL_MB_READ ( DRX_CTRL_BASE + 30) /**< */
589#define DRX_CTRL_MB_WRITE ( DRX_CTRL_BASE + 31) /**< */
590#define DRX_CTRL_MB_CONSTEL ( DRX_CTRL_BASE + 32) /**< */
591#define DRX_CTRL_MB_MER ( DRX_CTRL_BASE + 33) /**< */
592
593 /* Misc */
594#define DRX_CTRL_UIO_CFG DRX_CTRL_SET_UIO_CFG /**< Configure UIO */
595#define DRX_CTRL_SET_UIO_CFG ( DRX_CTRL_BASE + 34) /**< Configure UIO */
596#define DRX_CTRL_GET_UIO_CFG ( DRX_CTRL_BASE + 35) /**< Configure UIO */
597#define DRX_CTRL_UIO_READ ( DRX_CTRL_BASE + 36) /**< Read from UIO */
598#define DRX_CTRL_UIO_WRITE ( DRX_CTRL_BASE + 37) /**< Write to UIO */
599#define DRX_CTRL_READ_EVENTS ( DRX_CTRL_BASE + 38) /**< Read events */
600#define DRX_CTRL_HDL_EVENTS ( DRX_CTRL_BASE + 39) /**< Handle events */
601#define DRX_CTRL_POWER_MODE ( DRX_CTRL_BASE + 40) /**< Set power mode */
602#define DRX_CTRL_LOAD_FILTER ( DRX_CTRL_BASE + 41) /**< Load chan. filter */
603#define DRX_CTRL_VALIDATE_UCODE ( DRX_CTRL_BASE + 42) /**< Validate ucode */
604#define DRX_CTRL_DUMP_REGISTERS ( DRX_CTRL_BASE + 43) /**< Dump registers */
605
606#define DRX_CTRL_MAX ( DRX_CTRL_BASE + 44) /* never to be used */
607
608/**
609* \enum DRXUCodeAction_t
610* \brief Used to indicate if firmware has to be uploaded or verified.
611*/
612
613typedef enum {
614 UCODE_UPLOAD, /**< Upload the microcode image to device */
615 UCODE_VERIFY /**< Compare microcode image with code on device */
616} DRXUCodeAction_t, *pDRXUCodeAction_t;
617
618
619/**
620* \enum DRXLockStatus_t
621* \brief Used to reflect current lock status of demodulator.
622*
623* The generic lock states have device dependent semantics.
624*/
625typedef enum{
626 DRX_NEVER_LOCK = 0, /**< Device will never lock on this signal */
627 DRX_NOT_LOCKED, /**< Device has no lock at all */
628 DRX_LOCK_STATE_1, /**< Generic lock state */
629 DRX_LOCK_STATE_2, /**< Generic lock state */
630 DRX_LOCK_STATE_3, /**< Generic lock state */
631 DRX_LOCK_STATE_4, /**< Generic lock state */
632 DRX_LOCK_STATE_5, /**< Generic lock state */
633 DRX_LOCK_STATE_6, /**< Generic lock state */
634 DRX_LOCK_STATE_7, /**< Generic lock state */
635 DRX_LOCK_STATE_8, /**< Generic lock state */
636 DRX_LOCK_STATE_9, /**< Generic lock state */
637 DRX_LOCKED /**< Device is in lock */
638} DRXLockStatus_t, *pDRXLockStatus_t;
639
640/**
641* \enum DRXUIO_t
642* \brief Used to address a User IO (UIO).
643*/
644typedef enum{
645 DRX_UIO1 ,
646 DRX_UIO2 ,
647 DRX_UIO3 ,
648 DRX_UIO4 ,
649 DRX_UIO5 ,
650 DRX_UIO6 ,
651 DRX_UIO7 ,
652 DRX_UIO8 ,
653 DRX_UIO9 ,
654 DRX_UIO10 ,
655 DRX_UIO11 ,
656 DRX_UIO12 ,
657 DRX_UIO13 ,
658 DRX_UIO14 ,
659 DRX_UIO15 ,
660 DRX_UIO16 ,
661 DRX_UIO17 ,
662 DRX_UIO18 ,
663 DRX_UIO19 ,
664 DRX_UIO20 ,
665 DRX_UIO21 ,
666 DRX_UIO22 ,
667 DRX_UIO23 ,
668 DRX_UIO24 ,
669 DRX_UIO25 ,
670 DRX_UIO26 ,
671 DRX_UIO27 ,
672 DRX_UIO28 ,
673 DRX_UIO29 ,
674 DRX_UIO30 ,
675 DRX_UIO31 ,
676 DRX_UIO32 ,
677 DRX_UIO_MAX = DRX_UIO32
678} DRXUIO_t, *pDRXUIO_t;
679
680/**
681* \enum DRXUIOMode_t
682* \brief Used to configure the modus oprandi of a UIO.
683*
684* DRX_UIO_MODE_FIRMWARE is an old uio mode.
685* It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9.
686* To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to
687* DRX_UIO_MODE_FIRMWARE0.
688*/
689typedef enum{
690 DRX_UIO_MODE_DISABLE = 0x01, /**< not used, pin is configured as input */
691 DRX_UIO_MODE_READWRITE = 0x02, /**< used for read/write by application */
692 DRX_UIO_MODE_FIRMWARE = 0x04, /**< controlled by firmware, function 0 */
693 DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE , /**< same as above */
694 DRX_UIO_MODE_FIRMWARE1 = 0x08, /**< controlled by firmware, function 1 */
695 DRX_UIO_MODE_FIRMWARE2 = 0x10, /**< controlled by firmware, function 2 */
696 DRX_UIO_MODE_FIRMWARE3 = 0x20, /**< controlled by firmware, function 3 */
697 DRX_UIO_MODE_FIRMWARE4 = 0x40, /**< controlled by firmware, function 4 */
698 DRX_UIO_MODE_FIRMWARE5 = 0x80 /**< controlled by firmware, function 5 */
699} DRXUIOMode_t, *pDRXUIOMode_t;
700
701/**
702* \enum DRXOOBDownstreamStandard_t
703* \brief Used to select OOB standard.
704*
705* Based on ANSI 55-1 and 55-2
706*/
707typedef enum {
708 DRX_OOB_MODE_A = 0, /**< ANSI 55-1 */
709 DRX_OOB_MODE_B_GRADE_A, /**< ANSI 55-2 A */
710 DRX_OOB_MODE_B_GRADE_B /**< ANSI 55-2 B */
711} DRXOOBDownstreamStandard_t, *pDRXOOBDownstreamStandard_t;
712
713
714/*-------------------------------------------------------------------------
715STRUCTS
716-------------------------------------------------------------------------*/
717
718/*============================================================================*/
719/*============================================================================*/
720/*== CTRL CFG related data structures ========================================*/
721/*============================================================================*/
722/*============================================================================*/
723
724/**
725* \enum DRXCfgType_t
726* \brief Generic configuration function identifiers.
727*/
728typedef u32_t DRXCfgType_t, *pDRXCfgType_t;
729
730#ifndef DRX_CFG_BASE
731#define DRX_CFG_BASE ((DRXCfgType_t)0)
732#endif
733
734#define DRX_CFG_MPEG_OUTPUT ( DRX_CFG_BASE + 0) /* MPEG TS output */
735#define DRX_CFG_PKTERR ( DRX_CFG_BASE + 1) /* Packet Error */
736#define DRX_CFG_SYMCLK_OFFS ( DRX_CFG_BASE + 2) /* Symbol Clk Offset */
737#define DRX_CFG_SMA ( DRX_CFG_BASE + 3) /* Smart Antenna */
738#define DRX_CFG_PINSAFE ( DRX_CFG_BASE + 4) /* Pin safe mode */
739#define DRX_CFG_SUBSTANDARD ( DRX_CFG_BASE + 5) /* substandard */
740#define DRX_CFG_AUD_VOLUME ( DRX_CFG_BASE + 6) /* volume */
741#define DRX_CFG_AUD_RDS ( DRX_CFG_BASE + 7) /* rds */
742#define DRX_CFG_AUD_AUTOSOUND ( DRX_CFG_BASE + 8) /* ASS & ASC */
743#define DRX_CFG_AUD_ASS_THRES ( DRX_CFG_BASE + 9) /* ASS Thresholds */
744#define DRX_CFG_AUD_DEVIATION ( DRX_CFG_BASE + 10) /* Deviation */
745#define DRX_CFG_AUD_PRESCALE ( DRX_CFG_BASE + 11) /* Prescale */
746#define DRX_CFG_AUD_MIXER ( DRX_CFG_BASE + 12) /* Mixer */
747#define DRX_CFG_AUD_AVSYNC ( DRX_CFG_BASE + 13) /* AVSync */
748#define DRX_CFG_AUD_CARRIER ( DRX_CFG_BASE + 14) /* Audio carriers */
749#define DRX_CFG_I2S_OUTPUT ( DRX_CFG_BASE + 15) /* I2S output */
750#define DRX_CFG_ATV_STANDARD ( DRX_CFG_BASE + 16) /* ATV standard */
751#define DRX_CFG_SQI_SPEED ( DRX_CFG_BASE + 17) /* SQI speed */
752#define DRX_CTRL_CFG_MAX ( DRX_CFG_BASE + 18) /* never to be used */
753
754#define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE
755/*============================================================================*/
756/*============================================================================*/
757/*== CTRL related data structures ============================================*/
758/*============================================================================*/
759/*============================================================================*/
760
761/**
762* \struct DRXUCodeInfo_t
763* \brief Parameters for microcode upload and verfiy.
764*
765* Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE
766*/
767typedef struct {
768 pu8_t mcData; /**< Pointer to microcode image. */
769 u16_t mcSize; /**< Microcode image size. */
770} DRXUCodeInfo_t, *pDRXUCodeInfo_t;
771
772/**
773* \struct DRXMcVersionRec_t
774* \brief Microcode version record
775* Version numbers are stored in BCD format, as usual:
776* o major number = bits 31-20 (first three nibbles of MSW)
777* o minor number = bits 19-16 (fourth nibble of MSW)
778* o patch number = bits 15-0 (remaining nibbles in LSW)
779*
780* The device type indicates for which the device is meant. It is based on the
781* JTAG ID, using everything except the bond ID and the metal fix.
782*
783* Special values:
784* - mcDevType == 0 => any device allowed
785* - mcBaseVersion == 0.0.0 => full microcode (mcVersion is the version)
786* - mcBaseVersion != 0.0.0 => patch microcode, the base microcode version
787* (mcVersion is the version)
788*/
789#define AUX_VER_RECORD 0x8000
790
791typedef struct {
792 u16_t auxType; /* type of aux data - 0x8000 for version record */
793 u32_t mcDevType; /* device type, based on JTAG ID */
794 u32_t mcVersion; /* version of microcode */
795 u32_t mcBaseVersion; /* in case of patch: the original microcode version */
796} DRXMcVersionRec_t, *pDRXMcVersionRec_t;
797
798/*========================================*/
799
800/**
801* \struct DRXFilterInfo_t
802* \brief Parameters for loading filter coefficients
803*
804* Used by DRX_CTRL_LOAD_FILTER
805*/
806typedef struct {
807 pu8_t dataRe; /**< pointer to coefficients for RE */
808 pu8_t dataIm; /**< pointer to coefficients for IM */
809 u16_t sizeRe; /**< size of coefficients for RE */
810 u16_t sizeIm; /**< size of coefficients for IM */
811} DRXFilterInfo_t, *pDRXFilterInfo_t;
812
813
814
815/*========================================*/
816
817/**
818* \struct DRXChannel_t
819* \brief The set of parameters describing a single channel.
820*
821* Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL.
822* Only certain fields need to be used for a specfic standard.
823*
824*/
825typedef struct {
826 DRXFrequency_t frequency; /**< frequency in kHz */
827 DRXBandwidth_t bandwidth; /**< bandwidth */
828 DRXMirror_t mirror; /**< mirrored or not on RF */
829 DRXConstellation_t constellation; /**< constellation */
830 DRXHierarchy_t hierarchy; /**< hierarchy */
831 DRXPriority_t priority; /**< priority */
832 DRXCoderate_t coderate; /**< coderate */
833 DRXGuard_t guard; /**< guard interval */
834 DRXFftmode_t fftmode; /**< fftmode */
835 DRXClassification_t classification; /**< classification */
836 DRXSymbolrate_t symbolrate; /**< symbolrate in symbols/sec */
837 DRXInterleaveModes_t interleavemode; /**< interleaveMode QAM */
838 DRXLDPC_t ldpc; /**< ldpc */
839 DRXCarrier_t carrier; /**< carrier */
840 DRXFramemode_t framemode; /**< frame mode */
841 DRXPilotMode_t pilot; /**< pilot mode */
842} DRXChannel_t, *pDRXChannel_t;
843
844/*========================================*/
845
846/**
847* \struct DRXSigQuality_t
848* Signal quality metrics.
849*
850* Used by DRX_CTRL_SIG_QUALITY.
851*/
852typedef struct {
853 u16_t MER; /**< in steps of 0.1 dB */
854 u32_t preViterbiBER ; /**< in steps of 1/scaleFactorBER */
855 u32_t postViterbiBER ; /**< in steps of 1/scaleFactorBER */
856 u32_t scaleFactorBER; /**< scale factor for BER */
857 u16_t packetError ; /**< number of packet errors */
858 u32_t postReedSolomonBER ; /**< in steps of 1/scaleFactorBER */
859 u32_t preLdpcBER; /**< in steps of 1/scaleFactorBER */
860 u32_t averIter; /**< in steps of 0.01 */
861 u16_t indicator; /**< indicative signal quality low=0..100=high */
862}DRXSigQuality_t, *pDRXSigQuality_t;
863
864
865typedef enum {
866 DRX_SQI_SPEED_FAST = 0,
867 DRX_SQI_SPEED_MEDIUM,
868 DRX_SQI_SPEED_SLOW,
869 DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
870} DRXCfgSqiSpeed_t, *pDRXCfgSqiSpeed_t;
871
872/*========================================*/
873
874/**
875* \struct DRXComplex_t
876* A complex number.
877*
878* Used by DRX_CTRL_CONSTEL.
879*/
880typedef struct {
881 s16_t im; /**< Imaginary part. */
882 s16_t re; /**< Real part. */
883} DRXComplex_t, *pDRXComplex_t;
884
885
886/*========================================*/
887
888/**
889* \struct DRXFrequencyPlan_t
890* Array element of a frequency plan.
891*
892* Used by DRX_CTRL_SCAN_INIT.
893*/
894typedef struct {
895 DRXFrequency_t first; /**< First centre frequency in this band */
896 DRXFrequency_t last; /**< Last centre frequency in this band */
897 DRXFrequency_t step; /**< Stepping frequency in this band */
898 DRXBandwidth_t bandwidth; /**< Bandwidth within this frequency band */
899 u16_t chNumber; /**< First channel number in this band, or first
900 index in chNames */
901 char **chNames; /**< Optional list of channel names in this
902 band */
903} DRXFrequencyPlan_t, *pDRXFrequencyPlan_t;
904
905/*========================================*/
906
907/**
908* \struct DRXFrequencyPlanInfo_t
909* Array element of a list of frequency plans.
910*
911* Used by frequency_plan.h
912*/
913typedef struct{
914 pDRXFrequencyPlan_t freqPlan;
915 int freqPlanSize;
916 char *freqPlanName;
917}DRXFrequencyPlanInfo_t, *pDRXFrequencyPlanInfo_t;
918
919/*========================================*/
920
921/**
922* /struct DRXScanDataQam_t
923* QAM specific scanning variables
924*/
925typedef struct {
926 pu32_t symbolrate; /**< list of symbolrates to scan */
927 u16_t symbolrateSize; /**< size of symbolrate array */
928 pDRXConstellation_t constellation; /**< list of constellations */
929 u16_t constellationSize; /**< size of constellation array */
930 u16_t ifAgcThreshold; /**< thresholf for IF-AGC based
931 scanning filter */
932} DRXScanDataQam_t, *pDRXScanDataQam_t;
933
934/*========================================*/
935
936/**
937* /struct DRXScanDataAtv_t
938* ATV specific scanning variables
939*/
940typedef struct {
941 s16_t svrThreshold; /**< threshold of Sound/Video ratio in 0.1dB steps */
942} DRXScanDataAtv_t, *pDRXScanDataAtv_t;
943
944/*========================================*/
945
946/**
947* \struct DRXScanParam_t
948* Parameters for channel scan.
949*
950* Used by DRX_CTRL_SCAN_INIT.
951*/
952typedef struct {
953 pDRXFrequencyPlan_t frequencyPlan; /**< Frequency plan (array)*/
954 u16_t frequencyPlanSize; /**< Number of bands */
955 u32_t numTries; /**< Max channels tried */
956 DRXFrequency_t skip; /**< Minimum frequency step to take
957 after a channel is found */
958 void *extParams; /**< Standard specific params */
959} DRXScanParam_t, *pDRXScanParam_t;
960
961/*========================================*/
962
963/**
964* \brief Scan commands.
965* Used by scanning algorithms.
966*/
967typedef enum {
968 DRX_SCAN_COMMAND_INIT = 0, /**< Initialize scanning */
969 DRX_SCAN_COMMAND_NEXT, /**< Next scan */
970 DRX_SCAN_COMMAND_STOP /**< Stop scanning */
971}DRXScanCommand_t, *pDRXScanCommand_t;
972
973/*========================================*/
974
975/**
976* \brief Inner scan function prototype.
977*/
978typedef DRXStatus_t (*DRXScanFunc_t) (void* scanContext,
979 DRXScanCommand_t scanCommand,
980 pDRXChannel_t scanChannel,
981 pBool_t getNextChannel );
982
983/*========================================*/
984
985/**
986* \struct DRXTPSInfo_t
987* TPS information, DVB-T specific.
988*
989* Used by DRX_CTRL_TPS_INFO.
990*/
991typedef struct {
992 DRXFftmode_t fftmode; /**< Fft mode */
993 DRXGuard_t guard; /**< Guard interval */
994 DRXConstellation_t constellation; /**< Constellation */
995 DRXHierarchy_t hierarchy; /**< Hierarchy */
996 DRXCoderate_t highCoderate; /**< High code rate */
997 DRXCoderate_t lowCoderate; /**< Low cod rate */
998 DRXTPSFrame_t frame; /**< Tps frame */
999 u8_t length; /**< Length */
1000 u16_t cellId; /**< Cell id */
1001}DRXTPSInfo_t, *pDRXTPSInfo_t;
1002
1003/*========================================*/
1004
1005/**
1006* \brief Power mode of device.
1007*
1008* Used by DRX_CTRL_SET_POWER_MODE.
1009*/
1010typedef enum {
1011 DRX_POWER_UP = 0, /**< Generic , Power Up Mode */
1012 DRX_POWER_MODE_1, /**< Device specific , Power Up Mode */
1013 DRX_POWER_MODE_2, /**< Device specific , Power Up Mode */
1014 DRX_POWER_MODE_3, /**< Device specific , Power Up Mode */
1015 DRX_POWER_MODE_4, /**< Device specific , Power Up Mode */
1016 DRX_POWER_MODE_5, /**< Device specific , Power Up Mode */
1017 DRX_POWER_MODE_6, /**< Device specific , Power Up Mode */
1018 DRX_POWER_MODE_7, /**< Device specific , Power Up Mode */
1019 DRX_POWER_MODE_8, /**< Device specific , Power Up Mode */
1020
1021 DRX_POWER_MODE_9, /**< Device specific , Power Down Mode */
1022 DRX_POWER_MODE_10, /**< Device specific , Power Down Mode */
1023 DRX_POWER_MODE_11, /**< Device specific , Power Down Mode */
1024 DRX_POWER_MODE_12, /**< Device specific , Power Down Mode */
1025 DRX_POWER_MODE_13, /**< Device specific , Power Down Mode */
1026 DRX_POWER_MODE_14, /**< Device specific , Power Down Mode */
1027 DRX_POWER_MODE_15, /**< Device specific , Power Down Mode */
1028 DRX_POWER_MODE_16, /**< Device specific , Power Down Mode */
1029 DRX_POWER_DOWN = 255 /**< Generic , Power Down Mode */
1030}DRXPowerMode_t, *pDRXPowerMode_t;
1031
1032/*========================================*/
1033
1034/**
1035* \enum DRXModule_t
1036* \brief Software module identification.
1037*
1038* Used by DRX_CTRL_VERSION.
1039*/
1040typedef enum {
1041 DRX_MODULE_DEVICE,
1042 DRX_MODULE_MICROCODE,
1043 DRX_MODULE_DRIVERCORE,
1044 DRX_MODULE_DEVICEDRIVER,
1045 DRX_MODULE_DAP,
1046 DRX_MODULE_BSP_I2C,
1047 DRX_MODULE_BSP_TUNER,
1048 DRX_MODULE_BSP_HOST,
1049 DRX_MODULE_UNKNOWN
1050} DRXModule_t, *pDRXModule_t;
1051
1052
1053/**
1054* \enum DRXVersion_t
1055* \brief Version information of one software module.
1056*
1057* Used by DRX_CTRL_VERSION.
1058*/
1059typedef struct {
1060 DRXModule_t moduleType; /**< Type identifier of the module */
1061 char *moduleName; /**< Name or description of module */
1062 u16_t vMajor; /**< Major version number */
1063 u16_t vMinor; /**< Minor version number */
1064 u16_t vPatch; /**< Patch version number */
1065 char *vString; /**< Version as text string */
1066} DRXVersion_t, *pDRXVersion_t;
1067
1068/**
1069* \enum DRXVersionList_t
1070* \brief List element of NULL terminated, linked list for version information.
1071*
1072* Used by DRX_CTRL_VERSION.
1073*/
1074typedef struct DRXVersionList_s {
1075 pDRXVersion_t version; /**< Version information */
1076 struct DRXVersionList_s *next; /**< Next list element */
1077} DRXVersionList_t, *pDRXVersionList_t;
1078
1079/*========================================*/
1080
1081/**
1082* \brief Parameters needed to confiugure a UIO.
1083*
1084* Used by DRX_CTRL_UIO_CFG.
1085*/
1086typedef struct {
1087 DRXUIO_t uio; /**< UIO identifier */
1088 DRXUIOMode_t mode; /**< UIO operational mode */
1089} DRXUIOCfg_t, *pDRXUIOCfg_t;
1090
1091/*========================================*/
1092
1093/**
1094* \brief Parameters needed to read from or write to a UIO.
1095*
1096* Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE.
1097*/
1098typedef struct {
1099 DRXUIO_t uio; /**< UIO identifier */
1100 Bool_t value; /**< UIO value (TRUE=1, FALSE=0) */
1101} DRXUIOData_t, *pDRXUIOData_t;
1102
1103/*========================================*/
1104
1105/**
1106* \brief Parameters needed to configure OOB.
1107*
1108* Used by DRX_CTRL_SET_OOB.
1109*/
1110typedef struct {
1111 DRXFrequency_t frequency; /**< Frequency in kHz */
1112 DRXOOBDownstreamStandard_t standard; /**< OOB standard */
1113 Bool_t spectrumInverted; /**< If TRUE, then spectrum
1114 is inverted */
1115} DRXOOB_t, *pDRXOOB_t;
1116
1117
1118/*========================================*/
1119
1120/**
1121* \brief Metrics from OOB.
1122*
1123* Used by DRX_CTRL_GET_OOB.
1124*/
1125typedef struct {
1126 DRXFrequency_t frequency; /**< Frequency in Khz */
1127 DRXLockStatus_t lock; /**< Lock status */
1128 u32_t mer; /**< MER */
1129 s32_t symbolRateOffset; /**< Symbolrate offset in ppm */
1130} DRXOOBStatus_t, *pDRXOOBStatus_t;
1131
1132
1133/*========================================*/
1134
1135/**
1136* \brief Device dependent configuration data.
1137*
1138* Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG.
1139* A sort of nested DRX_Ctrl() functionality for device specific controls.
1140*/
1141typedef struct {
1142 DRXCfgType_t cfgType ; /**< Function identifier */
1143 void* cfgData ; /**< Function data */
1144} DRXCfg_t, *pDRXCfg_t;
1145
1146/*========================================*/
1147
1148/**
1149* /struct DRXMpegStartWidth_t
1150* MStart width [nr MCLK cycles] for serial MPEG output.
1151*/
1152
1153typedef enum {
1154 DRX_MPEG_STR_WIDTH_1,
1155 DRX_MPEG_STR_WIDTH_8
1156} DRXMPEGStrWidth_t, *pDRXMPEGStrWidth_t;
1157
1158
1159/* CTRL CFG MPEG ouput */
1160/**
1161* \struct DRXCfgMPEGOutput_t
1162* \brief Configuartion parameters for MPEG output control.
1163*
1164* Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and
1165* DRX_CTRL_GET_CFG.
1166*/
1167
1168typedef struct {
1169 Bool_t enableMPEGOutput; /**< If TRUE, enable MPEG output */
1170 Bool_t insertRSByte; /**< If TRUE, insert RS byte */
1171 Bool_t enableParallel; /**< If TRUE, parallel out otherwise
1172 serial */
1173 Bool_t invertDATA; /**< If TRUE, invert DATA signals */
1174 Bool_t invertERR; /**< If TRUE, invert ERR signal */
1175 Bool_t invertSTR; /**< If TRUE, invert STR signals */
1176 Bool_t invertVAL; /**< If TRUE, invert VAL signals */
1177 Bool_t invertCLK; /**< If TRUE, invert CLK signals */
1178 Bool_t staticCLK; /**< If TRUE, static MPEG clockrate
1179 will be used, otherwise clockrate
1180 will adapt to the bitrate of the
1181 TS */
1182 u32_t bitrate; /**< Maximum bitrate in b/s in case
1183 static clockrate is selected */
1184 DRXMPEGStrWidth_t widthSTR; /**< MPEG start width */
1185} DRXCfgMPEGOutput_t, *pDRXCfgMPEGOutput_t;
1186
1187/* CTRL CFG SMA */
1188/**
1189* /struct DRXCfgSMAIO_t
1190* smart antenna i/o.
1191*/
1192typedef enum DRXCfgSMAIO_t {
1193 DRX_SMA_OUTPUT = 0,
1194 DRX_SMA_INPUT
1195} DRXCfgSMAIO_t, *pDRXCfgSMAIO_t;
1196
1197/**
1198* /struct DRXCfgSMA_t
1199* Set smart antenna.
1200*/
1201typedef struct {
1202 DRXCfgSMAIO_t io;
1203 u16_t ctrlData;
1204 Bool_t smartAntInverted;
1205} DRXCfgSMA_t, *pDRXCfgSMA_t;
1206
1207/*========================================*/
1208
1209/**
1210* \struct DRXI2CData_t
1211* \brief Data for I2C via 2nd or 3rd or etc I2C port.
1212*
1213* Used by DRX_CTRL_I2C_READWRITE.
1214* If portNr is equal to primairy portNr BSPI2C will be used.
1215*
1216*/
1217typedef struct {
1218 u16_t portNr; /**< I2C port number */
1219 pI2CDeviceAddr_t wDevAddr; /**< Write device address */
1220 u16_t wCount; /**< Size of write data in bytes */
1221 pu8_t wData; /**< Pointer to write data */
1222 pI2CDeviceAddr_t rDevAddr; /**< Read device address */
1223 u16_t rCount; /**< Size of data to read in bytes */
1224 pu8_t rData; /**< Pointer to read buffer */
1225} DRXI2CData_t, *pDRXI2CData_t;
1226
1227/*========================================*/
1228
1229/**
1230* \enum DRXAudStandard_t
1231* \brief Audio standard identifier.
1232*
1233* Used by DRX_CTRL_SET_AUD.
1234*/
1235typedef enum {
1236 DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */
1237 DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */
1238 DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */
1239 DRX_AUD_STANDARD_FM_STEREO, /**< set to FM-Stereo Radio */
1240 DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */
1241 DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */
1242 DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */
1243 DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */
1244 DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */
1245 DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */
1246 DRX_AUD_STANDARD_BG_NICAM_FM, /**< set BG_NICAM_FM standard */
1247 DRX_AUD_STANDARD_L_NICAM_AM, /**< set L_NICAM_AM standard */
1248 DRX_AUD_STANDARD_I_NICAM_FM, /**< set I_NICAM_FM standard */
1249 DRX_AUD_STANDARD_D_K_NICAM_FM, /**< set D_K_NICAM_FM standard */
1250 DRX_AUD_STANDARD_NOT_READY, /**< used to detect audio standard */
1251 DRX_AUD_STANDARD_AUTO = DRX_AUTO, /**< Automatic Standard Detection */
1252 DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN /**< used as auto and for readback */
1253} DRXAudStandard_t, *pDRXAudStandard_t;
1254
1255/* CTRL_AUD_GET_STATUS - DRXAudStatus_t */
1256/**
1257* \enum DRXAudNICAMStatus_t
1258* \brief Status of NICAM carrier.
1259*/
1260typedef enum {
1261 DRX_AUD_NICAM_DETECTED = 0, /**< NICAM carrier detected */
1262 DRX_AUD_NICAM_NOT_DETECTED, /**< NICAM carrier not detected */
1263 DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */
1264} DRXAudNICAMStatus_t, *pDRXAudNICAMStatus_t;
1265
1266/**
1267* \struct DRXAudStatus_t
1268* \brief Audio status characteristics.
1269*/
1270typedef struct {
1271 Bool_t stereo; /**< stereo detection */
1272 Bool_t carrierA; /**< carrier A detected */
1273 Bool_t carrierB; /**< carrier B detected */
1274 Bool_t sap; /**< sap / bilingual detection */
1275 Bool_t rds; /**< RDS data array present */
1276 DRXAudNICAMStatus_t nicamStatus; /**< status of NICAM carrier */
1277 s8_t fmIdent; /**< FM Identification value */
1278} DRXAudStatus_t, *pDRXAudStatus_t;
1279
1280/* CTRL_AUD_READ_RDS - DRXRDSdata_t */
1281
1282/**
1283* \struct DRXRDSdata_t
1284* \brief Raw RDS data array.
1285*/
1286typedef struct {
1287 Bool_t valid; /**< RDS data validation */
1288 u16_t data[18]; /**< data from one RDS data array */
1289} DRXCfgAudRDS_t, *pDRXCfgAudRDS_t;
1290
1291/* DRX_CFG_AUD_VOLUME - DRXCfgAudVolume_t - set/get */
1292/**
1293* \enum DRXAudAVCDecayTime_t
1294* \brief Automatic volume control configuration.
1295*/
1296typedef enum {
1297 DRX_AUD_AVC_OFF, /**< Automatic volume control off */
1298 DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */
1299 DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */
1300 DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */
1301 DRX_AUD_AVC_DECAYTIME_20MS /**< level volume in 20 millisec */
1302} DRXAudAVCMode_t, *pDRXAudAVCMode_t;
1303
1304/**
1305* /enum DRXAudMaxAVCGain_t
1306* /brief Automatic volume control max gain in audio baseband.
1307*/
1308typedef enum {
1309 DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */
1310 DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */
1311 DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */
1312} DRXAudAVCMaxGain_t, *pDRXAudAVCMaxGain_t;
1313
1314/**
1315* /enum DRXAudMaxAVCAtten_t
1316* /brief Automatic volume control max attenuation in audio baseband.
1317*/
1318typedef enum {
1319 DRX_AUD_AVC_MAX_ATTEN_12DB, /**< maximum AVC attenuation 12 dB */
1320 DRX_AUD_AVC_MAX_ATTEN_18DB, /**< maximum AVC attenuation 18 dB */
1321 DRX_AUD_AVC_MAX_ATTEN_24DB /**< maximum AVC attenuation 24 dB */
1322} DRXAudAVCMaxAtten_t, *pDRXAudAVCMaxAtten_t;
1323/**
1324* \struct DRXCfgAudVolume_t
1325* \brief Audio volume configuration.
1326*/
1327typedef struct {
1328 Bool_t mute; /**< mute overrides volume setting */
1329 s16_t volume; /**< volume, range -114 to 12 dB */
1330 DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */
1331 u16_t avcRefLevel; /**< AVC reference level */
1332 DRXAudAVCMaxGain_t avcMaxGain; /**< AVC max gain selection */
1333 DRXAudAVCMaxAtten_t avcMaxAtten; /**< AVC max attenuation selection */
1334 s16_t strengthLeft; /**< quasi-peak, left speaker */
1335 s16_t strengthRight; /**< quasi-peak, right speaker */
1336} DRXCfgAudVolume_t, *pDRXCfgAudVolume_t;
1337
1338/* DRX_CFG_I2S_OUTPUT - DRXCfgI2SOutput_t - set/get */
1339/**
1340* \enum DRXI2SMode_t
1341* \brief I2S output mode.
1342*/
1343typedef enum {
1344 DRX_I2S_MODE_MASTER, /**< I2S is in master mode */
1345 DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */
1346} DRXI2SMode_t, *pDRXI2SMode_t;
1347
1348/**
1349* \enum DRXI2SWordLength_t
1350* \brief Width of I2S data.
1351*/
1352typedef enum {
1353 DRX_I2S_WORDLENGTH_32 = 0, /**< I2S data is 32 bit wide */
1354 DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */
1355} DRXI2SWordLength_t, *pDRXI2SWordLength_t;
1356
1357/**
1358* \enum DRXI2SFormat_t
1359* \brief Data wordstrobe alignment for I2S.
1360*/
1361typedef enum {
1362 DRX_I2S_FORMAT_WS_WITH_DATA, /**< I2S data and wordstrobe are aligned */
1363 DRX_I2S_FORMAT_WS_ADVANCED /**< I2S data one cycle after wordstrobe */
1364} DRXI2SFormat_t, *pDRXI2SFormat_t;
1365
1366/**
1367* \enum DRXI2SPolarity_t
1368* \brief Polarity of I2S data.
1369*/
1370typedef enum {
1371 DRX_I2S_POLARITY_RIGHT, /**< wordstrobe - right high, left low */
1372 DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */
1373} DRXI2SPolarity_t, *pDRXI2SPolarity_t;
1374
1375
1376
1377/**
1378* \struct DRXCfgI2SOutput_t
1379* \brief I2S output configuration.
1380*/
1381typedef struct {
1382 Bool_t outputEnable; /**< I2S output enable */
1383 u32_t frequency; /**< range from 8000-48000 Hz */
1384 DRXI2SMode_t mode; /**< I2S mode, master or slave */
1385 DRXI2SWordLength_t wordLength; /**< I2S wordlength, 16 or 32 bits */
1386 DRXI2SPolarity_t polarity; /**< I2S wordstrobe polarity */
1387 DRXI2SFormat_t format; /**< I2S wordstrobe delay to data */
1388} DRXCfgI2SOutput_t, *pDRXCfgI2SOutput_t;
1389
1390
1391/* ------------------------------expert interface-----------------------------*/
1392/**
1393* /enum DRXAudFMDeemphasis_t
1394* setting for FM-Deemphasis in audio demodulator.
1395*
1396*/
1397typedef enum {
1398 DRX_AUD_FM_DEEMPH_50US,
1399 DRX_AUD_FM_DEEMPH_75US,
1400 DRX_AUD_FM_DEEMPH_OFF
1401} DRXAudFMDeemphasis_t, *pDRXAudFMDeemphasis_t;
1402
1403/**
1404* /enum DRXAudDeviation_t
1405* setting for deviation mode in audio demodulator.
1406*
1407*/
1408typedef enum {
1409 DRX_AUD_DEVIATION_NORMAL,
1410 DRX_AUD_DEVIATION_HIGH
1411} DRXCfgAudDeviation_t, *pDRXCfgAudDeviation_t;
1412
1413/**
1414* /enum DRXNoCarrierOption_t
1415* setting for carrier, mute/noise.
1416*
1417*/
1418typedef enum {
1419 DRX_NO_CARRIER_MUTE,
1420 DRX_NO_CARRIER_NOISE
1421} DRXNoCarrierOption_t, *pDRXNoCarrierOption_t;
1422
1423
1424/**
1425* \enum DRXAudAutoSound_t
1426* \brief Automatic Sound
1427*/
1428typedef enum {
1429 DRX_AUD_AUTO_SOUND_OFF = 0,
1430 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,
1431 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF
1432} DRXCfgAudAutoSound_t, *pDRXCfgAudAutoSound_t;
1433
1434/**
1435* \enum DRXAudASSThres_t
1436* \brief Automatic Sound Select Thresholds
1437*/
1438typedef struct {
1439 u16_t a2; /* A2 Threshold for ASS configuration */
1440 u16_t btsc; /* BTSC Threshold for ASS configuration */
1441 u16_t nicam; /* Nicam Threshold for ASS configuration */
1442} DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t;
1443
1444/**
1445* \struct DRXAudCarrier_t
1446* \brief Carrier detection related parameters
1447*/
1448typedef struct {
1449 u16_t thres; /* carrier detetcion threshold for primary carrier (A) */
1450 DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */
1451 DRXFrequency_t shift; /* DC level of incoming signal (A) */
1452 DRXFrequency_t dco; /* frequency adjustment (A) */
1453} DRXAudCarrier_t, *pDRXCfgAudCarrier_t;
1454
1455/**
1456* \struct DRXCfgAudCarriers_t
1457* \brief combining carrier A & B to one struct
1458*/
1459typedef struct {
1460 DRXAudCarrier_t a;
1461 DRXAudCarrier_t b;
1462} DRXCfgAudCarriers_t, *pDRXCfgAudCarriers_t;
1463
1464/**
1465* /enum DRXAudI2SSrc_t
1466* Selection of audio source
1467*/
1468typedef enum {
1469 DRX_AUD_SRC_MONO,
1470 DRX_AUD_SRC_STEREO_OR_AB,
1471 DRX_AUD_SRC_STEREO_OR_A,
1472 DRX_AUD_SRC_STEREO_OR_B
1473} DRXAudI2SSrc_t, *pDRXAudI2SSrc_t;
1474
1475
1476/**
1477* \enum DRXAudI2SMatrix_t
1478* \brief Used for selecting I2S output.
1479*/
1480typedef enum {
1481 DRX_AUD_I2S_MATRIX_A_MONO, /**< A sound only, stereo or mono */
1482 DRX_AUD_I2S_MATRIX_B_MONO, /**< B sound only, stereo or mono */
1483 DRX_AUD_I2S_MATRIX_STEREO, /**< A+B sound, transparant */
1484 DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */
1485} DRXAudI2SMatrix_t, *pDRXAudI2SMatrix_t;
1486
1487
1488/**
1489* /enum DRXAudFMMatrix_t
1490* setting for FM-Matrix in audio demodulator.
1491*
1492*/
1493typedef enum {
1494 DRX_AUD_FM_MATRIX_NO_MATRIX,
1495 DRX_AUD_FM_MATRIX_GERMAN,
1496 DRX_AUD_FM_MATRIX_KOREAN,
1497 DRX_AUD_FM_MATRIX_SOUND_A,
1498 DRX_AUD_FM_MATRIX_SOUND_B
1499} DRXAudFMMatrix_t, *pDRXAudFMMatrix_t;
1500
1501/**
1502* \struct DRXAudMatrices_t
1503* \brief Mixer settings
1504*/
1505typedef struct {
1506 DRXAudI2SSrc_t sourceI2S;
1507 DRXAudI2SMatrix_t matrixI2S;
1508 DRXAudFMMatrix_t matrixFm;
1509} DRXCfgAudMixer_t, *pDRXCfgAudMixer_t;
1510
1511/**
1512* \enum DRXI2SVidSync_t
1513* \brief Audio/video synchronization, interacts with I2S mode.
1514* AUTO_1 and AUTO_2 are for automatic video standard detection with preference
1515* for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz)
1516*/
1517typedef enum {
1518 DRX_AUD_AVSYNC_OFF, /**< audio/video synchronization is off */
1519 DRX_AUD_AVSYNC_NTSC, /**< it is an NTSC system */
1520 DRX_AUD_AVSYNC_MONOCHROME, /**< it is a MONOCHROME system */
1521 DRX_AUD_AVSYNC_PAL_SECAM /**< it is a PAL/SECAM system */
1522} DRXCfgAudAVSync_t, *pDRXCfgAudAVSync_t;
1523
1524/**
1525* \struct DRXCfgAudPrescale_t
1526* \brief Prescalers
1527*/
1528typedef struct {
1529 u16_t fmDeviation;
1530 s16_t nicamGain;
1531} DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t;
1532
1533/**
1534* \struct DRXAudBeep_t
1535* \brief Beep
1536*/
1537typedef struct {
1538 s16_t volume; /* dB */
1539 u16_t frequency; /* Hz */
1540 Bool_t mute;
1541} DRXAudBeep_t, *pDRXAudBeep_t;
1542
1543
1544/**
1545* \enum DRXAudBtscDetect_t
1546* \brief BTSC detetcion mode
1547*/
1548typedef enum {
1549 DRX_BTSC_STEREO,
1550 DRX_BTSC_MONO_AND_SAP
1551} DRXAudBtscDetect_t, *pDRXAudBtscDetect_t;
1552
1553/**
1554* \struct DRXAudData_t
1555* \brief Audio data structure
1556*/
1557typedef struct
1558{
1559 /* audio storage */
1560 Bool_t audioIsActive;
1561 DRXAudStandard_t audioStandard;
1562 DRXCfgI2SOutput_t i2sdata;
1563 DRXCfgAudVolume_t volume;
1564 DRXCfgAudAutoSound_t autoSound;
1565 DRXCfgAudASSThres_t assThresholds;
1566 DRXCfgAudCarriers_t carriers;
1567 DRXCfgAudMixer_t mixer;
1568 DRXCfgAudDeviation_t deviation;
1569 DRXCfgAudAVSync_t avSync;
1570 DRXCfgAudPrescale_t prescale;
1571 DRXAudFMDeemphasis_t deemph;
1572 DRXAudBtscDetect_t btscDetect;
1573 /* rds */
1574 u16_t rdsDataCounter;
1575 Bool_t rdsDataPresent;
1576} DRXAudData_t, *pDRXAudData_t;
1577
1578
1579/**
1580* \enum DRXQamLockRange_t
1581* \brief QAM lock range mode
1582*/
1583typedef enum
1584{
1585 DRX_QAM_LOCKRANGE_NORMAL,
1586 DRX_QAM_LOCKRANGE_EXTENDED
1587}DRXQamLockRange_t, *pDRXQamLockRange_t;
1588
1589/*============================================================================*/
1590/*============================================================================*/
1591/*== Data access structures ==================================================*/
1592/*============================================================================*/
1593/*============================================================================*/
1594
1595/* Address on device */
1596typedef u32_t DRXaddr_t, *pDRXaddr_t;
1597
1598/* Protocol specific flags */
1599typedef u32_t DRXflags_t, *pDRXflags_t;
1600
1601/* Write block of data to device */
1602typedef DRXStatus_t (*DRXWriteBlockFunc_t) (
1603 pI2CDeviceAddr_t devAddr, /* address of I2C device */
1604 DRXaddr_t addr, /* address of register/memory */
1605 u16_t datasize, /* size of data in bytes */
1606 pu8_t data, /* data to send */
1607 DRXflags_t flags);
1608
1609/* Read block of data from device */
1610typedef DRXStatus_t (*DRXReadBlockFunc_t) (
1611 pI2CDeviceAddr_t devAddr, /* address of I2C device */
1612 DRXaddr_t addr, /* address of register/memory */
1613 u16_t datasize, /* size of data in bytes */
1614 pu8_t data, /* receive buffer */
1615 DRXflags_t flags);
1616
1617/* Write 8-bits value to device */
1618typedef DRXStatus_t (*DRXWriteReg8Func_t) (
1619 pI2CDeviceAddr_t devAddr, /* address of I2C device */
1620 DRXaddr_t addr, /* address of register/memory */
1621 u8_t data, /* data to send */
1622 DRXflags_t flags);
1623
1624/* Read 8-bits value to device */
1625typedef DRXStatus_t (*DRXReadReg8Func_t) (
1626 pI2CDeviceAddr_t devAddr, /* address of I2C device */
1627 DRXaddr_t addr, /* address of register/memory */
1628 pu8_t data, /* receive buffer */
1629 DRXflags_t flags);
1630
1631/* Read modify write 8-bits value to device */
1632typedef DRXStatus_t (*DRXReadModifyWriteReg8Func_t) (
1633 pI2CDeviceAddr_t devAddr, /* address of I2C device */
1634 DRXaddr_t waddr, /* write address of register */
1635 DRXaddr_t raddr, /* read address of register */
1636 u8_t wdata, /* data to write */
1637 pu8_t rdata); /* data to read */
1638
1639/* Write 16-bits value to device */
1640typedef DRXStatus_t (*DRXWriteReg16Func_t) (
1641 pI2CDeviceAddr_t devAddr, /* address of I2C device */
1642 DRXaddr_t addr, /* address of register/memory */
1643 u16_t data, /* data to send */
1644 DRXflags_t flags);
1645
1646/* Read 16-bits value to device */
1647typedef DRXStatus_t (*DRXReadReg16Func_t) (
1648 pI2CDeviceAddr_t devAddr, /* address of I2C device */
1649 DRXaddr_t addr, /* address of register/memory */
1650 pu16_t data, /* receive buffer */
1651 DRXflags_t flags);
1652
1653/* Read modify write 16-bits value to device */
1654typedef DRXStatus_t (*DRXReadModifyWriteReg16Func_t) (
1655 pI2CDeviceAddr_t devAddr, /* address of I2C device */
1656 DRXaddr_t waddr, /* write address of register */
1657 DRXaddr_t raddr, /* read address of register */
1658 u16_t wdata, /* data to write */
1659 pu16_t rdata); /* data to read */
1660
1661/* Write 32-bits value to device */
1662typedef DRXStatus_t (*DRXWriteReg32Func_t) (
1663 pI2CDeviceAddr_t devAddr, /* address of I2C device */
1664 DRXaddr_t addr, /* address of register/memory */
1665 u32_t data, /* data to send */
1666 DRXflags_t flags);
1667
1668/* Read 32-bits value to device */
1669typedef DRXStatus_t (*DRXReadReg32Func_t) (
1670 pI2CDeviceAddr_t devAddr, /* address of I2C device */
1671 DRXaddr_t addr, /* address of register/memory */
1672 pu32_t data, /* receive buffer */
1673 DRXflags_t flags);
1674
1675/* Read modify write 32-bits value to device */
1676typedef DRXStatus_t (*DRXReadModifyWriteReg32Func_t) (
1677 pI2CDeviceAddr_t devAddr, /* address of I2C device */
1678 DRXaddr_t waddr, /* write address of register */
1679 DRXaddr_t raddr, /* read address of register */
1680 u32_t wdata, /* data to write */
1681 pu32_t rdata); /* data to read */
1682
1683/**
1684* \struct DRXAccessFunc_t
1685* \brief Interface to an access protocol.
1686*/
1687typedef struct {
1688 pDRXVersion_t protocolVersion;
1689 DRXWriteBlockFunc_t writeBlockFunc;
1690 DRXReadBlockFunc_t readBlockFunc;
1691 DRXWriteReg8Func_t writeReg8Func;
1692 DRXReadReg8Func_t readReg8Func;
1693 DRXReadModifyWriteReg8Func_t readModifyWriteReg8Func;
1694 DRXWriteReg16Func_t writeReg16Func;
1695 DRXReadReg16Func_t readReg16Func;
1696 DRXReadModifyWriteReg16Func_t readModifyWriteReg16Func;
1697 DRXWriteReg32Func_t writeReg32Func;
1698 DRXReadReg32Func_t readReg32Func;
1699 DRXReadModifyWriteReg32Func_t readModifyWriteReg32Func;
1700} DRXAccessFunc_t, *pDRXAccessFunc_t;
1701
1702/* Register address and data for register dump function */
1703typedef struct {
1704
1705 DRXaddr_t address;
1706 u32_t data;
1707
1708} DRXRegDump_t, *pDRXRegDump_t ;
1709
1710/*============================================================================*/
1711/*============================================================================*/
1712/*== Demod instance data structures ==========================================*/
1713/*============================================================================*/
1714/*============================================================================*/
1715
1716/**
1717* \struct DRXCommonAttr_t
1718* \brief Set of common attributes, shared by all DRX devices.
1719*/
1720typedef struct {
1721 /* Microcode (firmware) attributes */
1722 pu8_t microcode; /**< Pointer to microcode image. */
1723 u16_t microcodeSize; /**< Size of microcode image in bytes. */
1724 Bool_t verifyMicrocode; /**< Use microcode verify or not. */
1725 DRXMcVersionRec_t mcversion; /**< Version record of microcode from file */
1726
1727 /* Clocks and tuner attributes */
1728 DRXFrequency_t intermediateFreq; /**< IF,if tuner instance not used. (kHz)*/
1729 DRXFrequency_t sysClockFreq; /**< Systemclock frequency. (kHz) */
1730 DRXFrequency_t oscClockFreq; /**< Oscillator clock frequency. (kHz) */
1731 s16_t oscClockDeviation; /**< Oscillator clock deviation. (ppm) */
1732 Bool_t mirrorFreqSpect; /**< Mirror IF frequency spectrum or not.*/
1733
1734 /* Initial MPEG output attributes */
1735 DRXCfgMPEGOutput_t mpegCfg; /**< MPEG configuration */
1736
1737 Bool_t isOpened; /**< if TRUE instance is already opened. */
1738
1739 /* Channel scan */
1740 pDRXScanParam_t scanParam; /**< scan parameters */
1741 u16_t scanFreqPlanIndex; /**< next index in freq plan */
1742 DRXFrequency_t scanNextFrequency; /**< next freq to scan */
1743 Bool_t scanReady; /**< scan ready flag */
1744 u32_t scanMaxChannels; /**< number of channels in freqplan */
1745 u32_t scanChannelsScanned; /**< number of channels scanned */
1746 /* Channel scan - inner loop: demod related */
1747 DRXScanFunc_t scanFunction; /**< function to check channel */
1748 /* Channel scan - inner loop: SYSObj related */
1749 void* scanContext; /**< Context Pointer of SYSObj */
1750 /* Channel scan - parameters for default DTV scan function in core driver */
1751 u16_t scanDemodLockTimeout; /**< millisecs to wait for lock */
1752 DRXLockStatus_t scanDesiredLock; /**< lock requirement for channel found */
1753 /* scanActive can be used by SetChannel to decide how to program the tuner,
1754 fast or slow (but stable). Usually fast during scan. */
1755 Bool_t scanActive; /**< TRUE when scan routines are active */
1756
1757 /* Power management */
1758 DRXPowerMode_t currentPowerMode; /**< current power management mode */
1759
1760 /* Tuner */
1761 u8_t tunerPortNr; /**< nr of I2C port to wich tuner is */
1762 DRXFrequency_t tunerMinFreqRF; /**< minimum RF input frequency, in kHz */
1763 DRXFrequency_t tunerMaxFreqRF; /**< maximum RF input frequency, in kHz */
1764 Bool_t tunerRfAgcPol; /**< if TRUE invert RF AGC polarity */
1765 Bool_t tunerIfAgcPol; /**< if TRUE invert IF AGC polarity */
1766 Bool_t tunerSlowMode; /**< if TRUE invert IF AGC polarity */
1767
1768 DRXChannel_t currentChannel; /**< current channel parameters */
1769 DRXStandard_t currentStandard; /**< current standard selection */
1770 DRXStandard_t prevStandard; /**< previous standard selection */
1771 DRXStandard_t diCacheStandard; /**< standard in DI cache if available */
1772 Bool_t useBootloader; /**< use bootloader in open */
1773 u32_t capabilities; /**< capabilities flags */
1774 u32_t productId; /**< product ID inc. metal fix number */
1775
1776} DRXCommonAttr_t, *pDRXCommonAttr_t;
1777
1778
1779/*
1780* Generic functions for DRX devices.
1781*/
1782typedef struct DRXDemodInstance_s *pDRXDemodInstance_t;
1783
1784typedef DRXStatus_t (*DRXOpenFunc_t) (pDRXDemodInstance_t demod);
1785typedef DRXStatus_t (*DRXCloseFunc_t) (pDRXDemodInstance_t demod);
1786typedef DRXStatus_t (*DRXCtrlFunc_t) (pDRXDemodInstance_t demod,
1787 DRXCtrlIndex_t ctrl,
1788 void *ctrlData);
1789
1790/**
1791* \struct DRXDemodFunc_t
1792* \brief A stucture containing all functions of a demodulator.
1793*/
1794typedef struct {
1795 u32_t typeId; /**< Device type identifier. */
1796 DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */
1797 DRXCloseFunc_t closeFunc; /**< Pointer to Close() function. */
1798 DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */
1799} DRXDemodFunc_t, *pDRXDemodFunc_t;
1800
1801/**
1802* \struct DRXDemodInstance_t
1803* \brief Top structure of demodulator instance.
1804*/
1805typedef struct DRXDemodInstance_s {
1806 /* type specific demodulator data */
1807 pDRXDemodFunc_t myDemodFunct; /**< demodulator functions */
1808 pDRXAccessFunc_t myAccessFunct; /**< data access protocol functions */
1809 pTUNERInstance_t myTuner; /**< tuner instance,if NULL then baseband */
1810 pI2CDeviceAddr_t myI2CDevAddr; /**< i2c address and device identifier */
1811 pDRXCommonAttr_t myCommonAttr; /**< common DRX attributes */
1812 void* myExtAttr; /**< device specific attributes */
1813 /* generic demodulator data */
1814} DRXDemodInstance_t;
1815
1816
1817
1818/*-------------------------------------------------------------------------
1819MACROS
1820Conversion from enum values to human readable form.
1821-------------------------------------------------------------------------*/
1822
1823/* standard */
1824
1825#define DRX_STR_STANDARD(x) ( \
1826 ( x == DRX_STANDARD_DVBT ) ? "DVB-T" : \
1827 ( x == DRX_STANDARD_8VSB ) ? "8VSB" : \
1828 ( x == DRX_STANDARD_NTSC ) ? "NTSC" : \
1829 ( x == DRX_STANDARD_PAL_SECAM_BG ) ? "PAL/SECAM B/G" : \
1830 ( x == DRX_STANDARD_PAL_SECAM_DK ) ? "PAL/SECAM D/K" : \
1831 ( x == DRX_STANDARD_PAL_SECAM_I ) ? "PAL/SECAM I" : \
1832 ( x == DRX_STANDARD_PAL_SECAM_L ) ? "PAL/SECAM L" : \
1833 ( x == DRX_STANDARD_PAL_SECAM_LP ) ? "PAL/SECAM LP" : \
1834 ( x == DRX_STANDARD_ITU_A ) ? "ITU-A" : \
1835 ( x == DRX_STANDARD_ITU_B ) ? "ITU-B" : \
1836 ( x == DRX_STANDARD_ITU_C ) ? "ITU-C" : \
1837 ( x == DRX_STANDARD_ITU_D ) ? "ITU-D" : \
1838 ( x == DRX_STANDARD_FM ) ? "FM" : \
1839 ( x == DRX_STANDARD_DTMB ) ? "DTMB" : \
1840 ( x == DRX_STANDARD_AUTO ) ? "Auto" : \
1841 ( x == DRX_STANDARD_UNKNOWN ) ? "Unknown" : \
1842 "(Invalid)" )
1843
1844/* channel */
1845
1846#define DRX_STR_BANDWIDTH(x) ( \
1847 ( x == DRX_BANDWIDTH_8MHZ ) ? "8 MHz" : \
1848 ( x == DRX_BANDWIDTH_7MHZ ) ? "7 MHz" : \
1849 ( x == DRX_BANDWIDTH_6MHZ ) ? "6 MHz" : \
1850 ( x == DRX_BANDWIDTH_AUTO ) ? "Auto" : \
1851 ( x == DRX_BANDWIDTH_UNKNOWN ) ? "Unknown" : \
1852 "(Invalid)" )
1853#define DRX_STR_FFTMODE(x) ( \
1854 ( x == DRX_FFTMODE_2K ) ? "2k" : \
1855 ( x == DRX_FFTMODE_4K ) ? "4k" : \
1856 ( x == DRX_FFTMODE_8K ) ? "8k" : \
1857 ( x == DRX_FFTMODE_AUTO ) ? "Auto" : \
1858 ( x == DRX_FFTMODE_UNKNOWN ) ? "Unknown" : \
1859 "(Invalid)" )
1860#define DRX_STR_GUARD(x) ( \
1861 ( x == DRX_GUARD_1DIV32 ) ? "1/32nd" : \
1862 ( x == DRX_GUARD_1DIV16 ) ? "1/16th" : \
1863 ( x == DRX_GUARD_1DIV8 ) ? "1/8th" : \
1864 ( x == DRX_GUARD_1DIV4 ) ? "1/4th" : \
1865 ( x == DRX_GUARD_AUTO ) ? "Auto" : \
1866 ( x == DRX_GUARD_UNKNOWN ) ? "Unknown" : \
1867 "(Invalid)" )
1868#define DRX_STR_CONSTELLATION(x) ( \
1869 ( x == DRX_CONSTELLATION_BPSK ) ? "BPSK" : \
1870 ( x == DRX_CONSTELLATION_QPSK ) ? "QPSK" : \
1871 ( x == DRX_CONSTELLATION_PSK8 ) ? "PSK8" : \
1872 ( x == DRX_CONSTELLATION_QAM16 ) ? "QAM16" : \
1873 ( x == DRX_CONSTELLATION_QAM32 ) ? "QAM32" : \
1874 ( x == DRX_CONSTELLATION_QAM64 ) ? "QAM64" : \
1875 ( x == DRX_CONSTELLATION_QAM128 ) ? "QAM128" : \
1876 ( x == DRX_CONSTELLATION_QAM256 ) ? "QAM256" : \
1877 ( x == DRX_CONSTELLATION_QAM512 ) ? "QAM512" : \
1878 ( x == DRX_CONSTELLATION_QAM1024 ) ? "QAM1024" : \
1879 ( x == DRX_CONSTELLATION_QPSK_NR ) ? "QPSK_NR" : \
1880 ( x == DRX_CONSTELLATION_AUTO ) ? "Auto" : \
1881 ( x == DRX_CONSTELLATION_UNKNOWN ) ? "Unknown" : \
1882 "(Invalid)" )
1883#define DRX_STR_CODERATE(x) ( \
1884 ( x == DRX_CODERATE_1DIV2 ) ? "1/2nd" : \
1885 ( x == DRX_CODERATE_2DIV3 ) ? "2/3rd" : \
1886 ( x == DRX_CODERATE_3DIV4 ) ? "3/4th" : \
1887 ( x == DRX_CODERATE_5DIV6 ) ? "5/6th" : \
1888 ( x == DRX_CODERATE_7DIV8 ) ? "7/8th" : \
1889 ( x == DRX_CODERATE_AUTO ) ? "Auto" : \
1890 ( x == DRX_CODERATE_UNKNOWN ) ? "Unknown" : \
1891 "(Invalid)" )
1892#define DRX_STR_HIERARCHY(x) ( \
1893 ( x == DRX_HIERARCHY_NONE ) ? "None" : \
1894 ( x == DRX_HIERARCHY_ALPHA1 ) ? "Alpha=1" : \
1895 ( x == DRX_HIERARCHY_ALPHA2 ) ? "Alpha=2" : \
1896 ( x == DRX_HIERARCHY_ALPHA4 ) ? "Alpha=4" : \
1897 ( x == DRX_HIERARCHY_AUTO ) ? "Auto" : \
1898 ( x == DRX_HIERARCHY_UNKNOWN ) ? "Unknown" : \
1899 "(Invalid)" )
1900#define DRX_STR_PRIORITY(x) ( \
1901 ( x == DRX_PRIORITY_LOW ) ? "Low" : \
1902 ( x == DRX_PRIORITY_HIGH ) ? "High" : \
1903 ( x == DRX_PRIORITY_UNKNOWN ) ? "Unknown" : \
1904 "(Invalid)" )
1905#define DRX_STR_MIRROR(x) ( \
1906 ( x == DRX_MIRROR_NO ) ? "Normal" : \
1907 ( x == DRX_MIRROR_YES ) ? "Mirrored" : \
1908 ( x == DRX_MIRROR_AUTO ) ? "Auto" : \
1909 ( x == DRX_MIRROR_UNKNOWN ) ? "Unknown" : \
1910 "(Invalid)" )
1911#define DRX_STR_CLASSIFICATION(x) ( \
1912 ( x == DRX_CLASSIFICATION_GAUSS ) ? "Gaussion" : \
1913 ( x == DRX_CLASSIFICATION_HVY_GAUSS ) ? "Heavy Gaussion" : \
1914 ( x == DRX_CLASSIFICATION_COCHANNEL ) ? "Co-channel" : \
1915 ( x == DRX_CLASSIFICATION_STATIC ) ? "Static echo" : \
1916 ( x == DRX_CLASSIFICATION_MOVING ) ? "Moving echo" : \
1917 ( x == DRX_CLASSIFICATION_ZERODB ) ? "Zero dB echo" : \
1918 ( x == DRX_CLASSIFICATION_UNKNOWN ) ? "Unknown" : \
1919 ( x == DRX_CLASSIFICATION_AUTO ) ? "Auto" : \
1920 "(Invalid)" )
1921
1922#define DRX_STR_INTERLEAVEMODE(x) ( \
1923 ( x == DRX_INTERLEAVEMODE_I128_J1 ) ? "I128_J1" : \
1924 ( x == DRX_INTERLEAVEMODE_I128_J1_V2 ) ? "I128_J1_V2" : \
1925 ( x == DRX_INTERLEAVEMODE_I128_J2 ) ? "I128_J2" : \
1926 ( x == DRX_INTERLEAVEMODE_I64_J2 ) ? "I64_J2" : \
1927 ( x == DRX_INTERLEAVEMODE_I128_J3 ) ? "I128_J3" : \
1928 ( x == DRX_INTERLEAVEMODE_I32_J4 ) ? "I32_J4" : \
1929 ( x == DRX_INTERLEAVEMODE_I128_J4 ) ? "I128_J4" : \
1930 ( x == DRX_INTERLEAVEMODE_I16_J8 ) ? "I16_J8" : \
1931 ( x == DRX_INTERLEAVEMODE_I128_J5 ) ? "I128_J5" : \
1932 ( x == DRX_INTERLEAVEMODE_I8_J16 ) ? "I8_J16" : \
1933 ( x == DRX_INTERLEAVEMODE_I128_J6 ) ? "I128_J6" : \
1934 ( x == DRX_INTERLEAVEMODE_RESERVED_11 ) ? "Reserved 11" : \
1935 ( x == DRX_INTERLEAVEMODE_I128_J7 ) ? "I128_J7" : \
1936 ( x == DRX_INTERLEAVEMODE_RESERVED_13 ) ? "Reserved 13" : \
1937 ( x == DRX_INTERLEAVEMODE_I128_J8 ) ? "I128_J8" : \
1938 ( x == DRX_INTERLEAVEMODE_RESERVED_15 ) ? "Reserved 15" : \
1939 ( x == DRX_INTERLEAVEMODE_I12_J17 ) ? "I12_J17" : \
1940 ( x == DRX_INTERLEAVEMODE_I5_J4 ) ? "I5_J4" : \
1941 ( x == DRX_INTERLEAVEMODE_B52_M240 ) ? "B52_M240" : \
1942 ( x == DRX_INTERLEAVEMODE_B52_M720 ) ? "B52_M720" : \
1943 ( x == DRX_INTERLEAVEMODE_B52_M48 ) ? "B52_M48" : \
1944 ( x == DRX_INTERLEAVEMODE_B52_M0 ) ? "B52_M0" : \
1945 ( x == DRX_INTERLEAVEMODE_UNKNOWN ) ? "Unknown" : \
1946 ( x == DRX_INTERLEAVEMODE_AUTO ) ? "Auto" : \
1947 "(Invalid)" )
1948
1949#define DRX_STR_LDPC(x) ( \
1950 ( x == DRX_LDPC_0_4 ) ? "0.4" : \
1951 ( x == DRX_LDPC_0_6 ) ? "0.6" : \
1952 ( x == DRX_LDPC_0_8 ) ? "0.8" : \
1953 ( x == DRX_LDPC_AUTO ) ? "Auto" : \
1954 ( x == DRX_LDPC_UNKNOWN ) ? "Unknown" : \
1955 "(Invalid)" )
1956
1957#define DRX_STR_CARRIER(x) ( \
1958 ( x == DRX_CARRIER_MULTI ) ? "Multi" : \
1959 ( x == DRX_CARRIER_SINGLE ) ? "Single" : \
1960 ( x == DRX_CARRIER_AUTO ) ? "Auto" : \
1961 ( x == DRX_CARRIER_UNKNOWN ) ? "Unknown" : \
1962 "(Invalid)" )
1963
1964#define DRX_STR_FRAMEMODE(x) ( \
1965 ( x == DRX_FRAMEMODE_420 ) ? "420" : \
1966 ( x == DRX_FRAMEMODE_595 ) ? "595" : \
1967 ( x == DRX_FRAMEMODE_945 ) ? "945" : \
1968 ( x == DRX_FRAMEMODE_420_FIXED_PN ) ? "420 with fixed PN" : \
1969 ( x == DRX_FRAMEMODE_945_FIXED_PN ) ? "945 with fixed PN" : \
1970 ( x == DRX_FRAMEMODE_AUTO ) ? "Auto" : \
1971 ( x == DRX_FRAMEMODE_UNKNOWN ) ? "Unknown" : \
1972 "(Invalid)" )
1973
1974#define DRX_STR_PILOT(x) ( \
1975 ( x == DRX_PILOT_ON ) ? "On" : \
1976 ( x == DRX_PILOT_OFF ) ? "Off" : \
1977 ( x == DRX_PILOT_AUTO ) ? "Auto" : \
1978 ( x == DRX_PILOT_UNKNOWN ) ? "Unknown" : \
1979 "(Invalid)" )
1980/* TPS */
1981
1982#define DRX_STR_TPS_FRAME(x) ( \
1983 ( x == DRX_TPS_FRAME1 ) ? "Frame1" : \
1984 ( x == DRX_TPS_FRAME2 ) ? "Frame2" : \
1985 ( x == DRX_TPS_FRAME3 ) ? "Frame3" : \
1986 ( x == DRX_TPS_FRAME4 ) ? "Frame4" : \
1987 ( x == DRX_TPS_FRAME_UNKNOWN ) ? "Unknown" : \
1988 "(Invalid)" )
1989
1990/* lock status */
1991
1992#define DRX_STR_LOCKSTATUS(x) ( \
1993 ( x == DRX_NEVER_LOCK ) ? "Never" : \
1994 ( x == DRX_NOT_LOCKED ) ? "No" : \
1995 ( x == DRX_LOCKED ) ? "Locked" : \
1996 ( x == DRX_LOCK_STATE_1 ) ? "Lock state 1" : \
1997 ( x == DRX_LOCK_STATE_2 ) ? "Lock state 2" : \
1998 ( x == DRX_LOCK_STATE_3 ) ? "Lock state 3" : \
1999 ( x == DRX_LOCK_STATE_4 ) ? "Lock state 4" : \
2000 ( x == DRX_LOCK_STATE_5 ) ? "Lock state 5" : \
2001 ( x == DRX_LOCK_STATE_6 ) ? "Lock state 6" : \
2002 ( x == DRX_LOCK_STATE_7 ) ? "Lock state 7" : \
2003 ( x == DRX_LOCK_STATE_8 ) ? "Lock state 8" : \
2004 ( x == DRX_LOCK_STATE_9 ) ? "Lock state 9" : \
2005 "(Invalid)" )
2006
2007/* version information , modules */
2008#define DRX_STR_MODULE(x) ( \
2009 ( x == DRX_MODULE_DEVICE ) ? "Device" : \
2010 ( x == DRX_MODULE_MICROCODE ) ? "Microcode" : \
2011 ( x == DRX_MODULE_DRIVERCORE ) ? "CoreDriver" : \
2012 ( x == DRX_MODULE_DEVICEDRIVER ) ? "DeviceDriver" : \
2013 ( x == DRX_MODULE_BSP_I2C ) ? "BSP I2C" : \
2014 ( x == DRX_MODULE_BSP_TUNER ) ? "BSP Tuner" : \
2015 ( x == DRX_MODULE_BSP_HOST ) ? "BSP Host" : \
2016 ( x == DRX_MODULE_DAP ) ? "Data Access Protocol" : \
2017 ( x == DRX_MODULE_UNKNOWN ) ? "Unknown" : \
2018 "(Invalid)" )
2019
2020#define DRX_STR_POWER_MODE(x) ( \
2021 ( x == DRX_POWER_UP ) ? "DRX_POWER_UP " : \
2022 ( x == DRX_POWER_MODE_1 ) ? "DRX_POWER_MODE_1" : \
2023 ( x == DRX_POWER_MODE_2 ) ? "DRX_POWER_MODE_2" : \
2024 ( x == DRX_POWER_MODE_3 ) ? "DRX_POWER_MODE_3" : \
2025 ( x == DRX_POWER_MODE_4 ) ? "DRX_POWER_MODE_4" : \
2026 ( x == DRX_POWER_MODE_5 ) ? "DRX_POWER_MODE_5" : \
2027 ( x == DRX_POWER_MODE_6 ) ? "DRX_POWER_MODE_6" : \
2028 ( x == DRX_POWER_MODE_7 ) ? "DRX_POWER_MODE_7" : \
2029 ( x == DRX_POWER_MODE_8 ) ? "DRX_POWER_MODE_8" : \
2030 ( x == DRX_POWER_MODE_9 ) ? "DRX_POWER_MODE_9" : \
2031 ( x == DRX_POWER_MODE_10 ) ? "DRX_POWER_MODE_10" : \
2032 ( x == DRX_POWER_MODE_11 ) ? "DRX_POWER_MODE_11" : \
2033 ( x == DRX_POWER_MODE_12 ) ? "DRX_POWER_MODE_12" : \
2034 ( x == DRX_POWER_MODE_13 ) ? "DRX_POWER_MODE_13" : \
2035 ( x == DRX_POWER_MODE_14 ) ? "DRX_POWER_MODE_14" : \
2036 ( x == DRX_POWER_MODE_15 ) ? "DRX_POWER_MODE_15" : \
2037 ( x == DRX_POWER_MODE_16 ) ? "DRX_POWER_MODE_16" : \
2038 ( x == DRX_POWER_DOWN ) ? "DRX_POWER_DOWN " : \
2039 "(Invalid)" )
2040
2041#define DRX_STR_OOB_STANDARD(x) ( \
2042 ( x == DRX_OOB_MODE_A ) ? "ANSI 55-1 " : \
2043 ( x == DRX_OOB_MODE_B_GRADE_A ) ? "ANSI 55-2 A" : \
2044 ( x == DRX_OOB_MODE_B_GRADE_B ) ? "ANSI 55-2 B" : \
2045 "(Invalid)" )
2046
2047#define DRX_STR_AUD_STANDARD(x) ( \
2048 ( x == DRX_AUD_STANDARD_BTSC ) ? "BTSC" : \
2049 ( x == DRX_AUD_STANDARD_A2 ) ? "A2" : \
2050 ( x == DRX_AUD_STANDARD_EIAJ ) ? "EIAJ" : \
2051 ( x == DRX_AUD_STANDARD_FM_STEREO ) ? "FM Stereo" : \
2052 ( x == DRX_AUD_STANDARD_AUTO ) ? "Auto" : \
2053 ( x == DRX_AUD_STANDARD_M_MONO ) ? "M-Standard Mono" : \
2054 ( x == DRX_AUD_STANDARD_D_K_MONO ) ? "D/K Mono FM" : \
2055 ( x == DRX_AUD_STANDARD_BG_FM ) ? "B/G-Dual Carrier FM (A2)" : \
2056 ( x == DRX_AUD_STANDARD_D_K1 ) ? "D/K1-Dual Carrier FM" : \
2057 ( x == DRX_AUD_STANDARD_D_K2 ) ? "D/K2-Dual Carrier FM" : \
2058 ( x == DRX_AUD_STANDARD_D_K3 ) ? "D/K3-Dual Carrier FM" : \
2059 ( x == DRX_AUD_STANDARD_BG_NICAM_FM ) ? "B/G-NICAM-FM" : \
2060 ( x == DRX_AUD_STANDARD_L_NICAM_AM ) ? "L-NICAM-AM" : \
2061 ( x == DRX_AUD_STANDARD_I_NICAM_FM ) ? "I-NICAM-FM" : \
2062 ( x == DRX_AUD_STANDARD_D_K_NICAM_FM ) ? "D/K-NICAM-FM" : \
2063 ( x == DRX_AUD_STANDARD_UNKNOWN ) ? "Unknown" : \
2064 "(Invalid)" )
2065#define DRX_STR_AUD_STEREO(x) ( \
2066 ( x == TRUE ) ? "Stereo" : \
2067 ( x == FALSE ) ? "Mono" : \
2068 "(Invalid)" )
2069
2070#define DRX_STR_AUD_SAP(x) ( \
2071 ( x == TRUE ) ? "Present" : \
2072 ( x == FALSE ) ? "Not present" : \
2073 "(Invalid)" )
2074
2075#define DRX_STR_AUD_CARRIER(x) ( \
2076 ( x == TRUE ) ? "Present" : \
2077 ( x == FALSE ) ? "Not present" : \
2078 "(Invalid)" )
2079
2080#define DRX_STR_AUD_RDS(x) ( \
2081 ( x == TRUE ) ? "Available" : \
2082 ( x == FALSE ) ? "Not Available" : \
2083 "(Invalid)" )
2084
2085#define DRX_STR_AUD_NICAM_STATUS(x) ( \
2086 ( x == DRX_AUD_NICAM_DETECTED ) ? "Detected" : \
2087 ( x == DRX_AUD_NICAM_NOT_DETECTED ) ? "Not detected" : \
2088 ( x == DRX_AUD_NICAM_BAD ) ? "Bad" : \
2089 "(Invalid)" )
2090
2091#define DRX_STR_RDS_VALID(x) ( \
2092 ( x == TRUE ) ? "Valid" : \
2093 ( x == FALSE ) ? "Not Valid" : \
2094 "(Invalid)" )
2095
2096/*-------------------------------------------------------------------------
2097Access macros
2098-------------------------------------------------------------------------*/
2099
2100
2101/**
2102* \brief Create a compilable reference to the microcode attribute
2103* \param d pointer to demod instance
2104*
2105* Used as main reference to an attribute field.
2106* Used by both macro implementation and function implementation.
2107* These macros are defined to avoid duplication of code in macro and function
2108* definitions that handle access of demod common or extended attributes.
2109*
2110*/
2111
2112#define DRX_ATTR_MCRECORD( d ) ((d)->myCommonAttr->mcversion)
2113#define DRX_ATTR_MIRRORFREQSPECT( d ) ((d)->myCommonAttr->mirrorFreqSpect)
2114#define DRX_ATTR_CURRENTPOWERMODE( d )((d)->myCommonAttr->currentPowerMode)
2115#define DRX_ATTR_ISOPENED( d ) ((d)->myCommonAttr->isOpened)
2116#define DRX_ATTR_USEBOOTLOADER( d ) ((d)->myCommonAttr->useBootloader)
2117#define DRX_ATTR_CURRENTSTANDARD( d ) ((d)->myCommonAttr->currentStandard)
2118#define DRX_ATTR_PREVSTANDARD( d ) ((d)->myCommonAttr->prevStandard)
2119#define DRX_ATTR_CACHESTANDARD( d ) ((d)->myCommonAttr->diCacheStandard)
2120#define DRX_ATTR_CURRENTCHANNEL( d ) ((d)->myCommonAttr->currentChannel)
2121#define DRX_ATTR_MICROCODE( d ) ((d)->myCommonAttr->microcode)
2122#define DRX_ATTR_MICROCODESIZE( d ) ((d)->myCommonAttr->microcodeSize)
2123#define DRX_ATTR_VERIFYMICROCODE( d ) ((d)->myCommonAttr->verifyMicrocode)
2124#define DRX_ATTR_CAPABILITIES( d ) ((d)->myCommonAttr->capabilities)
2125#define DRX_ATTR_PRODUCTID( d ) ((d)->myCommonAttr->productId)
2126#define DRX_ATTR_INTERMEDIATEFREQ( d) ((d)->myCommonAttr->intermediateFreq)
2127#define DRX_ATTR_SYSCLOCKFREQ( d) ((d)->myCommonAttr->sysClockFreq)
2128#define DRX_ATTR_TUNERRFAGCPOL( d ) ((d)->myCommonAttr->tunerRfAgcPol)
2129#define DRX_ATTR_TUNERIFAGCPOL( d) ((d)->myCommonAttr->tunerIfAgcPol)
2130#define DRX_ATTR_TUNERSLOWMODE( d) ((d)->myCommonAttr->tunerSlowMode)
2131#define DRX_ATTR_TUNERSPORTNR( d) ((d)->myCommonAttr->tunerPortNr)
2132#define DRX_ATTR_TUNER( d ) ((d)->myTuner)
2133#define DRX_ATTR_I2CADDR( d ) ((d)->myI2CDevAddr->i2cAddr)
2134#define DRX_ATTR_I2CDEVID( d ) ((d)->myI2CDevAddr->i2cDevId)
2135
2136/**
2137* \brief Actual access macro's
2138* \param d pointer to demod instance
2139* \param x value to set ar to get
2140*
2141* SET macro's must be used to set the value of an attribute.
2142* GET macro's must be used to retrieve the value of an attribute.
2143*
2144*/
2145
2146/**************************/
2147
2148#define DRX_SET_MIRRORFREQSPECT( d, x ) \
2149 do { \
2150 DRX_ATTR_MIRRORFREQSPECT( d ) = (x); \
2151 } while(0)
2152
2153#define DRX_GET_MIRRORFREQSPECT( d, x ) \
2154 do { \
2155 (x)=DRX_ATTR_MIRRORFREQSPECT( d ); \
2156 } while(0)
2157
2158/**************************/
2159
2160#define DRX_SET_CURRENTPOWERMODE( d, x ) \
2161 do { \
2162 DRX_ATTR_CURRENTPOWERMODE( d ) = (x); \
2163 } while(0)
2164
2165#define DRX_GET_CURRENTPOWERMODE( d, x ) \
2166 do { \
2167 (x)=DRX_ATTR_CURRENTPOWERMODE( d ); \
2168 } while(0)
2169
2170/**************************/
2171
2172#define DRX_SET_MICROCODE( d, x ) \
2173 do { \
2174 DRX_ATTR_MICROCODE( d ) = (x); \
2175 } while(0)
2176
2177#define DRX_GET_MICROCODE( d, x ) \
2178 do { \
2179 (x)=DRX_ATTR_MICROCODE( d ); \
2180 } while(0)
2181
2182/**************************/
2183
2184#define DRX_SET_MICROCODESIZE( d, x ) \
2185 do { \
2186 DRX_ATTR_MICROCODESIZE(d) = (x); \
2187 } while(0)
2188
2189#define DRX_GET_MICROCODESIZE( d, x ) \
2190 do { \
2191 (x)=DRX_ATTR_MICROCODESIZE(d); \
2192 } while(0)
2193
2194/**************************/
2195
2196#define DRX_SET_VERIFYMICROCODE( d, x ) \
2197 do { \
2198 DRX_ATTR_VERIFYMICROCODE(d) = (x); \
2199 } while(0)
2200
2201#define DRX_GET_VERIFYMICROCODE( d, x ) \
2202 do { \
2203 (x)=DRX_ATTR_VERIFYMICROCODE(d); \
2204 } while(0)
2205
2206/**************************/
2207
2208#define DRX_SET_MCVERTYPE( d, x ) \
2209 do { \
2210 DRX_ATTR_MCRECORD(d).auxType = (x); \
2211 } while (0)
2212
2213#define DRX_GET_MCVERTYPE( d, x ) \
2214 do { \
2215 (x) = DRX_ATTR_MCRECORD(d).auxType; \
2216 } while (0)
2217
2218/**************************/
2219
2220#define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD)
2221
2222/**************************/
2223
2224#define DRX_SET_MCDEV( d, x ) \
2225 do { \
2226 DRX_ATTR_MCRECORD(d).mcDevType = (x); \
2227 } while (0)
2228
2229#define DRX_GET_MCDEV( d, x ) \
2230 do { \
2231 (x) = DRX_ATTR_MCRECORD(d).mcDevType; \
2232 } while (0)
2233
2234/**************************/
2235
2236#define DRX_SET_MCVERSION( d, x ) \
2237 do { \
2238 DRX_ATTR_MCRECORD(d).mcVersion = (x); \
2239 } while (0)
2240
2241#define DRX_GET_MCVERSION( d, x ) \
2242 do { \
2243 (x) = DRX_ATTR_MCRECORD(d).mcVersion; \
2244 } while (0)
2245
2246/**************************/
2247#define DRX_SET_MCPATCH( d, x ) \
2248 do { \
2249 DRX_ATTR_MCRECORD(d).mcBaseVersion = (x); \
2250 } while (0)
2251
2252#define DRX_GET_MCPATCH( d, x ) \
2253 do { \
2254 (x) = DRX_ATTR_MCRECORD(d).mcBaseVersion; \
2255 } while (0)
2256
2257/**************************/
2258
2259#define DRX_SET_I2CADDR( d, x ) \
2260 do { \
2261 DRX_ATTR_I2CADDR(d) = (x); \
2262 } while(0)
2263
2264#define DRX_GET_I2CADDR( d, x ) \
2265 do { \
2266 (x)=DRX_ATTR_I2CADDR(d); \
2267 } while(0)
2268
2269/**************************/
2270
2271#define DRX_SET_I2CDEVID( d, x ) \
2272 do { \
2273 DRX_ATTR_I2CDEVID(d) = (x); \
2274 } while(0)
2275
2276#define DRX_GET_I2CDEVID( d, x ) \
2277 do { \
2278 (x)=DRX_ATTR_I2CDEVID(d); \
2279 } while(0)
2280
2281/**************************/
2282
2283#define DRX_SET_USEBOOTLOADER( d, x ) \
2284 do { \
2285 DRX_ATTR_USEBOOTLOADER(d) = (x); \
2286 } while(0)
2287
2288#define DRX_GET_USEBOOTLOADER( d, x) \
2289 do { \
2290 (x)=DRX_ATTR_USEBOOTLOADER(d); \
2291 } while(0)
2292
2293/**************************/
2294
2295#define DRX_SET_CURRENTSTANDARD( d, x ) \
2296 do { \
2297 DRX_ATTR_CURRENTSTANDARD(d) = (x); \
2298 } while(0)
2299
2300#define DRX_GET_CURRENTSTANDARD( d, x) \
2301 do { \
2302 (x)=DRX_ATTR_CURRENTSTANDARD(d); \
2303 } while(0)
2304
2305/**************************/
2306
2307#define DRX_SET_PREVSTANDARD( d, x ) \
2308 do { \
2309 DRX_ATTR_PREVSTANDARD(d) = (x); \
2310 } while(0)
2311
2312#define DRX_GET_PREVSTANDARD( d, x) \
2313 do { \
2314 (x)=DRX_ATTR_PREVSTANDARD(d); \
2315 } while(0)
2316
2317/**************************/
2318
2319#define DRX_SET_CACHESTANDARD( d, x ) \
2320 do { \
2321 DRX_ATTR_CACHESTANDARD(d) = (x); \
2322 } while(0)
2323
2324#define DRX_GET_CACHESTANDARD( d, x) \
2325 do { \
2326 (x)=DRX_ATTR_CACHESTANDARD(d); \
2327 } while(0)
2328
2329/**************************/
2330
2331#define DRX_SET_CURRENTCHANNEL( d, x ) \
2332 do { \
2333 DRX_ATTR_CURRENTCHANNEL(d) = (x); \
2334 } while(0)
2335
2336#define DRX_GET_CURRENTCHANNEL( d, x) \
2337 do { \
2338 (x)=DRX_ATTR_CURRENTCHANNEL(d); \
2339 } while(0)
2340
2341/**************************/
2342
2343#define DRX_SET_ISOPENED( d, x ) \
2344 do { \
2345 DRX_ATTR_ISOPENED(d) = (x); \
2346 } while(0)
2347
2348#define DRX_GET_ISOPENED( d, x) \
2349 do { \
2350 (x) = DRX_ATTR_ISOPENED(d); \
2351 } while(0)
2352
2353/**************************/
2354
2355#define DRX_SET_TUNER( d, x ) \
2356 do { \
2357 DRX_ATTR_TUNER(d) = (x); \
2358 } while(0)
2359
2360#define DRX_GET_TUNER( d, x) \
2361 do { \
2362 (x) = DRX_ATTR_TUNER(d); \
2363 } while(0)
2364
2365/**************************/
2366
2367#define DRX_SET_CAPABILITIES( d, x ) \
2368 do { \
2369 DRX_ATTR_CAPABILITIES(d) = (x); \
2370 } while(0)
2371
2372#define DRX_GET_CAPABILITIES( d, x) \
2373 do { \
2374 (x) = DRX_ATTR_CAPABILITIES(d); \
2375 } while(0)
2376
2377/**************************/
2378
2379#define DRX_SET_PRODUCTID( d, x ) \
2380 do { \
2381 DRX_ATTR_PRODUCTID(d) |= (x << 4); \
2382 } while(0)
2383
2384#define DRX_GET_PRODUCTID( d, x) \
2385 do { \
2386 (x) = (DRX_ATTR_PRODUCTID(d) >> 4); \
2387 } while(0)
2388
2389/**************************/
2390
2391#define DRX_SET_MFX( d, x ) \
2392 do { \
2393 DRX_ATTR_PRODUCTID(d) |= (x); \
2394 } while(0)
2395
2396#define DRX_GET_MFX( d, x) \
2397 do { \
2398 (x) = (DRX_ATTR_PRODUCTID(d) & 0xF); \
2399 } while(0)
2400
2401/**************************/
2402
2403#define DRX_SET_INTERMEDIATEFREQ( d, x ) \
2404 do { \
2405 DRX_ATTR_INTERMEDIATEFREQ(d) = (x); \
2406 } while(0)
2407
2408#define DRX_GET_INTERMEDIATEFREQ( d, x) \
2409 do { \
2410 (x) = DRX_ATTR_INTERMEDIATEFREQ(d); \
2411 } while(0)
2412
2413/**************************/
2414
2415#define DRX_SET_SYSCLOCKFREQ( d, x ) \
2416 do { \
2417 DRX_ATTR_SYSCLOCKFREQ(d) = (x); \
2418 } while(0)
2419
2420#define DRX_GET_SYSCLOCKFREQ( d, x) \
2421 do { \
2422 (x) = DRX_ATTR_SYSCLOCKFREQ(d); \
2423 } while(0)
2424
2425/**************************/
2426
2427#define DRX_SET_TUNERRFAGCPOL( d, x ) \
2428 do { \
2429 DRX_ATTR_TUNERRFAGCPOL(d) = (x); \
2430 } while(0)
2431
2432#define DRX_GET_TUNERRFAGCPOL( d, x) \
2433 do { \
2434 (x) = DRX_ATTR_TUNERRFAGCPOL(d); \
2435 } while(0)
2436
2437/**************************/
2438
2439#define DRX_SET_TUNERIFAGCPOL( d, x ) \
2440 do { \
2441 DRX_ATTR_TUNERIFAGCPOL(d) = (x); \
2442 } while(0)
2443
2444#define DRX_GET_TUNERIFAGCPOL( d, x) \
2445 do { \
2446 (x) = DRX_ATTR_TUNERIFAGCPOL(d); \
2447 } while(0)
2448
2449/**************************/
2450
2451#define DRX_SET_TUNERSLOWMODE( d, x ) \
2452 do { \
2453 DRX_ATTR_TUNERSLOWMODE(d) = (x); \
2454 } while(0)
2455
2456#define DRX_GET_TUNERSLOWMODE( d, x) \
2457 do { \
2458 (x) = DRX_ATTR_TUNERSLOWMODE(d); \
2459 } while(0)
2460
2461/**************************/
2462
2463#define DRX_SET_TUNERPORTNR( d, x ) \
2464 do { \
2465 DRX_ATTR_TUNERSPORTNR(d) = (x); \
2466 } while(0)
2467
2468/**************************/
2469
2470/* Macros with device-specific handling are converted to CFG functions */
2471
2472#define DRX_ACCESSMACRO_SET( demod, value, cfgName, dataType ) \
2473 do { \
2474 DRXCfg_t config; \
2475 dataType cfgData; \
2476 config.cfgType = cfgName; \
2477 config.cfgData = &cfgData; \
2478 cfgData = value; \
2479 DRX_Ctrl( demod, DRX_CTRL_SET_CFG, &config ); \
2480 } while ( 0 )
2481
2482#define DRX_ACCESSMACRO_GET( demod, value, cfgName, dataType, errorValue ) \
2483 do { \
2484 DRXStatus_t cfgStatus; \
2485 DRXCfg_t config; \
2486 dataType cfgData; \
2487 config.cfgType = cfgName; \
2488 config.cfgData = &cfgData; \
2489 cfgStatus = DRX_Ctrl( demod, DRX_CTRL_GET_CFG, &config ); \
2490 if ( cfgStatus == DRX_STS_OK ) { \
2491 value = cfgData; \
2492 } else { \
2493 value = (dataType)errorValue; \
2494 } \
2495 } while ( 0 )
2496
2497
2498/* Configuration functions for usage by Access (XS) Macros */
2499
2500#ifndef DRX_XS_CFG_BASE
2501#define DRX_XS_CFG_BASE (500)
2502#endif
2503
2504#define DRX_XS_CFG_PRESET ( DRX_XS_CFG_BASE + 0 )
2505#define DRX_XS_CFG_AUD_BTSC_DETECT ( DRX_XS_CFG_BASE + 1 )
2506#define DRX_XS_CFG_QAM_LOCKRANGE ( DRX_XS_CFG_BASE + 2 )
2507
2508/* Access Macros with device-specific handling */
2509
2510#define DRX_SET_PRESET( d, x ) \
2511 DRX_ACCESSMACRO_SET( (d), (x), DRX_XS_CFG_PRESET, char* )
2512#define DRX_GET_PRESET( d, x ) \
2513 DRX_ACCESSMACRO_GET( (d), (x), DRX_XS_CFG_PRESET, char*, "ERROR" )
2514
2515#define DRX_SET_AUD_BTSC_DETECT( d, x ) DRX_ACCESSMACRO_SET( (d), (x), \
2516 DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t )
2517#define DRX_GET_AUD_BTSC_DETECT( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \
2518 DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t, DRX_UNKNOWN )
2519
2520#define DRX_SET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_SET( (d), (x), \
2521 DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t )
2522#define DRX_GET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \
2523 DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t, DRX_UNKNOWN )
2524
2525
2526/**
2527* \brief Macro to check if std is an ATV standard
2528* \retval TRUE std is an ATV standard
2529* \retval FALSE std is an ATV standard
2530*/
2531#define DRX_ISATVSTD( std ) ( ( (std) == DRX_STANDARD_PAL_SECAM_BG ) || \
2532 ( (std) == DRX_STANDARD_PAL_SECAM_DK ) || \
2533 ( (std) == DRX_STANDARD_PAL_SECAM_I ) || \
2534 ( (std) == DRX_STANDARD_PAL_SECAM_L ) || \
2535 ( (std) == DRX_STANDARD_PAL_SECAM_LP ) || \
2536 ( (std) == DRX_STANDARD_NTSC ) || \
2537 ( (std) == DRX_STANDARD_FM ) )
2538
2539/**
2540* \brief Macro to check if std is an QAM standard
2541* \retval TRUE std is an QAM standards
2542* \retval FALSE std is an QAM standards
2543*/
2544#define DRX_ISQAMSTD( std ) ( ( (std) == DRX_STANDARD_ITU_A ) || \
2545 ( (std) == DRX_STANDARD_ITU_B ) || \
2546 ( (std) == DRX_STANDARD_ITU_C ) || \
2547 ( (std) == DRX_STANDARD_ITU_D ))
2548
2549/**
2550* \brief Macro to check if std is VSB standard
2551* \retval TRUE std is VSB standard
2552* \retval FALSE std is not VSB standard
2553*/
2554#define DRX_ISVSBSTD( std ) ( (std) == DRX_STANDARD_8VSB )
2555
2556/**
2557* \brief Macro to check if std is DVBT standard
2558* \retval TRUE std is DVBT standard
2559* \retval FALSE std is not DVBT standard
2560*/
2561#define DRX_ISDVBTSTD( std ) ( (std) == DRX_STANDARD_DVBT )
2562
2563
2564
2565
2566/*-------------------------------------------------------------------------
2567Exported FUNCTIONS
2568-------------------------------------------------------------------------*/
2569
2570DRXStatus_t DRX_Init( pDRXDemodInstance_t demods[] );
2571
2572DRXStatus_t DRX_Term( void );
2573
2574DRXStatus_t DRX_Open(pDRXDemodInstance_t demod);
2575
2576DRXStatus_t DRX_Close(pDRXDemodInstance_t demod);
2577
2578DRXStatus_t DRX_Ctrl(pDRXDemodInstance_t demod,
2579 DRXCtrlIndex_t ctrl,
2580 void *ctrlData);
2581
2582/*-------------------------------------------------------------------------
2583THE END
2584-------------------------------------------------------------------------*/
2585#ifdef __cplusplus
2586}
2587#endif
2588#endif /* __DRXDRIVER_H__ */
Linux kernel - Deliverables
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