Commit | Line | Data |
---|---|---|
ca3355a9 DH |
1 | /* |
2 | Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. | |
3 | All rights reserved. | |
4 | ||
5 | Redistribution and use in source and binary forms, with or without | |
6 | modification, are permitted provided that the following conditions are met: | |
7 | ||
8 | * Redistributions of source code must retain the above copyright notice, | |
9 | this list of conditions and the following disclaimer. | |
10 | * Redistributions in binary form must reproduce the above copyright notice, | |
11 | this list of conditions and the following disclaimer in the documentation | |
12 | and/or other materials provided with the distribution. | |
13 | * Neither the name of Trident Microsystems nor Hauppauge Computer Works | |
14 | nor the names of its contributors may be used to endorse or promote | |
15 | products derived from this software without specific prior written | |
16 | permission. | |
17 | ||
18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
19 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
20 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
21 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE | |
22 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
23 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
24 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
25 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
26 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
27 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
28 | POSSIBILITY OF SUCH DAMAGE. | |
29 | */ | |
30 | ||
38b2df95 DH |
31 | /** |
32 | * \file $Id: drxj.h,v 1.132 2009/12/22 12:13:48 danielg Exp $ | |
33 | * | |
34 | * \brief DRXJ specific header file | |
35 | * | |
36 | * \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen | |
37 | */ | |
38 | ||
38b2df95 DH |
39 | #ifndef __DRXJ_H__ |
40 | #define __DRXJ_H__ | |
41 | /*------------------------------------------------------------------------- | |
42 | INCLUDES | |
43 | -------------------------------------------------------------------------*/ | |
44 | ||
45 | #include "drx_driver.h" | |
46 | #include "drx_dap_fasi.h" | |
47 | ||
48 | #ifdef __cplusplus | |
49 | extern "C" { | |
50 | #endif | |
51 | ||
52 | /* Check DRX-J specific dap condition */ | |
53 | /* Multi master mode and short addr format only will not work. | |
54 | RMW, CRC reset, broadcast and switching back to single master mode | |
55 | cannot be done with short addr only in multi master mode. */ | |
7ef66759 | 56 | #if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)) |
38b2df95 | 57 | #error "Multi master mode and short addressing only is an illegal combination" |
443f18d0 MCC |
58 | *; /* Generate a fatal compiler error to make sure it stops here, |
59 | this is necesarry because not all compilers stop after a #error. */ | |
38b2df95 DH |
60 | #endif |
61 | ||
62 | /*------------------------------------------------------------------------- | |
63 | TYPEDEFS | |
64 | -------------------------------------------------------------------------*/ | |
65 | /*============================================================================*/ | |
66 | /*============================================================================*/ | |
67 | /*== code support ============================================================*/ | |
68 | /*============================================================================*/ | |
69 | /*============================================================================*/ | |
70 | ||
71 | /*============================================================================*/ | |
72 | /*============================================================================*/ | |
73 | /*== SCU cmd if =============================================================*/ | |
74 | /*============================================================================*/ | |
75 | /*============================================================================*/ | |
76 | ||
443f18d0 | 77 | typedef struct { |
43a431e4 | 78 | u16 command; |
443f18d0 | 79 | /**< Command number */ |
57afe2f0 | 80 | u16 parameter_len; |
443f18d0 | 81 | /**< Data length in byte */ |
57afe2f0 | 82 | u16 result_len; |
443f18d0 | 83 | /**< result length in byte */ |
43a431e4 | 84 | u16 *parameter; |
443f18d0 | 85 | /**< General purpous param */ |
43a431e4 | 86 | u16 *result; |
443f18d0 | 87 | /**< General purpous param */ |
57afe2f0 | 88 | } drxjscu_cmd_t, *p_drxjscu_cmd_t; |
38b2df95 DH |
89 | |
90 | /*============================================================================*/ | |
91 | /*============================================================================*/ | |
92 | /*== CTRL CFG related data structures ========================================*/ | |
93 | /*============================================================================*/ | |
94 | /*============================================================================*/ | |
95 | ||
96 | /* extra intermediate lock state for VSB,QAM,NTSC */ | |
97 | #define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1) | |
98 | ||
99 | /* OOB lock states */ | |
443f18d0 MCC |
100 | #define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ |
101 | #define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ | |
38b2df95 DH |
102 | |
103 | /* Intermediate powermodes for DRXJ */ | |
104 | #define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8 | |
105 | #define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9 | |
106 | #define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10 | |
107 | ||
108 | /* supstition for GPIO FNC mux */ | |
109 | #define APP_O (0x0000) | |
110 | ||
111 | /*#define DRX_CTRL_BASE (0x0000)*/ | |
112 | ||
113 | #define DRXJ_CTRL_CFG_BASE (0x1000) | |
443f18d0 MCC |
114 | typedef enum { |
115 | DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, | |
116 | DRXJ_CFG_AGC_IF, | |
117 | DRXJ_CFG_AGC_INTERNAL, | |
118 | DRXJ_CFG_PRE_SAW, | |
119 | DRXJ_CFG_AFE_GAIN, | |
120 | DRXJ_CFG_SYMBOL_CLK_OFFSET, | |
121 | DRXJ_CFG_ACCUM_CR_RS_CW_ERR, | |
122 | DRXJ_CFG_FEC_MERS_SEQ_COUNT, | |
123 | DRXJ_CFG_OOB_MISC, | |
124 | DRXJ_CFG_SMART_ANT, | |
125 | DRXJ_CFG_OOB_PRE_SAW, | |
126 | DRXJ_CFG_VSB_MISC, | |
127 | DRXJ_CFG_RESET_PACKET_ERR, | |
128 | ||
129 | /* ATV (FM) */ | |
130 | DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ | |
131 | DRXJ_CFG_ATV_MISC, | |
132 | DRXJ_CFG_ATV_EQU_COEF, | |
133 | DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ | |
134 | ||
135 | DRXJ_CFG_MPEG_OUTPUT_MISC, | |
136 | DRXJ_CFG_HW_CFG, | |
137 | DRXJ_CFG_OOB_LO_POW, | |
138 | ||
139 | DRXJ_CFG_MAX /* dummy, never to be used */ | |
57afe2f0 | 140 | } drxj_cfg_type_t, *pdrxj_cfg_type_t; |
38b2df95 DH |
141 | |
142 | /** | |
57afe2f0 | 143 | * /struct drxj_cfg_smart_ant_io_t |
38b2df95 DH |
144 | * smart antenna i/o. |
145 | */ | |
57afe2f0 | 146 | typedef enum drxj_cfg_smart_ant_io_t { |
443f18d0 MCC |
147 | DRXJ_SMT_ANT_OUTPUT = 0, |
148 | DRXJ_SMT_ANT_INPUT | |
57afe2f0 | 149 | } drxj_cfg_smart_ant_io_t, *pdrxj_cfg_smart_ant_io_t; |
38b2df95 DH |
150 | |
151 | /** | |
57afe2f0 | 152 | * /struct drxj_cfg_smart_ant_t |
38b2df95 DH |
153 | * Set smart antenna. |
154 | */ | |
443f18d0 | 155 | typedef struct { |
57afe2f0 MCC |
156 | drxj_cfg_smart_ant_io_t io; |
157 | u16 ctrl_data; | |
158 | } drxj_cfg_smart_ant_t, *p_drxj_cfg_smart_ant_t; | |
38b2df95 DH |
159 | |
160 | /** | |
161 | * /struct DRXJAGCSTATUS_t | |
162 | * AGC status information from the DRXJ-IQM-AF. | |
163 | */ | |
443f18d0 | 164 | typedef struct { |
43a431e4 MCC |
165 | u16 IFAGC; |
166 | u16 RFAGC; | |
57afe2f0 MCC |
167 | u16 digital_agc; |
168 | } drxj_agc_status_t, *pdrxj_agc_status_t; | |
38b2df95 DH |
169 | |
170 | /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ | |
171 | ||
172 | /** | |
57afe2f0 | 173 | * /struct drxj_agc_ctrl_mode_t |
38b2df95 DH |
174 | * Available AGCs modes in the DRXJ. |
175 | */ | |
443f18d0 MCC |
176 | typedef enum { |
177 | DRX_AGC_CTRL_AUTO = 0, | |
178 | DRX_AGC_CTRL_USER, | |
179 | DRX_AGC_CTRL_OFF | |
57afe2f0 | 180 | } drxj_agc_ctrl_mode_t, *pdrxj_agc_ctrl_mode_t; |
38b2df95 DH |
181 | |
182 | /** | |
57afe2f0 | 183 | * /struct drxj_cfg_agc_t |
38b2df95 DH |
184 | * Generic interface for all AGCs present on the DRXJ. |
185 | */ | |
443f18d0 | 186 | typedef struct { |
61263c75 | 187 | enum drx_standard standard; /* standard for which these settings apply */ |
57afe2f0 MCC |
188 | drxj_agc_ctrl_mode_t ctrl_mode; /* off, user, auto */ |
189 | u16 output_level; /* range dependent on AGC */ | |
190 | u16 min_output_level; /* range dependent on AGC */ | |
191 | u16 max_output_level; /* range dependent on AGC */ | |
43a431e4 MCC |
192 | u16 speed; /* range dependent on AGC */ |
193 | u16 top; /* rf-agc take over point */ | |
57afe2f0 | 194 | u16 cut_off_current; /* rf-agc is accelerated if output current |
443f18d0 | 195 | is below cut-off current */ |
57afe2f0 | 196 | } drxj_cfg_agc_t, *p_drxj_cfg_agc_t; |
38b2df95 DH |
197 | |
198 | /* DRXJ_CFG_PRE_SAW */ | |
199 | ||
200 | /** | |
57afe2f0 | 201 | * /struct drxj_cfg_pre_saw_t |
38b2df95 DH |
202 | * Interface to configure pre SAW sense. |
203 | */ | |
443f18d0 | 204 | typedef struct { |
61263c75 | 205 | enum drx_standard standard; /* standard to which these settings apply */ |
43a431e4 | 206 | u16 reference; /* pre SAW reference value, range 0 .. 31 */ |
57afe2f0 MCC |
207 | bool use_pre_saw; /* true algorithms must use pre SAW sense */ |
208 | } drxj_cfg_pre_saw_t, *p_drxj_cfg_pre_saw_t; | |
38b2df95 DH |
209 | |
210 | /* DRXJ_CFG_AFE_GAIN */ | |
211 | ||
212 | /** | |
57afe2f0 | 213 | * /struct drxj_cfg_afe_gain_t |
38b2df95 DH |
214 | * Interface to configure gain of AFE (LNA + PGA). |
215 | */ | |
443f18d0 | 216 | typedef struct { |
61263c75 | 217 | enum drx_standard standard; /* standard to which these settings apply */ |
43a431e4 | 218 | u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ |
57afe2f0 | 219 | } drxj_cfg_afe_gain_t, *p_drxj_cfg_afe_gain_t; |
38b2df95 DH |
220 | |
221 | /** | |
57afe2f0 | 222 | * /struct DRXJrs_errors_t |
38b2df95 DH |
223 | * Available failure information in DRXJ_FEC_RS. |
224 | * | |
225 | * Container for errors that are received in the most recently finished measurment period | |
226 | * | |
227 | */ | |
443f18d0 | 228 | typedef struct { |
57afe2f0 | 229 | u16 nr_bit_errors; |
443f18d0 | 230 | /**< no of pre RS bit errors */ |
57afe2f0 | 231 | u16 nr_symbol_errors; |
443f18d0 | 232 | /**< no of pre RS symbol errors */ |
57afe2f0 | 233 | u16 nr_packet_errors; |
443f18d0 | 234 | /**< no of pre RS packet errors */ |
57afe2f0 | 235 | u16 nr_failures; |
443f18d0 | 236 | /**< no of post RS failures to decode */ |
57afe2f0 | 237 | u16 nr_snc_par_fail_count; |
443f18d0 | 238 | /**< no of post RS bit erros */ |
57afe2f0 | 239 | } DRXJrs_errors_t, *p_drxjrs_errors_t; |
38b2df95 DH |
240 | |
241 | /** | |
57afe2f0 | 242 | * /struct drxj_cfg_vsb_misc_t |
38b2df95 DH |
243 | * symbol error rate |
244 | */ | |
443f18d0 | 245 | typedef struct { |
57afe2f0 | 246 | u32 symb_error; |
443f18d0 | 247 | /**< symbol error rate sps */ |
57afe2f0 | 248 | } drxj_cfg_vsb_misc_t, *p_drxj_cfg_vsb_misc_t; |
38b2df95 DH |
249 | |
250 | /** | |
57afe2f0 | 251 | * /enum drxj_mpeg_output_clock_rate_t |
38b2df95 DH |
252 | * Mpeg output clock rate. |
253 | * | |
254 | */ | |
443f18d0 MCC |
255 | typedef enum { |
256 | DRXJ_MPEG_START_WIDTH_1CLKCYC, | |
257 | DRXJ_MPEG_START_WIDTH_8CLKCYC | |
57afe2f0 | 258 | } drxj_mpeg_start_width_t, *pdrxj_mpeg_start_width_t; |
38b2df95 DH |
259 | |
260 | /** | |
57afe2f0 | 261 | * /enum drxj_mpeg_output_clock_rate_t |
38b2df95 DH |
262 | * Mpeg output clock rate. |
263 | * | |
264 | */ | |
443f18d0 MCC |
265 | typedef enum { |
266 | DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, | |
267 | DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, | |
268 | DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, | |
269 | DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, | |
270 | DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, | |
271 | DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, | |
272 | DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K | |
57afe2f0 | 273 | } drxj_mpeg_output_clock_rate_t, *pdrxj_mpeg_output_clock_rate_t; |
38b2df95 DH |
274 | |
275 | /** | |
276 | * /struct DRXJCfgMisc_t | |
277 | * Change TEI bit of MPEG output | |
278 | * reverse MPEG output bit order | |
279 | * set MPEG output clock rate | |
280 | */ | |
443f18d0 | 281 | typedef struct { |
57afe2f0 MCC |
282 | bool disable_tei_handling; /**< if true pass (not change) TEI bit */ |
283 | bool bit_reverse_mpeg_outout; /**< if true, parallel: msb on MD0; serial: lsb out first */ | |
284 | drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate; | |
443f18d0 | 285 | /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ |
57afe2f0 MCC |
286 | drxj_mpeg_start_width_t mpeg_start_width; /**< set MPEG output start width */ |
287 | } drxj_cfg_mpeg_output_misc_t, *p_drxj_cfg_mpeg_output_misc_t; | |
38b2df95 DH |
288 | |
289 | /** | |
57afe2f0 | 290 | * /enum drxj_xtal_freq_t |
38b2df95 DH |
291 | * Supported external crystal reference frequency. |
292 | */ | |
443f18d0 MCC |
293 | typedef enum { |
294 | DRXJ_XTAL_FREQ_RSVD, | |
295 | DRXJ_XTAL_FREQ_27MHZ, | |
296 | DRXJ_XTAL_FREQ_20P25MHZ, | |
297 | DRXJ_XTAL_FREQ_4MHZ | |
57afe2f0 | 298 | } drxj_xtal_freq_t, *pdrxj_xtal_freq_t; |
38b2df95 DH |
299 | |
300 | /** | |
57afe2f0 | 301 | * /enum drxj_xtal_freq_t |
38b2df95 DH |
302 | * Supported external crystal reference frequency. |
303 | */ | |
443f18d0 MCC |
304 | typedef enum { |
305 | DRXJ_I2C_SPEED_400KBPS, | |
306 | DRXJ_I2C_SPEED_100KBPS | |
57afe2f0 | 307 | } drxji2c_speed_t, *pdrxji2c_speed_t; |
38b2df95 DH |
308 | |
309 | /** | |
57afe2f0 | 310 | * /struct drxj_cfg_hw_cfg_t |
38b2df95 DH |
311 | * Get hw configuration, such as crystal reference frequency, I2C speed, etc... |
312 | */ | |
443f18d0 | 313 | typedef struct { |
57afe2f0 | 314 | drxj_xtal_freq_t xtal_freq; |
443f18d0 | 315 | /**< crystal reference frequency */ |
57afe2f0 | 316 | drxji2c_speed_t i2c_speed; |
443f18d0 | 317 | /**< 100 or 400 kbps */ |
57afe2f0 | 318 | } drxj_cfg_hw_cfg_t, *p_drxj_cfg_hw_cfg_t; |
38b2df95 DH |
319 | |
320 | /* | |
321 | * DRXJ_CFG_ATV_MISC | |
322 | */ | |
443f18d0 | 323 | typedef struct { |
57afe2f0 MCC |
324 | s16 peak_filter; /* -8 .. 15 */ |
325 | u16 noise_filter; /* 0 .. 15 */ | |
326 | } drxj_cfg_atv_misc_t, *p_drxj_cfg_atv_misc_t; | |
38b2df95 DH |
327 | |
328 | /* | |
57afe2f0 | 329 | * drxj_cfg_oob_misc_t |
38b2df95 DH |
330 | */ |
331 | #define DRXJ_OOB_STATE_RESET 0x0 | |
332 | #define DRXJ_OOB_STATE_AGN_HUNT 0x1 | |
333 | #define DRXJ_OOB_STATE_DGN_HUNT 0x2 | |
334 | #define DRXJ_OOB_STATE_AGC_HUNT 0x3 | |
335 | #define DRXJ_OOB_STATE_FRQ_HUNT 0x4 | |
336 | #define DRXJ_OOB_STATE_PHA_HUNT 0x8 | |
337 | #define DRXJ_OOB_STATE_TIM_HUNT 0x10 | |
338 | #define DRXJ_OOB_STATE_EQU_HUNT 0x20 | |
339 | #define DRXJ_OOB_STATE_EQT_HUNT 0x30 | |
340 | #define DRXJ_OOB_STATE_SYNC 0x40 | |
341 | ||
443f18d0 | 342 | typedef struct { |
57afe2f0 MCC |
343 | drxj_agc_status_t agc; |
344 | bool eq_lock; | |
345 | bool sym_timing_lock; | |
346 | bool phase_lock; | |
347 | bool freq_lock; | |
348 | bool dig_gain_lock; | |
349 | bool ana_gain_lock; | |
43a431e4 | 350 | u8 state; |
57afe2f0 | 351 | } drxj_cfg_oob_misc_t, *p_drxj_cfg_oob_misc_t; |
38b2df95 DH |
352 | |
353 | /* | |
354 | * Index of in array of coef | |
355 | */ | |
443f18d0 MCC |
356 | typedef enum { |
357 | DRXJ_OOB_LO_POW_MINUS0DB = 0, | |
358 | DRXJ_OOB_LO_POW_MINUS5DB, | |
359 | DRXJ_OOB_LO_POW_MINUS10DB, | |
360 | DRXJ_OOB_LO_POW_MINUS15DB, | |
361 | DRXJ_OOB_LO_POW_MAX | |
57afe2f0 | 362 | } drxj_cfg_oob_lo_power_t, *p_drxj_cfg_oob_lo_power_t; |
38b2df95 DH |
363 | |
364 | /* | |
365 | * DRXJ_CFG_ATV_EQU_COEF | |
366 | */ | |
443f18d0 | 367 | typedef struct { |
43a431e4 MCC |
368 | s16 coef0; /* -256 .. 255 */ |
369 | s16 coef1; /* -256 .. 255 */ | |
370 | s16 coef2; /* -256 .. 255 */ | |
371 | s16 coef3; /* -256 .. 255 */ | |
57afe2f0 | 372 | } drxj_cfg_atv_equ_coef_t, *p_drxj_cfg_atv_equ_coef_t; |
38b2df95 DH |
373 | |
374 | /* | |
375 | * Index of in array of coef | |
376 | */ | |
443f18d0 MCC |
377 | typedef enum { |
378 | DRXJ_COEF_IDX_MN = 0, | |
379 | DRXJ_COEF_IDX_FM, | |
380 | DRXJ_COEF_IDX_L, | |
381 | DRXJ_COEF_IDX_LP, | |
382 | DRXJ_COEF_IDX_BG, | |
383 | DRXJ_COEF_IDX_DK, | |
384 | DRXJ_COEF_IDX_I, | |
385 | DRXJ_COEF_IDX_MAX | |
57afe2f0 | 386 | } drxj_coef_array_index_t, *pdrxj_coef_array_index_t; |
38b2df95 DH |
387 | |
388 | /* | |
389 | * DRXJ_CFG_ATV_OUTPUT | |
390 | */ | |
391 | ||
392 | /** | |
393 | * /enum DRXJAttenuation_t | |
394 | * Attenuation setting for SIF AGC. | |
395 | * | |
396 | */ | |
443f18d0 MCC |
397 | typedef enum { |
398 | DRXJ_SIF_ATTENUATION_0DB, | |
399 | DRXJ_SIF_ATTENUATION_3DB, | |
400 | DRXJ_SIF_ATTENUATION_6DB, | |
401 | DRXJ_SIF_ATTENUATION_9DB | |
57afe2f0 | 402 | } drxjsif_attenuation_t, *pdrxjsif_attenuation_t; |
38b2df95 DH |
403 | |
404 | /** | |
57afe2f0 | 405 | * /struct drxj_cfg_atv_output_t |
38b2df95 DH |
406 | * SIF attenuation setting. |
407 | * | |
408 | */ | |
443f18d0 | 409 | typedef struct { |
57afe2f0 MCC |
410 | bool enable_cvbs_output; /* true= enabled */ |
411 | bool enable_sif_output; /* true= enabled */ | |
412 | drxjsif_attenuation_t sif_attenuation; | |
413 | } drxj_cfg_atv_output_t, *p_drxj_cfg_atv_output_t; | |
38b2df95 DH |
414 | |
415 | /* | |
416 | DRXJ_CFG_ATV_AGC_STATUS (get only) | |
417 | */ | |
418 | /* TODO : AFE interface not yet finished, subject to change */ | |
443f18d0 | 419 | typedef struct { |
57afe2f0 MCC |
420 | u16 rf_agc_gain; /* 0 .. 877 uA */ |
421 | u16 if_agc_gain; /* 0 .. 877 uA */ | |
422 | s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */ | |
423 | s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */ | |
424 | u16 rf_agc_loop_gain; /* 0 .. 7 */ | |
425 | u16 if_agc_loop_gain; /* 0 .. 7 */ | |
426 | u16 video_agc_loop_gain; /* 0 .. 7 */ | |
427 | } drxj_cfg_atv_agc_status_t, *p_drxj_cfg_atv_agc_status_t; | |
38b2df95 DH |
428 | |
429 | /*============================================================================*/ | |
430 | /*============================================================================*/ | |
431 | /*== CTRL related data structures ============================================*/ | |
432 | /*============================================================================*/ | |
433 | /*============================================================================*/ | |
434 | ||
435 | /* NONE */ | |
436 | ||
437 | /*============================================================================*/ | |
438 | /*============================================================================*/ | |
439 | ||
440 | /*========================================*/ | |
441 | /** | |
57afe2f0 | 442 | * /struct drxj_data_t |
38b2df95 DH |
443 | * DRXJ specific attributes. |
444 | * | |
445 | * Global data container for DRXJ specific data. | |
446 | * | |
447 | */ | |
443f18d0 | 448 | typedef struct { |
57afe2f0 MCC |
449 | /* device capabilties (determined during drx_open()) */ |
450 | bool has_lna; /**< true if LNA (aka PGA) present */ | |
451 | bool has_oob; /**< true if OOB supported */ | |
452 | bool has_ntsc; /**< true if NTSC supported */ | |
453 | bool has_btsc; /**< true if BTSC supported */ | |
454 | bool has_smatx; /**< true if mat_tx is available */ | |
455 | bool has_smarx; /**< true if mat_rx is available */ | |
456 | bool has_gpio; /**< true if GPIO is available */ | |
457 | bool has_irqn; /**< true if IRQN is available */ | |
443f18d0 | 458 | /* A1/A2/A... */ |
43a431e4 | 459 | u8 mfx; /**< metal fix */ |
443f18d0 MCC |
460 | |
461 | /* tuner settings */ | |
57afe2f0 | 462 | bool mirror_freq_spectOOB;/**< tuner inversion (true = tuner mirrors the signal */ |
443f18d0 MCC |
463 | |
464 | /* standard/channel settings */ | |
61263c75 MCC |
465 | enum drx_standard standard; /**< current standard information */ |
466 | enum drx_modulation constellation; | |
443f18d0 | 467 | /**< current constellation */ |
73f7065b | 468 | s32 frequency; /**< center signal frequency in KHz */ |
57afe2f0 | 469 | enum drx_bandwidth curr_bandwidth; |
443f18d0 | 470 | /**< current channel bandwidth */ |
61263c75 | 471 | enum drx_mirror mirror; /**< current channel mirror */ |
443f18d0 MCC |
472 | |
473 | /* signal quality information */ | |
57afe2f0 MCC |
474 | u32 fec_bits_desired; /**< BER accounting period */ |
475 | u16 fec_vd_plen; /**< no of trellis symbols: VD SER measurement period */ | |
476 | u16 qam_vd_prescale; /**< Viterbi Measurement Prescale */ | |
477 | u16 qam_vd_period; /**< Viterbi Measurement period */ | |
478 | u16 fec_rs_plen; /**< defines RS BER measurement period */ | |
479 | u16 fec_rs_prescale; /**< ReedSolomon Measurement Prescale */ | |
480 | u16 fec_rs_period; /**< ReedSolomon Measurement period */ | |
481 | bool reset_pkt_err_acc; /**< Set a flag to reset accumulated packet error */ | |
482 | u16 pkt_errAccStart; /**< Set a flag to reset accumulated packet error */ | |
443f18d0 MCC |
483 | |
484 | /* HI configuration */ | |
57afe2f0 MCC |
485 | u16 hi_cfg_timing_div; /**< HI Configure() parameter 2 */ |
486 | u16 hi_cfg_bridge_delay; /**< HI Configure() parameter 3 */ | |
487 | u16 hi_cfg_wake_up_key; /**< HI Configure() parameter 4 */ | |
488 | u16 hi_cfg_ctrl; /**< HI Configure() parameter 5 */ | |
489 | u16 hi_cfg_transmit; /**< HI Configure() parameter 6 */ | |
443f18d0 MCC |
490 | |
491 | /* UIO configuartion */ | |
1bfc9e15 MCC |
492 | enum drxuio_mode uio_sma_rx_mode;/**< current mode of SmaRx pin */ |
493 | enum drxuio_mode uio_sma_tx_mode;/**< current mode of SmaTx pin */ | |
494 | enum drxuio_mode uio_gpio_mode; /**< current mode of ASEL pin */ | |
495 | enum drxuio_mode uio_irqn_mode; /**< current mode of IRQN pin */ | |
443f18d0 MCC |
496 | |
497 | /* IQM fs frequecy shift and inversion */ | |
57afe2f0 MCC |
498 | u32 iqm_fs_rate_ofs; /**< frequency shifter setting after setchannel */ |
499 | bool pos_image; /**< Ture: positive image */ | |
443f18d0 | 500 | /* IQM RC frequecy shift */ |
57afe2f0 | 501 | u32 iqm_rc_rate_ofs; /**< frequency shifter setting after setchannel */ |
443f18d0 MCC |
502 | |
503 | /* ATV configuartion */ | |
57afe2f0 MCC |
504 | u32 atv_cfg_changed_flags; /**< flag: flags cfg changes */ |
505 | s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ | |
506 | s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ | |
507 | s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ | |
508 | s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ | |
509 | bool phase_correction_bypass;/**< flag: true=bypass */ | |
510 | s16 atv_top_vid_peak; /**< shadow of ATV_TOP_VID_PEAK__A */ | |
511 | u16 atv_top_noise_th; /**< shadow of ATV_TOP_NOISE_TH__A */ | |
512 | bool enable_cvbs_output; /**< flag CVBS ouput enable */ | |
513 | bool enable_sif_output; /**< flag SIF ouput enable */ | |
514 | drxjsif_attenuation_t sif_attenuation; | |
443f18d0 MCC |
515 | /**< current SIF att setting */ |
516 | /* Agc configuration for QAM and VSB */ | |
57afe2f0 MCC |
517 | drxj_cfg_agc_t qam_rf_agc_cfg; /**< qam RF AGC config */ |
518 | drxj_cfg_agc_t qam_if_agc_cfg; /**< qam IF AGC config */ | |
519 | drxj_cfg_agc_t vsb_rf_agc_cfg; /**< vsb RF AGC config */ | |
520 | drxj_cfg_agc_t vsb_if_agc_cfg; /**< vsb IF AGC config */ | |
443f18d0 MCC |
521 | |
522 | /* PGA gain configuration for QAM and VSB */ | |
57afe2f0 MCC |
523 | u16 qam_pga_cfg; /**< qam PGA config */ |
524 | u16 vsb_pga_cfg; /**< vsb PGA config */ | |
443f18d0 MCC |
525 | |
526 | /* Pre SAW configuration for QAM and VSB */ | |
57afe2f0 | 527 | drxj_cfg_pre_saw_t qam_pre_saw_cfg; |
443f18d0 | 528 | /**< qam pre SAW config */ |
57afe2f0 | 529 | drxj_cfg_pre_saw_t vsb_pre_saw_cfg; |
443f18d0 MCC |
530 | /**< qam pre SAW config */ |
531 | ||
532 | /* Version information */ | |
57afe2f0 | 533 | char v_text[2][12]; /**< allocated text versions */ |
1bfc9e15 MCC |
534 | struct drx_version v_version[2]; /**< allocated versions structs */ |
535 | struct drx_version_list v_list_elements[2]; | |
443f18d0 MCC |
536 | /**< allocated version list */ |
537 | ||
538 | /* smart antenna configuration */ | |
57afe2f0 | 539 | bool smart_ant_inverted; |
443f18d0 MCC |
540 | |
541 | /* Tracking filter setting for OOB */ | |
57afe2f0 MCC |
542 | u16 oob_trk_filter_cfg[8]; |
543 | bool oob_power_on; | |
443f18d0 MCC |
544 | |
545 | /* MPEG static bitrate setting */ | |
57afe2f0 MCC |
546 | u32 mpeg_ts_static_bitrate; /**< bitrate static MPEG output */ |
547 | bool disable_te_ihandling; /**< MPEG TS TEI handling */ | |
548 | bool bit_reverse_mpeg_outout;/**< MPEG output bit order */ | |
549 | drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate; | |
443f18d0 | 550 | /**< MPEG output clock rate */ |
57afe2f0 | 551 | drxj_mpeg_start_width_t mpeg_start_width; |
443f18d0 MCC |
552 | /**< MPEG Start width */ |
553 | ||
554 | /* Pre SAW & Agc configuration for ATV */ | |
57afe2f0 | 555 | drxj_cfg_pre_saw_t atv_pre_saw_cfg; |
443f18d0 | 556 | /**< atv pre SAW config */ |
57afe2f0 MCC |
557 | drxj_cfg_agc_t atv_rf_agc_cfg; /**< atv RF AGC config */ |
558 | drxj_cfg_agc_t atv_if_agc_cfg; /**< atv IF AGC config */ | |
559 | u16 atv_pga_cfg; /**< atv pga config */ | |
443f18d0 | 560 | |
57afe2f0 | 561 | u32 curr_symbol_rate; |
443f18d0 MCC |
562 | |
563 | /* pin-safe mode */ | |
57afe2f0 MCC |
564 | bool pdr_safe_mode; /**< PDR safe mode activated */ |
565 | u16 pdr_safe_restore_val_gpio; | |
566 | u16 pdr_safe_restore_val_v_sync; | |
567 | u16 pdr_safe_restore_val_sma_rx; | |
568 | u16 pdr_safe_restore_val_sma_tx; | |
443f18d0 MCC |
569 | |
570 | /* OOB pre-saw value */ | |
57afe2f0 MCC |
571 | u16 oob_pre_saw; |
572 | drxj_cfg_oob_lo_power_t oob_lo_pow; | |
443f18d0 | 573 | |
1bfc9e15 | 574 | struct drx_aud_data aud_data; |
443f18d0 MCC |
575 | /**< audio storage */ |
576 | ||
57afe2f0 | 577 | } drxj_data_t, *pdrxj_data_t; |
38b2df95 DH |
578 | |
579 | /*------------------------------------------------------------------------- | |
580 | Access MACROS | |
581 | -------------------------------------------------------------------------*/ | |
582 | /** | |
583 | * \brief Compilable references to attributes | |
584 | * \param d pointer to demod instance | |
585 | * | |
586 | * Used as main reference to an attribute field. | |
587 | * Can be used by both macro implementation and function implementation. | |
588 | * These macros are defined to avoid duplication of code in macro and function | |
589 | * definitions that handle access of demod common or extended attributes. | |
590 | * | |
591 | */ | |
592 | ||
7ef66759 | 593 | #define DRXJ_ATTR_BTSC_DETECT(d) \ |
57afe2f0 | 594 | (((pdrxj_data_t)(d)->my_ext_attr)->aud_data.btsc_detect) |
38b2df95 DH |
595 | |
596 | /** | |
597 | * \brief Actual access macros | |
598 | * \param d pointer to demod instance | |
599 | * \param x value to set or to get | |
600 | * | |
601 | * SET macros must be used to set the value of an attribute. | |
602 | * GET macros must be used to retrieve the value of an attribute. | |
603 | * Depending on the value of DRX_USE_ACCESS_FUNCTIONS the macro's will be | |
604 | * substituted by "direct-access-inline-code" or a function call. | |
605 | * | |
606 | */ | |
7ef66759 | 607 | #define DRXJ_GET_BTSC_DETECT(d, x) \ |
38b2df95 | 608 | do { \ |
7ef66759 MCC |
609 | (x) = DRXJ_ATTR_BTSC_DETECT((d); \ |
610 | } while (0) | |
38b2df95 | 611 | |
7ef66759 | 612 | #define DRXJ_SET_BTSC_DETECT(d, x) \ |
38b2df95 | 613 | do { \ |
7ef66759 MCC |
614 | DRXJ_ATTR_BTSC_DETECT(d) = (x); \ |
615 | } while (0) | |
38b2df95 | 616 | |
38b2df95 DH |
617 | /*------------------------------------------------------------------------- |
618 | DEFINES | |
619 | -------------------------------------------------------------------------*/ | |
620 | ||
621 | /** | |
622 | * \def DRXJ_NTSC_CARRIER_FREQ_OFFSET | |
623 | * \brief Offset from picture carrier to centre frequency in kHz, in RF domain | |
624 | * | |
625 | * For NTSC standard. | |
626 | * NTSC channels are listed by their picture carrier frequency (Fpc). | |
627 | * The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input. | |
628 | * In case the tuner module is not used the DRX-J requires that the tuner is | |
629 | * tuned to the centre frequency of the channel: | |
630 | * | |
631 | * Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET | |
632 | * | |
633 | */ | |
73f7065b | 634 | #define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750)) |
38b2df95 DH |
635 | |
636 | /** | |
637 | * \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET | |
638 | * \brief Offset from picture carrier to centre frequency in kHz, in RF domain | |
639 | * | |
640 | * For PAL/SECAM - BG standard. This define is needed in case the tuner module | |
641 | * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). | |
642 | * The DRX-J requires that the tuner is tuned to: | |
643 | * Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET | |
644 | * | |
645 | * In case the tuner module is used the drxdriver takes care of this. | |
646 | * In case the tuner module is NOT used the application programmer must take | |
647 | * care of this. | |
648 | * | |
649 | */ | |
73f7065b | 650 | #define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375)) |
38b2df95 DH |
651 | |
652 | /** | |
653 | * \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET | |
654 | * \brief Offset from picture carrier to centre frequency in kHz, in RF domain | |
655 | * | |
656 | * For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module | |
657 | * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). | |
658 | * The DRX-J requires that the tuner is tuned to: | |
659 | * Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET | |
660 | * | |
661 | * In case the tuner module is used the drxdriver takes care of this. | |
662 | * In case the tuner module is NOT used the application programmer must take | |
663 | * care of this. | |
664 | * | |
665 | */ | |
73f7065b | 666 | #define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775)) |
38b2df95 DH |
667 | |
668 | /** | |
669 | * \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET | |
670 | * \brief Offset from picture carrier to centre frequency in kHz, in RF domain | |
671 | * | |
672 | * For PAL/SECAM - LP standard. This define is needed in case the tuner module | |
673 | * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). | |
674 | * The DRX-J requires that the tuner is tuned to: | |
675 | * Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET | |
676 | * | |
677 | * In case the tuner module is used the drxdriver takes care of this. | |
678 | * In case the tuner module is NOT used the application programmer must take | |
679 | * care of this. | |
680 | */ | |
73f7065b | 681 | #define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255)) |
38b2df95 DH |
682 | |
683 | /** | |
684 | * \def DRXJ_FM_CARRIER_FREQ_OFFSET | |
685 | * \brief Offset from sound carrier to centre frequency in kHz, in RF domain | |
686 | * | |
687 | * For FM standard. | |
688 | * FM channels are listed by their sound carrier frequency (Fsc). | |
689 | * The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as | |
690 | * input. | |
691 | * In case the tuner module is not used the DRX-J requires that the tuner is | |
692 | * tuned to the Ffm frequency of the channel. | |
693 | * | |
694 | * Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET | |
695 | * | |
696 | */ | |
73f7065b | 697 | #define DRXJ_FM_CARRIER_FREQ_OFFSET ((s32)(-3000)) |
38b2df95 DH |
698 | |
699 | /* Revision types -------------------------------------------------------*/ | |
700 | ||
701 | #define DRXJ_TYPE_ID (0x3946000DUL) | |
702 | ||
703 | /* Macros ---------------------------------------------------------------*/ | |
704 | ||
705 | /* Convert OOB lock status to string */ | |
706 | #define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ | |
7ef66759 MCC |
707 | (x == DRX_NEVER_LOCK) ? "Never" : \ |
708 | (x == DRX_NOT_LOCKED) ? "No" : \ | |
709 | (x == DRX_LOCKED) ? "Locked" : \ | |
710 | (x == DRX_LOCK_STATE_1) ? "AGC lock" : \ | |
711 | (x == DRX_LOCK_STATE_2) ? "sync lock" : \ | |
712 | "(Invalid)") | |
38b2df95 DH |
713 | |
714 | /*------------------------------------------------------------------------- | |
715 | ENUM | |
716 | -------------------------------------------------------------------------*/ | |
717 | ||
718 | /*------------------------------------------------------------------------- | |
719 | STRUCTS | |
720 | -------------------------------------------------------------------------*/ | |
721 | ||
722 | /*------------------------------------------------------------------------- | |
723 | Exported FUNCTIONS | |
724 | -------------------------------------------------------------------------*/ | |
725 | ||
1bfc9e15 MCC |
726 | int drxj_open(struct drx_demod_instance *demod); |
727 | int drxj_close(struct drx_demod_instance *demod); | |
728 | int drxj_ctrl(struct drx_demod_instance *demod, | |
57afe2f0 | 729 | u32 ctrl, void *ctrl_data); |
38b2df95 DH |
730 | |
731 | /*------------------------------------------------------------------------- | |
732 | Exported GLOBAL VARIABLES | |
733 | -------------------------------------------------------------------------*/ | |
1bfc9e15 MCC |
734 | extern struct drx_access_func drx_dap_drxj_funct_g; |
735 | extern struct drx_demod_func drxj_functions_g; | |
57afe2f0 MCC |
736 | extern drxj_data_t drxj_data_g; |
737 | extern struct i2c_device_addr drxj_default_addr_g; | |
1bfc9e15 MCC |
738 | extern struct drx_common_attr drxj_default_comm_attr_g; |
739 | extern struct drx_demod_instance drxj_default_demod_g; | |
38b2df95 DH |
740 | |
741 | /*------------------------------------------------------------------------- | |
742 | THE END | |
743 | -------------------------------------------------------------------------*/ | |
744 | #ifdef __cplusplus | |
745 | } | |
746 | #endif | |
443f18d0 | 747 | #endif /* __DRXJ_H__ */ |