[deliverable/linux.git] / drivers / media / dvb-frontends / it913x-fe.h

/*
 *  Driver for it913x Frontend
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
 */

#ifndef IT913X_FE_H
#define IT913X_FE_H

#include <linux/kconfig.h>
#include <linux/dvb/frontend.h>
#include "dvb_frontend.h"

struct ite_config {
	u8 chip_ver;
	u16 chip_type;
	u32 firmware;
	u8 firmware_ver;
	u8 adc_x2;
	u8 tuner_id_0;
	u8 tuner_id_1;
	u8 dual_mode;
	u8 adf;
	/* option to read SIGNAL_LEVEL */
	u8 read_slevel;
};

#if IS_ENABLED(CONFIG_DVB_IT913X_FE)
extern struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
			u8 i2c_addr, struct ite_config *config);
#else
static inline struct dvb_frontend *it913x_fe_attach(
		struct i2c_adapter *i2c_adap,
			u8 i2c_addr, struct ite_config *config)
{
	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
	return NULL;
}
#endif /* CONFIG_IT913X_FE */
#define I2C_BASE_ADDR		0x10
#define DEV_0			0x0
#define DEV_1			0x10
#define PRO_LINK		0x0
#define PRO_DMOD		0x1
#define DEV_0_DMOD		(PRO_DMOD << 0x7)
#define DEV_1_DMOD		(DEV_0_DMOD | DEV_1)
#define CHIP2_I2C_ADDR		0x3a

#define AFE_MEM0		0xfb24

#define MP2_SW_RST		0xf99d
#define MP2IF2_SW_RST		0xf9a4

#define	PADODPU			0xd827
#define THIRDODPU		0xd828
#define AGC_O_D			0xd829

#define EP0_TX_EN		0xdd11
#define EP0_TX_NAK		0xdd13
#define EP4_TX_LEN_LSB		0xdd88
#define EP4_TX_LEN_MSB		0xdd89
#define EP4_MAX_PKT		0xdd0c
#define EP5_TX_LEN_LSB		0xdd8a
#define EP5_TX_LEN_MSB		0xdd8b
#define EP5_MAX_PKT		0xdd0d

#define IO_MUX_POWER_CLK	0xd800
#define CLK_O_EN		0xd81a
#define I2C_CLK			0xf103
#define I2C_CLK_100		0x7
#define I2C_CLK_400		0x1a

#define D_TPSD_LOCK		0xf5a9
#define MP2IF2_EN		0xf9a3
#define MP2IF_SERIAL		0xf985
#define TSIS_ENABLE		0xf9cd
#define MP2IF2_HALF_PSB		0xf9a5
#define MP2IF_STOP_EN		0xf9b5
#define MPEG_FULL_SPEED		0xf990
#define TOP_HOSTB_SER_MODE	0xd91c

#define PID_RST			0xf992
#define PID_EN			0xf993
#define PID_INX_EN		0xf994
#define PID_INX			0xf995
#define PID_LSB			0xf996
#define PID_MSB			0xf997

#define MP2IF_MPEG_PAR_MODE	0xf986
#define DCA_UPPER_CHIP		0xf731
#define DCA_LOWER_CHIP		0xf732
#define DCA_PLATCH		0xf730
#define DCA_FPGA_LATCH		0xf778
#define DCA_STAND_ALONE		0xf73c
#define DCA_ENABLE		0xf776

#define DVBT_INTEN		0xf41f
#define DVBT_ENABLE		0xf41a
#define HOSTB_DCA_LOWER		0xd91f
#define HOSTB_MPEG_PAR_MODE	0xd91b
#define HOSTB_MPEG_SER_MODE	0xd91c
#define HOSTB_MPEG_SER_DO7	0xd91d
#define HOSTB_DCA_UPPER		0xd91e
#define PADMISCDR2		0xd830
#define PADMISCDR4		0xd831
#define PADMISCDR8		0xd832
#define PADMISCDRSR		0xd833
#define LOCK3_OUT		0xd8fd

#define GPIOH1_O		0xd8af
#define GPIOH1_EN		0xd8b0
#define GPIOH1_ON		0xd8b1
#define GPIOH3_O		0xd8b3
#define GPIOH3_EN		0xd8b4
#define GPIOH3_ON		0xd8b5
#define GPIOH5_O		0xd8bb
#define GPIOH5_EN		0xd8bc
#define GPIOH5_ON		0xd8bd

#define AFE_MEM0		0xfb24

#define REG_TPSD_TX_MODE	0xf900
#define REG_TPSD_GI		0xf901
#define REG_TPSD_HIER		0xf902
#define REG_TPSD_CONST		0xf903
#define REG_BW			0xf904
#define REG_PRIV		0xf905
#define REG_TPSD_HP_CODE	0xf906
#define REG_TPSD_LP_CODE	0xf907

#define MP2IF_SYNC_LK		0xf999
#define ADC_FREQ		0xf1cd

#define TRIGGER_OFSM		0x0000
/* COEFF Registers start at 0x0001 to 0x0020 */
#define COEFF_1_2048		0x0001
#define XTAL_CLK		0x0025
#define BFS_FCW			0x0029

/* Error Regs */
#define RSD_ABORT_PKT_LSB	0x0032
#define RSD_ABORT_PKT_MSB	0x0033
#define RSD_BIT_ERR_0_7		0x0034
#define RSD_BIT_ERR_8_15	0x0035
#define RSD_BIT_ERR_23_16	0x0036
#define RSD_BIT_COUNT_LSB	0x0037
#define RSD_BIT_COUNT_MSB	0x0038

#define TPSD_LOCK		0x003c
#define TRAINING_MODE		0x0040
#define ADC_X_2			0x0045
#define TUNER_ID		0x0046
#define EMPTY_CHANNEL_STATUS	0x0047
#define SIGNAL_LEVEL		0x0048
#define SIGNAL_QUALITY		0x0049
#define EST_SIGNAL_LEVEL	0x004a
#define FREE_BAND		0x004b
#define SUSPEND_FLAG		0x004c
#define VAR_P_INBAND		0x00f7

/* Build in tuner types */
#define IT9137 0x38
#define IT9135_38 0x38
#define IT9135_51 0x51
#define IT9135_52 0x52
#define IT9135_60 0x60
#define IT9135_61 0x61
#define IT9135_62 0x62

enum {
	CMD_DEMOD_READ = 0,
	CMD_DEMOD_WRITE,
	CMD_TUNER_READ,
	CMD_TUNER_WRITE,
	CMD_REG_EEPROM_READ,
	CMD_REG_EEPROM_WRITE,
	CMD_DATA_READ,
	CMD_VAR_READ = 8,
	CMD_VAR_WRITE,
	CMD_PLATFORM_GET,
	CMD_PLATFORM_SET,
	CMD_IP_CACHE,
	CMD_IP_ADD,
	CMD_IP_REMOVE,
	CMD_PID_ADD,
	CMD_PID_REMOVE,
	CMD_SIPSI_GET,
	CMD_SIPSI_MPE_RESET,
	CMD_H_PID_ADD = 0x15,
	CMD_H_PID_REMOVE,
	CMD_ABORT,
	CMD_IR_GET,
	CMD_IR_SET,
	CMD_FW_DOWNLOAD = 0x21,
	CMD_QUERYINFO,
	CMD_BOOT,
	CMD_FW_DOWNLOAD_BEGIN,
	CMD_FW_DOWNLOAD_END,
	CMD_RUN_CODE,
	CMD_SCATTER_READ = 0x28,
	CMD_SCATTER_WRITE,
	CMD_GENERIC_READ,
	CMD_GENERIC_WRITE
};

enum {
	READ_LONG,
	WRITE_LONG,
	READ_SHORT,
	WRITE_SHORT,
	READ_DATA,
	WRITE_DATA,
	WRITE_CMD,
};

enum {
	IT9135_AUTO = 0,
	IT9137_FW,
	IT9135_V1_FW,
	IT9135_V2_FW,
};

#endif /* IT913X_FE_H */
Commit	Line	Data
3dbbf82f MP	1	/*
	2	* Driver for it913x Frontend
	3	*
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	*
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
	19	*/
	20
	21	#ifndef IT913X_FE_H
	22	#define IT913X_FE_H
	23
782d8b74	24	#include <linux/kconfig.h>
3dbbf82f MP	25	#include <linux/dvb/frontend.h>
3dbbf82f MP	26	#include "dvb_frontend.h"
b7d425d3 MP	27
	28	struct ite_config {
	29	u8 chip_ver;
	30	u16 chip_type;
	31	u32 firmware;
990f49af MP	32	u8 firmware_ver;
990f49af MP	33	u8 adc_x2;
b7d425d3 MP	34	u8 tuner_id_0;
	35	u8 tuner_id_1;
	36	u8 dual_mode;
	37	u8 adf;
6c5637e4 MP	38	/* option to read SIGNAL_LEVEL */
6c5637e4 MP	39	u8 read_slevel;
b7d425d3 MP	40	};
b7d425d3 MP	41
782d8b74	42	#if IS_ENABLED(CONFIG_DVB_IT913X_FE)
3dbbf82f	43	extern struct dvb_frontend it913x_fe_attach(struct i2c_adapter i2c_adap,
b7d425d3	44	u8 i2c_addr, struct ite_config *config);
3dbbf82f MP	45	#else
3dbbf82f MP	46	static inline struct dvb_frontend *it913x_fe_attach(
b7d425d3 MP	47	struct i2c_adapter *i2c_adap,
b7d425d3 MP	48	u8 i2c_addr, struct ite_config *config)
3dbbf82f MP	49	{
	50	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
	51	return NULL;
	52	}
	53	#endif /* CONFIG_IT913X_FE */
	54	#define I2C_BASE_ADDR 0x10
	55	#define DEV_0 0x0
	56	#define DEV_1 0x10
	57	#define PRO_LINK 0x0
	58	#define PRO_DMOD 0x1
	59	#define DEV_0_DMOD (PRO_DMOD << 0x7)
	60	#define DEV_1_DMOD (DEV_0_DMOD \| DEV_1)
	61	#define CHIP2_I2C_ADDR 0x3a
	62
	63	#define AFE_MEM0 0xfb24
	64
	65	#define MP2_SW_RST 0xf99d
	66	#define MP2IF2_SW_RST 0xf9a4
	67
	68	#define PADODPU 0xd827
	69	#define THIRDODPU 0xd828
	70	#define AGC_O_D 0xd829
	71
	72	#define EP0_TX_EN 0xdd11
	73	#define EP0_TX_NAK 0xdd13
	74	#define EP4_TX_LEN_LSB 0xdd88
	75	#define EP4_TX_LEN_MSB 0xdd89
	76	#define EP4_MAX_PKT 0xdd0c
	77	#define EP5_TX_LEN_LSB 0xdd8a
	78	#define EP5_TX_LEN_MSB 0xdd8b
	79	#define EP5_MAX_PKT 0xdd0d
	80
	81	#define IO_MUX_POWER_CLK 0xd800
	82	#define CLK_O_EN 0xd81a
	83	#define I2C_CLK 0xf103
	84	#define I2C_CLK_100 0x7
	85	#define I2C_CLK_400 0x1a
	86
	87	#define D_TPSD_LOCK 0xf5a9
	88	#define MP2IF2_EN 0xf9a3
	89	#define MP2IF_SERIAL 0xf985
	90	#define TSIS_ENABLE 0xf9cd
	91	#define MP2IF2_HALF_PSB 0xf9a5
	92	#define MP2IF_STOP_EN 0xf9b5
	93	#define MPEG_FULL_SPEED 0xf990
	94	#define TOP_HOSTB_SER_MODE 0xd91c
	95
	96	#define PID_RST 0xf992
	97	#define PID_EN 0xf993
	98	#define PID_INX_EN 0xf994
	99	#define PID_INX 0xf995
	100	#define PID_LSB 0xf996
	101	#define PID_MSB 0xf997
	102
	103	#define MP2IF_MPEG_PAR_MODE 0xf986
	104	#define DCA_UPPER_CHIP 0xf731
	105	#define DCA_LOWER_CHIP 0xf732
	106	#define DCA_PLATCH 0xf730
	107	#define DCA_FPGA_LATCH 0xf778
	108	#define DCA_STAND_ALONE 0xf73c
	109	#define DCA_ENABLE 0xf776
	110
	111	#define DVBT_INTEN 0xf41f
	112	#define DVBT_ENABLE 0xf41a
113	#define HOSTB_DCA_LOWER 0xd91f
114	#define HOSTB_MPEG_PAR_MODE 0xd91b
115	#define HOSTB_MPEG_SER_MODE 0xd91c
116	#define HOSTB_MPEG_SER_DO7 0xd91d
117	#define HOSTB_DCA_UPPER 0xd91e
118	#define PADMISCDR2 0xd830
119	#define PADMISCDR4 0xd831
120	#define PADMISCDR8 0xd832
121	#define PADMISCDRSR 0xd833
122	#define LOCK3_OUT 0xd8fd
123
124	#define GPIOH1_O 0xd8af
125	#define GPIOH1_EN 0xd8b0
126	#define GPIOH1_ON 0xd8b1
127	#define GPIOH3_O 0xd8b3
128	#define GPIOH3_EN 0xd8b4
129	#define GPIOH3_ON 0xd8b5
130	#define GPIOH5_O 0xd8bb
131	#define GPIOH5_EN 0xd8bc
132	#define GPIOH5_ON 0xd8bd
133
134	#define AFE_MEM0 0xfb24
135
136	#define REG_TPSD_TX_MODE 0xf900
137	#define REG_TPSD_GI 0xf901
138	#define REG_TPSD_HIER 0xf902
139	#define REG_TPSD_CONST 0xf903
140	#define REG_BW 0xf904
141	#define REG_PRIV 0xf905
142	#define REG_TPSD_HP_CODE 0xf906
143	#define REG_TPSD_LP_CODE 0xf907
144
145	#define MP2IF_SYNC_LK 0xf999
146	#define ADC_FREQ 0xf1cd
147
148	#define TRIGGER_OFSM 0x0000
149	/* COEFF Registers start at 0x0001 to 0x0020 */
150	#define COEFF_1_2048 0x0001
151	#define XTAL_CLK 0x0025
152	#define BFS_FCW 0x0029
82a05014 MP	153
	154	/* Error Regs */
	155	#define RSD_ABORT_PKT_LSB 0x0032
	156	#define RSD_ABORT_PKT_MSB 0x0033
	157	#define RSD_BIT_ERR_0_7 0x0034
	158	#define RSD_BIT_ERR_8_15 0x0035
	159	#define RSD_BIT_ERR_23_16 0x0036
	160	#define RSD_BIT_COUNT_LSB 0x0037
	161	#define RSD_BIT_COUNT_MSB 0x0038
	162
3dbbf82f MP	163	#define TPSD_LOCK 0x003c
	164	#define TRAINING_MODE 0x0040
	165	#define ADC_X_2 0x0045
	166	#define TUNER_ID 0x0046
	167	#define EMPTY_CHANNEL_STATUS 0x0047
	168	#define SIGNAL_LEVEL 0x0048
	169	#define SIGNAL_QUALITY 0x0049
	170	#define EST_SIGNAL_LEVEL 0x004a
	171	#define FREE_BAND 0x004b
	172	#define SUSPEND_FLAG 0x004c
6c5637e4 MP	173	#define VAR_P_INBAND 0x00f7
6c5637e4 MP	174
b7d425d3	175	/* Build in tuner types */
3dbbf82f	176	#define IT9137 0x38
b7d425d3	177	#define IT9135_38 0x38
245900c4	178	#define IT9135_51 0x51
b7d425d3 MP	179	#define IT9135_52 0x52
	180	#define IT9135_60 0x60
	181	#define IT9135_61 0x61
	182	#define IT9135_62 0x62
3dbbf82f MP	183
	184	enum {
	185	CMD_DEMOD_READ = 0,
	186	CMD_DEMOD_WRITE,
	187	CMD_TUNER_READ,
	188	CMD_TUNER_WRITE,
	189	CMD_REG_EEPROM_READ,
	190	CMD_REG_EEPROM_WRITE,
	191	CMD_DATA_READ,
	192	CMD_VAR_READ = 8,
	193	CMD_VAR_WRITE,
	194	CMD_PLATFORM_GET,
	195	CMD_PLATFORM_SET,
	196	CMD_IP_CACHE,
	197	CMD_IP_ADD,
	198	CMD_IP_REMOVE,
	199	CMD_PID_ADD,
	200	CMD_PID_REMOVE,
	201	CMD_SIPSI_GET,
	202	CMD_SIPSI_MPE_RESET,
	203	CMD_H_PID_ADD = 0x15,
	204	CMD_H_PID_REMOVE,
	205	CMD_ABORT,
	206	CMD_IR_GET,
	207	CMD_IR_SET,
	208	CMD_FW_DOWNLOAD = 0x21,
	209	CMD_QUERYINFO,
	210	CMD_BOOT,
	211	CMD_FW_DOWNLOAD_BEGIN,
	212	CMD_FW_DOWNLOAD_END,
	213	CMD_RUN_CODE,
	214	CMD_SCATTER_READ = 0x28,
	215	CMD_SCATTER_WRITE,
	216	CMD_GENERIC_READ,
	217	CMD_GENERIC_WRITE
	218	};
	219
	220	enum {
	221	READ_LONG,
	222	WRITE_LONG,
	223	READ_SHORT,
	224	WRITE_SHORT,
	225	READ_DATA,
	226	WRITE_DATA,
	227	WRITE_CMD,
	228	};
	229
990f49af MP	230	enum {
	231	IT9135_AUTO = 0,
	232	IT9137_FW,
	233	IT9135_V1_FW,
	234	IT9135_V2_FW,
	235	};
	236
3dbbf82f	237	#endif /* IT913X_FE_H */