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[media] m88ds3103: remove dead code 2nd part
[deliverable/linux.git] / drivers / media / dvb-frontends / m88ds3103.c
CommitLineData
395d00d1
AP		 1/*
2 * Montage M88DS3103 demodulator driver
3 *
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
395d00d1
AP		 15 */
16
17#include "m88ds3103_priv.h"
18
19static struct dvb_frontend_ops m88ds3103_ops;
20
21/* write multiple registers */
22static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
23 u8 reg, const u8 *val, int len)
24{
63c80f70
AP		 25#define MAX_WR_LEN 32
26#define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
395d00d1 27 int ret;
63c80f70 28 u8 buf[MAX_WR_XFER_LEN];
395d00d1
AP		 29 struct i2c_msg msg[1] = {
30 {
31 .addr = priv->cfg->i2c_addr,
32 .flags = 0,
63c80f70 33 .len = 1 + len,
395d00d1
AP		 34 .buf = buf,
35 }
36 };
37
63c80f70
AP		 38 if (WARN_ON(len > MAX_WR_LEN))
39 return -EINVAL;
40
395d00d1
AP		 41 buf[0] = reg;
42 memcpy(&buf[1], val, len);
43
44 mutex_lock(&priv->i2c_mutex);
45 ret = i2c_transfer(priv->i2c, msg, 1);
46 mutex_unlock(&priv->i2c_mutex);
47 if (ret == 1) {
48 ret = 0;
49 } else {
50 dev_warn(&priv->i2c->dev,
51 "%s: i2c wr failed=%d reg=%02x len=%d\n",
52 KBUILD_MODNAME, ret, reg, len);
53 ret = -EREMOTEIO;
54 }
55
56 return ret;
57}
58
59/* read multiple registers */
60static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
61 u8 reg, u8 *val, int len)
62{
63c80f70
AP		 63#define MAX_RD_LEN 3
64#define MAX_RD_XFER_LEN (MAX_RD_LEN)
395d00d1 65 int ret;
63c80f70 66 u8 buf[MAX_RD_XFER_LEN];
395d00d1
AP		 67 struct i2c_msg msg[2] = {
68 {
69 .addr = priv->cfg->i2c_addr,
70 .flags = 0,
71 .len = 1,
72 .buf = &reg,
73 }, {
74 .addr = priv->cfg->i2c_addr,
75 .flags = I2C_M_RD,
63c80f70 76 .len = len,
395d00d1
AP		 77 .buf = buf,
78 }
79 };
80
63c80f70
AP		 81 if (WARN_ON(len > MAX_RD_LEN))
82 return -EINVAL;
83
395d00d1
AP		 84 mutex_lock(&priv->i2c_mutex);
85 ret = i2c_transfer(priv->i2c, msg, 2);
86 mutex_unlock(&priv->i2c_mutex);
87 if (ret == 2) {
88 memcpy(val, buf, len);
89 ret = 0;
90 } else {
91 dev_warn(&priv->i2c->dev,
92 "%s: i2c rd failed=%d reg=%02x len=%d\n",
93 KBUILD_MODNAME, ret, reg, len);
94 ret = -EREMOTEIO;
95 }
96
97 return ret;
98}
99
100/* write single register */
101static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
102{
103 return m88ds3103_wr_regs(priv, reg, &val, 1);
104}
105
106/* read single register */
107static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
108{
109 return m88ds3103_rd_regs(priv, reg, val, 1);
110}
111
112/* write single register with mask */
113static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
114 u8 reg, u8 val, u8 mask)
115{
116 int ret;
117 u8 u8tmp;
118
119 /* no need for read if whole reg is written */
120 if (mask != 0xff) {
121 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
122 if (ret)
123 return ret;
124
125 val &= mask;
126 u8tmp &= ~mask;
127 val |= u8tmp;
128 }
129
130 return m88ds3103_wr_regs(priv, reg, &val, 1);
131}
132
133/* read single register with mask */
134static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
135 u8 reg, u8 *val, u8 mask)
136{
137 int ret, i;
138 u8 u8tmp;
139
140 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
141 if (ret)
142 return ret;
143
144 u8tmp &= mask;
145
146 /* find position of the first bit */
147 for (i = 0; i < 8; i++) {
148 if ((mask >> i) & 0x01)
149 break;
150 }
151 *val = u8tmp >> i;
152
153 return 0;
154}
155
06487dee
AP		 156/* write reg val table using reg addr auto increment */
157static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv,
158 const struct m88ds3103_reg_val *tab, int tab_len)
159{
160 int ret, i, j;
161 u8 buf[83];
162 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
163
164 if (tab_len > 83) {
165 ret = -EINVAL;
166 goto err;
167 }
168
169 for (i = 0, j = 0; i < tab_len; i++, j++) {
170 buf[j] = tab[i].val;
171
172 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
173 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) {
174 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1);
175 if (ret)
176 goto err;
177
178 j = -1;
179 }
180 }
181
182 return 0;
183err:
184 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
185 return ret;
186}
187
395d00d1
AP		 188static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status)
189{
190 struct m88ds3103_priv *priv = fe->demodulator_priv;
191 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
192 int ret;
193 u8 u8tmp;
194
195 *status = 0;
196
197 if (!priv->warm) {
198 ret = -EAGAIN;
199 goto err;
200 }
201
202 switch (c->delivery_system) {
203 case SYS_DVBS:
204 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
205 if (ret)
206 goto err;
207
208 if (u8tmp == 0x07)
209 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
210 FE_HAS_VITERBI | FE_HAS_SYNC |
211 FE_HAS_LOCK;
212 break;
213 case SYS_DVBS2:
214 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
215 if (ret)
216 goto err;
217
218 if (u8tmp == 0x8f)
219 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
220 FE_HAS_VITERBI | FE_HAS_SYNC |
221 FE_HAS_LOCK;
222 break;
223 default:
224 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
225 __func__);
226 ret = -EINVAL;
227 goto err;
228 }
229
230 priv->fe_status = *status;
231
232 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
233 __func__, u8tmp, *status);
234
235 return 0;
236err:
237 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
238 return ret;
239}
240
241static int m88ds3103_set_frontend(struct dvb_frontend *fe)
242{
243 struct m88ds3103_priv *priv = fe->demodulator_priv;
244 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
06487dee 245 int ret, len;
395d00d1
AP		 246 const struct m88ds3103_reg_val *init;
247 u8 u8tmp, u8tmp1, u8tmp2;
248 u8 buf[2];
249 u16 u16tmp, divide_ratio;
250 u32 tuner_frequency, target_mclk, ts_clk;
251 s32 s32tmp;
252 dev_dbg(&priv->i2c->dev,
253 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
254 __func__, c->delivery_system,
255 c->modulation, c->frequency, c->symbol_rate,
256 c->inversion, c->pilot, c->rolloff);
257
258 if (!priv->warm) {
259 ret = -EAGAIN;
260 goto err;
261 }
262
263 /* program tuner */
264 if (fe->ops.tuner_ops.set_params) {
265 ret = fe->ops.tuner_ops.set_params(fe);
266 if (ret)
267 goto err;
268 }
269
270 if (fe->ops.tuner_ops.get_frequency) {
271 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
272 if (ret)
273 goto err;
274 }
275
276 /* reset */
277 ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
278 if (ret)
279 goto err;
280
281 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
282 if (ret)
283 goto err;
284
285 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
286 if (ret)
287 goto err;
288
289 ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
290 if (ret)
291 goto err;
292
293 switch (c->delivery_system) {
294 case SYS_DVBS:
295 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
296 init = m88ds3103_dvbs_init_reg_vals;
297 target_mclk = 96000;
298 break;
299 case SYS_DVBS2:
300 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
301 init = m88ds3103_dvbs2_init_reg_vals;
302
303 switch (priv->cfg->ts_mode) {
304 case M88DS3103_TS_SERIAL:
305 case M88DS3103_TS_SERIAL_D7:
306 if (c->symbol_rate < 18000000)
307 target_mclk = 96000;
308 else
309 target_mclk = 144000;
310 break;
311 case M88DS3103_TS_PARALLEL:
312 case M88DS3103_TS_PARALLEL_12:
313 case M88DS3103_TS_PARALLEL_16:
314 case M88DS3103_TS_PARALLEL_19_2:
315 case M88DS3103_TS_CI:
316 if (c->symbol_rate < 18000000)
317 target_mclk = 96000;
318 else if (c->symbol_rate < 28000000)
319 target_mclk = 144000;
320 else
321 target_mclk = 192000;
322 break;
323 default:
324 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
325 __func__);
326 ret = -EINVAL;
327 goto err;
328 }
329 break;
330 default:
331 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
332 __func__);
333 ret = -EINVAL;
334 goto err;
335 }
336
337 /* program init table */
338 if (c->delivery_system != priv->delivery_system) {
06487dee
AP		 339 ret = m88ds3103_wr_reg_val_tab(priv, init, len);
340 if (ret)
341 goto err;
395d00d1
AP		 342 }
343
344 u8tmp1 = 0; /* silence compiler warning */
345 switch (priv->cfg->ts_mode) {
346 case M88DS3103_TS_SERIAL:
347 u8tmp1 = 0x00;
348 ts_clk = 0;
92676ac9 349 u8tmp = 0x46;
395d00d1
AP		 350 break;
351 case M88DS3103_TS_SERIAL_D7:
352 u8tmp1 = 0x20;
353 ts_clk = 0;
92676ac9 354 u8tmp = 0x46;
395d00d1
AP		 355 break;
356 case M88DS3103_TS_PARALLEL:
357 ts_clk = 24000;
92676ac9 358 u8tmp = 0x42;
395d00d1
AP		 359 break;
360 case M88DS3103_TS_PARALLEL_12:
361 ts_clk = 12000;
92676ac9 362 u8tmp = 0x42;
395d00d1
AP		 363 break;
364 case M88DS3103_TS_PARALLEL_16:
365 ts_clk = 16000;
92676ac9 366 u8tmp = 0x42;
395d00d1
AP		 367 break;
368 case M88DS3103_TS_PARALLEL_19_2:
369 ts_clk = 19200;
92676ac9 370 u8tmp = 0x42;
395d00d1
AP		 371 break;
372 case M88DS3103_TS_CI:
373 ts_clk = 6000;
92676ac9 374 u8tmp = 0x43;
395d00d1
AP		 375 break;
376 default:
377 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
378 ret = -EINVAL;
379 goto err;
380 }
381
382 /* TS mode */
92676ac9 383 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp);
395d00d1
AP		 384 if (ret)
385 goto err;
386
387 switch (priv->cfg->ts_mode) {
388 case M88DS3103_TS_SERIAL:
389 case M88DS3103_TS_SERIAL_D7:
390 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
391 if (ret)
392 goto err;
393 }
394
395 if (ts_clk) {
396 divide_ratio = DIV_ROUND_UP(target_mclk, ts_clk);
397 u8tmp1 = divide_ratio / 2;
398 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
399 } else {
400 divide_ratio = 0;
401 u8tmp1 = 0;
402 u8tmp2 = 0;
403 }
404
405 dev_dbg(&priv->i2c->dev,
406 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
407 __func__, target_mclk, ts_clk, divide_ratio);
408
409 u8tmp1--;
410 u8tmp2--;
411 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
412 u8tmp1 &= 0x3f;
413 /* u8tmp2[5:0] => ea[5:0] */
414 u8tmp2 &= 0x3f;
415
416 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
417 if (ret)
418 goto err;
419
420 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
421 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
422 if (ret)
423 goto err;
424
425 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
426 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
427 if (ret)
428 goto err;
429
430 switch (target_mclk) {
395d00d1
AP		 431 case 96000:
432 u8tmp1 = 0x02; /* 0b10 */
433 u8tmp2 = 0x01; /* 0b01 */
434 break;
395d00d1
AP		 435 case 144000:
436 u8tmp1 = 0x00; /* 0b00 */
437 u8tmp2 = 0x01; /* 0b01 */
438 break;
439 case 192000:
440 u8tmp1 = 0x03; /* 0b11 */
441 u8tmp2 = 0x00; /* 0b00 */
442 break;
395d00d1
AP		 443 }
444
445 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
446 if (ret)
447 goto err;
448
449 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
450 if (ret)
451 goto err;
452
453 if (c->symbol_rate <= 3000000)
454 u8tmp = 0x20;
455 else if (c->symbol_rate <= 10000000)
456 u8tmp = 0x10;
457 else
458 u8tmp = 0x06;
459
460 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
461 if (ret)
462 goto err;
463
464 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
465 if (ret)
466 goto err;
467
468 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
469 if (ret)
470 goto err;
471
472 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
473 if (ret)
474 goto err;
475
39c0029e 476 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, M88DS3103_MCLK_KHZ / 2);
395d00d1
AP		 477 buf[0] = (u16tmp >> 0) & 0xff;
478 buf[1] = (u16tmp >> 8) & 0xff;
479 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
480 if (ret)
481 goto err;
482
483 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
484 if (ret)
485 goto err;
486
487 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
488 if (ret)
489 goto err;
490
491 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
492 if (ret)
493 goto err;
494
495 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
496 (tuner_frequency - c->frequency));
497
498 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
39c0029e 499 s32tmp = DIV_ROUND_CLOSEST(s32tmp, M88DS3103_MCLK_KHZ);
395d00d1
AP		 500 if (s32tmp < 0)
501 s32tmp += 0x10000;
502
503 buf[0] = (s32tmp >> 0) & 0xff;
504 buf[1] = (s32tmp >> 8) & 0xff;
505 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
506 if (ret)
507 goto err;
508
509 ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
510 if (ret)
511 goto err;
512
513 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
514 if (ret)
515 goto err;
516
517 priv->delivery_system = c->delivery_system;
518
519 return 0;
520err:
521 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
522 return ret;
523}
524
525static int m88ds3103_init(struct dvb_frontend *fe)
526{
527 struct m88ds3103_priv *priv = fe->demodulator_priv;
528 int ret, len, remaining;
529 const struct firmware *fw = NULL;
530 u8 *fw_file = M88DS3103_FIRMWARE;
531 u8 u8tmp;
532 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
533
534 /* set cold state by default */
535 priv->warm = false;
536
537 /* wake up device from sleep */
538 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
539 if (ret)
540 goto err;
541
542 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
543 if (ret)
544 goto err;
545
546 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
547 if (ret)
548 goto err;
549
550 /* reset */
551 ret = m88ds3103_wr_reg(priv, 0x07, 0x60);
552 if (ret)
553 goto err;
554
555 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
556 if (ret)
557 goto err;
558
559 /* firmware status */
560 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
561 if (ret)
562 goto err;
563
564 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
565
566 if (u8tmp)
567 goto skip_fw_download;
568
569 /* cold state - try to download firmware */
570 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
571 KBUILD_MODNAME, m88ds3103_ops.info.name);
572
573 /* request the firmware, this will block and timeout */
574 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
575 if (ret) {
576 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n",
577 KBUILD_MODNAME, fw_file);
578 goto err;
579 }
580
581 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
582 KBUILD_MODNAME, fw_file);
583
584 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
585 if (ret)
586 goto err;
587
588 for (remaining = fw->size; remaining > 0;
589 remaining -= (priv->cfg->i2c_wr_max - 1)) {
590 len = remaining;
591 if (len > (priv->cfg->i2c_wr_max - 1))
592 len = (priv->cfg->i2c_wr_max - 1);
593
594 ret = m88ds3103_wr_regs(priv, 0xb0,
595 &fw->data[fw->size - remaining], len);
596 if (ret) {
597 dev_err(&priv->i2c->dev,
598 "%s: firmware download failed=%d\n",
599 KBUILD_MODNAME, ret);
600 goto err;
601 }
602 }
603
604 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
605 if (ret)
606 goto err;
607
608 release_firmware(fw);
609 fw = NULL;
610
611 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
612 if (ret)
613 goto err;
614
615 if (!u8tmp) {
616 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
617 KBUILD_MODNAME);
618 ret = -EFAULT;
619 goto err;
620 }
621
622 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
623 KBUILD_MODNAME, m88ds3103_ops.info.name);
624 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
625 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
626
627skip_fw_download:
628 /* warm state */
629 priv->warm = true;
630
631 return 0;
632err:
633 if (fw)
634 release_firmware(fw);
635
636 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
637 return ret;
638}
639
640static int m88ds3103_sleep(struct dvb_frontend *fe)
641{
642 struct m88ds3103_priv *priv = fe->demodulator_priv;
643 int ret;
644 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
645
646 priv->delivery_system = SYS_UNDEFINED;
647
648 /* TS Hi-Z */
649 ret = m88ds3103_wr_reg_mask(priv, 0x27, 0x00, 0x01);
650 if (ret)
651 goto err;
652
653 /* sleep */
654 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
655 if (ret)
656 goto err;
657
658 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
659 if (ret)
660 goto err;
661
662 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
663 if (ret)
664 goto err;
665
666 return 0;
667err:
668 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
669 return ret;
670}
671
672static int m88ds3103_get_frontend(struct dvb_frontend *fe)
673{
674 struct m88ds3103_priv *priv = fe->demodulator_priv;
675 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
676 int ret;
677 u8 buf[3];
678 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
679
680 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
681 ret = -EAGAIN;
682 goto err;
683 }
684
685 switch (c->delivery_system) {
686 case SYS_DVBS:
687 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
688 if (ret)
689 goto err;
690
691 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
692 if (ret)
693 goto err;
694
695 switch ((buf[0] >> 2) & 0x01) {
696 case 0:
697 c->inversion = INVERSION_OFF;
698 break;
699 case 1:
700 c->inversion = INVERSION_ON;
701 break;
395d00d1
AP		 702 }
703
704 switch ((buf[1] >> 5) & 0x07) {
705 case 0:
706 c->fec_inner = FEC_7_8;
707 break;
708 case 1:
709 c->fec_inner = FEC_5_6;
710 break;
711 case 2:
712 c->fec_inner = FEC_3_4;
713 break;
714 case 3:
715 c->fec_inner = FEC_2_3;
716 break;
717 case 4:
718 c->fec_inner = FEC_1_2;
719 break;
720 default:
721 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
722 __func__);
723 }
724
725 c->modulation = QPSK;
726
727 break;
728 case SYS_DVBS2:
729 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
730 if (ret)
731 goto err;
732
733 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
734 if (ret)
735 goto err;
736
737 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
738 if (ret)
739 goto err;
740
741 switch ((buf[0] >> 0) & 0x0f) {
742 case 2:
743 c->fec_inner = FEC_2_5;
744 break;
745 case 3:
746 c->fec_inner = FEC_1_2;
747 break;
748 case 4:
749 c->fec_inner = FEC_3_5;
750 break;
751 case 5:
752 c->fec_inner = FEC_2_3;
753 break;
754 case 6:
755 c->fec_inner = FEC_3_4;
756 break;
757 case 7:
758 c->fec_inner = FEC_4_5;
759 break;
760 case 8:
761 c->fec_inner = FEC_5_6;
762 break;
763 case 9:
764 c->fec_inner = FEC_8_9;
765 break;
766 case 10:
767 c->fec_inner = FEC_9_10;
768 break;
769 default:
770 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
771 __func__);
772 }
773
774 switch ((buf[0] >> 5) & 0x01) {
775 case 0:
776 c->pilot = PILOT_OFF;
777 break;
778 case 1:
779 c->pilot = PILOT_ON;
780 break;
395d00d1
AP		 781 }
782
783 switch ((buf[0] >> 6) & 0x07) {
784 case 0:
785 c->modulation = QPSK;
786 break;
787 case 1:
788 c->modulation = PSK_8;
789 break;
790 case 2:
791 c->modulation = APSK_16;
792 break;
793 case 3:
794 c->modulation = APSK_32;
795 break;
796 default:
797 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
798 __func__);
799 }
800
801 switch ((buf[1] >> 7) & 0x01) {
802 case 0:
803 c->inversion = INVERSION_OFF;
804 break;
805 case 1:
806 c->inversion = INVERSION_ON;
807 break;
395d00d1
AP		 808 }
809
810 switch ((buf[2] >> 0) & 0x03) {
811 case 0:
812 c->rolloff = ROLLOFF_35;
813 break;
814 case 1:
815 c->rolloff = ROLLOFF_25;
816 break;
817 case 2:
818 c->rolloff = ROLLOFF_20;
819 break;
820 default:
821 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
822 __func__);
823 }
824 break;
825 default:
826 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
827 __func__);
828 ret = -EINVAL;
829 goto err;
830 }
831
832 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
833 if (ret)
834 goto err;
835
836 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
837 M88DS3103_MCLK_KHZ * 1000 / 0x10000;
838
839 return 0;
840err:
841 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
842 return ret;
843}
844
845static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
846{
847 struct m88ds3103_priv *priv = fe->demodulator_priv;
848 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
849 int ret, i, tmp;
850 u8 buf[3];
851 u16 noise, signal;
852 u32 noise_tot, signal_tot;
853 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
854 /* reports SNR in resolution of 0.1 dB */
855
856 /* more iterations for more accurate estimation */
857 #define M88DS3103_SNR_ITERATIONS 3
858
859 switch (c->delivery_system) {
860 case SYS_DVBS:
861 tmp = 0;
862
863 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
864 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
865 if (ret)
866 goto err;
867
868 tmp += buf[0];
869 }
870
871 /* use of one register limits max value to 15 dB */
872 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
873 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS);
874 if (tmp)
875 *snr = 100ul * intlog2(tmp) / intlog2(10);
876 else
877 *snr = 0;
878 break;
879 case SYS_DVBS2:
880 noise_tot = 0;
881 signal_tot = 0;
882
883 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
884 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
885 if (ret)
886 goto err;
887
888 noise = buf[1] << 6; /* [13:6] */
889 noise |= buf[0] & 0x3f; /* [5:0] */
890 noise >>= 2;
891 signal = buf[2] * buf[2];
892 signal >>= 1;
893
894 noise_tot += noise;
895 signal_tot += signal;
896 }
897
898 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
899 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
900
901 /* SNR(X) dB = 10 * log10(X) dB */
902 if (signal > noise) {
903 tmp = signal / noise;
904 *snr = 100ul * intlog10(tmp) / (1 << 24);
8a878dc4 905 } else {
395d00d1 906 *snr = 0;
8a878dc4 907 }
395d00d1
AP		 908 break;
909 default:
910 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
911 __func__);
912 ret = -EINVAL;
913 goto err;
914 }
915
916 return 0;
917err:
918 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
919 return ret;
920}
921
922
923static int m88ds3103_set_tone(struct dvb_frontend *fe,
924 fe_sec_tone_mode_t fe_sec_tone_mode)
925{
926 struct m88ds3103_priv *priv = fe->demodulator_priv;
927 int ret;
928 u8 u8tmp, tone, reg_a1_mask;
929 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
930 fe_sec_tone_mode);
931
932 if (!priv->warm) {
933 ret = -EAGAIN;
934 goto err;
935 }
936
937 switch (fe_sec_tone_mode) {
938 case SEC_TONE_ON:
939 tone = 0;
940 reg_a1_mask = 0x87;
941 break;
942 case SEC_TONE_OFF:
943 tone = 1;
944 reg_a1_mask = 0x00;
945 break;
946 default:
947 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
948 __func__);
949 ret = -EINVAL;
950 goto err;
951 }
952
953 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
954 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
955 if (ret)
956 goto err;
957
958 u8tmp = 1 << 2;
959 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
960 if (ret)
961 goto err;
962
963 return 0;
964err:
965 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
966 return ret;
967}
968
969static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
970 struct dvb_diseqc_master_cmd *diseqc_cmd)
971{
972 struct m88ds3103_priv *priv = fe->demodulator_priv;
973 int ret, i;
974 u8 u8tmp;
975 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
976 diseqc_cmd->msg_len, diseqc_cmd->msg);
977
978 if (!priv->warm) {
979 ret = -EAGAIN;
980 goto err;
981 }
982
983 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
984 ret = -EINVAL;
985 goto err;
986 }
987
988 u8tmp = priv->cfg->envelope_mode << 5;
989 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
990 if (ret)
991 goto err;
992
993 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
994 diseqc_cmd->msg_len);
995 if (ret)
996 goto err;
997
998 ret = m88ds3103_wr_reg(priv, 0xa1,
999 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1000 if (ret)
1001 goto err;
1002
1003 /* DiSEqC message typical period is 54 ms */
1004 usleep_range(40000, 60000);
1005
1006 /* wait DiSEqC TX ready */
1007 for (i = 20, u8tmp = 1; i && u8tmp; i--) {
1008 usleep_range(5000, 10000);
1009
1010 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1011 if (ret)
1012 goto err;
1013 }
1014
1015 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1016
1017 if (i == 0) {
1018 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1019
1020 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1021 if (ret)
1022 goto err;
1023 }
1024
1025 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1026 if (ret)
1027 goto err;
1028
1029 if (i == 0) {
1030 ret = -ETIMEDOUT;
1031 goto err;
1032 }
1033
1034 return 0;
1035err:
1036 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1037 return ret;
1038}
1039
1040static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1041 fe_sec_mini_cmd_t fe_sec_mini_cmd)
1042{
1043 struct m88ds3103_priv *priv = fe->demodulator_priv;
1044 int ret, i;
1045 u8 u8tmp, burst;
1046 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1047 fe_sec_mini_cmd);
1048
1049 if (!priv->warm) {
1050 ret = -EAGAIN;
1051 goto err;
1052 }
1053
1054 u8tmp = priv->cfg->envelope_mode << 5;
1055 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1056 if (ret)
1057 goto err;
1058
1059 switch (fe_sec_mini_cmd) {
1060 case SEC_MINI_A:
1061 burst = 0x02;
1062 break;
1063 case SEC_MINI_B:
1064 burst = 0x01;
1065 break;
1066 default:
1067 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1068 __func__);
1069 ret = -EINVAL;
1070 goto err;
1071 }
1072
1073 ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1074 if (ret)
1075 goto err;
1076
1077 /* DiSEqC ToneBurst period is 12.5 ms */
1078 usleep_range(11000, 20000);
1079
1080 /* wait DiSEqC TX ready */
1081 for (i = 5, u8tmp = 1; i && u8tmp; i--) {
1082 usleep_range(800, 2000);
1083
1084 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1085 if (ret)
1086 goto err;
1087 }
1088
1089 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1090
1091 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1092 if (ret)
1093 goto err;
1094
1095 if (i == 0) {
1096 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1097 ret = -ETIMEDOUT;
1098 goto err;
1099 }
1100
1101 return 0;
1102err:
1103 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1104 return ret;
1105}
1106
1107static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1108 struct dvb_frontend_tune_settings *s)
1109{
1110 s->min_delay_ms = 3000;
1111
1112 return 0;
1113}
1114
44b9055b 1115static void m88ds3103_release(struct dvb_frontend *fe)
395d00d1 1116{
44b9055b
AP		 1117 struct m88ds3103_priv *priv = fe->demodulator_priv;
1118 i2c_del_mux_adapter(priv->i2c_adapter);
1119 kfree(priv);
395d00d1
AP		 1120}
1121
44b9055b 1122static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
395d00d1 1123{
44b9055b 1124 struct m88ds3103_priv *priv = mux_priv;
395d00d1
AP		 1125 int ret;
1126 struct i2c_msg gate_open_msg[1] = {
1127 {
1128 .addr = priv->cfg->i2c_addr,
1129 .flags = 0,
1130 .len = 2,
1131 .buf = "\x03\x11",
1132 }
1133 };
395d00d1
AP		 1134
1135 mutex_lock(&priv->i2c_mutex);
1136
44b9055b 1137 /* open tuner I2C repeater for 1 xfer, closes automatically */
4fc57876 1138 ret = __i2c_transfer(priv->i2c, gate_open_msg, 1);
395d00d1 1139 if (ret != 1) {
44b9055b 1140 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n",
395d00d1 1141 KBUILD_MODNAME, ret);
44b9055b
AP		 1142 if (ret >= 0)
1143 ret = -EREMOTEIO;
395d00d1 1144
44b9055b
AP		 1145 return ret;
1146 }
395d00d1 1147
44b9055b 1148 return 0;
395d00d1
AP		 1149}
1150
44b9055b
AP		 1151static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv,
1152 u32 chan)
395d00d1 1153{
44b9055b
AP		 1154 struct m88ds3103_priv *priv = mux_priv;
1155
1156 mutex_unlock(&priv->i2c_mutex);
1157
1158 return 0;
395d00d1
AP		 1159}
1160
1161struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1162 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1163{
1164 int ret;
1165 struct m88ds3103_priv *priv;
1166 u8 chip_id, u8tmp;
1167
1168 /* allocate memory for the internal priv */
8a878dc4 1169 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
395d00d1
AP		 1170 if (!priv) {
1171 ret = -ENOMEM;
1172 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
1173 goto err;
1174 }
1175
1176 priv->cfg = cfg;
1177 priv->i2c = i2c;
1178 mutex_init(&priv->i2c_mutex);
1179
1180 ret = m88ds3103_rd_reg(priv, 0x01, &chip_id);
1181 if (ret)
1182 goto err;
1183
1184 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
1185
1186 switch (chip_id) {
1187 case 0xd0:
1188 break;
1189 default:
1190 goto err;
1191 }
1192
1193 switch (priv->cfg->clock_out) {
1194 case M88DS3103_CLOCK_OUT_DISABLED:
1195 u8tmp = 0x80;
1196 break;
1197 case M88DS3103_CLOCK_OUT_ENABLED:
1198 u8tmp = 0x00;
1199 break;
1200 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1201 u8tmp = 0x10;
1202 break;
1203 default:
1204 goto err;
1205 }
1206
1207 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp);
1208 if (ret)
1209 goto err;
1210
1211 /* sleep */
1212 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
1213 if (ret)
1214 goto err;
1215
1216 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
1217 if (ret)
1218 goto err;
1219
1220 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
1221 if (ret)
1222 goto err;
1223
44b9055b
AP		 1224 /* create mux i2c adapter for tuner */
1225 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
1226 m88ds3103_select, m88ds3103_deselect);
1227 if (priv->i2c_adapter == NULL)
1228 goto err;
1229
1230 *tuner_i2c_adapter = priv->i2c_adapter;
1231
395d00d1
AP		 1232 /* create dvb_frontend */
1233 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1234 priv->fe.demodulator_priv = priv;
1235
395d00d1
AP		 1236 return &priv->fe;
1237err:
1238 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
1239 kfree(priv);
1240 return NULL;
1241}
1242EXPORT_SYMBOL(m88ds3103_attach);
1243
1244static struct dvb_frontend_ops m88ds3103_ops = {
1245 .delsys = { SYS_DVBS, SYS_DVBS2 },
1246 .info = {
1247 .name = "Montage M88DS3103",
1248 .frequency_min = 950000,
1249 .frequency_max = 2150000,
1250 .frequency_tolerance = 5000,
1251 .symbol_rate_min = 1000000,
1252 .symbol_rate_max = 45000000,
1253 .caps = FE_CAN_INVERSION_AUTO |
1254 FE_CAN_FEC_1_2 |
1255 FE_CAN_FEC_2_3 |
1256 FE_CAN_FEC_3_4 |
1257 FE_CAN_FEC_4_5 |
1258 FE_CAN_FEC_5_6 |
1259 FE_CAN_FEC_6_7 |
1260 FE_CAN_FEC_7_8 |
1261 FE_CAN_FEC_8_9 |
1262 FE_CAN_FEC_AUTO |
1263 FE_CAN_QPSK |
1264 FE_CAN_RECOVER |
1265 FE_CAN_2G_MODULATION
1266 },
1267
1268 .release = m88ds3103_release,
1269
1270 .get_tune_settings = m88ds3103_get_tune_settings,
1271
1272 .init = m88ds3103_init,
1273 .sleep = m88ds3103_sleep,
1274
1275 .set_frontend = m88ds3103_set_frontend,
1276 .get_frontend = m88ds3103_get_frontend,
1277
1278 .read_status = m88ds3103_read_status,
1279 .read_snr = m88ds3103_read_snr,
1280
1281 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1282 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1283
1284 .set_tone = m88ds3103_set_tone,
1285};
1286
1287MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1288MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1289MODULE_LICENSE("GPL");
1290MODULE_FIRMWARE(M88DS3103_FIRMWARE);
Linux kernel - Deliverables
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