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[media] DVB-frontends: Deletion of unnecessary checks before the function call "relea...
[deliverable/linux.git] / drivers / media / dvb-frontends / m88ds3103.c
CommitLineData
395d00d1 1/*
f4df95bc 2 * Montage M88DS3103/M88RS6000 demodulator driver
395d00d1
AP		 3 *
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
395d00d1
AP		 15 */
16
17#include "m88ds3103_priv.h"
18
19static struct dvb_frontend_ops m88ds3103_ops;
20
21/* write multiple registers */
22static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
23 u8 reg, const u8 *val, int len)
24{
63c80f70
AP		 25#define MAX_WR_LEN 32
26#define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
395d00d1 27 int ret;
63c80f70 28 u8 buf[MAX_WR_XFER_LEN];
395d00d1
AP		 29 struct i2c_msg msg[1] = {
30 {
31 .addr = priv->cfg->i2c_addr,
32 .flags = 0,
63c80f70 33 .len = 1 + len,
395d00d1
AP		 34 .buf = buf,
35 }
36 };
37
63c80f70
AP		 38 if (WARN_ON(len > MAX_WR_LEN))
39 return -EINVAL;
40
395d00d1
AP		 41 buf[0] = reg;
42 memcpy(&buf[1], val, len);
43
44 mutex_lock(&priv->i2c_mutex);
45 ret = i2c_transfer(priv->i2c, msg, 1);
46 mutex_unlock(&priv->i2c_mutex);
47 if (ret == 1) {
48 ret = 0;
49 } else {
50 dev_warn(&priv->i2c->dev,
51 "%s: i2c wr failed=%d reg=%02x len=%d\n",
52 KBUILD_MODNAME, ret, reg, len);
53 ret = -EREMOTEIO;
54 }
55
56 return ret;
57}
58
59/* read multiple registers */
60static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
61 u8 reg, u8 *val, int len)
62{
63c80f70
AP		 63#define MAX_RD_LEN 3
64#define MAX_RD_XFER_LEN (MAX_RD_LEN)
395d00d1 65 int ret;
63c80f70 66 u8 buf[MAX_RD_XFER_LEN];
395d00d1
AP		 67 struct i2c_msg msg[2] = {
68 {
69 .addr = priv->cfg->i2c_addr,
70 .flags = 0,
71 .len = 1,
72 .buf = &reg,
73 }, {
74 .addr = priv->cfg->i2c_addr,
75 .flags = I2C_M_RD,
63c80f70 76 .len = len,
395d00d1
AP		 77 .buf = buf,
78 }
79 };
80
63c80f70
AP		 81 if (WARN_ON(len > MAX_RD_LEN))
82 return -EINVAL;
83
395d00d1
AP		 84 mutex_lock(&priv->i2c_mutex);
85 ret = i2c_transfer(priv->i2c, msg, 2);
86 mutex_unlock(&priv->i2c_mutex);
87 if (ret == 2) {
88 memcpy(val, buf, len);
89 ret = 0;
90 } else {
91 dev_warn(&priv->i2c->dev,
92 "%s: i2c rd failed=%d reg=%02x len=%d\n",
93 KBUILD_MODNAME, ret, reg, len);
94 ret = -EREMOTEIO;
95 }
96
97 return ret;
98}
99
100/* write single register */
101static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
102{
103 return m88ds3103_wr_regs(priv, reg, &val, 1);
104}
105
106/* read single register */
107static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
108{
109 return m88ds3103_rd_regs(priv, reg, val, 1);
110}
111
112/* write single register with mask */
113static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
114 u8 reg, u8 val, u8 mask)
115{
116 int ret;
117 u8 u8tmp;
118
119 /* no need for read if whole reg is written */
120 if (mask != 0xff) {
121 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
122 if (ret)
123 return ret;
124
125 val &= mask;
126 u8tmp &= ~mask;
127 val |= u8tmp;
128 }
129
130 return m88ds3103_wr_regs(priv, reg, &val, 1);
131}
132
133/* read single register with mask */
134static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
135 u8 reg, u8 *val, u8 mask)
136{
137 int ret, i;
138 u8 u8tmp;
139
140 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
141 if (ret)
142 return ret;
143
144 u8tmp &= mask;
145
146 /* find position of the first bit */
147 for (i = 0; i < 8; i++) {
148 if ((mask >> i) & 0x01)
149 break;
150 }
151 *val = u8tmp >> i;
152
153 return 0;
154}
155
06487dee
AP		 156/* write reg val table using reg addr auto increment */
157static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv,
158 const struct m88ds3103_reg_val *tab, int tab_len)
159{
160 int ret, i, j;
161 u8 buf[83];
41b9aa00 162
06487dee
AP		 163 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
164
f4df95bc 165 if (tab_len > 86) {
06487dee
AP		 166 ret = -EINVAL;
167 goto err;
168 }
169
170 for (i = 0, j = 0; i < tab_len; i++, j++) {
171 buf[j] = tab[i].val;
172
173 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
174 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) {
175 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1);
176 if (ret)
177 goto err;
178
179 j = -1;
180 }
181 }
182
183 return 0;
184err:
185 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
186 return ret;
187}
188
395d00d1
AP		 189static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status)
190{
191 struct m88ds3103_priv *priv = fe->demodulator_priv;
192 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
193 int ret;
194 u8 u8tmp;
195
196 *status = 0;
197
198 if (!priv->warm) {
199 ret = -EAGAIN;
200 goto err;
201 }
202
203 switch (c->delivery_system) {
204 case SYS_DVBS:
205 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
206 if (ret)
207 goto err;
208
209 if (u8tmp == 0x07)
210 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
211 FE_HAS_VITERBI | FE_HAS_SYNC |
212 FE_HAS_LOCK;
213 break;
214 case SYS_DVBS2:
215 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
216 if (ret)
217 goto err;
218
219 if (u8tmp == 0x8f)
220 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
221 FE_HAS_VITERBI | FE_HAS_SYNC |
222 FE_HAS_LOCK;
223 break;
224 default:
225 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
226 __func__);
227 ret = -EINVAL;
228 goto err;
229 }
230
231 priv->fe_status = *status;
232
233 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
234 __func__, u8tmp, *status);
235
236 return 0;
237err:
238 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
239 return ret;
240}
241
242static int m88ds3103_set_frontend(struct dvb_frontend *fe)
243{
244 struct m88ds3103_priv *priv = fe->demodulator_priv;
245 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
06487dee 246 int ret, len;
395d00d1 247 const struct m88ds3103_reg_val *init;
b6851419 248 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
f4df95bc 249 u8 buf[3];
b6851419 250 u16 u16tmp, divide_ratio = 0;
79d09330 251 u32 tuner_frequency, target_mclk;
395d00d1 252 s32 s32tmp;
41b9aa00 253
395d00d1
AP		 254 dev_dbg(&priv->i2c->dev,
255 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
256 __func__, c->delivery_system,
257 c->modulation, c->frequency, c->symbol_rate,
258 c->inversion, c->pilot, c->rolloff);
259
260 if (!priv->warm) {
261 ret = -EAGAIN;
262 goto err;
263 }
264
f4df95bc 265 /* reset */
266 ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
267 if (ret)
268 goto err;
269
270 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
271 if (ret)
272 goto err;
273
274 /* Disable demod clock path */
275 if (priv->chip_id == M88RS6000_CHIP_ID) {
276 ret = m88ds3103_wr_reg(priv, 0x06, 0xe0);
277 if (ret)
278 goto err;
279 }
280
395d00d1
AP		 281 /* program tuner */
282 if (fe->ops.tuner_ops.set_params) {
283 ret = fe->ops.tuner_ops.set_params(fe);
284 if (ret)
285 goto err;
286 }
287
288 if (fe->ops.tuner_ops.get_frequency) {
289 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
290 if (ret)
291 goto err;
2f9dff3f
AP		 292 } else {
293 /*
294 * Use nominal target frequency as tuner driver does not provide
295 * actual frequency used. Carrier offset calculation is not
296 * valid.
297 */
298 tuner_frequency = c->frequency;
395d00d1
AP		 299 }
300
f4df95bc 301 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */
302 if (priv->chip_id == M88RS6000_CHIP_ID) {
303 if (c->symbol_rate > 45010000)
304 priv->mclk_khz = 110250;
305 else
306 priv->mclk_khz = 96000;
395d00d1 307
f4df95bc 308 if (c->delivery_system == SYS_DVBS)
309 target_mclk = 96000;
310 else
311 target_mclk = 144000;
312
313 /* Enable demod clock path */
314 ret = m88ds3103_wr_reg(priv, 0x06, 0x00);
315 if (ret)
316 goto err;
317 usleep_range(10000, 20000);
318 } else {
319 /* set M88DS3103 mclk and ts mclk. */
320 priv->mclk_khz = 96000;
321
b6851419 322 switch (priv->cfg->ts_mode) {
323 case M88DS3103_TS_SERIAL:
324 case M88DS3103_TS_SERIAL_D7:
325 target_mclk = priv->cfg->ts_clk;
326 break;
327 case M88DS3103_TS_PARALLEL:
328 case M88DS3103_TS_CI:
329 if (c->delivery_system == SYS_DVBS)
330 target_mclk = 96000;
331 else {
f4df95bc 332 if (c->symbol_rate < 18000000)
333 target_mclk = 96000;
334 else if (c->symbol_rate < 28000000)
335 target_mclk = 144000;
336 else
337 target_mclk = 192000;
f4df95bc 338 }
b6851419 339 break;
340 default:
341 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
342 __func__);
343 ret = -EINVAL;
344 goto err;
f4df95bc 345 }
346
347 switch (target_mclk) {
348 case 96000:
349 u8tmp1 = 0x02; /* 0b10 */
350 u8tmp2 = 0x01; /* 0b01 */
351 break;
352 case 144000:
353 u8tmp1 = 0x00; /* 0b00 */
354 u8tmp2 = 0x01; /* 0b01 */
355 break;
356 case 192000:
357 u8tmp1 = 0x03; /* 0b11 */
358 u8tmp2 = 0x00; /* 0b00 */
359 break;
360 }
361 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
362 if (ret)
363 goto err;
364 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
365 if (ret)
366 goto err;
367 }
395d00d1
AP		 368
369 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
370 if (ret)
371 goto err;
372
373 ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
374 if (ret)
375 goto err;
376
377 switch (c->delivery_system) {
378 case SYS_DVBS:
f4df95bc 379 if (priv->chip_id == M88RS6000_CHIP_ID) {
380 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
381 init = m88rs6000_dvbs_init_reg_vals;
382 } else {
383 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
384 init = m88ds3103_dvbs_init_reg_vals;
385 }
395d00d1
AP		 386 break;
387 case SYS_DVBS2:
f4df95bc 388 if (priv->chip_id == M88RS6000_CHIP_ID) {
389 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
390 init = m88rs6000_dvbs2_init_reg_vals;
391 } else {
392 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
393 init = m88ds3103_dvbs2_init_reg_vals;
395d00d1
AP		 394 }
395 break;
396 default:
397 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
398 __func__);
399 ret = -EINVAL;
400 goto err;
401 }
402
403 /* program init table */
404 if (c->delivery_system != priv->delivery_system) {
06487dee
AP		 405 ret = m88ds3103_wr_reg_val_tab(priv, init, len);
406 if (ret)
407 goto err;
395d00d1
AP		 408 }
409
f4df95bc 410 if (priv->chip_id == M88RS6000_CHIP_ID) {
411 if ((c->delivery_system == SYS_DVBS2)
412 && ((c->symbol_rate / 1000) <= 5000)) {
413 ret = m88ds3103_wr_reg(priv, 0xc0, 0x04);
414 if (ret)
415 goto err;
416 buf[0] = 0x09;
417 buf[1] = 0x22;
418 buf[2] = 0x88;
419 ret = m88ds3103_wr_regs(priv, 0x8a, buf, 3);
420 if (ret)
421 goto err;
422 }
423 ret = m88ds3103_wr_reg_mask(priv, 0x9d, 0x08, 0x08);
424 if (ret)
425 goto err;
426 ret = m88ds3103_wr_reg(priv, 0xf1, 0x01);
427 if (ret)
428 goto err;
429 ret = m88ds3103_wr_reg_mask(priv, 0x30, 0x80, 0x80);
430 if (ret)
431 goto err;
432 }
433
395d00d1
AP		 434 switch (priv->cfg->ts_mode) {
435 case M88DS3103_TS_SERIAL:
436 u8tmp1 = 0x00;
79d09330 437 u8tmp = 0x06;
395d00d1
AP		 438 break;
439 case M88DS3103_TS_SERIAL_D7:
440 u8tmp1 = 0x20;
79d09330 441 u8tmp = 0x06;
395d00d1
AP		 442 break;
443 case M88DS3103_TS_PARALLEL:
79d09330 444 u8tmp = 0x02;
395d00d1
AP		 445 break;
446 case M88DS3103_TS_CI:
79d09330 447 u8tmp = 0x03;
395d00d1
AP		 448 break;
449 default:
450 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
451 ret = -EINVAL;
452 goto err;
453 }
454
79d09330 455 if (priv->cfg->ts_clk_pol)
456 u8tmp |= 0x40;
457
395d00d1 458 /* TS mode */
92676ac9 459 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp);
395d00d1
AP		 460 if (ret)
461 goto err;
462
463 switch (priv->cfg->ts_mode) {
464 case M88DS3103_TS_SERIAL:
465 case M88DS3103_TS_SERIAL_D7:
466 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
467 if (ret)
468 goto err;
395d00d1
AP		 469 u8tmp1 = 0;
470 u8tmp2 = 0;
b6851419 471 break;
472 default:
473 if (priv->cfg->ts_clk) {
474 divide_ratio = DIV_ROUND_UP(target_mclk, priv->cfg->ts_clk);
475 u8tmp1 = divide_ratio / 2;
476 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
477 }
395d00d1
AP		 478 }
479
480 dev_dbg(&priv->i2c->dev,
481 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
79d09330 482 __func__, target_mclk, priv->cfg->ts_clk, divide_ratio);
395d00d1
AP		 483
484 u8tmp1--;
485 u8tmp2--;
486 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
487 u8tmp1 &= 0x3f;
488 /* u8tmp2[5:0] => ea[5:0] */
489 u8tmp2 &= 0x3f;
490
491 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
492 if (ret)
493 goto err;
494
495 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
496 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
497 if (ret)
498 goto err;
499
500 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
501 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
502 if (ret)
503 goto err;
504
395d00d1
AP		 505 if (c->symbol_rate <= 3000000)
506 u8tmp = 0x20;
507 else if (c->symbol_rate <= 10000000)
508 u8tmp = 0x10;
509 else
510 u8tmp = 0x06;
511
512 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
513 if (ret)
514 goto err;
515
516 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
517 if (ret)
518 goto err;
519
520 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
521 if (ret)
522 goto err;
523
524 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
525 if (ret)
526 goto err;
527
f4df95bc 528 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, priv->mclk_khz / 2);
395d00d1
AP		 529 buf[0] = (u16tmp >> 0) & 0xff;
530 buf[1] = (u16tmp >> 8) & 0xff;
531 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
532 if (ret)
533 goto err;
534
535 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
536 if (ret)
537 goto err;
538
539 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
540 if (ret)
541 goto err;
542
543 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
544 if (ret)
545 goto err;
546
547 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
548 (tuner_frequency - c->frequency));
549
550 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
f4df95bc 551 s32tmp = DIV_ROUND_CLOSEST(s32tmp, priv->mclk_khz);
395d00d1
AP		 552 if (s32tmp < 0)
553 s32tmp += 0x10000;
554
555 buf[0] = (s32tmp >> 0) & 0xff;
556 buf[1] = (s32tmp >> 8) & 0xff;
557 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
558 if (ret)
559 goto err;
560
561 ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
562 if (ret)
563 goto err;
564
565 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
566 if (ret)
567 goto err;
568
569 priv->delivery_system = c->delivery_system;
570
571 return 0;
572err:
573 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
574 return ret;
575}
576
577static int m88ds3103_init(struct dvb_frontend *fe)
578{
579 struct m88ds3103_priv *priv = fe->demodulator_priv;
580 int ret, len, remaining;
581 const struct firmware *fw = NULL;
f4df95bc 582 u8 *fw_file;
395d00d1 583 u8 u8tmp;
41b9aa00 584
395d00d1
AP		 585 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
586
587 /* set cold state by default */
588 priv->warm = false;
589
590 /* wake up device from sleep */
591 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
592 if (ret)
593 goto err;
594
595 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
596 if (ret)
597 goto err;
598
599 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
600 if (ret)
601 goto err;
602
395d00d1
AP		 603 /* firmware status */
604 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
605 if (ret)
606 goto err;
607
608 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
609
610 if (u8tmp)
611 goto skip_fw_download;
612
f4df95bc 613 /* global reset, global diseqc reset, golbal fec reset */
614 ret = m88ds3103_wr_reg(priv, 0x07, 0xe0);
615 if (ret)
616 goto err;
617
618 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
619 if (ret)
620 goto err;
621
395d00d1
AP		 622 /* cold state - try to download firmware */
623 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
624 KBUILD_MODNAME, m88ds3103_ops.info.name);
625
f4df95bc 626 if (priv->chip_id == M88RS6000_CHIP_ID)
627 fw_file = M88RS6000_FIRMWARE;
628 else
629 fw_file = M88DS3103_FIRMWARE;
395d00d1
AP		 630 /* request the firmware, this will block and timeout */
631 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
632 if (ret) {
633 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n",
634 KBUILD_MODNAME, fw_file);
635 goto err;
636 }
637
638 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
639 KBUILD_MODNAME, fw_file);
640
641 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
642 if (ret)
643 goto err;
644
645 for (remaining = fw->size; remaining > 0;
646 remaining -= (priv->cfg->i2c_wr_max - 1)) {
647 len = remaining;
648 if (len > (priv->cfg->i2c_wr_max - 1))
649 len = (priv->cfg->i2c_wr_max - 1);
650
651 ret = m88ds3103_wr_regs(priv, 0xb0,
652 &fw->data[fw->size - remaining], len);
653 if (ret) {
654 dev_err(&priv->i2c->dev,
655 "%s: firmware download failed=%d\n",
656 KBUILD_MODNAME, ret);
657 goto err;
658 }
659 }
660
661 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
662 if (ret)
663 goto err;
664
665 release_firmware(fw);
666 fw = NULL;
667
668 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
669 if (ret)
670 goto err;
671
672 if (!u8tmp) {
673 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
674 KBUILD_MODNAME);
675 ret = -EFAULT;
676 goto err;
677 }
678
679 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
680 KBUILD_MODNAME, m88ds3103_ops.info.name);
681 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
682 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
683
684skip_fw_download:
685 /* warm state */
686 priv->warm = true;
687
688 return 0;
689err:
9bc2dd7e 690 release_firmware(fw);
395d00d1
AP		 691
692 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
693 return ret;
694}
695
696static int m88ds3103_sleep(struct dvb_frontend *fe)
697{
698 struct m88ds3103_priv *priv = fe->demodulator_priv;
699 int ret;
f4df95bc 700 u8 u8tmp;
41b9aa00 701
395d00d1
AP		 702 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
703
704 priv->delivery_system = SYS_UNDEFINED;
705
706 /* TS Hi-Z */
f4df95bc 707 if (priv->chip_id == M88RS6000_CHIP_ID)
708 u8tmp = 0x29;
709 else
710 u8tmp = 0x27;
711 ret = m88ds3103_wr_reg_mask(priv, u8tmp, 0x00, 0x01);
395d00d1
AP		 712 if (ret)
713 goto err;
714
715 /* sleep */
716 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
717 if (ret)
718 goto err;
719
720 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
721 if (ret)
722 goto err;
723
724 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
725 if (ret)
726 goto err;
727
728 return 0;
729err:
730 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
731 return ret;
732}
733
734static int m88ds3103_get_frontend(struct dvb_frontend *fe)
735{
736 struct m88ds3103_priv *priv = fe->demodulator_priv;
737 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
738 int ret;
739 u8 buf[3];
41b9aa00 740
395d00d1
AP		 741 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
742
743 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
744 ret = -EAGAIN;
745 goto err;
746 }
747
748 switch (c->delivery_system) {
749 case SYS_DVBS:
750 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
751 if (ret)
752 goto err;
753
754 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
755 if (ret)
756 goto err;
757
758 switch ((buf[0] >> 2) & 0x01) {
759 case 0:
760 c->inversion = INVERSION_OFF;
761 break;
762 case 1:
763 c->inversion = INVERSION_ON;
764 break;
395d00d1
AP		 765 }
766
767 switch ((buf[1] >> 5) & 0x07) {
768 case 0:
769 c->fec_inner = FEC_7_8;
770 break;
771 case 1:
772 c->fec_inner = FEC_5_6;
773 break;
774 case 2:
775 c->fec_inner = FEC_3_4;
776 break;
777 case 3:
778 c->fec_inner = FEC_2_3;
779 break;
780 case 4:
781 c->fec_inner = FEC_1_2;
782 break;
783 default:
784 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
785 __func__);
786 }
787
788 c->modulation = QPSK;
789
790 break;
791 case SYS_DVBS2:
792 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
793 if (ret)
794 goto err;
795
796 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
797 if (ret)
798 goto err;
799
800 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
801 if (ret)
802 goto err;
803
804 switch ((buf[0] >> 0) & 0x0f) {
805 case 2:
806 c->fec_inner = FEC_2_5;
807 break;
808 case 3:
809 c->fec_inner = FEC_1_2;
810 break;
811 case 4:
812 c->fec_inner = FEC_3_5;
813 break;
814 case 5:
815 c->fec_inner = FEC_2_3;
816 break;
817 case 6:
818 c->fec_inner = FEC_3_4;
819 break;
820 case 7:
821 c->fec_inner = FEC_4_5;
822 break;
823 case 8:
824 c->fec_inner = FEC_5_6;
825 break;
826 case 9:
827 c->fec_inner = FEC_8_9;
828 break;
829 case 10:
830 c->fec_inner = FEC_9_10;
831 break;
832 default:
833 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
834 __func__);
835 }
836
837 switch ((buf[0] >> 5) & 0x01) {
838 case 0:
839 c->pilot = PILOT_OFF;
840 break;
841 case 1:
842 c->pilot = PILOT_ON;
843 break;
395d00d1
AP		 844 }
845
846 switch ((buf[0] >> 6) & 0x07) {
847 case 0:
848 c->modulation = QPSK;
849 break;
850 case 1:
851 c->modulation = PSK_8;
852 break;
853 case 2:
854 c->modulation = APSK_16;
855 break;
856 case 3:
857 c->modulation = APSK_32;
858 break;
859 default:
860 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
861 __func__);
862 }
863
864 switch ((buf[1] >> 7) & 0x01) {
865 case 0:
866 c->inversion = INVERSION_OFF;
867 break;
868 case 1:
869 c->inversion = INVERSION_ON;
870 break;
395d00d1
AP		 871 }
872
873 switch ((buf[2] >> 0) & 0x03) {
874 case 0:
875 c->rolloff = ROLLOFF_35;
876 break;
877 case 1:
878 c->rolloff = ROLLOFF_25;
879 break;
880 case 2:
881 c->rolloff = ROLLOFF_20;
882 break;
883 default:
884 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
885 __func__);
886 }
887 break;
888 default:
889 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
890 __func__);
891 ret = -EINVAL;
892 goto err;
893 }
894
895 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
896 if (ret)
897 goto err;
898
899 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
f4df95bc 900 priv->mclk_khz * 1000 / 0x10000;
395d00d1
AP		 901
902 return 0;
903err:
904 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
905 return ret;
906}
907
908static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
909{
910 struct m88ds3103_priv *priv = fe->demodulator_priv;
911 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
912 int ret, i, tmp;
913 u8 buf[3];
914 u16 noise, signal;
915 u32 noise_tot, signal_tot;
41b9aa00 916
395d00d1
AP		 917 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
918 /* reports SNR in resolution of 0.1 dB */
919
920 /* more iterations for more accurate estimation */
921 #define M88DS3103_SNR_ITERATIONS 3
922
923 switch (c->delivery_system) {
924 case SYS_DVBS:
925 tmp = 0;
926
927 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
928 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
929 if (ret)
930 goto err;
931
932 tmp += buf[0];
933 }
934
935 /* use of one register limits max value to 15 dB */
936 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
937 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS);
938 if (tmp)
3ae266f8 939 *snr = div_u64((u64) 100 * intlog2(tmp), intlog2(10));
395d00d1
AP		 940 else
941 *snr = 0;
942 break;
943 case SYS_DVBS2:
944 noise_tot = 0;
945 signal_tot = 0;
946
947 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
948 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
949 if (ret)
950 goto err;
951
952 noise = buf[1] << 6; /* [13:6] */
953 noise |= buf[0] & 0x3f; /* [5:0] */
954 noise >>= 2;
955 signal = buf[2] * buf[2];
956 signal >>= 1;
957
958 noise_tot += noise;
959 signal_tot += signal;
960 }
961
962 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
963 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
964
965 /* SNR(X) dB = 10 * log10(X) dB */
966 if (signal > noise) {
967 tmp = signal / noise;
3ae266f8 968 *snr = div_u64((u64) 100 * intlog10(tmp), (1 << 24));
8a878dc4 969 } else {
395d00d1 970 *snr = 0;
8a878dc4 971 }
395d00d1
AP		 972 break;
973 default:
974 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
975 __func__);
976 ret = -EINVAL;
977 goto err;
978 }
979
980 return 0;
981err:
982 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
983 return ret;
984}
985
4423a2ba
AP		 986static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
987{
988 struct m88ds3103_priv *priv = fe->demodulator_priv;
989 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
990 int ret;
991 unsigned int utmp;
992 u8 buf[3], u8tmp;
41b9aa00 993
4423a2ba
AP		 994 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
995
996 switch (c->delivery_system) {
997 case SYS_DVBS:
998 ret = m88ds3103_wr_reg(priv, 0xf9, 0x04);
999 if (ret)
1000 goto err;
1001
1002 ret = m88ds3103_rd_reg(priv, 0xf8, &u8tmp);
1003 if (ret)
1004 goto err;
1005
1006 if (!(u8tmp & 0x10)) {
1007 u8tmp |= 0x10;
1008
1009 ret = m88ds3103_rd_regs(priv, 0xf6, buf, 2);
1010 if (ret)
1011 goto err;
1012
1013 priv->ber = (buf[1] << 8) | (buf[0] << 0);
1014
1015 /* restart counters */
1016 ret = m88ds3103_wr_reg(priv, 0xf8, u8tmp);
1017 if (ret)
1018 goto err;
1019 }
1020 break;
1021 case SYS_DVBS2:
1022 ret = m88ds3103_rd_regs(priv, 0xd5, buf, 3);
1023 if (ret)
1024 goto err;
1025
1026 utmp = (buf[2] << 16) | (buf[1] << 8) | (buf[0] << 0);
1027
1028 if (utmp > 3000) {
1029 ret = m88ds3103_rd_regs(priv, 0xf7, buf, 2);
1030 if (ret)
1031 goto err;
1032
1033 priv->ber = (buf[1] << 8) | (buf[0] << 0);
1034
1035 /* restart counters */
1036 ret = m88ds3103_wr_reg(priv, 0xd1, 0x01);
1037 if (ret)
1038 goto err;
1039
1040 ret = m88ds3103_wr_reg(priv, 0xf9, 0x01);
1041 if (ret)
1042 goto err;
1043
1044 ret = m88ds3103_wr_reg(priv, 0xf9, 0x00);
1045 if (ret)
1046 goto err;
1047
1048 ret = m88ds3103_wr_reg(priv, 0xd1, 0x00);
1049 if (ret)
1050 goto err;
1051 }
1052 break;
1053 default:
1054 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
1055 __func__);
1056 ret = -EINVAL;
1057 goto err;
1058 }
1059
1060 *ber = priv->ber;
1061
1062 return 0;
1063err:
1064 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1065 return ret;
1066}
395d00d1
AP		 1067
1068static int m88ds3103_set_tone(struct dvb_frontend *fe,
1069 fe_sec_tone_mode_t fe_sec_tone_mode)
1070{
1071 struct m88ds3103_priv *priv = fe->demodulator_priv;
1072 int ret;
1073 u8 u8tmp, tone, reg_a1_mask;
41b9aa00 1074
395d00d1
AP		 1075 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
1076 fe_sec_tone_mode);
1077
1078 if (!priv->warm) {
1079 ret = -EAGAIN;
1080 goto err;
1081 }
1082
1083 switch (fe_sec_tone_mode) {
1084 case SEC_TONE_ON:
1085 tone = 0;
418a97cb 1086 reg_a1_mask = 0x47;
395d00d1
AP		 1087 break;
1088 case SEC_TONE_OFF:
1089 tone = 1;
1090 reg_a1_mask = 0x00;
1091 break;
1092 default:
1093 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
1094 __func__);
1095 ret = -EINVAL;
1096 goto err;
1097 }
1098
1099 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
1100 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1101 if (ret)
1102 goto err;
1103
1104 u8tmp = 1 << 2;
1105 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
1106 if (ret)
1107 goto err;
1108
1109 return 0;
1110err:
1111 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1112 return ret;
1113}
1114
79d09330 1115static int m88ds3103_set_voltage(struct dvb_frontend *fe,
d28677ff 1116 fe_sec_voltage_t fe_sec_voltage)
79d09330 1117{
1118 struct m88ds3103_priv *priv = fe->demodulator_priv;
d28677ff
AP		 1119 int ret;
1120 u8 u8tmp;
1121 bool voltage_sel, voltage_dis;
79d09330 1122
d28677ff
AP		 1123 dev_dbg(&priv->i2c->dev, "%s: fe_sec_voltage=%d\n", __func__,
1124 fe_sec_voltage);
79d09330 1125
d28677ff
AP		 1126 if (!priv->warm) {
1127 ret = -EAGAIN;
1128 goto err;
1129 }
79d09330 1130
d28677ff 1131 switch (fe_sec_voltage) {
79d09330 1132 case SEC_VOLTAGE_18:
afbd6eb4
MCC		 1133 voltage_sel = true;
1134 voltage_dis = false;
79d09330 1135 break;
1136 case SEC_VOLTAGE_13:
afbd6eb4
MCC		 1137 voltage_sel = false;
1138 voltage_dis = false;
79d09330 1139 break;
1140 case SEC_VOLTAGE_OFF:
afbd6eb4
MCC		 1141 voltage_sel = false;
1142 voltage_dis = true;
79d09330 1143 break;
d28677ff
AP		 1144 default:
1145 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_voltage\n",
1146 __func__);
1147 ret = -EINVAL;
1148 goto err;
79d09330 1149 }
d28677ff
AP		 1150
1151 /* output pin polarity */
1152 voltage_sel ^= priv->cfg->lnb_hv_pol;
1153 voltage_dis ^= priv->cfg->lnb_en_pol;
1154
1155 u8tmp = voltage_dis << 1 | voltage_sel << 0;
1156 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0x03);
1157 if (ret)
1158 goto err;
79d09330 1159
1160 return 0;
d28677ff
AP		 1161err:
1162 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1163 return ret;
79d09330 1164}
1165
395d00d1
AP		 1166static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1167 struct dvb_diseqc_master_cmd *diseqc_cmd)
1168{
1169 struct m88ds3103_priv *priv = fe->demodulator_priv;
1170 int ret, i;
1171 u8 u8tmp;
41b9aa00 1172
395d00d1
AP		 1173 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
1174 diseqc_cmd->msg_len, diseqc_cmd->msg);
1175
1176 if (!priv->warm) {
1177 ret = -EAGAIN;
1178 goto err;
1179 }
1180
1181 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1182 ret = -EINVAL;
1183 goto err;
1184 }
1185
1186 u8tmp = priv->cfg->envelope_mode << 5;
1187 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1188 if (ret)
1189 goto err;
1190
1191 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
1192 diseqc_cmd->msg_len);
1193 if (ret)
1194 goto err;
1195
1196 ret = m88ds3103_wr_reg(priv, 0xa1,
1197 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1198 if (ret)
1199 goto err;
1200
1201 /* DiSEqC message typical period is 54 ms */
1202 usleep_range(40000, 60000);
1203
1204 /* wait DiSEqC TX ready */
1205 for (i = 20, u8tmp = 1; i && u8tmp; i--) {
1206 usleep_range(5000, 10000);
1207
1208 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1209 if (ret)
1210 goto err;
1211 }
1212
1213 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1214
1215 if (i == 0) {
1216 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1217
1218 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1219 if (ret)
1220 goto err;
1221 }
1222
1223 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1224 if (ret)
1225 goto err;
1226
1227 if (i == 0) {
1228 ret = -ETIMEDOUT;
1229 goto err;
1230 }
1231
1232 return 0;
1233err:
1234 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1235 return ret;
1236}
1237
1238static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1239 fe_sec_mini_cmd_t fe_sec_mini_cmd)
1240{
1241 struct m88ds3103_priv *priv = fe->demodulator_priv;
1242 int ret, i;
1243 u8 u8tmp, burst;
41b9aa00 1244
395d00d1
AP		 1245 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1246 fe_sec_mini_cmd);
1247
1248 if (!priv->warm) {
1249 ret = -EAGAIN;
1250 goto err;
1251 }
1252
1253 u8tmp = priv->cfg->envelope_mode << 5;
1254 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1255 if (ret)
1256 goto err;
1257
1258 switch (fe_sec_mini_cmd) {
1259 case SEC_MINI_A:
1260 burst = 0x02;
1261 break;
1262 case SEC_MINI_B:
1263 burst = 0x01;
1264 break;
1265 default:
1266 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1267 __func__);
1268 ret = -EINVAL;
1269 goto err;
1270 }
1271
1272 ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1273 if (ret)
1274 goto err;
1275
1276 /* DiSEqC ToneBurst period is 12.5 ms */
1277 usleep_range(11000, 20000);
1278
1279 /* wait DiSEqC TX ready */
1280 for (i = 5, u8tmp = 1; i && u8tmp; i--) {
1281 usleep_range(800, 2000);
1282
1283 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1284 if (ret)
1285 goto err;
1286 }
1287
1288 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1289
1290 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1291 if (ret)
1292 goto err;
1293
1294 if (i == 0) {
1295 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1296 ret = -ETIMEDOUT;
1297 goto err;
1298 }
1299
1300 return 0;
1301err:
1302 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1303 return ret;
1304}
1305
1306static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1307 struct dvb_frontend_tune_settings *s)
1308{
1309 s->min_delay_ms = 3000;
1310
1311 return 0;
1312}
1313
44b9055b 1314static void m88ds3103_release(struct dvb_frontend *fe)
395d00d1 1315{
44b9055b 1316 struct m88ds3103_priv *priv = fe->demodulator_priv;
41b9aa00 1317
44b9055b
AP		 1318 i2c_del_mux_adapter(priv->i2c_adapter);
1319 kfree(priv);
395d00d1
AP		 1320}
1321
44b9055b 1322static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
395d00d1 1323{
44b9055b 1324 struct m88ds3103_priv *priv = mux_priv;
395d00d1
AP		 1325 int ret;
1326 struct i2c_msg gate_open_msg[1] = {
1327 {
1328 .addr = priv->cfg->i2c_addr,
1329 .flags = 0,
1330 .len = 2,
1331 .buf = "\x03\x11",
1332 }
1333 };
395d00d1
AP		 1334
1335 mutex_lock(&priv->i2c_mutex);
1336
44b9055b 1337 /* open tuner I2C repeater for 1 xfer, closes automatically */
4fc57876 1338 ret = __i2c_transfer(priv->i2c, gate_open_msg, 1);
395d00d1 1339 if (ret != 1) {
44b9055b 1340 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n",
395d00d1 1341 KBUILD_MODNAME, ret);
44b9055b
AP		 1342 if (ret >= 0)
1343 ret = -EREMOTEIO;
395d00d1 1344
44b9055b
AP		 1345 return ret;
1346 }
395d00d1 1347
44b9055b 1348 return 0;
395d00d1
AP		 1349}
1350
44b9055b
AP		 1351static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv,
1352 u32 chan)
395d00d1 1353{
44b9055b
AP		 1354 struct m88ds3103_priv *priv = mux_priv;
1355
1356 mutex_unlock(&priv->i2c_mutex);
1357
1358 return 0;
395d00d1
AP		 1359}
1360
1361struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1362 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1363{
1364 int ret;
1365 struct m88ds3103_priv *priv;
1366 u8 chip_id, u8tmp;
1367
1368 /* allocate memory for the internal priv */
8a878dc4 1369 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
395d00d1
AP		 1370 if (!priv) {
1371 ret = -ENOMEM;
1372 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
1373 goto err;
1374 }
1375
1376 priv->cfg = cfg;
1377 priv->i2c = i2c;
1378 mutex_init(&priv->i2c_mutex);
1379
f4df95bc 1380 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1381 ret = m88ds3103_rd_reg(priv, 0x00, &chip_id);
395d00d1
AP		 1382 if (ret)
1383 goto err;
1384
f4df95bc 1385 chip_id >>= 1;
1386 dev_info(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
395d00d1
AP		 1387
1388 switch (chip_id) {
f4df95bc 1389 case M88RS6000_CHIP_ID:
1390 case M88DS3103_CHIP_ID:
395d00d1
AP		 1391 break;
1392 default:
1393 goto err;
1394 }
f4df95bc 1395 priv->chip_id = chip_id;
395d00d1
AP		 1396
1397 switch (priv->cfg->clock_out) {
1398 case M88DS3103_CLOCK_OUT_DISABLED:
1399 u8tmp = 0x80;
1400 break;
1401 case M88DS3103_CLOCK_OUT_ENABLED:
1402 u8tmp = 0x00;
1403 break;
1404 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1405 u8tmp = 0x10;
1406 break;
1407 default:
1408 goto err;
1409 }
1410
f4df95bc 1411 /* 0x29 register is defined differently for m88rs6000. */
1412 /* set internal tuner address to 0x21 */
1413 if (chip_id == M88RS6000_CHIP_ID)
1414 u8tmp = 0x00;
1415
395d00d1
AP		 1416 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp);
1417 if (ret)
1418 goto err;
1419
1420 /* sleep */
1421 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
1422 if (ret)
1423 goto err;
1424
1425 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
1426 if (ret)
1427 goto err;
1428
1429 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
1430 if (ret)
1431 goto err;
1432
44b9055b
AP		 1433 /* create mux i2c adapter for tuner */
1434 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
1435 m88ds3103_select, m88ds3103_deselect);
1436 if (priv->i2c_adapter == NULL)
1437 goto err;
1438
1439 *tuner_i2c_adapter = priv->i2c_adapter;
1440
395d00d1
AP		 1441 /* create dvb_frontend */
1442 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
f4df95bc 1443 if (priv->chip_id == M88RS6000_CHIP_ID)
1444 strncpy(priv->fe.ops.info.name,
1445 "Montage M88RS6000", sizeof(priv->fe.ops.info.name));
395d00d1
AP		 1446 priv->fe.demodulator_priv = priv;
1447
395d00d1
AP		 1448 return &priv->fe;
1449err:
1450 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
1451 kfree(priv);
1452 return NULL;
1453}
1454EXPORT_SYMBOL(m88ds3103_attach);
1455
1456static struct dvb_frontend_ops m88ds3103_ops = {
1457 .delsys = { SYS_DVBS, SYS_DVBS2 },
1458 .info = {
1459 .name = "Montage M88DS3103",
1460 .frequency_min = 950000,
1461 .frequency_max = 2150000,
1462 .frequency_tolerance = 5000,
1463 .symbol_rate_min = 1000000,
1464 .symbol_rate_max = 45000000,
1465 .caps = FE_CAN_INVERSION_AUTO |
1466 FE_CAN_FEC_1_2 |
1467 FE_CAN_FEC_2_3 |
1468 FE_CAN_FEC_3_4 |
1469 FE_CAN_FEC_4_5 |
1470 FE_CAN_FEC_5_6 |
1471 FE_CAN_FEC_6_7 |
1472 FE_CAN_FEC_7_8 |
1473 FE_CAN_FEC_8_9 |
1474 FE_CAN_FEC_AUTO |
1475 FE_CAN_QPSK |
1476 FE_CAN_RECOVER |
1477 FE_CAN_2G_MODULATION
1478 },
1479
1480 .release = m88ds3103_release,
1481
1482 .get_tune_settings = m88ds3103_get_tune_settings,
1483
1484 .init = m88ds3103_init,
1485 .sleep = m88ds3103_sleep,
1486
1487 .set_frontend = m88ds3103_set_frontend,
1488 .get_frontend = m88ds3103_get_frontend,
1489
1490 .read_status = m88ds3103_read_status,
1491 .read_snr = m88ds3103_read_snr,
4423a2ba 1492 .read_ber = m88ds3103_read_ber,
395d00d1
AP		 1493
1494 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1495 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1496
1497 .set_tone = m88ds3103_set_tone,
79d09330 1498 .set_voltage = m88ds3103_set_voltage,
395d00d1
AP		 1499};
1500
1501MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1502MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1503MODULE_LICENSE("GPL");
1504MODULE_FIRMWARE(M88DS3103_FIRMWARE);
f4df95bc 1505MODULE_FIRMWARE(M88RS6000_FIRMWARE);
Linux kernel - Deliverables
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