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[media] rtl2832: add support for GoTView MasterHD 3 USB tuner
[deliverable/linux.git] / drivers / media / dvb-frontends / rtl2832.c
CommitLineData
82041c0a
TM		 1/*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
75c24005 5 * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
82041c0a
TM		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#include "rtl2832_priv.h"
82041c0a 23
298f18a3 24#define REG_MASK(b) (BIT(b + 1) - 1)
82041c0a
TM		 25
26static const struct rtl2832_reg_entry registers[] = {
eec21beb
AP		 27 [DVBT_SOFT_RST] = {0x101, 2, 2},
28 [DVBT_IIC_REPEAT] = {0x101, 3, 3},
29 [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
30 [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
31 [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
32 [DVBT_AD_EN_REG] = {0x008, 7, 7},
33 [DVBT_AD_EN_REG1] = {0x008, 6, 6},
34 [DVBT_EN_BBIN] = {0x1b1, 0, 0},
35 [DVBT_MGD_THD0] = {0x195, 7, 0},
36 [DVBT_MGD_THD1] = {0x196, 7, 0},
37 [DVBT_MGD_THD2] = {0x197, 7, 0},
38 [DVBT_MGD_THD3] = {0x198, 7, 0},
39 [DVBT_MGD_THD4] = {0x199, 7, 0},
40 [DVBT_MGD_THD5] = {0x19a, 7, 0},
41 [DVBT_MGD_THD6] = {0x19b, 7, 0},
42 [DVBT_MGD_THD7] = {0x19c, 7, 0},
43 [DVBT_EN_CACQ_NOTCH] = {0x161, 4, 4},
44 [DVBT_AD_AV_REF] = {0x009, 6, 0},
45 [DVBT_REG_PI] = {0x00a, 2, 0},
46 [DVBT_PIP_ON] = {0x021, 3, 3},
47 [DVBT_SCALE1_B92] = {0x292, 7, 0},
48 [DVBT_SCALE1_B93] = {0x293, 7, 0},
49 [DVBT_SCALE1_BA7] = {0x2a7, 7, 0},
50 [DVBT_SCALE1_BA9] = {0x2a9, 7, 0},
51 [DVBT_SCALE1_BAA] = {0x2aa, 7, 0},
52 [DVBT_SCALE1_BAB] = {0x2ab, 7, 0},
53 [DVBT_SCALE1_BAC] = {0x2ac, 7, 0},
54 [DVBT_SCALE1_BB0] = {0x2b0, 7, 0},
55 [DVBT_SCALE1_BB1] = {0x2b1, 7, 0},
56 [DVBT_KB_P1] = {0x164, 3, 1},
57 [DVBT_KB_P2] = {0x164, 6, 4},
58 [DVBT_KB_P3] = {0x165, 2, 0},
59 [DVBT_OPT_ADC_IQ] = {0x006, 5, 4},
60 [DVBT_AD_AVI] = {0x009, 1, 0},
61 [DVBT_AD_AVQ] = {0x009, 3, 2},
62 [DVBT_K1_CR_STEP12] = {0x2ad, 9, 4},
63 [DVBT_TRK_KS_P2] = {0x16f, 2, 0},
64 [DVBT_TRK_KS_I2] = {0x170, 5, 3},
65 [DVBT_TR_THD_SET2] = {0x172, 3, 0},
66 [DVBT_TRK_KC_P2] = {0x173, 5, 3},
67 [DVBT_TRK_KC_I2] = {0x175, 2, 0},
68 [DVBT_CR_THD_SET2] = {0x176, 7, 6},
69 [DVBT_PSET_IFFREQ] = {0x119, 21, 0},
70 [DVBT_SPEC_INV] = {0x115, 0, 0},
71 [DVBT_RSAMP_RATIO] = {0x19f, 27, 2},
72 [DVBT_CFREQ_OFF_RATIO] = {0x19d, 23, 4},
73 [DVBT_FSM_STAGE] = {0x351, 6, 3},
74 [DVBT_RX_CONSTEL] = {0x33c, 3, 2},
75 [DVBT_RX_HIER] = {0x33c, 6, 4},
76 [DVBT_RX_C_RATE_LP] = {0x33d, 2, 0},
77 [DVBT_RX_C_RATE_HP] = {0x33d, 5, 3},
78 [DVBT_GI_IDX] = {0x351, 1, 0},
79 [DVBT_FFT_MODE_IDX] = {0x351, 2, 2},
80 [DVBT_RSD_BER_EST] = {0x34e, 15, 0},
81 [DVBT_CE_EST_EVM] = {0x40c, 15, 0},
82 [DVBT_RF_AGC_VAL] = {0x35b, 13, 0},
83 [DVBT_IF_AGC_VAL] = {0x359, 13, 0},
84 [DVBT_DAGC_VAL] = {0x305, 7, 0},
85 [DVBT_SFREQ_OFF] = {0x318, 13, 0},
86 [DVBT_CFREQ_OFF] = {0x35f, 17, 0},
87 [DVBT_POLAR_RF_AGC] = {0x00e, 1, 1},
88 [DVBT_POLAR_IF_AGC] = {0x00e, 0, 0},
89 [DVBT_AAGC_HOLD] = {0x104, 5, 5},
90 [DVBT_EN_RF_AGC] = {0x104, 6, 6},
91 [DVBT_EN_IF_AGC] = {0x104, 7, 7},
92 [DVBT_IF_AGC_MIN] = {0x108, 7, 0},
93 [DVBT_IF_AGC_MAX] = {0x109, 7, 0},
94 [DVBT_RF_AGC_MIN] = {0x10a, 7, 0},
95 [DVBT_RF_AGC_MAX] = {0x10b, 7, 0},
96 [DVBT_IF_AGC_MAN] = {0x10c, 6, 6},
97 [DVBT_IF_AGC_MAN_VAL] = {0x10c, 13, 0},
98 [DVBT_RF_AGC_MAN] = {0x10e, 6, 6},
99 [DVBT_RF_AGC_MAN_VAL] = {0x10e, 13, 0},
100 [DVBT_DAGC_TRG_VAL] = {0x112, 7, 0},
101 [DVBT_AGC_TARG_VAL_0] = {0x102, 0, 0},
102 [DVBT_AGC_TARG_VAL_8_1] = {0x103, 7, 0},
103 [DVBT_AAGC_LOOP_GAIN] = {0x1c7, 5, 1},
104 [DVBT_LOOP_GAIN2_3_0] = {0x104, 4, 1},
105 [DVBT_LOOP_GAIN2_4] = {0x105, 7, 7},
106 [DVBT_LOOP_GAIN3] = {0x1c8, 4, 0},
107 [DVBT_VTOP1] = {0x106, 5, 0},
108 [DVBT_VTOP2] = {0x1c9, 5, 0},
109 [DVBT_VTOP3] = {0x1ca, 5, 0},
110 [DVBT_KRF1] = {0x1cb, 7, 0},
111 [DVBT_KRF2] = {0x107, 7, 0},
112 [DVBT_KRF3] = {0x1cd, 7, 0},
113 [DVBT_KRF4] = {0x1ce, 7, 0},
114 [DVBT_EN_GI_PGA] = {0x1e5, 0, 0},
115 [DVBT_THD_LOCK_UP] = {0x1d9, 8, 0},
116 [DVBT_THD_LOCK_DW] = {0x1db, 8, 0},
117 [DVBT_THD_UP1] = {0x1dd, 7, 0},
118 [DVBT_THD_DW1] = {0x1de, 7, 0},
119 [DVBT_INTER_CNT_LEN] = {0x1d8, 3, 0},
120 [DVBT_GI_PGA_STATE] = {0x1e6, 3, 3},
121 [DVBT_EN_AGC_PGA] = {0x1d7, 0, 0},
122 [DVBT_CKOUTPAR] = {0x17b, 5, 5},
123 [DVBT_CKOUT_PWR] = {0x17b, 6, 6},
124 [DVBT_SYNC_DUR] = {0x17b, 7, 7},
125 [DVBT_ERR_DUR] = {0x17c, 0, 0},
126 [DVBT_SYNC_LVL] = {0x17c, 1, 1},
127 [DVBT_ERR_LVL] = {0x17c, 2, 2},
128 [DVBT_VAL_LVL] = {0x17c, 3, 3},
129 [DVBT_SERIAL] = {0x17c, 4, 4},
130 [DVBT_SER_LSB] = {0x17c, 5, 5},
131 [DVBT_CDIV_PH0] = {0x17d, 3, 0},
132 [DVBT_CDIV_PH1] = {0x17d, 7, 4},
133 [DVBT_MPEG_IO_OPT_2_2] = {0x006, 7, 7},
134 [DVBT_MPEG_IO_OPT_1_0] = {0x007, 7, 6},
135 [DVBT_CKOUTPAR_PIP] = {0x0b7, 4, 4},
136 [DVBT_CKOUT_PWR_PIP] = {0x0b7, 3, 3},
137 [DVBT_SYNC_LVL_PIP] = {0x0b7, 2, 2},
138 [DVBT_ERR_LVL_PIP] = {0x0b7, 1, 1},
139 [DVBT_VAL_LVL_PIP] = {0x0b7, 0, 0},
140 [DVBT_CKOUTPAR_PID] = {0x0b9, 4, 4},
141 [DVBT_CKOUT_PWR_PID] = {0x0b9, 3, 3},
142 [DVBT_SYNC_LVL_PID] = {0x0b9, 2, 2},
143 [DVBT_ERR_LVL_PID] = {0x0b9, 1, 1},
144 [DVBT_VAL_LVL_PID] = {0x0b9, 0, 0},
145 [DVBT_SM_PASS] = {0x193, 11, 0},
146 [DVBT_AD7_SETTING] = {0x011, 15, 0},
147 [DVBT_RSSI_R] = {0x301, 6, 0},
148 [DVBT_ACI_DET_IND] = {0x312, 0, 0},
149 [DVBT_REG_MON] = {0x00d, 1, 0},
150 [DVBT_REG_MONSEL] = {0x00d, 2, 2},
151 [DVBT_REG_GPE] = {0x00d, 7, 7},
152 [DVBT_REG_GPO] = {0x010, 0, 0},
153 [DVBT_REG_4MSEL] = {0x013, 0, 0},
82041c0a
TM		 154};
155
d1016581 156/* Our regmap is bypassing I2C adapter lock, thus we do it! */
bda977b7
MCC		 157static int rtl2832_bulk_write(struct i2c_client *client, unsigned int reg,
158 const void *val, size_t val_count)
82041c0a 159{
d1016581 160 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a 161 int ret;
82041c0a 162
d1016581
AP		 163 i2c_lock_adapter(client->adapter);
164 ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
165 i2c_unlock_adapter(client->adapter);
82041c0a
TM		 166 return ret;
167}
168
bda977b7
MCC		 169static int rtl2832_update_bits(struct i2c_client *client, unsigned int reg,
170 unsigned int mask, unsigned int val)
82041c0a 171{
d1016581 172 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a 173 int ret;
82041c0a 174
d1016581
AP		 175 i2c_lock_adapter(client->adapter);
176 ret = regmap_update_bits(dev->regmap, reg, mask, val);
177 i2c_unlock_adapter(client->adapter);
298efdd3 178 return ret;
82041c0a
TM		 179}
180
bda977b7
MCC		 181static int rtl2832_bulk_read(struct i2c_client *client, unsigned int reg,
182 void *val, size_t val_count)
82041c0a 183{
d1016581 184 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a
TM		 185 int ret;
186
d1016581
AP		 187 i2c_lock_adapter(client->adapter);
188 ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
189 i2c_unlock_adapter(client->adapter);
190 return ret;
191}
82041c0a 192
038c6f24 193static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
82041c0a 194{
6e6aac65 195 struct i2c_client *client = dev->client;
cd559e0b 196 int ret, i;
eec21beb 197 u16 reg_start_addr;
cd559e0b
AP		 198 u8 msb, lsb, reading[4], len;
199 u32 reading_tmp, mask;
82041c0a
TM		 200
201 reg_start_addr = registers[reg].start_address;
202 msb = registers[reg].msb;
203 lsb = registers[reg].lsb;
82041c0a 204 len = (msb >> 3) + 1;
298f18a3 205 mask = REG_MASK(msb - lsb);
82041c0a 206
eec21beb 207 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
82041c0a
TM		 208 if (ret)
209 goto err;
210
211 reading_tmp = 0;
212 for (i = 0; i < len; i++)
213 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
214
215 *val = (reading_tmp >> lsb) & mask;
216
cd559e0b 217 return 0;
82041c0a 218err:
6e6aac65 219 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a 220 return ret;
82041c0a
TM		 221}
222
038c6f24 223static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
82041c0a 224{
6e6aac65 225 struct i2c_client *client = dev->client;
82041c0a 226 int ret, i;
eec21beb 227 u16 reg_start_addr;
cd559e0b
AP		 228 u8 msb, lsb, reading[4], writing[4], len;
229 u32 reading_tmp, writing_tmp, mask;
82041c0a
TM		 230
231 reg_start_addr = registers[reg].start_address;
232 msb = registers[reg].msb;
233 lsb = registers[reg].lsb;
82041c0a 234 len = (msb >> 3) + 1;
298f18a3 235 mask = REG_MASK(msb - lsb);
82041c0a 236
eec21beb 237 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
82041c0a
TM		 238 if (ret)
239 goto err;
240
241 reading_tmp = 0;
242 for (i = 0; i < len; i++)
243 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
244
245 writing_tmp = reading_tmp & ~(mask << lsb);
246 writing_tmp |= ((val & mask) << lsb);
247
82041c0a
TM		 248 for (i = 0; i < len; i++)
249 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
250
eec21beb 251 ret = rtl2832_bulk_write(client, reg_start_addr, writing, len);
82041c0a
TM		 252 if (ret)
253 goto err;
254
cd559e0b 255 return 0;
82041c0a 256err:
6e6aac65 257 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a 258 return ret;
82041c0a
TM		 259}
260
884655ad 261static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
82041c0a 262{
038c6f24 263 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 264 struct i2c_client *client = dev->client;
884655ad 265 int ret;
82041c0a 266 u64 pset_iffreq;
884655ad
MCC		 267 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
268
269 /*
270 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
271 * / CrystalFreqHz)
272 */
e1174d78 273 pset_iffreq = if_freq % dev->pdata->clk;
884655ad 274 pset_iffreq *= 0x400000;
e1174d78 275 pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
c8832e8f 276 pset_iffreq = -pset_iffreq;
884655ad 277 pset_iffreq = pset_iffreq & 0x3fffff;
6e6aac65
AP		 278 dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
279 if_freq, (unsigned)pset_iffreq);
c8832e8f 280
038c6f24 281 ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
884655ad 282 if (ret)
cd559e0b 283 goto err;
884655ad 284
038c6f24 285 ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
cd559e0b
AP		 286 if (ret)
287 goto err;
884655ad 288
cd559e0b
AP		 289 return 0;
290err:
291 dev_dbg(&client->dev, "failed=%d\n", ret);
3ca2418d 292 return ret;
884655ad
MCC		 293}
294
295static int rtl2832_init(struct dvb_frontend *fe)
296{
038c6f24 297 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 298 struct i2c_client *client = dev->client;
19d273d6 299 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
832cc7cd 300 const struct rtl2832_reg_value *init;
884655ad 301 int i, ret, len;
82041c0a
TM		 302 /* initialization values for the demodulator registers */
303 struct rtl2832_reg_value rtl2832_initial_regs[] = {
304 {DVBT_AD_EN_REG, 0x1},
305 {DVBT_AD_EN_REG1, 0x1},
306 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
307 {DVBT_MGD_THD0, 0x10},
308 {DVBT_MGD_THD1, 0x20},
309 {DVBT_MGD_THD2, 0x20},
310 {DVBT_MGD_THD3, 0x40},
311 {DVBT_MGD_THD4, 0x22},
312 {DVBT_MGD_THD5, 0x32},
313 {DVBT_MGD_THD6, 0x37},
314 {DVBT_MGD_THD7, 0x39},
315 {DVBT_EN_BK_TRK, 0x0},
316 {DVBT_EN_CACQ_NOTCH, 0x0},
317 {DVBT_AD_AV_REF, 0x2a},
318 {DVBT_REG_PI, 0x6},
319 {DVBT_PIP_ON, 0x0},
320 {DVBT_CDIV_PH0, 0x8},
321 {DVBT_CDIV_PH1, 0x8},
322 {DVBT_SCALE1_B92, 0x4},
323 {DVBT_SCALE1_B93, 0xb0},
324 {DVBT_SCALE1_BA7, 0x78},
325 {DVBT_SCALE1_BA9, 0x28},
326 {DVBT_SCALE1_BAA, 0x59},
327 {DVBT_SCALE1_BAB, 0x83},
328 {DVBT_SCALE1_BAC, 0xd4},
329 {DVBT_SCALE1_BB0, 0x65},
330 {DVBT_SCALE1_BB1, 0x43},
331 {DVBT_KB_P1, 0x1},
332 {DVBT_KB_P2, 0x4},
333 {DVBT_KB_P3, 0x7},
334 {DVBT_K1_CR_STEP12, 0xa},
335 {DVBT_REG_GPE, 0x1},
336 {DVBT_SERIAL, 0x0},
337 {DVBT_CDIV_PH0, 0x9},
338 {DVBT_CDIV_PH1, 0x9},
339 {DVBT_MPEG_IO_OPT_2_2, 0x0},
340 {DVBT_MPEG_IO_OPT_1_0, 0x0},
341 {DVBT_TRK_KS_P2, 0x4},
342 {DVBT_TRK_KS_I2, 0x7},
343 {DVBT_TR_THD_SET2, 0x6},
344 {DVBT_TRK_KC_I2, 0x5},
345 {DVBT_CR_THD_SET2, 0x1},
82041c0a
TM		 346 };
347
6e6aac65 348 dev_dbg(&client->dev, "\n");
82041c0a 349
82041c0a 350 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
038c6f24 351 ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
82041c0a
TM		 352 rtl2832_initial_regs[i].value);
353 if (ret)
354 goto err;
355 }
356
832cc7cd 357 /* load tuner specific settings */
e1174d78
AP		 358 dev_dbg(&client->dev, "load settings for tuner=%02x\n",
359 dev->pdata->tuner);
360 switch (dev->pdata->tuner) {
832cc7cd
AP		 361 case RTL2832_TUNER_FC0012:
362 case RTL2832_TUNER_FC0013:
363 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
364 init = rtl2832_tuner_init_fc0012;
365 break;
5db4187a
AP		 366 case RTL2832_TUNER_TUA9001:
367 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
368 init = rtl2832_tuner_init_tua9001;
369 break;
7e688de0
AP		 370 case RTL2832_TUNER_E4000:
371 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
372 init = rtl2832_tuner_init_e4000;
373 break;
fa4bfd2b 374 case RTL2832_TUNER_R820T:
a26758ed 375 case RTL2832_TUNER_R828D:
fa4bfd2b
MCC		 376 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
377 init = rtl2832_tuner_init_r820t;
378 break;
699dcffc
OS		 379 case RTL2832_TUNER_SI2157:
380 len = ARRAY_SIZE(rtl2832_tuner_init_si2157);
381 init = rtl2832_tuner_init_si2157;
382 break;
832cc7cd
AP		 383 default:
384 ret = -EINVAL;
385 goto err;
386 }
387
388 for (i = 0; i < len; i++) {
038c6f24 389 ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
832cc7cd
AP		 390 if (ret)
391 goto err;
392 }
393
19d273d6 394 /* init stats here in order signal app which stats are supported */
25ef9f55
AP		 395 c->strength.len = 1;
396 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
19d273d6
AP		 397 c->cnr.len = 1;
398 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6b4fd018
AP		 399 c->post_bit_error.len = 1;
400 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
401 c->post_bit_count.len = 1;
402 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
19d273d6
AP		 403 /* start statistics polling */
404 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
038c6f24 405 dev->sleeping = false;
82041c0a 406
cd559e0b 407 return 0;
82041c0a 408err:
6e6aac65 409 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 410 return ret;
411}
412
413static int rtl2832_sleep(struct dvb_frontend *fe)
414{
038c6f24 415 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 416 struct i2c_client *client = dev->client;
a08c3781 417 int ret;
82041c0a 418
6e6aac65 419 dev_dbg(&client->dev, "\n");
a08c3781 420
038c6f24 421 dev->sleeping = true;
19d273d6
AP		 422 /* stop statistics polling */
423 cancel_delayed_work_sync(&dev->stat_work);
424 dev->fe_status = 0;
a08c3781
AP		 425
426 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
427 if (ret)
428 goto err;
429
82041c0a 430 return 0;
a08c3781
AP		 431err:
432 dev_dbg(&client->dev, "failed=%d\n", ret);
433 return ret;
82041c0a
TM		 434}
435
b0944ea2 436static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
82041c0a
TM		 437 struct dvb_frontend_tune_settings *s)
438{
038c6f24 439 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 440 struct i2c_client *client = dev->client;
298efdd3 441
6e6aac65 442 dev_dbg(&client->dev, "\n");
82041c0a
TM		 443 s->min_delay_ms = 1000;
444 s->step_size = fe->ops.info.frequency_stepsize * 2;
445 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
446 return 0;
447}
448
449static int rtl2832_set_frontend(struct dvb_frontend *fe)
450{
038c6f24 451 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 452 struct i2c_client *client = dev->client;
82041c0a
TM		 453 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
454 int ret, i, j;
455 u64 bw_mode, num, num2;
456 u32 resamp_ratio, cfreq_off_ratio;
82041c0a
TM		 457 static u8 bw_params[3][32] = {
458 /* 6 MHz bandwidth */
459 {
460 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
461 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
462 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
463 0x19, 0xe0,
464 },
465
466 /* 7 MHz bandwidth */
467 {
468 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
469 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
470 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
471 0x19, 0x10,
472 },
473
474 /* 8 MHz bandwidth */
475 {
476 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
477 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
478 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
479 0x19, 0xe0,
480 },
481 };
482
6e6aac65
AP		 483 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
484 c->frequency, c->bandwidth_hz, c->inversion);
82041c0a
TM		 485
486 /* program tuner */
487 if (fe->ops.tuner_ops.set_params)
488 fe->ops.tuner_ops.set_params(fe);
489
fe37b38b 490 /* PIP mode related */
eec21beb 491 ret = rtl2832_bulk_write(client, 0x192, "\x00\x0f\xff", 3);
fe37b38b
AP		 492 if (ret)
493 goto err;
494
fa4bfd2b
MCC		 495 /* If the frontend has get_if_frequency(), use it */
496 if (fe->ops.tuner_ops.get_if_frequency) {
497 u32 if_freq;
fa4bfd2b
MCC		 498
499 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
500 if (ret)
501 goto err;
502
884655ad 503 ret = rtl2832_set_if(fe, if_freq);
fa4bfd2b
MCC		 504 if (ret)
505 goto err;
506 }
507
82041c0a
TM		 508 switch (c->bandwidth_hz) {
509 case 6000000:
510 i = 0;
511 bw_mode = 48000000;
512 break;
513 case 7000000:
514 i = 1;
515 bw_mode = 56000000;
516 break;
517 case 8000000:
518 i = 2;
519 bw_mode = 64000000;
520 break;
521 default:
6e6aac65
AP		 522 dev_err(&client->dev, "invalid bandwidth_hz %u\n",
523 c->bandwidth_hz);
524 ret = -EINVAL;
525 goto err;
82041c0a
TM		 526 }
527
fc4b3fa7 528 for (j = 0; j < sizeof(bw_params[0]); j++) {
eec21beb 529 ret = rtl2832_bulk_write(client, 0x11c + j, &bw_params[i][j], 1);
82041c0a
TM		 530 if (ret)
531 goto err;
532 }
533
534 /* calculate and set resample ratio
535 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
536 * / ConstWithBandwidthMode)
537 */
e1174d78 538 num = dev->pdata->clk * 7;
82041c0a
TM		 539 num *= 0x400000;
540 num = div_u64(num, bw_mode);
541 resamp_ratio = num & 0x3ffffff;
038c6f24 542 ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
82041c0a
TM		 543 if (ret)
544 goto err;
545
546 /* calculate and set cfreq off ratio
547 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
548 * / (CrystalFreqHz * 7))
549 */
550 num = bw_mode << 20;
e1174d78 551 num2 = dev->pdata->clk * 7;
82041c0a
TM		 552 num = div_u64(num, num2);
553 num = -num;
554 cfreq_off_ratio = num & 0xfffff;
038c6f24 555 ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
82041c0a
TM		 556 if (ret)
557 goto err;
558
82041c0a 559 /* soft reset */
038c6f24 560 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
82041c0a
TM		 561 if (ret)
562 goto err;
563
038c6f24 564 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
82041c0a
TM		 565 if (ret)
566 goto err;
567
cd559e0b 568 return 0;
82041c0a 569err:
6e6aac65 570 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 571 return ret;
572}
573
0ce67a2a
AP		 574static int rtl2832_get_frontend(struct dvb_frontend *fe)
575{
038c6f24 576 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 577 struct i2c_client *client = dev->client;
0ce67a2a
AP		 578 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
579 int ret;
580 u8 buf[3];
581
038c6f24 582 if (dev->sleeping)
0ce67a2a
AP		 583 return 0;
584
eec21beb 585 ret = rtl2832_bulk_read(client, 0x33c, buf, 2);
0ce67a2a
AP		 586 if (ret)
587 goto err;
588
eec21beb 589 ret = rtl2832_bulk_read(client, 0x351, &buf[2], 1);
0ce67a2a
AP		 590 if (ret)
591 goto err;
592
6e6aac65 593 dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
0ce67a2a
AP		 594
595 switch ((buf[0] >> 2) & 3) {
596 case 0:
597 c->modulation = QPSK;
598 break;
599 case 1:
600 c->modulation = QAM_16;
601 break;
602 case 2:
603 c->modulation = QAM_64;
604 break;
605 }
606
607 switch ((buf[2] >> 2) & 1) {
608 case 0:
609 c->transmission_mode = TRANSMISSION_MODE_2K;
610 break;
611 case 1:
612 c->transmission_mode = TRANSMISSION_MODE_8K;
613 }
614
615 switch ((buf[2] >> 0) & 3) {
616 case 0:
617 c->guard_interval = GUARD_INTERVAL_1_32;
618 break;
619 case 1:
620 c->guard_interval = GUARD_INTERVAL_1_16;
621 break;
622 case 2:
623 c->guard_interval = GUARD_INTERVAL_1_8;
624 break;
625 case 3:
626 c->guard_interval = GUARD_INTERVAL_1_4;
627 break;
628 }
629
630 switch ((buf[0] >> 4) & 7) {
631 case 0:
632 c->hierarchy = HIERARCHY_NONE;
633 break;
634 case 1:
635 c->hierarchy = HIERARCHY_1;
636 break;
637 case 2:
638 c->hierarchy = HIERARCHY_2;
639 break;
640 case 3:
641 c->hierarchy = HIERARCHY_4;
642 break;
643 }
644
645 switch ((buf[1] >> 3) & 7) {
646 case 0:
647 c->code_rate_HP = FEC_1_2;
648 break;
649 case 1:
650 c->code_rate_HP = FEC_2_3;
651 break;
652 case 2:
653 c->code_rate_HP = FEC_3_4;
654 break;
655 case 3:
656 c->code_rate_HP = FEC_5_6;
657 break;
658 case 4:
659 c->code_rate_HP = FEC_7_8;
660 break;
661 }
662
663 switch ((buf[1] >> 0) & 7) {
664 case 0:
665 c->code_rate_LP = FEC_1_2;
666 break;
667 case 1:
668 c->code_rate_LP = FEC_2_3;
669 break;
670 case 2:
671 c->code_rate_LP = FEC_3_4;
672 break;
673 case 3:
674 c->code_rate_LP = FEC_5_6;
675 break;
676 case 4:
677 c->code_rate_LP = FEC_7_8;
678 break;
679 }
680
681 return 0;
682err:
6e6aac65 683 dev_dbg(&client->dev, "failed=%d\n", ret);
0ce67a2a
AP		 684 return ret;
685}
686
82041c0a
TM		 687static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
688{
038c6f24 689 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 690 struct i2c_client *client = dev->client;
82041c0a 691 int ret;
20357756 692 u32 uninitialized_var(tmp);
82041c0a 693
6e6aac65
AP		 694 dev_dbg(&client->dev, "\n");
695
696 *status = 0;
038c6f24 697 if (dev->sleeping)
82041c0a
TM		 698 return 0;
699
038c6f24 700 ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
82041c0a
TM		 701 if (ret)
702 goto err;
703
704 if (tmp == 11) {
705 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
706 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1c7da405 707 } else if (tmp == 10) {
82041c0a
TM		 708 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
709 FE_HAS_VITERBI;
1c7da405 710 }
82041c0a 711
19d273d6 712 dev->fe_status = *status;
cd559e0b 713 return 0;
82041c0a 714err:
6e6aac65 715 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 716 return ret;
717}
718
73983497
AP		 719static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
720{
f7caf93f 721 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
73983497 722
f7caf93f
AP		 723 /* report SNR in resolution of 0.1 dB */
724 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
725 *snr = div_s64(c->cnr.stat[0].svalue, 100);
73983497
AP		 726 else
727 *snr = 0;
728
729 return 0;
73983497
AP		 730}
731
db32d74a
AP		 732static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
733{
038c6f24 734 struct rtl2832_dev *dev = fe->demodulator_priv;
db32d74a 735
084330b7
AP		 736 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
737 dev->post_bit_error_prev = dev->post_bit_error;
db32d74a
AP		 738
739 return 0;
db32d74a
AP		 740}
741
19d273d6
AP		 742static void rtl2832_stat_work(struct work_struct *work)
743{
744 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, stat_work.work);
745 struct i2c_client *client = dev->client;
746 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
747 int ret, tmp;
748 u8 u8tmp, buf[2];
749 u16 u16tmp;
750
751 dev_dbg(&client->dev, "\n");
752
25ef9f55
AP		 753 /* signal strength */
754 if (dev->fe_status & FE_HAS_SIGNAL) {
755 /* read digital AGC */
756 ret = rtl2832_bulk_read(client, 0x305, &u8tmp, 1);
757 if (ret)
758 goto err;
759
760 dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
761
762 u8tmp = ~u8tmp;
763 u16tmp = u8tmp << 8 | u8tmp << 0;
764
765 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
766 c->strength.stat[0].uvalue = u16tmp;
767 } else {
768 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
769 }
770
19d273d6
AP		 771 /* CNR */
772 if (dev->fe_status & FE_HAS_VITERBI) {
773 unsigned hierarchy, constellation;
774 #define CONSTELLATION_NUM 3
775 #define HIERARCHY_NUM 4
776 static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
777 {85387325, 85387325, 85387325, 85387325},
778 {86676178, 86676178, 87167949, 87795660},
779 {87659938, 87659938, 87885178, 88241743},
780 };
781
782 ret = rtl2832_bulk_read(client, 0x33c, &u8tmp, 1);
783 if (ret)
784 goto err;
785
786 constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
787 if (constellation > CONSTELLATION_NUM - 1)
788 goto err_schedule_delayed_work;
789
790 hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
791 if (hierarchy > HIERARCHY_NUM - 1)
792 goto err_schedule_delayed_work;
793
794 ret = rtl2832_bulk_read(client, 0x40c, buf, 2);
795 if (ret)
796 goto err;
797
798 u16tmp = buf[0] << 8 | buf[1] << 0;
799 if (u16tmp)
800 tmp = (constant[constellation][hierarchy] -
801 intlog10(u16tmp)) / ((1 << 24) / 10000);
802 else
803 tmp = 0;
804
805 dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
806
807 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
808 c->cnr.stat[0].svalue = tmp;
809 } else {
810 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
811 }
812
6b4fd018
AP		 813 /* BER */
814 if (dev->fe_status & FE_HAS_LOCK) {
815 ret = rtl2832_bulk_read(client, 0x34e, buf, 2);
816 if (ret)
817 goto err;
818
819 u16tmp = buf[0] << 8 | buf[1] << 0;
820 dev->post_bit_error += u16tmp;
821 dev->post_bit_count += 1000000;
822
823 dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
824
825 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
826 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
827 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
828 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
829 } else {
830 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
831 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
832 }
833
19d273d6
AP		 834err_schedule_delayed_work:
835 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
836 return;
837err:
838 dev_dbg(&client->dev, "failed=%d\n", ret);
839}
840
92d20d9f 841/*
d1016581
AP		 842 * I2C gate/mux/repeater logic
843 * We must use unlocked __i2c_transfer() here (through regmap) because of I2C
844 * adapter lock is already taken by tuner driver.
845 * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
846 * is delayed here a little bit in order to see if there is sequence of I2C
92d20d9f 847 * messages sent to same I2C bus.
92d20d9f
AP		 848 */
849static void rtl2832_i2c_gate_work(struct work_struct *work)
850{
d1016581 851 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
6e6aac65 852 struct i2c_client *client = dev->client;
92d20d9f 853 int ret;
6e6aac65 854
d1016581
AP		 855 /* close gate */
856 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
857 if (ret)
92d20d9f
AP		 858 goto err;
859
92d20d9f
AP		 860 return;
861err:
6e6aac65 862 dev_dbg(&client->dev, "failed=%d\n", ret);
92d20d9f
AP		 863}
864
0ea872d4 865static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
8823f028 866{
038c6f24 867 struct rtl2832_dev *dev = mux_priv;
6e6aac65 868 struct i2c_client *client = dev->client;
0ea872d4 869 int ret;
92d20d9f
AP		 870
871 /* terminate possible gate closing */
d1016581 872 cancel_delayed_work(&dev->i2c_gate_work);
8823f028 873
d1016581 874 /*
d1016581
AP		 875 * I2C adapter lock is already taken and due to that we will use
876 * regmap_update_bits() which does not lock again I2C adapter.
877 */
0d117901 878 ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
d1016581 879 if (ret)
0ea872d4
AP		 880 goto err;
881
0ea872d4
AP		 882 return 0;
883err:
6e6aac65 884 dev_dbg(&client->dev, "failed=%d\n", ret);
d1016581 885 return ret;
8823f028
AP		 886}
887
92d20d9f 888static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
d1016581 889 u32 chan_id)
92d20d9f 890{
038c6f24 891 struct rtl2832_dev *dev = mux_priv;
6e6aac65 892
038c6f24 893 schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
92d20d9f
AP		 894 return 0;
895}
896
82041c0a
TM		 897static struct dvb_frontend_ops rtl2832_ops = {
898 .delsys = { SYS_DVBT },
899 .info = {
900 .name = "Realtek RTL2832 (DVB-T)",
901 .frequency_min = 174000000,
902 .frequency_max = 862000000,
903 .frequency_stepsize = 166667,
904 .caps = FE_CAN_FEC_1_2 |
905 FE_CAN_FEC_2_3 |
906 FE_CAN_FEC_3_4 |
907 FE_CAN_FEC_5_6 |
908 FE_CAN_FEC_7_8 |
909 FE_CAN_FEC_AUTO |
910 FE_CAN_QPSK |
911 FE_CAN_QAM_16 |
912 FE_CAN_QAM_64 |
913 FE_CAN_QAM_AUTO |
914 FE_CAN_TRANSMISSION_MODE_AUTO |
915 FE_CAN_GUARD_INTERVAL_AUTO |
916 FE_CAN_HIERARCHY_AUTO |
917 FE_CAN_RECOVER |
918 FE_CAN_MUTE_TS
919 },
920
82041c0a
TM		 921 .init = rtl2832_init,
922 .sleep = rtl2832_sleep,
923
924 .get_tune_settings = rtl2832_get_tune_settings,
925
926 .set_frontend = rtl2832_set_frontend,
0ce67a2a 927 .get_frontend = rtl2832_get_frontend,
82041c0a
TM		 928
929 .read_status = rtl2832_read_status,
73983497 930 .read_snr = rtl2832_read_snr,
db32d74a 931 .read_ber = rtl2832_read_ber,
82041c0a
TM		 932};
933
dcadb82a
AP		 934static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg)
935{
936 switch (reg) {
937 case 0x305:
938 case 0x33c:
939 case 0x34e:
940 case 0x351:
941 case 0x40c ... 0x40d:
942 return true;
943 default:
944 break;
945 }
946
947 return false;
948}
949
d1016581
AP		 950/*
951 * We implement own I2C access routines for regmap in order to get manual access
952 * to I2C adapter lock, which is needed for I2C mux adapter.
953 */
954static int rtl2832_regmap_read(void *context, const void *reg_buf,
955 size_t reg_size, void *val_buf, size_t val_size)
956{
957 struct i2c_client *client = context;
958 int ret;
959 struct i2c_msg msg[2] = {
960 {
961 .addr = client->addr,
962 .flags = 0,
963 .len = reg_size,
964 .buf = (u8 *)reg_buf,
965 }, {
966 .addr = client->addr,
967 .flags = I2C_M_RD,
968 .len = val_size,
969 .buf = val_buf,
970 }
971 };
972
973 ret = __i2c_transfer(client->adapter, msg, 2);
974 if (ret != 2) {
975 dev_warn(&client->dev, "i2c reg read failed %d\n", ret);
976 if (ret >= 0)
977 ret = -EREMOTEIO;
978 return ret;
979 }
980 return 0;
981}
982
983static int rtl2832_regmap_write(void *context, const void *data, size_t count)
984{
985 struct i2c_client *client = context;
986 int ret;
987 struct i2c_msg msg[1] = {
988 {
989 .addr = client->addr,
990 .flags = 0,
991 .len = count,
992 .buf = (u8 *)data,
993 }
994 };
995
996 ret = __i2c_transfer(client->adapter, msg, 1);
997 if (ret != 1) {
998 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
999 if (ret >= 0)
1000 ret = -EREMOTEIO;
1001 return ret;
1002 }
1003 return 0;
1004}
1005
1006static int rtl2832_regmap_gather_write(void *context, const void *reg,
1007 size_t reg_len, const void *val,
1008 size_t val_len)
1009{
1010 struct i2c_client *client = context;
1011 int ret;
1012 u8 buf[256];
1013 struct i2c_msg msg[1] = {
1014 {
1015 .addr = client->addr,
1016 .flags = 0,
1017 .len = 1 + val_len,
1018 .buf = buf,
1019 }
1020 };
1021
1022 buf[0] = *(u8 const *)reg;
1023 memcpy(&buf[1], val, val_len);
1024
1025 ret = __i2c_transfer(client->adapter, msg, 1);
1026 if (ret != 1) {
1027 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1028 if (ret >= 0)
1029 ret = -EREMOTEIO;
1030 return ret;
1031 }
1032 return 0;
1033}
1034
b410dae4
AP		 1035/*
1036 * FIXME: Hack. Implement own regmap locking in order to silence lockdep
1037 * recursive lock warning. That happens when regmap I2C client calls I2C mux
1038 * adapter, which leads demod I2C repeater enable via demod regmap. Operation
1039 * takes two regmap locks recursively - but those are different regmap instances
1040 * in a two different I2C drivers, so it is not deadlock. Proper fix is to make
1041 * regmap aware of lockdep.
1042 */
1043static void rtl2832_regmap_lock(void *__dev)
1044{
1045 struct rtl2832_dev *dev = __dev;
1046 struct i2c_client *client = dev->client;
1047
1048 dev_dbg(&client->dev, "\n");
1049 mutex_lock(&dev->regmap_mutex);
1050}
1051
1052static void rtl2832_regmap_unlock(void *__dev)
1053{
1054 struct rtl2832_dev *dev = __dev;
1055 struct i2c_client *client = dev->client;
1056
1057 dev_dbg(&client->dev, "\n");
1058 mutex_unlock(&dev->regmap_mutex);
1059}
1060
6f5f6ee2
AP		 1061static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
1062{
038c6f24 1063 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1064
1065 dev_dbg(&client->dev, "\n");
1066 return &dev->fe;
1067}
1068
cd559e0b 1069static struct i2c_adapter *rtl2832_get_i2c_adapter(struct i2c_client *client)
6f5f6ee2 1070{
038c6f24 1071 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1072
1073 dev_dbg(&client->dev, "\n");
1074 return dev->i2c_adapter_tuner;
1075}
1076
6f5f6ee2
AP		 1077static int rtl2832_enable_slave_ts(struct i2c_client *client)
1078{
038c6f24 1079 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1080 int ret;
1081
6e6aac65 1082 dev_dbg(&client->dev, "\n");
6f5f6ee2 1083
eec21beb 1084 ret = rtl2832_bulk_write(client, 0x10c, "\x5f\xff", 2);
6f5f6ee2
AP		 1085 if (ret)
1086 goto err;
1087
1088 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
1089 if (ret)
1090 goto err;
1091
eec21beb 1092 ret = rtl2832_bulk_write(client, 0x0bc, "\x18", 1);
6f5f6ee2
AP		 1093 if (ret)
1094 goto err;
1095
eec21beb 1096 ret = rtl2832_bulk_write(client, 0x022, "\x01", 1);
6f5f6ee2
AP		 1097 if (ret)
1098 goto err;
1099
eec21beb 1100 ret = rtl2832_bulk_write(client, 0x026, "\x1f", 1);
6f5f6ee2
AP		 1101 if (ret)
1102 goto err;
1103
eec21beb 1104 ret = rtl2832_bulk_write(client, 0x027, "\xff", 1);
6f5f6ee2
AP		 1105 if (ret)
1106 goto err;
1107
eec21beb 1108 ret = rtl2832_bulk_write(client, 0x192, "\x7f\xf7\xff", 3);
6f5f6ee2
AP		 1109 if (ret)
1110 goto err;
1111
1112 /* soft reset */
1113 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
1114 if (ret)
1115 goto err;
1116
1117 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
1118 if (ret)
1119 goto err;
1120
1121 return 0;
1122err:
1123 dev_dbg(&client->dev, "failed=%d\n", ret);
1124 return ret;
1125}
1126
4b01e01a
AP		 1127static int rtl2832_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
1128{
1129 struct rtl2832_dev *dev = fe->demodulator_priv;
1130 struct i2c_client *client = dev->client;
1131 int ret;
1132 u8 u8tmp;
1133
1134 dev_dbg(&client->dev, "onoff=%d\n", onoff);
1135
1136 /* enable / disable PID filter */
1137 if (onoff)
1138 u8tmp = 0x80;
1139 else
1140 u8tmp = 0x00;
1141
1142 ret = rtl2832_update_bits(client, 0x061, 0xc0, u8tmp);
1143 if (ret)
1144 goto err;
1145
1146 return 0;
1147err:
1148 dev_dbg(&client->dev, "failed=%d\n", ret);
1149 return ret;
1150}
1151
1152static int rtl2832_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
1153 int onoff)
1154{
1155 struct rtl2832_dev *dev = fe->demodulator_priv;
1156 struct i2c_client *client = dev->client;
1157 int ret;
1158 u8 buf[4];
1159
1160 dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
1161 index, pid, onoff);
1162
1163 /* skip invalid PIDs (0x2000) */
1164 if (pid > 0x1fff || index > 32)
1165 return 0;
1166
1167 if (onoff)
1168 set_bit(index, &dev->filters);
1169 else
1170 clear_bit(index, &dev->filters);
1171
1172 /* enable / disable PIDs */
1173 buf[0] = (dev->filters >> 0) & 0xff;
1174 buf[1] = (dev->filters >> 8) & 0xff;
1175 buf[2] = (dev->filters >> 16) & 0xff;
1176 buf[3] = (dev->filters >> 24) & 0xff;
1177 ret = rtl2832_bulk_write(client, 0x062, buf, 4);
1178 if (ret)
1179 goto err;
1180
1181 /* add PID */
1182 buf[0] = (pid >> 8) & 0xff;
1183 buf[1] = (pid >> 0) & 0xff;
1184 ret = rtl2832_bulk_write(client, 0x066 + 2 * index, buf, 2);
1185 if (ret)
1186 goto err;
1187
1188 return 0;
1189err:
1190 dev_dbg(&client->dev, "failed=%d\n", ret);
1191 return ret;
1192}
1193
c2c8386f
AP		 1194static int rtl2832_probe(struct i2c_client *client,
1195 const struct i2c_device_id *id)
1196{
1197 struct rtl2832_platform_data *pdata = client->dev.platform_data;
c2c8386f 1198 struct i2c_adapter *i2c = client->adapter;
038c6f24 1199 struct rtl2832_dev *dev;
c2c8386f
AP		 1200 int ret;
1201 u8 tmp;
d1016581
AP		 1202 static const struct regmap_bus regmap_bus = {
1203 .read = rtl2832_regmap_read,
1204 .write = rtl2832_regmap_write,
1205 .gather_write = rtl2832_regmap_gather_write,
1206 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1207 };
1208 static const struct regmap_range_cfg regmap_range_cfg[] = {
1209 {
1210 .selector_reg = 0x00,
1211 .selector_mask = 0xff,
1212 .selector_shift = 0,
1213 .window_start = 0,
1214 .window_len = 0x100,
1215 .range_min = 0 * 0x100,
1216 .range_max = 5 * 0x100,
1217 },
1218 };
c2c8386f
AP		 1219
1220 dev_dbg(&client->dev, "\n");
1221
c2c8386f 1222 /* allocate memory for the internal state */
038c6f24
AP		 1223 dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1224 if (dev == NULL) {
c2c8386f
AP		 1225 ret = -ENOMEM;
1226 goto err;
1227 }
1228
038c6f24 1229 /* setup the state */
d1016581 1230 i2c_set_clientdata(client, dev);
038c6f24 1231 dev->client = client;
e1174d78 1232 dev->pdata = client->dev.platform_data;
038c6f24 1233 dev->sleeping = true;
038c6f24 1234 INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
19d273d6 1235 INIT_DELAYED_WORK(&dev->stat_work, rtl2832_stat_work);
d1016581 1236 /* create regmap */
b410dae4
AP		 1237 mutex_init(&dev->regmap_mutex);
1238 dev->regmap_config.reg_bits = 8,
1239 dev->regmap_config.val_bits = 8,
1240 dev->regmap_config.lock = rtl2832_regmap_lock,
1241 dev->regmap_config.unlock = rtl2832_regmap_unlock,
1242 dev->regmap_config.lock_arg = dev,
1243 dev->regmap_config.volatile_reg = rtl2832_volatile_reg,
1244 dev->regmap_config.max_register = 5 * 0x100,
1245 dev->regmap_config.ranges = regmap_range_cfg,
1246 dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg),
b3b2bf82 1247 dev->regmap_config.cache_type = REGCACHE_NONE,
d1016581 1248 dev->regmap = regmap_init(&client->dev, &regmap_bus, client,
b410dae4 1249 &dev->regmap_config);
d1016581
AP		 1250 if (IS_ERR(dev->regmap)) {
1251 ret = PTR_ERR(dev->regmap);
1252 goto err_kfree;
1253 }
c2c8386f
AP		 1254
1255 /* check if the demod is there */
eec21beb 1256 ret = rtl2832_bulk_read(client, 0x000, &tmp, 1);
c2c8386f 1257 if (ret)
0d117901 1258 goto err_regmap_exit;
c2c8386f
AP		 1259
1260 /* create muxed i2c adapter for demod tuner bus */
038c6f24 1261 dev->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, dev,
0d117901 1262 0, 0, 0, rtl2832_select, rtl2832_deselect);
038c6f24 1263 if (dev->i2c_adapter_tuner == NULL) {
c2c8386f 1264 ret = -ENODEV;
0d117901 1265 goto err_regmap_exit;
c2c8386f
AP		 1266 }
1267
1268 /* create dvb_frontend */
038c6f24
AP		 1269 memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1270 dev->fe.demodulator_priv = dev;
6f5f6ee2
AP		 1271
1272 /* setup callbacks */
1273 pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
cd559e0b 1274 pdata->get_i2c_adapter = rtl2832_get_i2c_adapter;
6f5f6ee2 1275 pdata->enable_slave_ts = rtl2832_enable_slave_ts;
4b01e01a
AP		 1276 pdata->pid_filter = rtl2832_pid_filter;
1277 pdata->pid_filter_ctrl = rtl2832_pid_filter_ctrl;
0aa32ef9
AP		 1278 pdata->bulk_read = rtl2832_bulk_read;
1279 pdata->bulk_write = rtl2832_bulk_write;
1280 pdata->update_bits = rtl2832_update_bits;
c2c8386f
AP		 1281
1282 dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1283 return 0;
d1016581
AP		 1284err_regmap_exit:
1285 regmap_exit(dev->regmap);
c2c8386f 1286err_kfree:
038c6f24 1287 kfree(dev);
c2c8386f
AP		 1288err:
1289 dev_dbg(&client->dev, "failed=%d\n", ret);
1290 return ret;
1291}
1292
1293static int rtl2832_remove(struct i2c_client *client)
1294{
038c6f24 1295 struct rtl2832_dev *dev = i2c_get_clientdata(client);
c2c8386f
AP		 1296
1297 dev_dbg(&client->dev, "\n");
1298
038c6f24 1299 cancel_delayed_work_sync(&dev->i2c_gate_work);
c2c8386f 1300
038c6f24 1301 i2c_del_mux_adapter(dev->i2c_adapter_tuner);
c2c8386f 1302
d1016581
AP		 1303 regmap_exit(dev->regmap);
1304
038c6f24 1305 kfree(dev);
c2c8386f
AP		 1306
1307 return 0;
1308}
1309
1310static const struct i2c_device_id rtl2832_id_table[] = {
1311 {"rtl2832", 0},
1312 {}
1313};
1314MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1315
1316static struct i2c_driver rtl2832_driver = {
1317 .driver = {
1318 .owner = THIS_MODULE,
1319 .name = "rtl2832",
1320 },
1321 .probe = rtl2832_probe,
1322 .remove = rtl2832_remove,
1323 .id_table = rtl2832_id_table,
1324};
1325
1326module_i2c_driver(rtl2832_driver);
1327
82041c0a 1328MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
75c24005 1329MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
82041c0a
TM		 1330MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1331MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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