[deliverable/linux.git] / drivers / media / dvb-frontends / s5h1432.c

/*
 *  Samsung s5h1432 DVB-T demodulator driver
 *
 *  Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include "dvb_frontend.h"
#include "s5h1432.h"

struct s5h1432_state {

	struct i2c_adapter *i2c;

	/* configuration settings */
	const struct s5h1432_config *config;

	struct dvb_frontend frontend;

	enum fe_modulation current_modulation;
	unsigned int first_tune:1;

	u32 current_frequency;
	int if_freq;

	u8 inversion;
};

static int debug;

#define dprintk(arg...) do {	\
	if (debug)		\
		printk(arg);	\
	} while (0)

static int s5h1432_writereg(struct s5h1432_state *state,
			    u8 addr, u8 reg, u8 data)
{
	int ret;
	u8 buf[] = { reg, data };

	struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 };

	ret = i2c_transfer(state->i2c, &msg, 1);

	if (ret != 1)
		printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, "
		       "ret == %i)\n", __func__, addr, reg, data, ret);

	return (ret != 1) ? -1 : 0;
}

static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
{
	int ret;
	u8 b0[] = { reg };
	u8 b1[] = { 0 };

	struct i2c_msg msg[] = {
		{.addr = addr, .flags = 0, .buf = b0, .len = 1},
		{.addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1}
	};

	ret = i2c_transfer(state->i2c, msg, 2);

	if (ret != 2)
		printk(KERN_ERR "%s: readreg error (ret == %i)\n",
		       __func__, ret);
	return b1[0];
}

static int s5h1432_sleep(struct dvb_frontend *fe)
{
	return 0;
}

static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe,
					 u32 bandwidth)
{
	struct s5h1432_state *state = fe->demodulator_priv;

	u8 reg = 0;

	/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */
	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
	reg &= ~(0x0C);
	switch (bandwidth) {
	case 6:
		reg |= 0x08;
		break;
	case 7:
		reg |= 0x04;
		break;
	case 8:
		reg |= 0x00;
		break;
	default:
		return 0;
	}
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
	return 1;
}

static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
{
	struct s5h1432_state *state = fe->demodulator_priv;

	switch (ifFreqHz) {
	case TAIWAN_HI_IF_FREQ_44_MHZ:
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);
		break;
	case EUROPE_HI_IF_FREQ_36_MHZ:
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);
		break;
	case IF_FREQ_6_MHZ:
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);
		break;
	case IF_FREQ_3point3_MHZ:
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
		break;
	case IF_FREQ_3point5_MHZ:
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);
		break;
	case IF_FREQ_4_MHZ:
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);
		break;
	default:
		{
			u32 value = 0;
			value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
					(u32) 32768) / (48 * 1000));
			printk(KERN_INFO
			       "Default IFFreq %d :reg value = 0x%x\n",
			       ifFreqHz, value);
			s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
					 (u8) value & 0xFF);
			s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,
					 (u8) (value >> 8) & 0xFF);
			s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,
					 (u8) (value >> 16) & 0xFF);
			break;
		}

	}

	return 1;
}

/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
static int s5h1432_set_frontend(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
	u32 dvb_bandwidth = 8;
	struct s5h1432_state *state = fe->demodulator_priv;

	if (p->frequency == state->current_frequency) {
		/*current_frequency = p->frequency; */
		/*state->current_frequency = p->frequency; */
	} else {
		fe->ops.tuner_ops.set_params(fe);
		msleep(300);
		s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
		switch (p->bandwidth_hz) {
		case 6000000:
			dvb_bandwidth = 6;
			s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
			break;
		case 7000000:
			dvb_bandwidth = 7;
			s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
			break;
		case 8000000:
			dvb_bandwidth = 8;
			s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
			break;
		default:
			return 0;
		}
		/*fe->ops.tuner_ops.set_params(fe); */
/*Soft Reset chip*/
		msleep(30);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
		msleep(30);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);

		s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
		switch (p->bandwidth_hz) {
		case 6000000:
			dvb_bandwidth = 6;
			s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
			break;
		case 7000000:
			dvb_bandwidth = 7;
			s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
			break;
		case 8000000:
			dvb_bandwidth = 8;
			s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
			break;
		default:
			return 0;
		}
		/*fe->ops.tuner_ops.set_params(fe); */
		/*Soft Reset chip*/
		msleep(30);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
		msleep(30);
		s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);

	}

	state->current_frequency = p->frequency;

	return 0;
}

static int s5h1432_init(struct dvb_frontend *fe)
{
	struct s5h1432_state *state = fe->demodulator_priv;

	u8 reg = 0;
	state->current_frequency = 0;
	printk(KERN_INFO " s5h1432_init().\n");

	/*Set VSB mode as default, this also does a soft reset */
	/*Initialize registers */

	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
	/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);

	/*For NXP tuner*/

	/*Set 3.3MHz as default IF frequency */
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
	/* Set reg 0x1E to get the full dynamic range */
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);

	/* Mode setting in demod */
	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
	reg |= 0x80;
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
	/* Serial mode */

	/* Soft Reset chip */

	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
	msleep(30);
	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);


	return 0;
}

static int s5h1432_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
	return 0;
}

static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
					u16 *signal_strength)
{
	return 0;
}

static int s5h1432_read_snr(struct dvb_frontend *fe, u16 *snr)
{
	return 0;
}

static int s5h1432_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{

	return 0;
}

static int s5h1432_read_ber(struct dvb_frontend *fe, u32 *ber)
{
	return 0;
}

static int s5h1432_get_tune_settings(struct dvb_frontend *fe,
				     struct dvb_frontend_tune_settings *tune)
{
	return 0;
}

static void s5h1432_release(struct dvb_frontend *fe)
{
	struct s5h1432_state *state = fe->demodulator_priv;
	kfree(state);
}

static struct dvb_frontend_ops s5h1432_ops;

struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
				    struct i2c_adapter *i2c)
{
	struct s5h1432_state *state = NULL;

	printk(KERN_INFO " Enter s5h1432_attach(). attach success!\n");
	/* allocate memory for the internal state */
	state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
	if (!state)
		return NULL;

	/* setup the state */
	state->config = config;
	state->i2c = i2c;
	state->current_modulation = QAM_16;
	state->inversion = state->config->inversion;

	/* create dvb_frontend */
	memcpy(&state->frontend.ops, &s5h1432_ops,
	       sizeof(struct dvb_frontend_ops));

	state->frontend.demodulator_priv = state;

	return &state->frontend;
}
EXPORT_SYMBOL(s5h1432_attach);

static struct dvb_frontend_ops s5h1432_ops = {
	.delsys = { SYS_DVBT },
	.info = {
		 .name = "Samsung s5h1432 DVB-T Frontend",
		 .frequency_min = 177000000,
		 .frequency_max = 858000000,
		 .frequency_stepsize = 166666,
		 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
		 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
		 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
		 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
		 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER},

	.init = s5h1432_init,
	.sleep = s5h1432_sleep,
	.set_frontend = s5h1432_set_frontend,
	.get_tune_settings = s5h1432_get_tune_settings,
	.read_status = s5h1432_read_status,
	.read_ber = s5h1432_read_ber,
	.read_signal_strength = s5h1432_read_signal_strength,
	.read_snr = s5h1432_read_snr,
	.read_ucblocks = s5h1432_read_ucblocks,
	.release = s5h1432_release,
};

module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Enable verbose debug messages");

MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver");
MODULE_AUTHOR("Bill Liu");
MODULE_LICENSE("GPL");
Commit	Line	Data
47b75ec1	1	/*
955e6ed8 MCC	2	* Samsung s5h1432 DVB-T demodulator driver
	3	*
	4	* Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
47b75ec1 PB	20
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
	23	#include <linux/module.h>
	24	#include <linux/string.h>
	25	#include <linux/slab.h>
	26	#include <linux/delay.h>
	27	#include "dvb_frontend.h"
	28	#include "s5h1432.h"
	29
	30	struct s5h1432_state {
	31
	32	struct i2c_adapter *i2c;
	33
	34	/* configuration settings */
	35	const struct s5h1432_config *config;
	36
	37	struct dvb_frontend frontend;
	38
0df289a2	39	enum fe_modulation current_modulation;
47b75ec1 PB	40	unsigned int first_tune:1;
	41
	42	u32 current_frequency;
	43	int if_freq;
	44
	45	u8 inversion;
	46	};
	47
	48	static int debug;
	49
	50	#define dprintk(arg...) do { \
	51	if (debug) \
	52	printk(arg); \
	53	} while (0)
	54
47b75ec1	55	static int s5h1432_writereg(struct s5h1432_state *state,
bda7f4ee	56	u8 addr, u8 reg, u8 data)
47b75ec1 PB	57	{
	58	int ret;
	59	u8 buf[] = { reg, data };
	60
bda7f4ee	61	struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 };
47b75ec1 PB	62
	63	ret = i2c_transfer(state->i2c, &msg, 1);
	64
	65	if (ret != 1)
	66	printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, "
	67	"ret == %i)\n", __func__, addr, reg, data, ret);
	68
	69	return (ret != 1) ? -1 : 0;
	70	}
	71
	72	static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
	73	{
	74	int ret;
	75	u8 b0[] = { reg };
	76	u8 b1[] = { 0 };
	77
	78	struct i2c_msg msg[] = {
bda7f4ee DH	79	{.addr = addr, .flags = 0, .buf = b0, .len = 1},
	80	{.addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1}
	81	};
47b75ec1 PB	82
	83	ret = i2c_transfer(state->i2c, msg, 2);
	84
	85	if (ret != 2)
	86	printk(KERN_ERR "%s: readreg error (ret == %i)\n",
bda7f4ee	87	__func__, ret);
47b75ec1 PB	88	return b1[0];
	89	}
	90
	91	static int s5h1432_sleep(struct dvb_frontend *fe)
	92	{
	93	return 0;
	94	}
	95
bda7f4ee DH	96	static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe,
bda7f4ee DH	97	u32 bandwidth)
47b75ec1	98	{
47b75ec1 PB	99	struct s5h1432_state *state = fe->demodulator_priv;
	100
	101	u8 reg = 0;
	102
bda7f4ee	103	/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */
47b75ec1 PB	104	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
	105	reg &= ~(0x0C);
	106	switch (bandwidth) {
	107	case 6:
	108	reg \|= 0x08;
	109	break;
	110	case 7:
	111	reg \|= 0x04;
	112	break;
	113	case 8:
	114	reg \|= 0x00;
	115	break;
	116	default:
bda7f4ee	117	return 0;
47b75ec1 PB	118	}
47b75ec1 PB	119	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
bda7f4ee	120	return 1;
47b75ec1 PB	121	}
	122
	123	static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
	124	{
47b75ec1 PB	125	struct s5h1432_state *state = fe->demodulator_priv;
	126
	127	switch (ifFreqHz) {
	128	case TAIWAN_HI_IF_FREQ_44_MHZ:
bda7f4ee DH	129	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
	130	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
	131	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);
	132	break;
47b75ec1	133	case EUROPE_HI_IF_FREQ_36_MHZ:
bda7f4ee DH	134	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
	135	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
	136	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);
	137	break;
47b75ec1	138	case IF_FREQ_6_MHZ:
bda7f4ee DH	139	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
	140	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
	141	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);
	142	break;
47b75ec1	143	case IF_FREQ_3point3_MHZ:
bda7f4ee DH	144	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
	145	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
	146	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
	147	break;
47b75ec1	148	case IF_FREQ_3point5_MHZ:
bda7f4ee DH	149	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
	150	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
	151	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);
	152	break;
47b75ec1	153	case IF_FREQ_4_MHZ:
bda7f4ee DH	154	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);
	155	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);
	156	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);
	157	break;
47b75ec1 PB	158	default:
47b75ec1 PB	159	{
bda7f4ee DH	160	u32 value = 0;
	161	value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
	162	(u32) 32768) / (48 * 1000));
	163	printk(KERN_INFO
955e6ed8	164	"Default IFFreq %d :reg value = 0x%x\n",
bda7f4ee DH	165	ifFreqHz, value);
	166	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
	167	(u8) value & 0xFF);
	168	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,
	169	(u8) (value >> 8) & 0xFF);
	170	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,
	171	(u8) (value >> 16) & 0xFF);
	172	break;
	173	}
47b75ec1 PB	174
	175	}
	176
bda7f4ee	177	return 1;
47b75ec1 PB	178	}
	179
	180	/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
6bfc3667	181	static int s5h1432_set_frontend(struct dvb_frontend *fe)
47b75ec1	182	{
6bfc3667	183	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
47b75ec1 PB	184	u32 dvb_bandwidth = 8;
	185	struct s5h1432_state *state = fe->demodulator_priv;
	186
	187	if (p->frequency == state->current_frequency) {
bda7f4ee DH	188	/current_frequency = p->frequency; /
bda7f4ee DH	189	/state->current_frequency = p->frequency; /
47b75ec1	190	} else {
14d24d14	191	fe->ops.tuner_ops.set_params(fe);
bda7f4ee	192	msleep(300);
47b75ec1	193	s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
6bfc3667 MCC	194	switch (p->bandwidth_hz) {
6bfc3667 MCC	195	case 6000000:
bda7f4ee DH	196	dvb_bandwidth = 6;
	197	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
	198	break;
6bfc3667	199	case 7000000:
bda7f4ee DH	200	dvb_bandwidth = 7;
	201	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
	202	break;
6bfc3667	203	case 8000000:
bda7f4ee DH	204	dvb_bandwidth = 8;
	205	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
	206	break;
47b75ec1	207	default:
bda7f4ee DH	208	return 0;
bda7f4ee DH	209	}
14d24d14	210	/fe->ops.tuner_ops.set_params(fe); /
47b75ec1	211	/Soft Reset chip/
bda7f4ee DH	212	msleep(30);
	213	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
	214	msleep(30);
	215	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
47b75ec1 PB	216
47b75ec1 PB	217	s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
6bfc3667 MCC	218	switch (p->bandwidth_hz) {
6bfc3667 MCC	219	case 6000000:
bda7f4ee DH	220	dvb_bandwidth = 6;
	221	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
	222	break;
6bfc3667	223	case 7000000:
bda7f4ee DH	224	dvb_bandwidth = 7;
	225	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
	226	break;
6bfc3667	227	case 8000000:
bda7f4ee DH	228	dvb_bandwidth = 8;
	229	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
	230	break;
47b75ec1	231	default:
bda7f4ee DH	232	return 0;
bda7f4ee DH	233	}
14d24d14	234	/fe->ops.tuner_ops.set_params(fe); /
bda7f4ee DH	235	/Soft Reset chip/
	236	msleep(30);
	237	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
	238	msleep(30);
	239	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
47b75ec1 PB	240
	241	}
	242
	243	state->current_frequency = p->frequency;
	244
	245	return 0;
	246	}
	247
47b75ec1 PB	248	static int s5h1432_init(struct dvb_frontend *fe)
	249	{
	250	struct s5h1432_state *state = fe->demodulator_priv;
	251
	252	u8 reg = 0;
	253	state->current_frequency = 0;
	254	printk(KERN_INFO " s5h1432_init().\n");
	255
bda7f4ee DH	256	/Set VSB mode as default, this also does a soft reset /
	257	/Initialize registers /
	258
	259	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
	260	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
	261	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
	262	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
	263	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
	264	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
	265	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
	266	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
	267	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
	268	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
	269	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
	270	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
	271	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
	272	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
	273	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
	274	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
	275	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
	276	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
	277	/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */
	278	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
	279
	280	/For NXP tuner/
	281
	282	/Set 3.3MHz as default IF frequency /
	283	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
	284	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
	285	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
	286	/* Set reg 0x1E to get the full dynamic range */
	287	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
	288
	289	/* Mode setting in demod */
47b75ec1 PB	290	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
	291	reg \|= 0x80;
	292	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
bda7f4ee	293	/* Serial mode */
47b75ec1	294
bda7f4ee	295	/* Soft Reset chip */
47b75ec1	296
bda7f4ee	297	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
47b75ec1	298	msleep(30);
bda7f4ee	299	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
47b75ec1 PB	300
	301
	302	return 0;
	303	}
	304
0df289a2	305	static int s5h1432_read_status(struct dvb_frontend fe, enum fe_status status)
47b75ec1 PB	306	{
	307	return 0;
	308	}
	309
47b75ec1	310	static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
bda7f4ee	311	u16 *signal_strength)
47b75ec1 PB	312	{
	313	return 0;
	314	}
	315
	316	static int s5h1432_read_snr(struct dvb_frontend fe, u16 snr)
	317	{
	318	return 0;
	319	}
	320
	321	static int s5h1432_read_ucblocks(struct dvb_frontend fe, u32 ucblocks)
	322	{
	323
	324	return 0;
	325	}
	326
	327	static int s5h1432_read_ber(struct dvb_frontend fe, u32 ber)
	328	{
	329	return 0;
	330	}
	331
47b75ec1 PB	332	static int s5h1432_get_tune_settings(struct dvb_frontend *fe,
	333	struct dvb_frontend_tune_settings *tune)
	334	{
	335	return 0;
	336	}
	337
	338	static void s5h1432_release(struct dvb_frontend *fe)
	339	{
	340	struct s5h1432_state *state = fe->demodulator_priv;
	341	kfree(state);
	342	}
	343
	344	static struct dvb_frontend_ops s5h1432_ops;
	345
	346	struct dvb_frontend s5h1432_attach(const struct s5h1432_config config,
	347	struct i2c_adapter *i2c)
	348	{
	349	struct s5h1432_state *state = NULL;
	350
	351	printk(KERN_INFO " Enter s5h1432_attach(). attach success!\n");
	352	/* allocate memory for the internal state */
	353	state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
47aab4ab PST	354	if (!state)
47aab4ab PST	355	return NULL;
47b75ec1 PB	356
	357	/* setup the state */
	358	state->config = config;
	359	state->i2c = i2c;
	360	state->current_modulation = QAM_16;
	361	state->inversion = state->config->inversion;
	362
	363	/* create dvb_frontend */
	364	memcpy(&state->frontend.ops, &s5h1432_ops,
	365	sizeof(struct dvb_frontend_ops));
	366
	367	state->frontend.demodulator_priv = state;
	368
	369	return &state->frontend;
47b75ec1 PB	370	}
	371	EXPORT_SYMBOL(s5h1432_attach);
	372
	373	static struct dvb_frontend_ops s5h1432_ops = {
533b673b	374	.delsys = { SYS_DVBT },
47b75ec1	375	.info = {
bda7f4ee	376	.name = "Samsung s5h1432 DVB-T Frontend",
bda7f4ee DH	377	.frequency_min = 177000000,
	378	.frequency_max = 858000000,
	379	.frequency_stepsize = 166666,
	380	.caps = FE_CAN_FEC_1_2 \| FE_CAN_FEC_2_3 \| FE_CAN_FEC_3_4 \|
	381	FE_CAN_FEC_5_6 \| FE_CAN_FEC_7_8 \| FE_CAN_FEC_AUTO \|
	382	FE_CAN_QPSK \| FE_CAN_QAM_16 \| FE_CAN_QAM_64 \| FE_CAN_QAM_AUTO \|
	383	FE_CAN_HIERARCHY_AUTO \| FE_CAN_GUARD_INTERVAL_AUTO \|
	384	FE_CAN_TRANSMISSION_MODE_AUTO \| FE_CAN_RECOVER},
	385
	386	.init = s5h1432_init,
	387	.sleep = s5h1432_sleep,
6bfc3667	388	.set_frontend = s5h1432_set_frontend,
bda7f4ee DH	389	.get_tune_settings = s5h1432_get_tune_settings,
	390	.read_status = s5h1432_read_status,
	391	.read_ber = s5h1432_read_ber,
47b75ec1	392	.read_signal_strength = s5h1432_read_signal_strength,
bda7f4ee DH	393	.read_snr = s5h1432_read_snr,
	394	.read_ucblocks = s5h1432_read_ucblocks,
	395	.release = s5h1432_release,
47b75ec1 PB	396	};
	397
	398	module_param(debug, int, 0644);
	399	MODULE_PARM_DESC(debug, "Enable verbose debug messages");
	400
	401	MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver");
	402	MODULE_AUTHOR("Bill Liu");
	403	MODULE_LICENSE("GPL");