Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | Driver for VES1893 and VES1993 QPSK Demodulators | |
3 | ||
4 | Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de> | |
5 | Copyright (C) 2001 Ronny Strutz <3des@elitedvb.de> | |
6 | Copyright (C) 2002 Dennis Noermann <dennis.noermann@noernet.de> | |
7 | Copyright (C) 2002-2003 Andreas Oberritter <obi@linuxtv.org> | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ||
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software | |
22 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | ||
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/delay.h> | |
32 | ||
33 | #include "dvb_frontend.h" | |
34 | #include "ves1x93.h" | |
35 | ||
36 | ||
37 | struct ves1x93_state { | |
38 | struct i2c_adapter* i2c; | |
1da177e4 LT |
39 | /* configuration settings */ |
40 | const struct ves1x93_config* config; | |
41 | struct dvb_frontend frontend; | |
42 | ||
43 | /* previous uncorrected block counter */ | |
0df289a2 | 44 | enum fe_spectral_inversion inversion; |
1da177e4 LT |
45 | u8 *init_1x93_tab; |
46 | u8 *init_1x93_wtab; | |
47 | u8 tab_size; | |
48 | u8 demod_type; | |
dba2b0c8 | 49 | u32 frequency; |
1da177e4 LT |
50 | }; |
51 | ||
ff699e6b | 52 | static int debug; |
1da177e4 LT |
53 | #define dprintk if (debug) printk |
54 | ||
55 | #define DEMOD_VES1893 0 | |
56 | #define DEMOD_VES1993 1 | |
57 | ||
58 | static u8 init_1893_tab [] = { | |
59 | 0x01, 0xa4, 0x35, 0x80, 0x2a, 0x0b, 0x55, 0xc4, | |
60 | 0x09, 0x69, 0x00, 0x86, 0x4c, 0x28, 0x7f, 0x00, | |
61 | 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
62 | 0x80, 0x00, 0x21, 0xb0, 0x14, 0x00, 0xdc, 0x00, | |
63 | 0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
64 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
65 | 0x00, 0x55, 0x00, 0x00, 0x7f, 0x00 | |
66 | }; | |
67 | ||
68 | static u8 init_1993_tab [] = { | |
69 | 0x00, 0x9c, 0x35, 0x80, 0x6a, 0x09, 0x72, 0x8c, | |
70 | 0x09, 0x6b, 0x00, 0x00, 0x4c, 0x08, 0x00, 0x00, | |
71 | 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
72 | 0x80, 0x40, 0x21, 0xb0, 0x00, 0x00, 0x00, 0x10, | |
73 | 0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
74 | 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, | |
75 | 0x00, 0x55, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, | |
76 | 0x00, 0x00, 0x0e, 0x80, 0x00 | |
77 | }; | |
78 | ||
79 | static u8 init_1893_wtab[] = | |
80 | { | |
81 | 1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0, | |
82 | 0,1,0,0,0,0,0,0, 1,0,1,1,0,0,0,1, | |
83 | 1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0, | |
84 | 1,1,1,0,1,1 | |
85 | }; | |
86 | ||
87 | static u8 init_1993_wtab[] = | |
88 | { | |
89 | 1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0, | |
90 | 0,1,0,0,0,0,0,0, 1,1,1,1,0,0,0,1, | |
91 | 1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0, | |
92 | 1,1,1,0,1,1,1,1, 1,1,1,1,1 | |
93 | }; | |
94 | ||
95 | static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data) | |
96 | { | |
97 | u8 buf [] = { 0x00, reg, data }; | |
98 | struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 3 }; | |
99 | int err; | |
100 | ||
101 | if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { | |
271ddbf7 | 102 | dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data); |
1da177e4 LT |
103 | return -EREMOTEIO; |
104 | } | |
105 | ||
106 | return 0; | |
107 | } | |
108 | ||
109 | static u8 ves1x93_readreg (struct ves1x93_state* state, u8 reg) | |
110 | { | |
111 | int ret; | |
112 | u8 b0 [] = { 0x00, reg }; | |
113 | u8 b1 [] = { 0 }; | |
114 | struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 }, | |
115 | { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; | |
116 | ||
117 | ret = i2c_transfer (state->i2c, msg, 2); | |
118 | ||
119 | if (ret != 2) return ret; | |
120 | ||
121 | return b1[0]; | |
122 | } | |
123 | ||
124 | static int ves1x93_clr_bit (struct ves1x93_state* state) | |
125 | { | |
126 | msleep(10); | |
127 | ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe); | |
128 | ves1x93_writereg (state, 0, state->init_1x93_tab[0]); | |
129 | msleep(50); | |
130 | return 0; | |
131 | } | |
132 | ||
0df289a2 MCC |
133 | static int ves1x93_set_inversion(struct ves1x93_state *state, |
134 | enum fe_spectral_inversion inversion) | |
1da177e4 LT |
135 | { |
136 | u8 val; | |
137 | ||
138 | /* | |
139 | * inversion on/off are interchanged because i and q seem to | |
140 | * be swapped on the hardware | |
141 | */ | |
142 | ||
143 | switch (inversion) { | |
144 | case INVERSION_OFF: | |
145 | val = 0xc0; | |
146 | break; | |
147 | case INVERSION_ON: | |
148 | val = 0x80; | |
149 | break; | |
150 | case INVERSION_AUTO: | |
151 | val = 0x00; | |
152 | break; | |
153 | default: | |
154 | return -EINVAL; | |
155 | } | |
156 | ||
157 | return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val); | |
158 | } | |
159 | ||
0df289a2 | 160 | static int ves1x93_set_fec(struct ves1x93_state *state, enum fe_code_rate fec) |
1da177e4 LT |
161 | { |
162 | if (fec == FEC_AUTO) | |
163 | return ves1x93_writereg (state, 0x0d, 0x08); | |
164 | else if (fec < FEC_1_2 || fec > FEC_8_9) | |
165 | return -EINVAL; | |
166 | else | |
167 | return ves1x93_writereg (state, 0x0d, fec - FEC_1_2); | |
168 | } | |
169 | ||
0df289a2 | 170 | static enum fe_code_rate ves1x93_get_fec(struct ves1x93_state *state) |
1da177e4 LT |
171 | { |
172 | return FEC_1_2 + ((ves1x93_readreg (state, 0x0d) >> 4) & 0x7); | |
173 | } | |
174 | ||
175 | static int ves1x93_set_symbolrate (struct ves1x93_state* state, u32 srate) | |
176 | { | |
177 | u32 BDR; | |
178 | u32 ratio; | |
179 | u8 ADCONF, FCONF, FNR, AGCR; | |
180 | u32 BDRI; | |
181 | u32 tmp; | |
182 | u32 FIN; | |
183 | ||
271ddbf7 | 184 | dprintk("%s: srate == %d\n", __func__, (unsigned int) srate); |
1da177e4 LT |
185 | |
186 | if (srate > state->config->xin/2) | |
187 | srate = state->config->xin/2; | |
188 | ||
189 | if (srate < 500000) | |
190 | srate = 500000; | |
191 | ||
192 | #define MUL (1UL<<26) | |
193 | ||
194 | FIN = (state->config->xin + 6000) >> 4; | |
195 | ||
196 | tmp = srate << 6; | |
197 | ratio = tmp / FIN; | |
198 | ||
199 | tmp = (tmp % FIN) << 8; | |
200 | ratio = (ratio << 8) + tmp / FIN; | |
201 | ||
202 | tmp = (tmp % FIN) << 8; | |
203 | ratio = (ratio << 8) + tmp / FIN; | |
204 | ||
205 | FNR = 0xff; | |
206 | ||
207 | if (ratio < MUL/3) FNR = 0; | |
208 | if (ratio < (MUL*11)/50) FNR = 1; | |
209 | if (ratio < MUL/6) FNR = 2; | |
210 | if (ratio < MUL/9) FNR = 3; | |
211 | if (ratio < MUL/12) FNR = 4; | |
212 | if (ratio < (MUL*11)/200) FNR = 5; | |
213 | if (ratio < MUL/24) FNR = 6; | |
214 | if (ratio < (MUL*27)/1000) FNR = 7; | |
215 | if (ratio < MUL/48) FNR = 8; | |
216 | if (ratio < (MUL*137)/10000) FNR = 9; | |
217 | ||
218 | if (FNR == 0xff) { | |
219 | ADCONF = 0x89; | |
220 | FCONF = 0x80; | |
221 | FNR = 0; | |
222 | } else { | |
223 | ADCONF = 0x81; | |
224 | FCONF = 0x88 | (FNR >> 1) | ((FNR & 0x01) << 5); | |
225 | /*FCONF = 0x80 | ((FNR & 0x01) << 5) | (((FNR > 1) & 0x03) << 3) | ((FNR >> 1) & 0x07);*/ | |
226 | } | |
227 | ||
228 | BDR = (( (ratio << (FNR >> 1)) >> 4) + 1) >> 1; | |
229 | BDRI = ( ((FIN << 8) / ((srate << (FNR >> 1)) >> 2)) + 1) >> 1; | |
230 | ||
231 | dprintk("FNR= %d\n", FNR); | |
232 | dprintk("ratio= %08x\n", (unsigned int) ratio); | |
233 | dprintk("BDR= %08x\n", (unsigned int) BDR); | |
234 | dprintk("BDRI= %02x\n", (unsigned int) BDRI); | |
235 | ||
236 | if (BDRI > 0xff) | |
237 | BDRI = 0xff; | |
238 | ||
239 | ves1x93_writereg (state, 0x06, 0xff & BDR); | |
240 | ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8)); | |
241 | ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16)); | |
242 | ||
243 | ves1x93_writereg (state, 0x09, BDRI); | |
244 | ves1x93_writereg (state, 0x20, ADCONF); | |
245 | ves1x93_writereg (state, 0x21, FCONF); | |
246 | ||
247 | AGCR = state->init_1x93_tab[0x05]; | |
248 | if (state->config->invert_pwm) | |
249 | AGCR |= 0x20; | |
250 | ||
251 | if (srate < 6000000) | |
252 | AGCR |= 0x80; | |
253 | else | |
254 | AGCR &= ~0x80; | |
255 | ||
256 | ves1x93_writereg (state, 0x05, AGCR); | |
257 | ||
258 | /* ves1993 hates this, will lose lock */ | |
259 | if (state->demod_type != DEMOD_VES1993) | |
260 | ves1x93_clr_bit (state); | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static int ves1x93_init (struct dvb_frontend* fe) | |
266 | { | |
b8742700 | 267 | struct ves1x93_state* state = fe->demodulator_priv; |
1da177e4 LT |
268 | int i; |
269 | int val; | |
270 | ||
271ddbf7 | 271 | dprintk("%s: init chip\n", __func__); |
1da177e4 LT |
272 | |
273 | for (i = 0; i < state->tab_size; i++) { | |
274 | if (state->init_1x93_wtab[i]) { | |
275 | val = state->init_1x93_tab[i]; | |
276 | ||
277 | if (state->config->invert_pwm && (i == 0x05)) val |= 0x20; /* invert PWM */ | |
278 | ves1x93_writereg (state, i, val); | |
279 | } | |
280 | } | |
281 | ||
1da177e4 LT |
282 | return 0; |
283 | } | |
284 | ||
0df289a2 MCC |
285 | static int ves1x93_set_voltage(struct dvb_frontend *fe, |
286 | enum fe_sec_voltage voltage) | |
1da177e4 | 287 | { |
b8742700 | 288 | struct ves1x93_state* state = fe->demodulator_priv; |
1da177e4 LT |
289 | |
290 | switch (voltage) { | |
291 | case SEC_VOLTAGE_13: | |
292 | return ves1x93_writereg (state, 0x1f, 0x20); | |
293 | case SEC_VOLTAGE_18: | |
294 | return ves1x93_writereg (state, 0x1f, 0x30); | |
295 | case SEC_VOLTAGE_OFF: | |
296 | return ves1x93_writereg (state, 0x1f, 0x00); | |
297 | default: | |
298 | return -EINVAL; | |
299 | } | |
300 | } | |
301 | ||
0df289a2 MCC |
302 | static int ves1x93_read_status(struct dvb_frontend *fe, |
303 | enum fe_status *status) | |
1da177e4 | 304 | { |
b8742700 | 305 | struct ves1x93_state* state = fe->demodulator_priv; |
1da177e4 LT |
306 | |
307 | u8 sync = ves1x93_readreg (state, 0x0e); | |
308 | ||
309 | /* | |
310 | * The ves1893 sometimes returns sync values that make no sense, | |
311 | * because, e.g., the SIGNAL bit is 0, while some of the higher | |
312 | * bits are 1 (and how can there be a CARRIER w/o a SIGNAL?). | |
59c51591 | 313 | * Tests showed that the VITERBI and SYNC bits are returned |
1da177e4 LT |
314 | * reliably, while the SIGNAL and CARRIER bits ar sometimes wrong. |
315 | * If such a case occurs, we read the value again, until we get a | |
316 | * valid value. | |
317 | */ | |
318 | int maxtry = 10; /* just for safety - let's not get stuck here */ | |
319 | while ((sync & 0x03) != 0x03 && (sync & 0x0c) && maxtry--) { | |
320 | msleep(10); | |
321 | sync = ves1x93_readreg (state, 0x0e); | |
322 | } | |
323 | ||
324 | *status = 0; | |
325 | ||
326 | if (sync & 1) | |
327 | *status |= FE_HAS_SIGNAL; | |
328 | ||
329 | if (sync & 2) | |
330 | *status |= FE_HAS_CARRIER; | |
331 | ||
332 | if (sync & 4) | |
333 | *status |= FE_HAS_VITERBI; | |
334 | ||
335 | if (sync & 8) | |
336 | *status |= FE_HAS_SYNC; | |
337 | ||
338 | if ((sync & 0x1f) == 0x1f) | |
339 | *status |= FE_HAS_LOCK; | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
344 | static int ves1x93_read_ber(struct dvb_frontend* fe, u32* ber) | |
345 | { | |
b8742700 | 346 | struct ves1x93_state* state = fe->demodulator_priv; |
1da177e4 LT |
347 | |
348 | *ber = ves1x93_readreg (state, 0x15); | |
349 | *ber |= (ves1x93_readreg (state, 0x16) << 8); | |
350 | *ber |= ((ves1x93_readreg (state, 0x17) & 0x0F) << 16); | |
351 | *ber *= 10; | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
356 | static int ves1x93_read_signal_strength(struct dvb_frontend* fe, u16* strength) | |
357 | { | |
b8742700 | 358 | struct ves1x93_state* state = fe->demodulator_priv; |
1da177e4 LT |
359 | |
360 | u8 signal = ~ves1x93_readreg (state, 0x0b); | |
361 | *strength = (signal << 8) | signal; | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | static int ves1x93_read_snr(struct dvb_frontend* fe, u16* snr) | |
367 | { | |
b8742700 | 368 | struct ves1x93_state* state = fe->demodulator_priv; |
1da177e4 LT |
369 | |
370 | u8 _snr = ~ves1x93_readreg (state, 0x1c); | |
371 | *snr = (_snr << 8) | _snr; | |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
376 | static int ves1x93_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) | |
377 | { | |
b8742700 | 378 | struct ves1x93_state* state = fe->demodulator_priv; |
1da177e4 LT |
379 | |
380 | *ucblocks = ves1x93_readreg (state, 0x18) & 0x7f; | |
381 | ||
382 | if (*ucblocks == 0x7f) | |
383 | *ucblocks = 0xffffffff; /* counter overflow... */ | |
384 | ||
385 | ves1x93_writereg (state, 0x18, 0x00); /* reset the counter */ | |
386 | ves1x93_writereg (state, 0x18, 0x80); /* dto. */ | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
dba2b0c8 | 391 | static int ves1x93_set_frontend(struct dvb_frontend *fe) |
1da177e4 | 392 | { |
dba2b0c8 | 393 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
b8742700 | 394 | struct ves1x93_state* state = fe->demodulator_priv; |
1da177e4 | 395 | |
dea74869 | 396 | if (fe->ops.tuner_ops.set_params) { |
14d24d14 | 397 | fe->ops.tuner_ops.set_params(fe); |
dea74869 | 398 | if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); |
66292ebe | 399 | } |
1da177e4 | 400 | ves1x93_set_inversion (state, p->inversion); |
dba2b0c8 MCC |
401 | ves1x93_set_fec(state, p->fec_inner); |
402 | ves1x93_set_symbolrate(state, p->symbol_rate); | |
1da177e4 | 403 | state->inversion = p->inversion; |
dba2b0c8 | 404 | state->frequency = p->frequency; |
1da177e4 LT |
405 | |
406 | return 0; | |
407 | } | |
408 | ||
7e3e68bc MCC |
409 | static int ves1x93_get_frontend(struct dvb_frontend *fe, |
410 | struct dtv_frontend_properties *p) | |
1da177e4 | 411 | { |
b8742700 | 412 | struct ves1x93_state* state = fe->demodulator_priv; |
1da177e4 LT |
413 | int afc; |
414 | ||
415 | afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2; | |
dba2b0c8 | 416 | afc = (afc * (int)(p->symbol_rate/1000/8))/16; |
1da177e4 | 417 | |
dba2b0c8 | 418 | p->frequency = state->frequency - afc; |
1da177e4 LT |
419 | |
420 | /* | |
421 | * inversion indicator is only valid | |
422 | * if auto inversion was used | |
423 | */ | |
424 | if (state->inversion == INVERSION_AUTO) | |
425 | p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ? | |
426 | INVERSION_OFF : INVERSION_ON; | |
dba2b0c8 | 427 | p->fec_inner = ves1x93_get_fec(state); |
1da177e4 LT |
428 | /* XXX FIXME: timing offset !! */ |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
433 | static int ves1x93_sleep(struct dvb_frontend* fe) | |
434 | { | |
b8742700 | 435 | struct ves1x93_state* state = fe->demodulator_priv; |
1da177e4 LT |
436 | |
437 | return ves1x93_writereg (state, 0x00, 0x08); | |
438 | } | |
439 | ||
440 | static void ves1x93_release(struct dvb_frontend* fe) | |
441 | { | |
b8742700 | 442 | struct ves1x93_state* state = fe->demodulator_priv; |
1da177e4 LT |
443 | kfree(state); |
444 | } | |
445 | ||
66292ebe AQ |
446 | static int ves1x93_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) |
447 | { | |
448 | struct ves1x93_state* state = fe->demodulator_priv; | |
449 | ||
450 | if (enable) { | |
451 | return ves1x93_writereg(state, 0x00, 0x11); | |
452 | } else { | |
453 | return ves1x93_writereg(state, 0x00, 0x01); | |
454 | } | |
455 | } | |
456 | ||
1da177e4 LT |
457 | static struct dvb_frontend_ops ves1x93_ops; |
458 | ||
459 | struct dvb_frontend* ves1x93_attach(const struct ves1x93_config* config, | |
460 | struct i2c_adapter* i2c) | |
461 | { | |
462 | struct ves1x93_state* state = NULL; | |
463 | u8 identity; | |
464 | ||
465 | /* allocate memory for the internal state */ | |
084e24ac | 466 | state = kzalloc(sizeof(struct ves1x93_state), GFP_KERNEL); |
1da177e4 LT |
467 | if (state == NULL) goto error; |
468 | ||
469 | /* setup the state */ | |
470 | state->config = config; | |
471 | state->i2c = i2c; | |
1da177e4 LT |
472 | state->inversion = INVERSION_OFF; |
473 | ||
474 | /* check if the demod is there + identify it */ | |
475 | identity = ves1x93_readreg(state, 0x1e); | |
476 | switch (identity) { | |
477 | case 0xdc: /* VES1893A rev1 */ | |
478 | printk("ves1x93: Detected ves1893a rev1\n"); | |
479 | state->demod_type = DEMOD_VES1893; | |
480 | state->init_1x93_tab = init_1893_tab; | |
481 | state->init_1x93_wtab = init_1893_wtab; | |
482 | state->tab_size = sizeof(init_1893_tab); | |
483 | break; | |
484 | ||
485 | case 0xdd: /* VES1893A rev2 */ | |
486 | printk("ves1x93: Detected ves1893a rev2\n"); | |
487 | state->demod_type = DEMOD_VES1893; | |
488 | state->init_1x93_tab = init_1893_tab; | |
489 | state->init_1x93_wtab = init_1893_wtab; | |
490 | state->tab_size = sizeof(init_1893_tab); | |
491 | break; | |
492 | ||
493 | case 0xde: /* VES1993 */ | |
494 | printk("ves1x93: Detected ves1993\n"); | |
495 | state->demod_type = DEMOD_VES1993; | |
496 | state->init_1x93_tab = init_1993_tab; | |
497 | state->init_1x93_wtab = init_1993_wtab; | |
498 | state->tab_size = sizeof(init_1993_tab); | |
499 | break; | |
500 | ||
501 | default: | |
502 | goto error; | |
503 | } | |
504 | ||
505 | /* create dvb_frontend */ | |
dea74869 | 506 | memcpy(&state->frontend.ops, &ves1x93_ops, sizeof(struct dvb_frontend_ops)); |
1da177e4 LT |
507 | state->frontend.demodulator_priv = state; |
508 | return &state->frontend; | |
509 | ||
510 | error: | |
511 | kfree(state); | |
512 | return NULL; | |
513 | } | |
514 | ||
515 | static struct dvb_frontend_ops ves1x93_ops = { | |
dba2b0c8 | 516 | .delsys = { SYS_DVBS }, |
1da177e4 LT |
517 | .info = { |
518 | .name = "VLSI VES1x93 DVB-S", | |
1da177e4 LT |
519 | .frequency_min = 950000, |
520 | .frequency_max = 2150000, | |
521 | .frequency_stepsize = 125, /* kHz for QPSK frontends */ | |
522 | .frequency_tolerance = 29500, | |
523 | .symbol_rate_min = 1000000, | |
524 | .symbol_rate_max = 45000000, | |
525 | /* .symbol_rate_tolerance = ???,*/ | |
526 | .caps = FE_CAN_INVERSION_AUTO | | |
527 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
528 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
529 | FE_CAN_QPSK | |
530 | }, | |
531 | ||
532 | .release = ves1x93_release, | |
533 | ||
534 | .init = ves1x93_init, | |
535 | .sleep = ves1x93_sleep, | |
66292ebe | 536 | .i2c_gate_ctrl = ves1x93_i2c_gate_ctrl, |
1da177e4 | 537 | |
dba2b0c8 MCC |
538 | .set_frontend = ves1x93_set_frontend, |
539 | .get_frontend = ves1x93_get_frontend, | |
1da177e4 LT |
540 | |
541 | .read_status = ves1x93_read_status, | |
542 | .read_ber = ves1x93_read_ber, | |
543 | .read_signal_strength = ves1x93_read_signal_strength, | |
544 | .read_snr = ves1x93_read_snr, | |
545 | .read_ucblocks = ves1x93_read_ucblocks, | |
546 | ||
547 | .set_voltage = ves1x93_set_voltage, | |
548 | }; | |
549 | ||
550 | module_param(debug, int, 0644); | |
551 | ||
552 | MODULE_DESCRIPTION("VLSI VES1x93 DVB-S Demodulator driver"); | |
553 | MODULE_AUTHOR("Ralph Metzler"); | |
554 | MODULE_LICENSE("GPL"); | |
555 | ||
556 | EXPORT_SYMBOL(ves1x93_attach); |