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[media] ad9389b/adv7604/ths8200: use new v4l2_print_dv_timings helper
[deliverable/linux.git] / drivers / media / i2c / ad9389b.c
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117a55b6
HV		 1/*
2 * Analog Devices AD9389B/AD9889B video encoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 */
19
20/*
21 * References (c = chapter, p = page):
22 * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
23 * HDMI Transitter, Rev. A, October 2010
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/slab.h>
29#include <linux/i2c.h>
30#include <linux/delay.h>
31#include <linux/videodev2.h>
32#include <linux/workqueue.h>
33#include <linux/v4l2-dv-timings.h>
34#include <media/v4l2-device.h>
117a55b6 35#include <media/v4l2-common.h>
25764158 36#include <media/v4l2-dv-timings.h>
117a55b6
HV		 37#include <media/v4l2-ctrls.h>
38#include <media/ad9389b.h>
39
40static int debug;
41module_param(debug, int, 0644);
42MODULE_PARM_DESC(debug, "debug level (0-2)");
43
44MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
45MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
46MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
47MODULE_LICENSE("GPL");
48
49#define MASK_AD9389B_EDID_RDY_INT 0x04
50#define MASK_AD9389B_MSEN_INT 0x40
51#define MASK_AD9389B_HPD_INT 0x80
52
53#define MASK_AD9389B_HPD_DETECT 0x40
54#define MASK_AD9389B_MSEN_DETECT 0x20
55#define MASK_AD9389B_EDID_RDY 0x10
56
57#define EDID_MAX_RETRIES (8)
58#define EDID_DELAY 250
59#define EDID_MAX_SEGM 8
60
61/*
62**********************************************************************
63*
64* Arrays with configuration parameters for the AD9389B
65*
66**********************************************************************
67*/
68
69struct i2c_reg_value {
70 u8 reg;
71 u8 value;
72};
73
74struct ad9389b_state_edid {
75 /* total number of blocks */
76 u32 blocks;
77 /* Number of segments read */
78 u32 segments;
79 u8 data[EDID_MAX_SEGM * 256];
80 /* Number of EDID read retries left */
81 unsigned read_retries;
82};
83
84struct ad9389b_state {
85 struct ad9389b_platform_data pdata;
86 struct v4l2_subdev sd;
87 struct media_pad pad;
88 struct v4l2_ctrl_handler hdl;
89 int chip_revision;
90 /* Is the ad9389b powered on? */
91 bool power_on;
92 /* Did we receive hotplug and rx-sense signals? */
93 bool have_monitor;
94 /* timings from s_dv_timings */
95 struct v4l2_dv_timings dv_timings;
96 /* controls */
97 struct v4l2_ctrl *hdmi_mode_ctrl;
98 struct v4l2_ctrl *hotplug_ctrl;
99 struct v4l2_ctrl *rx_sense_ctrl;
100 struct v4l2_ctrl *have_edid0_ctrl;
101 struct v4l2_ctrl *rgb_quantization_range_ctrl;
102 struct i2c_client *edid_i2c_client;
103 struct ad9389b_state_edid edid;
104 /* Running counter of the number of detected EDIDs (for debugging) */
105 unsigned edid_detect_counter;
106 struct workqueue_struct *work_queue;
107 struct delayed_work edid_handler; /* work entry */
108};
109
110static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
111static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
112static void ad9389b_setup(struct v4l2_subdev *sd);
113static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
114static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
115
116static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
117{
118 return container_of(sd, struct ad9389b_state, sd);
119}
120
121static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
122{
123 return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
124}
125
126/* ------------------------ I2C ----------------------------------------------- */
127
128static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
129{
130 struct i2c_client *client = v4l2_get_subdevdata(sd);
131
132 return i2c_smbus_read_byte_data(client, reg);
133}
134
135static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
136{
137 struct i2c_client *client = v4l2_get_subdevdata(sd);
138 int ret;
139 int i;
140
141 for (i = 0; i < 3; i++) {
142 ret = i2c_smbus_write_byte_data(client, reg, val);
143 if (ret == 0)
144 return 0;
145 }
146 v4l2_err(sd, "I2C Write Problem\n");
147 return ret;
148}
149
150/* To set specific bits in the register, a clear-mask is given (to be AND-ed),
151 and then the value-mask (to be OR-ed). */
152static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
153 u8 clr_mask, u8 val_mask)
154{
155 ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
156}
157
158static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
159{
160 struct ad9389b_state *state = get_ad9389b_state(sd);
161 int i;
162
163 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
164
165 for (i = 0; i < len; i++)
166 buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
167}
168
169static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
170{
171 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
172}
173
174static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
175{
176 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
177}
178
179static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
180{
181 ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
182 ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
183}
184
185static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
186 u16 A1, u16 A2, u16 A3, u16 A4,
187 u16 B1, u16 B2, u16 B3, u16 B4,
188 u16 C1, u16 C2, u16 C3, u16 C4)
189{
190 /* A */
191 ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
192 ad9389b_wr(sd, 0x19, A1);
193 ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
194 ad9389b_wr(sd, 0x1B, A2);
195 ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
196 ad9389b_wr(sd, 0x1d, A3);
197 ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
198 ad9389b_wr(sd, 0x1f, A4);
199
200 /* B */
201 ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
202 ad9389b_wr(sd, 0x21, B1);
203 ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
204 ad9389b_wr(sd, 0x23, B2);
205 ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
206 ad9389b_wr(sd, 0x25, B3);
207 ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
208 ad9389b_wr(sd, 0x27, B4);
209
210 /* C */
211 ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
212 ad9389b_wr(sd, 0x29, C1);
213 ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
214 ad9389b_wr(sd, 0x2B, C2);
215 ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
216 ad9389b_wr(sd, 0x2D, C3);
217 ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
218 ad9389b_wr(sd, 0x2F, C4);
219}
220
221static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
222{
223 if (enable) {
224 u8 csc_mode = 0;
225
226 ad9389b_csc_conversion_mode(sd, csc_mode);
227 ad9389b_csc_coeff(sd,
228 4096-564, 0, 0, 256,
229 0, 4096-564, 0, 256,
230 0, 0, 4096-564, 256);
231 /* enable CSC */
232 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
233 /* AVI infoframe: Limited range RGB (16-235) */
234 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
235 } else {
236 /* disable CSC */
237 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
238 /* AVI infoframe: Full range RGB (0-255) */
239 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
240 }
241}
242
243static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
244{
245 struct ad9389b_state *state = get_ad9389b_state(sd);
246
247 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
248 /* CEA format, not IT */
249 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
250 } else {
251 /* IT format */
252 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
253 }
254}
255
256static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
257{
258 struct ad9389b_state *state = get_ad9389b_state(sd);
259
260 switch (ctrl->val) {
261 case V4L2_DV_RGB_RANGE_AUTO:
262 /* automatic */
263 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
264 /* cea format, RGB limited range (16-235) */
265 ad9389b_csc_rgb_full2limit(sd, true);
266 } else {
267 /* not cea format, RGB full range (0-255) */
268 ad9389b_csc_rgb_full2limit(sd, false);
269 }
270 break;
271 case V4L2_DV_RGB_RANGE_LIMITED:
272 /* RGB limited range (16-235) */
273 ad9389b_csc_rgb_full2limit(sd, true);
274 break;
275 case V4L2_DV_RGB_RANGE_FULL:
276 /* RGB full range (0-255) */
277 ad9389b_csc_rgb_full2limit(sd, false);
278 break;
279 default:
280 return -EINVAL;
281 }
282 return 0;
283}
284
285static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
286{
287 u8 gear;
288
289 /* Workaround for TMDS PLL problem
290 * The TMDS PLL in AD9389b change gear when the chip is heated above a
291 * certain temperature. The output is disabled when the PLL change gear
292 * so the monitor has to lock on the signal again. A workaround for
293 * this is to use the manual PLL gears. This is a solution from Analog
294 * Devices that is not documented in the datasheets.
295 * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
296 *
297 * The pixel frequency ranges are based on readout of the gear the
298 * automatic gearing selects for different pixel clocks
299 * (read from 0x9e [3:1]).
300 */
301
302 if (pixelclock > 140000000)
303 gear = 0xc0; /* 4th gear */
304 else if (pixelclock > 117000000)
305 gear = 0xb0; /* 3rd gear */
306 else if (pixelclock > 87000000)
307 gear = 0xa0; /* 2nd gear */
308 else if (pixelclock > 60000000)
309 gear = 0x90; /* 1st gear */
310 else
311 gear = 0x80; /* 0th gear */
312
313 ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
314}
315
316/* ------------------------------ CTRL OPS ------------------------------ */
317
318static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
319{
320 struct v4l2_subdev *sd = to_sd(ctrl);
321 struct ad9389b_state *state = get_ad9389b_state(sd);
322
323 v4l2_dbg(1, debug, sd,
324 "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
325
326 if (state->hdmi_mode_ctrl == ctrl) {
327 /* Set HDMI or DVI-D */
328 ad9389b_wr_and_or(sd, 0xaf, 0xfd,
329 ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
330 return 0;
331 }
332 if (state->rgb_quantization_range_ctrl == ctrl)
333 return ad9389b_set_rgb_quantization_mode(sd, ctrl);
334 return -EINVAL;
335}
336
337static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
338 .s_ctrl = ad9389b_s_ctrl,
339};
340
341/* ---------------------------- CORE OPS ------------------------------------------- */
342
343#ifdef CONFIG_VIDEO_ADV_DEBUG
344static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
345{
117a55b6
HV		 346 reg->val = ad9389b_rd(sd, reg->reg & 0xff);
347 reg->size = 1;
348 return 0;
349}
350
977ba3b1 351static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
117a55b6 352{
117a55b6
HV		 353 ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
354 return 0;
355}
356#endif
357
117a55b6
HV		 358static int ad9389b_log_status(struct v4l2_subdev *sd)
359{
360 struct ad9389b_state *state = get_ad9389b_state(sd);
361 struct ad9389b_state_edid *edid = &state->edid;
362
363 static const char * const states[] = {
364 "in reset",
365 "reading EDID",
366 "idle",
367 "initializing HDCP",
368 "HDCP enabled",
369 "initializing HDCP repeater",
370 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
371 };
372 static const char * const errors[] = {
373 "no error",
374 "bad receiver BKSV",
375 "Ri mismatch",
376 "Pj mismatch",
377 "i2c error",
378 "timed out",
379 "max repeater cascade exceeded",
380 "hash check failed",
381 "too many devices",
382 "9", "A", "B", "C", "D", "E", "F"
383 };
384
385 u8 manual_gear;
386
387 v4l2_info(sd, "chip revision %d\n", state->chip_revision);
388 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
389 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
390 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
391 "detected" : "no",
392 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
393 "detected" : "no",
394 edid->segments ? "found" : "no", edid->blocks);
395 if (state->have_monitor) {
396 v4l2_info(sd, "%s output %s\n",
397 (ad9389b_rd(sd, 0xaf) & 0x02) ?
398 "HDMI" : "DVI-D",
399 (ad9389b_rd(sd, 0xa1) & 0x3c) ?
400 "disabled" : "enabled");
401 }
402 v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
403 "encrypted" : "no encryption");
404 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
405 states[ad9389b_rd(sd, 0xc8) & 0xf],
406 errors[ad9389b_rd(sd, 0xc8) >> 4],
407 state->edid_detect_counter,
408 ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
409 manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
410 v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
411 ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
412 v4l2_info(sd, "ad9389b: %s gear %d\n",
413 manual_gear ? "manual" : "automatic",
414 manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
415 ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
416 if (state->have_monitor) {
417 if (ad9389b_rd(sd, 0xaf) & 0x02) {
418 /* HDMI only */
419 u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
420 u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
421 ad9389b_rd(sd, 0x02) << 8 |
422 ad9389b_rd(sd, 0x03);
423 u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
424 u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
425 u32 CTS;
426
427 if (manual_cts)
428 CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
429 ad9389b_rd(sd, 0x08) << 8 |
430 ad9389b_rd(sd, 0x09);
431 else
432 CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
433 ad9389b_rd(sd, 0x05) << 8 |
434 ad9389b_rd(sd, 0x06);
435 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
436 ad9389b_rd(sd, 0x02) << 8 |
437 ad9389b_rd(sd, 0x03);
438
439 v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
440 manual_cts ? "manual" : "automatic", N, CTS);
441
442 v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
443 vic_detect, vic_sent);
444 }
445 }
11d034c8
HV		 446 if (state->dv_timings.type == V4L2_DV_BT_656_1120)
447 v4l2_print_dv_timings(sd->name, "timings: ",
448 &state->dv_timings, false);
449 else
117a55b6 450 v4l2_info(sd, "no timings set\n");
117a55b6
HV		 451 return 0;
452}
453
454/* Power up/down ad9389b */
455static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
456{
457 struct ad9389b_state *state = get_ad9389b_state(sd);
458 struct ad9389b_platform_data *pdata = &state->pdata;
459 const int retries = 20;
460 int i;
461
462 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
463
464 state->power_on = on;
465
466 if (!on) {
467 /* Power down */
468 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
469 return true;
470 }
471
472 /* Power up */
473 /* The ad9389b does not always come up immediately.
474 Retry multiple times. */
475 for (i = 0; i < retries; i++) {
476 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
477 if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
478 break;
479 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
480 msleep(10);
481 }
482 if (i == retries) {
483 v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
484 ad9389b_s_power(sd, 0);
485 return false;
486 }
487 if (i > 1)
488 v4l2_dbg(1, debug, sd,
489 "needed %d retries to powerup the ad9389b\n", i);
490
491 /* Select chip: AD9389B */
492 ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
493
494 /* Reserved registers that must be set according to REF_01 p. 11*/
495 ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
496 ad9389b_wr(sd, 0x9c, 0x38);
497 ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
498
499 /* Differential output drive strength */
500 if (pdata->diff_data_drive_strength > 0)
501 ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
502 else
503 ad9389b_wr(sd, 0xa2, 0x87);
504
505 if (pdata->diff_clk_drive_strength > 0)
506 ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
507 else
508 ad9389b_wr(sd, 0xa3, 0x87);
509
510 ad9389b_wr(sd, 0x0a, 0x01);
511 ad9389b_wr(sd, 0xbb, 0xff);
512
513 /* Set number of attempts to read the EDID */
514 ad9389b_wr(sd, 0xc9, 0xf);
515 return true;
516}
517
518/* Enable interrupts */
519static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
520{
521 u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
522 u8 irqs_rd;
523 int retries = 100;
524
525 /* The datasheet says that the EDID ready interrupt should be
526 disabled if there is no hotplug. */
527 if (!enable)
528 irqs = 0;
529 else if (ad9389b_have_hotplug(sd))
530 irqs |= MASK_AD9389B_EDID_RDY_INT;
531
532 /*
533 * This i2c write can fail (approx. 1 in 1000 writes). But it
534 * is essential that this register is correct, so retry it
535 * multiple times.
536 *
537 * Note that the i2c write does not report an error, but the readback
538 * clearly shows the wrong value.
539 */
540 do {
541 ad9389b_wr(sd, 0x94, irqs);
542 irqs_rd = ad9389b_rd(sd, 0x94);
543 } while (retries-- && irqs_rd != irqs);
544
545 if (irqs_rd != irqs)
546 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
547}
548
549/* Interrupt handler */
550static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
551{
552 u8 irq_status;
553
554 /* disable interrupts to prevent a race condition */
555 ad9389b_set_isr(sd, false);
556 irq_status = ad9389b_rd(sd, 0x96);
557 /* clear detected interrupts */
558 ad9389b_wr(sd, 0x96, irq_status);
559
560 if (irq_status & (MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT))
561 ad9389b_check_monitor_present_status(sd);
562 if (irq_status & MASK_AD9389B_EDID_RDY_INT)
563 ad9389b_check_edid_status(sd);
564
565 /* enable interrupts */
566 ad9389b_set_isr(sd, true);
567 *handled = true;
568 return 0;
569}
570
571static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
572 .log_status = ad9389b_log_status,
117a55b6
HV		 573#ifdef CONFIG_VIDEO_ADV_DEBUG
574 .g_register = ad9389b_g_register,
575 .s_register = ad9389b_s_register,
576#endif
577 .s_power = ad9389b_s_power,
578 .interrupt_service_routine = ad9389b_isr,
579};
580
581/* ------------------------------ PAD OPS ------------------------------ */
582
583static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
584{
585 struct ad9389b_state *state = get_ad9389b_state(sd);
586
587 if (edid->pad != 0)
588 return -EINVAL;
589 if (edid->blocks == 0 || edid->blocks > 256)
590 return -EINVAL;
591 if (!edid->edid)
592 return -EINVAL;
593 if (!state->edid.segments) {
594 v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
595 return -ENODATA;
596 }
597 if (edid->start_block >= state->edid.segments * 2)
598 return -E2BIG;
599 if (edid->blocks + edid->start_block >= state->edid.segments * 2)
600 edid->blocks = state->edid.segments * 2 - edid->start_block;
601 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
602 128 * edid->blocks);
603 return 0;
604}
605
606static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
607 .get_edid = ad9389b_get_edid,
608};
609
610/* ------------------------------ VIDEO OPS ------------------------------ */
611
612/* Enable/disable ad9389b output */
613static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
614{
615 struct ad9389b_state *state = get_ad9389b_state(sd);
616
617 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
618
619 ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
620 if (enable) {
621 ad9389b_check_monitor_present_status(sd);
622 } else {
623 ad9389b_s_power(sd, 0);
624 state->have_monitor = false;
625 }
626 return 0;
627}
628
04164904
HV		 629static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
630 .type = V4L2_DV_BT_656_1120,
631 .bt = {
632 .max_width = 1920,
633 .max_height = 1200,
634 .min_pixelclock = 27000000,
635 .max_pixelclock = 170000000,
636 .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
637 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
638 .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
639 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM,
640 },
117a55b6
HV		 641};
642
643static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
644 struct v4l2_dv_timings *timings)
645{
646 struct ad9389b_state *state = get_ad9389b_state(sd);
117a55b6
HV		 647
648 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
649
650 /* quick sanity check */
04164904 651 if (!v4l2_dv_valid_timings(timings, &ad9389b_timings_cap))
117a55b6
HV		 652 return -EINVAL;
653
654 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
04164904
HV		 655 if the format is one of the CEA or DMT timings. */
656 v4l2_find_dv_timings_cap(timings, &ad9389b_timings_cap, 0);
117a55b6
HV		 657
658 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
659
660 /* save timings */
661 state->dv_timings = *timings;
662
663 /* update quantization range based on new dv_timings */
664 ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
665
666 /* update PLL gear based on new dv_timings */
667 if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
668 ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
669
670 /* update AVI infoframe */
671 ad9389b_set_IT_content_AVI_InfoFrame(sd);
672
673 return 0;
674}
675
676static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
677 struct v4l2_dv_timings *timings)
678{
679 struct ad9389b_state *state = get_ad9389b_state(sd);
680
681 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
682
683 if (!timings)
684 return -EINVAL;
685
686 *timings = state->dv_timings;
687
688 return 0;
689}
690
691static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
692 struct v4l2_enum_dv_timings *timings)
693{
04164904 694 return v4l2_enum_dv_timings_cap(timings, &ad9389b_timings_cap);
117a55b6
HV		 695}
696
697static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
698 struct v4l2_dv_timings_cap *cap)
699{
04164904 700 *cap = ad9389b_timings_cap;
117a55b6
HV		 701 return 0;
702}
703
704static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
705 .s_stream = ad9389b_s_stream,
706 .s_dv_timings = ad9389b_s_dv_timings,
707 .g_dv_timings = ad9389b_g_dv_timings,
708 .enum_dv_timings = ad9389b_enum_dv_timings,
709 .dv_timings_cap = ad9389b_dv_timings_cap,
710};
711
712static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
713{
714 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
715
716 if (enable)
717 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
718 else
719 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
720
721 return 0;
722}
723
724static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
725{
726 u32 N;
727
728 switch (freq) {
729 case 32000: N = 4096; break;
730 case 44100: N = 6272; break;
731 case 48000: N = 6144; break;
732 case 88200: N = 12544; break;
733 case 96000: N = 12288; break;
734 case 176400: N = 25088; break;
735 case 192000: N = 24576; break;
736 default:
737 return -EINVAL;
738 }
739
740 /* Set N (used with CTS to regenerate the audio clock) */
741 ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
742 ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
743 ad9389b_wr(sd, 0x03, N & 0xff);
744
745 return 0;
746}
747
748static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
749{
750 u32 i2s_sf;
751
752 switch (freq) {
753 case 32000: i2s_sf = 0x30; break;
754 case 44100: i2s_sf = 0x00; break;
755 case 48000: i2s_sf = 0x20; break;
756 case 88200: i2s_sf = 0x80; break;
757 case 96000: i2s_sf = 0xa0; break;
758 case 176400: i2s_sf = 0xc0; break;
759 case 192000: i2s_sf = 0xe0; break;
760 default:
761 return -EINVAL;
762 }
763
764 /* Set sampling frequency for I2S audio to 48 kHz */
765 ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
766
767 return 0;
768}
769
770static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
771{
772 /* TODO based on input/output/config */
773 /* TODO See datasheet "Programmers guide" p. 39-40 */
774
775 /* Only 2 channels in use for application */
776 ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
777 /* Speaker mapping */
778 ad9389b_wr(sd, 0x51, 0x00);
779
780 /* TODO Where should this be placed? */
781 /* 16 bit audio word length */
782 ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
783
784 return 0;
785}
786
787static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
788 .s_stream = ad9389b_s_audio_stream,
789 .s_clock_freq = ad9389b_s_clock_freq,
790 .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
791 .s_routing = ad9389b_s_routing,
792};
793
794/* --------------------- SUBDEV OPS --------------------------------------- */
795
796static const struct v4l2_subdev_ops ad9389b_ops = {
797 .core = &ad9389b_core_ops,
798 .video = &ad9389b_video_ops,
799 .audio = &ad9389b_audio_ops,
800 .pad = &ad9389b_pad_ops,
801};
802
803/* ----------------------------------------------------------------------- */
804static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
805 int segment, u8 *buf)
806{
807 int i, j;
808
809 if (debug < lvl)
810 return;
811
812 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
813 for (i = 0; i < 256; i += 16) {
814 u8 b[128];
815 u8 *bp = b;
816
817 if (i == 128)
818 v4l2_dbg(lvl, debug, sd, "\n");
819 for (j = i; j < i + 16; j++) {
820 sprintf(bp, "0x%02x, ", buf[j]);
821 bp += 6;
822 }
823 bp[0] = '\0';
824 v4l2_dbg(lvl, debug, sd, "%s\n", b);
825 }
826}
827
828static void ad9389b_edid_handler(struct work_struct *work)
829{
830 struct delayed_work *dwork = to_delayed_work(work);
831 struct ad9389b_state *state = container_of(dwork,
832 struct ad9389b_state, edid_handler);
833 struct v4l2_subdev *sd = &state->sd;
834 struct ad9389b_edid_detect ed;
835
836 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
837
838 if (ad9389b_check_edid_status(sd)) {
839 /* Return if we received the EDID. */
840 return;
841 }
842
843 if (ad9389b_have_hotplug(sd)) {
844 /* We must retry reading the EDID several times, it is possible
845 * that initially the EDID couldn't be read due to i2c errors
846 * (DVI connectors are particularly prone to this problem). */
847 if (state->edid.read_retries) {
848 state->edid.read_retries--;
15edc1cc
MB		 849 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
850 state->have_monitor = false;
851 ad9389b_s_power(sd, false);
852 ad9389b_s_power(sd, true);
117a55b6
HV		 853 queue_delayed_work(state->work_queue,
854 &state->edid_handler, EDID_DELAY);
855 return;
856 }
857 }
858
859 /* We failed to read the EDID, so send an event for this. */
860 ed.present = false;
861 ed.segment = ad9389b_rd(sd, 0xc4);
862 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
863 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
864}
865
866static void ad9389b_audio_setup(struct v4l2_subdev *sd)
867{
868 v4l2_dbg(1, debug, sd, "%s\n", __func__);
869
870 ad9389b_s_i2s_clock_freq(sd, 48000);
871 ad9389b_s_clock_freq(sd, 48000);
872 ad9389b_s_routing(sd, 0, 0, 0);
873}
874
875/* Initial setup of AD9389b */
876
877/* Configure hdmi transmitter. */
878static void ad9389b_setup(struct v4l2_subdev *sd)
879{
880 struct ad9389b_state *state = get_ad9389b_state(sd);
881
882 v4l2_dbg(1, debug, sd, "%s\n", __func__);
883
884 /* Input format: RGB 4:4:4 */
885 ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
886 /* Output format: RGB 4:4:4 */
887 ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
f3b33ede
MR		 888 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion,
889 Aspect ratio: 16:9 */
890 ad9389b_wr_and_or(sd, 0x17, 0xf9, 0x06);
117a55b6
HV		 891 /* Output format: RGB 4:4:4, Active Format Information is valid. */
892 ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
893 /* Underscanned */
894 ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
895 /* Setup video format */
896 ad9389b_wr(sd, 0x3c, 0x0);
897 /* Active format aspect ratio: same as picure. */
898 ad9389b_wr(sd, 0x47, 0x80);
899 /* No encryption */
900 ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
901 /* Positive clk edge capture for input video clock */
902 ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
903
904 ad9389b_audio_setup(sd);
905
906 v4l2_ctrl_handler_setup(&state->hdl);
907
908 ad9389b_set_IT_content_AVI_InfoFrame(sd);
909}
910
911static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
912{
913 struct ad9389b_monitor_detect mdt;
914 struct ad9389b_state *state = get_ad9389b_state(sd);
915
916 mdt.present = state->have_monitor;
917 v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
918}
919
920static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
921{
922 struct ad9389b_state *state = get_ad9389b_state(sd);
923 /* read hotplug and rx-sense state */
924 u8 status = ad9389b_rd(sd, 0x42);
925
926 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
927 __func__,
928 status,
929 status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
930 status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
931
932 if ((status & MASK_AD9389B_HPD_DETECT) &&
933 ((status & MASK_AD9389B_MSEN_DETECT) || state->edid.segments)) {
934 v4l2_dbg(1, debug, sd,
935 "%s: hotplug and (rx-sense or edid)\n", __func__);
936 if (!state->have_monitor) {
937 v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__);
938 state->have_monitor = true;
939 ad9389b_set_isr(sd, true);
940 if (!ad9389b_s_power(sd, true)) {
941 v4l2_dbg(1, debug, sd,
942 "%s: monitor detected, powerup failed\n", __func__);
943 return;
944 }
945 ad9389b_setup(sd);
946 ad9389b_notify_monitor_detect(sd);
947 state->edid.read_retries = EDID_MAX_RETRIES;
948 queue_delayed_work(state->work_queue,
949 &state->edid_handler, EDID_DELAY);
950 }
951 } else if (status & MASK_AD9389B_HPD_DETECT) {
952 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
953 state->edid.read_retries = EDID_MAX_RETRIES;
954 queue_delayed_work(state->work_queue,
955 &state->edid_handler, EDID_DELAY);
956 } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
957 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
958 if (state->have_monitor) {
959 v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__);
960 state->have_monitor = false;
961 ad9389b_notify_monitor_detect(sd);
962 }
963 ad9389b_s_power(sd, false);
964 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
965 }
966
967 /* update read only ctrls */
968 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
969 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
970 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
971}
972
973static bool edid_block_verify_crc(u8 *edid_block)
974{
117a55b6 975 u8 sum = 0;
350a1815 976 int i;
117a55b6 977
350a1815
MB		 978 for (i = 0; i < 128; i++)
979 sum += edid_block[i];
980 return sum == 0;
117a55b6
HV		 981}
982
983static bool edid_segment_verify_crc(struct v4l2_subdev *sd, u32 segment)
984{
985 struct ad9389b_state *state = get_ad9389b_state(sd);
986 u32 blocks = state->edid.blocks;
987 u8 *data = state->edid.data;
988
989 if (edid_block_verify_crc(&data[segment * 256])) {
990 if ((segment + 1) * 2 <= blocks)
991 return edid_block_verify_crc(&data[segment * 256 + 128]);
992 return true;
993 }
994 return false;
995}
996
997static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
998{
999 struct ad9389b_state *state = get_ad9389b_state(sd);
1000 struct ad9389b_edid_detect ed;
1001 int segment;
1002 u8 edidRdy = ad9389b_rd(sd, 0xc5);
1003
1004 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1005 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1006
1007 if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1008 return false;
1009
1010 segment = ad9389b_rd(sd, 0xc4);
1011 if (segment >= EDID_MAX_SEGM) {
1012 v4l2_err(sd, "edid segment number too big\n");
1013 return false;
1014 }
1015 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1016 ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1017 ad9389b_dbg_dump_edid(2, debug, sd, segment,
1018 &state->edid.data[segment * 256]);
1019 if (segment == 0) {
1020 state->edid.blocks = state->edid.data[0x7e] + 1;
1021 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1022 __func__, state->edid.blocks);
1023 }
1024 if (!edid_segment_verify_crc(sd, segment)) {
1025 /* edid crc error, force reread of edid segment */
7be4f888
MR		 1026 v4l2_err(sd, "%s: edid crc error\n", __func__);
1027 state->have_monitor = false;
117a55b6
HV		 1028 ad9389b_s_power(sd, false);
1029 ad9389b_s_power(sd, true);
1030 return false;
1031 }
1032 /* one more segment read ok */
1033 state->edid.segments = segment + 1;
1034 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1035 /* Request next EDID segment */
1036 v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
1037 __func__, state->edid.segments);
1038 ad9389b_wr(sd, 0xc9, 0xf);
1039 ad9389b_wr(sd, 0xc4, state->edid.segments);
1040 state->edid.read_retries = EDID_MAX_RETRIES;
1041 queue_delayed_work(state->work_queue,
1042 &state->edid_handler, EDID_DELAY);
1043 return false;
1044 }
1045
1046 /* report when we have all segments but report only for segment 0 */
1047 ed.present = true;
1048 ed.segment = 0;
1049 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1050 state->edid_detect_counter++;
1051 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1052 return ed.present;
1053}
1054
1055/* ----------------------------------------------------------------------- */
1056
1057static void ad9389b_init_setup(struct v4l2_subdev *sd)
1058{
1059 struct ad9389b_state *state = get_ad9389b_state(sd);
1060 struct ad9389b_state_edid *edid = &state->edid;
1061
1062 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1063
1064 /* clear all interrupts */
1065 ad9389b_wr(sd, 0x96, 0xff);
1066
1067 memset(edid, 0, sizeof(struct ad9389b_state_edid));
1068 state->have_monitor = false;
1069 ad9389b_set_isr(sd, false);
1070}
1071
1072static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1073{
1074 const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1075 struct ad9389b_state *state;
1076 struct ad9389b_platform_data *pdata = client->dev.platform_data;
1077 struct v4l2_ctrl_handler *hdl;
1078 struct v4l2_subdev *sd;
1079 int err = -EIO;
1080
1081 /* Check if the adapter supports the needed features */
1082 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1083 return -EIO;
1084
1085 v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
1086 client->addr << 1);
1087
c02b211d 1088 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
117a55b6
HV		 1089 if (!state)
1090 return -ENOMEM;
1091
1092 /* Platform data */
1093 if (pdata == NULL) {
1094 v4l_err(client, "No platform data!\n");
c02b211d 1095 return -ENODEV;
117a55b6
HV		 1096 }
1097 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1098
1099 sd = &state->sd;
1100 v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1101 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1102
1103 hdl = &state->hdl;
1104 v4l2_ctrl_handler_init(hdl, 5);
1105
1106 /* private controls */
1107
1108 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1109 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1110 0, V4L2_DV_TX_MODE_DVI_D);
1111 state->hdmi_mode_ctrl->is_private = true;
1112 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1113 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1114 state->hotplug_ctrl->is_private = true;
1115 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1116 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1117 state->rx_sense_ctrl->is_private = true;
1118 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1119 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1120 state->have_edid0_ctrl->is_private = true;
1121 state->rgb_quantization_range_ctrl =
1122 v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1123 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1124 0, V4L2_DV_RGB_RANGE_AUTO);
1125 state->rgb_quantization_range_ctrl->is_private = true;
1126 sd->ctrl_handler = hdl;
1127 if (hdl->error) {
1128 err = hdl->error;
1129
1130 goto err_hdl;
1131 }
1132
1133 state->pad.flags = MEDIA_PAD_FL_SINK;
1134 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
1135 if (err)
1136 goto err_hdl;
1137
1138 state->chip_revision = ad9389b_rd(sd, 0x0);
1139 if (state->chip_revision != 2) {
1140 v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1141 err = -EIO;
1142 goto err_entity;
1143 }
1144 v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
1145 ad9389b_rd(sd, 0x41), state->chip_revision);
1146
1147 state->edid_i2c_client = i2c_new_dummy(client->adapter, (0x7e>>1));
1148 if (state->edid_i2c_client == NULL) {
1149 v4l2_err(sd, "failed to register edid i2c client\n");
6ec735df 1150 err = -ENOMEM;
117a55b6
HV		 1151 goto err_entity;
1152 }
1153
1154 state->work_queue = create_singlethread_workqueue(sd->name);
1155 if (state->work_queue == NULL) {
1156 v4l2_err(sd, "could not create workqueue\n");
6ec735df 1157 err = -ENOMEM;
117a55b6
HV		 1158 goto err_unreg;
1159 }
1160
1161 INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1162 state->dv_timings = dv1080p60;
1163
1164 ad9389b_init_setup(sd);
1165 ad9389b_set_isr(sd, true);
1166
1167 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1168 client->addr << 1, client->adapter->name);
1169 return 0;
1170
1171err_unreg:
1172 i2c_unregister_device(state->edid_i2c_client);
1173err_entity:
1174 media_entity_cleanup(&sd->entity);
1175err_hdl:
1176 v4l2_ctrl_handler_free(&state->hdl);
117a55b6
HV		 1177 return err;
1178}
1179
1180/* ----------------------------------------------------------------------- */
1181
1182static int ad9389b_remove(struct i2c_client *client)
1183{
1184 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1185 struct ad9389b_state *state = get_ad9389b_state(sd);
1186
1187 state->chip_revision = -1;
1188
1189 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1190 client->addr << 1, client->adapter->name);
1191
1192 ad9389b_s_stream(sd, false);
1193 ad9389b_s_audio_stream(sd, false);
1194 ad9389b_init_setup(sd);
1195 cancel_delayed_work(&state->edid_handler);
1196 i2c_unregister_device(state->edid_i2c_client);
1197 destroy_workqueue(state->work_queue);
1198 v4l2_device_unregister_subdev(sd);
1199 media_entity_cleanup(&sd->entity);
1200 v4l2_ctrl_handler_free(sd->ctrl_handler);
117a55b6
HV		 1201 return 0;
1202}
1203
1204/* ----------------------------------------------------------------------- */
1205
1206static struct i2c_device_id ad9389b_id[] = {
e1277110
HV		 1207 { "ad9389b", 0 },
1208 { "ad9889b", 0 },
117a55b6
HV		 1209 { }
1210};
1211MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1212
1213static struct i2c_driver ad9389b_driver = {
1214 .driver = {
1215 .owner = THIS_MODULE,
1216 .name = "ad9389b",
1217 },
1218 .probe = ad9389b_probe,
1219 .remove = ad9389b_remove,
1220 .id_table = ad9389b_id,
1221};
1222
1223module_i2c_driver(ad9389b_driver);
Linux kernel - Deliverables
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