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Merge branch 'perf/rbtree_copy' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / media / i2c / adv7180.c
CommitLineData
6789cb52
RR		 1/*
2 * adv7180.c Analog Devices ADV7180 video decoder driver
3 * Copyright (c) 2009 Intel Corporation
cccb83f7
VB		 4 * Copyright (C) 2013 Cogent Embedded, Inc.
5 * Copyright (C) 2013 Renesas Solutions Corp.
6789cb52
RR		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/errno.h>
24#include <linux/kernel.h>
25#include <linux/interrupt.h>
26#include <linux/i2c.h>
5a0e3ad6 27#include <linux/slab.h>
6789cb52
RR		 28#include <media/v4l2-ioctl.h>
29#include <linux/videodev2.h>
30#include <media/v4l2-device.h>
c9fbeddd 31#include <media/v4l2-ctrls.h>
42752f7a 32#include <linux/mutex.h>
c18818e9 33#include <linux/delay.h>
6789cb52 34
f5dde49b
LPC		 35#define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
36#define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
37#define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
38#define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
39#define ADV7180_STD_NTSC_J 0x4
40#define ADV7180_STD_NTSC_M 0x5
41#define ADV7180_STD_PAL60 0x6
42#define ADV7180_STD_NTSC_443 0x7
43#define ADV7180_STD_PAL_BG 0x8
44#define ADV7180_STD_PAL_N 0x9
45#define ADV7180_STD_PAL_M 0xa
46#define ADV7180_STD_PAL_M_PED 0xb
47#define ADV7180_STD_PAL_COMB_N 0xc
48#define ADV7180_STD_PAL_COMB_N_PED 0xd
49#define ADV7180_STD_PAL_SECAM 0xe
50#define ADV7180_STD_PAL_SECAM_PED 0xf
51
3999e5d0 52#define ADV7180_REG_INPUT_CONTROL 0x0000
bca7ad1a 53#define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
d3124294 54
c5ef8f8c
LPC		 55#define ADV7182_REG_INPUT_VIDSEL 0x0002
56
3999e5d0 57#define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
42752f7a 58#define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
6789cb52 59
029d6177 60#define ADV7180_REG_AUTODETECT_ENABLE 0x07
42752f7a 61#define ADV7180_AUTODETECT_DEFAULT 0x7f
c9fbeddd 62/* Contrast */
3999e5d0 63#define ADV7180_REG_CON 0x0008 /*Unsigned */
c9fbeddd
FV		 64#define ADV7180_CON_MIN 0
65#define ADV7180_CON_DEF 128
66#define ADV7180_CON_MAX 255
67/* Brightness*/
3999e5d0 68#define ADV7180_REG_BRI 0x000a /*Signed */
c9fbeddd
FV		 69#define ADV7180_BRI_MIN -128
70#define ADV7180_BRI_DEF 0
71#define ADV7180_BRI_MAX 127
72/* Hue */
3999e5d0 73#define ADV7180_REG_HUE 0x000b /*Signed, inverted */
c9fbeddd
FV		 74#define ADV7180_HUE_MIN -127
75#define ADV7180_HUE_DEF 0
76#define ADV7180_HUE_MAX 128
bca7ad1a 77
3999e5d0 78#define ADV7180_REG_CTRL 0x000e
029d6177 79#define ADV7180_CTRL_IRQ_SPACE 0x20
6789cb52 80
029d6177 81#define ADV7180_REG_PWR_MAN 0x0f
bca7ad1a
FV		 82#define ADV7180_PWR_MAN_ON 0x04
83#define ADV7180_PWR_MAN_OFF 0x24
84#define ADV7180_PWR_MAN_RES 0x80
85
3999e5d0 86#define ADV7180_REG_STATUS1 0x0010
d3124294
RR		 87#define ADV7180_STATUS1_IN_LOCK 0x01
88#define ADV7180_STATUS1_AUTOD_MASK 0x70
6789cb52
RR		 89#define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
90#define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
91#define ADV7180_STATUS1_AUTOD_PAL_M 0x20
92#define ADV7180_STATUS1_AUTOD_PAL_60 0x30
93#define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
94#define ADV7180_STATUS1_AUTOD_SECAM 0x50
95#define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
96#define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
97
3999e5d0 98#define ADV7180_REG_IDENT 0x0011
6789cb52
RR		 99#define ADV7180_ID_7180 0x18
100
3999e5d0 101#define ADV7180_REG_ICONF1 0x0040
42752f7a
RR		 102#define ADV7180_ICONF1_ACTIVE_LOW 0x01
103#define ADV7180_ICONF1_PSYNC_ONLY 0x10
104#define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
c9fbeddd 105/* Saturation */
3999e5d0
LPC		 106#define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
107#define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
c9fbeddd
FV		 108#define ADV7180_SAT_MIN 0
109#define ADV7180_SAT_DEF 128
110#define ADV7180_SAT_MAX 255
bca7ad1a 111
42752f7a
RR		 112#define ADV7180_IRQ1_LOCK 0x01
113#define ADV7180_IRQ1_UNLOCK 0x02
3999e5d0
LPC		 114#define ADV7180_REG_ISR1 0x0042
115#define ADV7180_REG_ICR1 0x0043
116#define ADV7180_REG_IMR1 0x0044
117#define ADV7180_REG_IMR2 0x0048
42752f7a 118#define ADV7180_IRQ3_AD_CHANGE 0x08
3999e5d0
LPC		 119#define ADV7180_REG_ISR3 0x004A
120#define ADV7180_REG_ICR3 0x004B
121#define ADV7180_REG_IMR3 0x004C
029d6177 122#define ADV7180_REG_IMR4 0x50
6789cb52 123
3999e5d0 124#define ADV7180_REG_NTSC_V_BIT_END 0x00E6
bca7ad1a
FV		 125#define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
126
851a54ef 127#define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
b37135e3
LPC		 128#define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
129
08b717c2
LPC		 130#define ADV7180_REG_FLCONTROL 0x40e0
131#define ADV7180_FLCONTROL_FL_ENABLE 0x1
132
b37135e3
LPC		 133#define ADV7180_CSI_REG_PWRDN 0x00
134#define ADV7180_CSI_PWRDN 0x80
135
f5dde49b
LPC		 136#define ADV7180_INPUT_CVBS_AIN1 0x00
137#define ADV7180_INPUT_CVBS_AIN2 0x01
138#define ADV7180_INPUT_CVBS_AIN3 0x02
139#define ADV7180_INPUT_CVBS_AIN4 0x03
140#define ADV7180_INPUT_CVBS_AIN5 0x04
141#define ADV7180_INPUT_CVBS_AIN6 0x05
142#define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
143#define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
144#define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
145#define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
146#define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
147
c5ef8f8c
LPC		 148#define ADV7182_INPUT_CVBS_AIN1 0x00
149#define ADV7182_INPUT_CVBS_AIN2 0x01
150#define ADV7182_INPUT_CVBS_AIN3 0x02
151#define ADV7182_INPUT_CVBS_AIN4 0x03
152#define ADV7182_INPUT_CVBS_AIN5 0x04
153#define ADV7182_INPUT_CVBS_AIN6 0x05
154#define ADV7182_INPUT_CVBS_AIN7 0x06
155#define ADV7182_INPUT_CVBS_AIN8 0x07
156#define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
157#define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
158#define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
159#define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
160#define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
161#define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
162#define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
163#define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
164#define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
165#define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
166
b37135e3 167#define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
851a54ef 168#define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
b37135e3 169
08b717c2
LPC		 170#define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
171
f5dde49b
LPC		 172struct adv7180_state;
173
174#define ADV7180_FLAG_RESET_POWERED BIT(0)
bf7dcb80 175#define ADV7180_FLAG_V2 BIT(1)
b37135e3 176#define ADV7180_FLAG_MIPI_CSI2 BIT(2)
851a54ef 177#define ADV7180_FLAG_I2P BIT(3)
f5dde49b
LPC		 178
179struct adv7180_chip_info {
180 unsigned int flags;
181 unsigned int valid_input_mask;
182 int (*set_std)(struct adv7180_state *st, unsigned int std);
183 int (*select_input)(struct adv7180_state *st, unsigned int input);
184 int (*init)(struct adv7180_state *state);
185};
186
6789cb52 187struct adv7180_state {
c9fbeddd 188 struct v4l2_ctrl_handler ctrl_hdl;
c277b60a 189 struct v4l2_subdev sd;
d5d51a82 190 struct media_pad pad;
42752f7a
RR		 191 struct mutex mutex; /* mutual excl. when accessing chip */
192 int irq;
c277b60a
RR		 193 v4l2_std_id curr_norm;
194 bool autodetect;
e246c333 195 bool powered;
bca7ad1a 196 u8 input;
3999e5d0
LPC		 197
198 struct i2c_client *client;
199 unsigned int register_page;
b37135e3 200 struct i2c_client *csi_client;
851a54ef 201 struct i2c_client *vpp_client;
f5dde49b 202 const struct adv7180_chip_info *chip_info;
851a54ef 203 enum v4l2_field field;
6789cb52 204};
c9fbeddd
FV		 205#define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
206 struct adv7180_state, \
207 ctrl_hdl)->sd)
6789cb52 208
3999e5d0
LPC		 209static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
210{
211 if (state->register_page != page) {
212 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
213 page);
214 state->register_page = page;
215 }
216
217 return 0;
218}
219
220static int adv7180_write(struct adv7180_state *state, unsigned int reg,
221 unsigned int value)
222{
223 lockdep_assert_held(&state->mutex);
224 adv7180_select_page(state, reg >> 8);
225 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
226}
227
228static int adv7180_read(struct adv7180_state *state, unsigned int reg)
229{
230 lockdep_assert_held(&state->mutex);
231 adv7180_select_page(state, reg >> 8);
232 return i2c_smbus_read_byte_data(state->client, reg & 0xff);
233}
234
b37135e3
LPC		 235static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
236 unsigned int value)
237{
238 return i2c_smbus_write_byte_data(state->csi_client, reg, value);
239}
240
f5dde49b
LPC		 241static int adv7180_set_video_standard(struct adv7180_state *state,
242 unsigned int std)
243{
244 return state->chip_info->set_std(state, std);
245}
3999e5d0 246
851a54ef
LPC		 247static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
248 unsigned int value)
249{
250 return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
251}
252
d3124294 253static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
6789cb52 254{
b294a192
VB		 255 /* in case V4L2_IN_ST_NO_SIGNAL */
256 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
257 return V4L2_STD_UNKNOWN;
258
6789cb52
RR		 259 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
260 case ADV7180_STATUS1_AUTOD_NTSM_M_J:
d3124294 261 return V4L2_STD_NTSC;
6789cb52
RR		 262 case ADV7180_STATUS1_AUTOD_NTSC_4_43:
263 return V4L2_STD_NTSC_443;
264 case ADV7180_STATUS1_AUTOD_PAL_M:
265 return V4L2_STD_PAL_M;
266 case ADV7180_STATUS1_AUTOD_PAL_60:
267 return V4L2_STD_PAL_60;
268 case ADV7180_STATUS1_AUTOD_PAL_B_G:
269 return V4L2_STD_PAL;
270 case ADV7180_STATUS1_AUTOD_SECAM:
271 return V4L2_STD_SECAM;
272 case ADV7180_STATUS1_AUTOD_PAL_COMB:
273 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
274 case ADV7180_STATUS1_AUTOD_SECAM_525:
275 return V4L2_STD_SECAM;
276 default:
277 return V4L2_STD_UNKNOWN;
278 }
279}
280
c277b60a
RR		 281static int v4l2_std_to_adv7180(v4l2_std_id std)
282{
283 if (std == V4L2_STD_PAL_60)
f5dde49b 284 return ADV7180_STD_PAL60;
c277b60a 285 if (std == V4L2_STD_NTSC_443)
f5dde49b 286 return ADV7180_STD_NTSC_443;
c277b60a 287 if (std == V4L2_STD_PAL_N)
f5dde49b 288 return ADV7180_STD_PAL_N;
c277b60a 289 if (std == V4L2_STD_PAL_M)
f5dde49b 290 return ADV7180_STD_PAL_M;
c277b60a 291 if (std == V4L2_STD_PAL_Nc)
f5dde49b 292 return ADV7180_STD_PAL_COMB_N;
c277b60a
RR		 293
294 if (std & V4L2_STD_PAL)
f5dde49b 295 return ADV7180_STD_PAL_BG;
c277b60a 296 if (std & V4L2_STD_NTSC)
f5dde49b 297 return ADV7180_STD_NTSC_M;
c277b60a 298 if (std & V4L2_STD_SECAM)
f5dde49b 299 return ADV7180_STD_PAL_SECAM;
c277b60a
RR		 300
301 return -EINVAL;
302}
303
d3124294
RR		 304static u32 adv7180_status_to_v4l2(u8 status1)
305{
306 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
307 return V4L2_IN_ST_NO_SIGNAL;
308
309 return 0;
310}
311
3999e5d0 312static int __adv7180_status(struct adv7180_state *state, u32 *status,
bca7ad1a 313 v4l2_std_id *std)
d3124294 314{
3999e5d0 315 int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
d3124294
RR		 316
317 if (status1 < 0)
318 return status1;
319
320 if (status)
321 *status = adv7180_status_to_v4l2(status1);
322 if (std)
323 *std = adv7180_std_to_v4l2(status1);
324
325 return 0;
326}
327
6789cb52
RR		 328static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
329{
330 return container_of(sd, struct adv7180_state, sd);
331}
332
333static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
334{
c277b60a 335 struct adv7180_state *state = to_state(sd);
42752f7a
RR		 336 int err = mutex_lock_interruptible(&state->mutex);
337 if (err)
338 return err;
c277b60a 339
42752f7a
RR		 340 /* when we are interrupt driven we know the state */
341 if (!state->autodetect || state->irq > 0)
c277b60a
RR		 342 *std = state->curr_norm;
343 else
3999e5d0 344 err = __adv7180_status(state, NULL, std);
c277b60a 345
42752f7a 346 mutex_unlock(&state->mutex);
c277b60a 347 return err;
d3124294 348}
6789cb52 349
bca7ad1a
FV		 350static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
351 u32 output, u32 config)
352{
353 struct adv7180_state *state = to_state(sd);
354 int ret = mutex_lock_interruptible(&state->mutex);
bca7ad1a
FV		 355
356 if (ret)
357 return ret;
358
f5dde49b
LPC		 359 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
360 ret = -EINVAL;
bca7ad1a 361 goto out;
f5dde49b 362 }
bca7ad1a 363
f5dde49b 364 ret = state->chip_info->select_input(state, input);
bca7ad1a 365
f5dde49b
LPC		 366 if (ret == 0)
367 state->input = input;
bca7ad1a
FV		 368out:
369 mutex_unlock(&state->mutex);
370 return ret;
371}
372
d3124294
RR		 373static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
374{
42752f7a
RR		 375 struct adv7180_state *state = to_state(sd);
376 int ret = mutex_lock_interruptible(&state->mutex);
377 if (ret)
378 return ret;
379
3999e5d0 380 ret = __adv7180_status(state, status, NULL);
42752f7a
RR		 381 mutex_unlock(&state->mutex);
382 return ret;
6789cb52
RR		 383}
384
3e35e33c 385static int adv7180_program_std(struct adv7180_state *state)
c277b60a 386{
3e35e33c 387 int ret;
c277b60a 388
3e35e33c 389 if (state->autodetect) {
f5dde49b
LPC		 390 ret = adv7180_set_video_standard(state,
391 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
c277b60a 392 if (ret < 0)
3e35e33c 393 return ret;
c277b60a 394
3999e5d0 395 __adv7180_status(state, NULL, &state->curr_norm);
c277b60a 396 } else {
3e35e33c 397 ret = v4l2_std_to_adv7180(state->curr_norm);
c277b60a 398 if (ret < 0)
3e35e33c 399 return ret;
c277b60a 400
f5dde49b 401 ret = adv7180_set_video_standard(state, ret);
3e35e33c
LPC		 402 if (ret < 0)
403 return ret;
404 }
405
406 return 0;
407}
408
409static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
410{
411 struct adv7180_state *state = to_state(sd);
412 int ret = mutex_lock_interruptible(&state->mutex);
413
414 if (ret)
415 return ret;
416
417 /* all standards -> autodetect */
418 if (std == V4L2_STD_ALL) {
419 state->autodetect = true;
420 } else {
421 /* Make sure we can support this std */
422 ret = v4l2_std_to_adv7180(std);
c277b60a
RR		 423 if (ret < 0)
424 goto out;
425
426 state->curr_norm = std;
427 state->autodetect = false;
428 }
3e35e33c
LPC		 429
430 ret = adv7180_program_std(state);
c277b60a 431out:
42752f7a 432 mutex_unlock(&state->mutex);
c277b60a
RR		 433 return ret;
434}
435
3999e5d0 436static int adv7180_set_power(struct adv7180_state *state, bool on)
e246c333
LPC		 437{
438 u8 val;
b37135e3 439 int ret;
e246c333
LPC		 440
441 if (on)
442 val = ADV7180_PWR_MAN_ON;
443 else
444 val = ADV7180_PWR_MAN_OFF;
445
b37135e3
LPC		 446 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
447 if (ret)
448 return ret;
449
450 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
451 if (on) {
452 adv7180_csi_write(state, 0xDE, 0x02);
453 adv7180_csi_write(state, 0xD2, 0xF7);
454 adv7180_csi_write(state, 0xD8, 0x65);
455 adv7180_csi_write(state, 0xE0, 0x09);
456 adv7180_csi_write(state, 0x2C, 0x00);
851a54ef
LPC		 457 if (state->field == V4L2_FIELD_NONE)
458 adv7180_csi_write(state, 0x1D, 0x80);
b37135e3
LPC		 459 adv7180_csi_write(state, 0x00, 0x00);
460 } else {
461 adv7180_csi_write(state, 0x00, 0x80);
462 }
463 }
464
465 return 0;
e246c333
LPC		 466}
467
468static int adv7180_s_power(struct v4l2_subdev *sd, int on)
469{
470 struct adv7180_state *state = to_state(sd);
e246c333
LPC		 471 int ret;
472
473 ret = mutex_lock_interruptible(&state->mutex);
474 if (ret)
475 return ret;
476
3999e5d0 477 ret = adv7180_set_power(state, on);
e246c333
LPC		 478 if (ret == 0)
479 state->powered = on;
480
481 mutex_unlock(&state->mutex);
482 return ret;
483}
484
c9fbeddd 485static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
bca7ad1a 486{
c9fbeddd 487 struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
bca7ad1a 488 struct adv7180_state *state = to_state(sd);
bca7ad1a 489 int ret = mutex_lock_interruptible(&state->mutex);
c9fbeddd
FV		 490 int val;
491
bca7ad1a
FV		 492 if (ret)
493 return ret;
c9fbeddd 494 val = ctrl->val;
bca7ad1a
FV		 495 switch (ctrl->id) {
496 case V4L2_CID_BRIGHTNESS:
3999e5d0 497 ret = adv7180_write(state, ADV7180_REG_BRI, val);
bca7ad1a
FV		 498 break;
499 case V4L2_CID_HUE:
bca7ad1a 500 /*Hue is inverted according to HSL chart */
3999e5d0 501 ret = adv7180_write(state, ADV7180_REG_HUE, -val);
bca7ad1a
FV		 502 break;
503 case V4L2_CID_CONTRAST:
3999e5d0 504 ret = adv7180_write(state, ADV7180_REG_CON, val);
bca7ad1a
FV		 505 break;
506 case V4L2_CID_SATURATION:
bca7ad1a
FV		 507 /*
508 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
509 *Let's not confuse the user, everybody understands saturation
510 */
3999e5d0 511 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
bca7ad1a
FV		 512 if (ret < 0)
513 break;
3999e5d0 514 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
bca7ad1a 515 break;
08b717c2
LPC		 516 case V4L2_CID_ADV_FAST_SWITCH:
517 if (ctrl->val) {
518 /* ADI required write */
519 adv7180_write(state, 0x80d9, 0x44);
520 adv7180_write(state, ADV7180_REG_FLCONTROL,
521 ADV7180_FLCONTROL_FL_ENABLE);
522 } else {
523 /* ADI required write */
524 adv7180_write(state, 0x80d9, 0xc4);
525 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
526 }
527 break;
bca7ad1a
FV		 528 default:
529 ret = -EINVAL;
530 }
531
532 mutex_unlock(&state->mutex);
533 return ret;
534}
535
c9fbeddd
FV		 536static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
537 .s_ctrl = adv7180_s_ctrl,
538};
539
08b717c2
LPC		 540static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
541 .ops = &adv7180_ctrl_ops,
542 .id = V4L2_CID_ADV_FAST_SWITCH,
543 .name = "Fast Switching",
544 .type = V4L2_CTRL_TYPE_BOOLEAN,
545 .min = 0,
546 .max = 1,
547 .step = 1,
548};
549
c9fbeddd
FV		 550static int adv7180_init_controls(struct adv7180_state *state)
551{
552 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
553
554 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
555 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
556 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
557 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
558 V4L2_CID_CONTRAST, ADV7180_CON_MIN,
559 ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
560 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
561 V4L2_CID_SATURATION, ADV7180_SAT_MIN,
562 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
563 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
564 V4L2_CID_HUE, ADV7180_HUE_MIN,
565 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
08b717c2
LPC		 566 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
567
c9fbeddd
FV		 568 state->sd.ctrl_handler = &state->ctrl_hdl;
569 if (state->ctrl_hdl.error) {
570 int err = state->ctrl_hdl.error;
571
572 v4l2_ctrl_handler_free(&state->ctrl_hdl);
573 return err;
574 }
575 v4l2_ctrl_handler_setup(&state->ctrl_hdl);
576
577 return 0;
578}
579static void adv7180_exit_controls(struct adv7180_state *state)
580{
581 v4l2_ctrl_handler_free(&state->ctrl_hdl);
582}
583
d5d51a82 584static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 585 struct v4l2_subdev_pad_config *cfg,
d5d51a82 586 struct v4l2_subdev_mbus_code_enum *code)
cccb83f7 587{
d5d51a82 588 if (code->index != 0)
cccb83f7
VB		 589 return -EINVAL;
590
d5d51a82 591 code->code = MEDIA_BUS_FMT_YUYV8_2X8;
cccb83f7
VB		 592
593 return 0;
594}
595
596static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
597 struct v4l2_mbus_framefmt *fmt)
598{
599 struct adv7180_state *state = to_state(sd);
600
f5fe58fd 601 fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
cccb83f7 602 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
cccb83f7
VB		 603 fmt->width = 720;
604 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
605
606 return 0;
607}
608
851a54ef
LPC		 609static int adv7180_set_field_mode(struct adv7180_state *state)
610{
611 if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
612 return 0;
613
614 if (state->field == V4L2_FIELD_NONE) {
615 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
616 adv7180_csi_write(state, 0x01, 0x20);
617 adv7180_csi_write(state, 0x02, 0x28);
618 adv7180_csi_write(state, 0x03, 0x38);
619 adv7180_csi_write(state, 0x04, 0x30);
620 adv7180_csi_write(state, 0x05, 0x30);
621 adv7180_csi_write(state, 0x06, 0x80);
622 adv7180_csi_write(state, 0x07, 0x70);
623 adv7180_csi_write(state, 0x08, 0x50);
624 }
625 adv7180_vpp_write(state, 0xa3, 0x00);
626 adv7180_vpp_write(state, 0x5b, 0x00);
627 adv7180_vpp_write(state, 0x55, 0x80);
628 } else {
629 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
630 adv7180_csi_write(state, 0x01, 0x18);
631 adv7180_csi_write(state, 0x02, 0x18);
632 adv7180_csi_write(state, 0x03, 0x30);
633 adv7180_csi_write(state, 0x04, 0x20);
634 adv7180_csi_write(state, 0x05, 0x28);
635 adv7180_csi_write(state, 0x06, 0x40);
636 adv7180_csi_write(state, 0x07, 0x58);
637 adv7180_csi_write(state, 0x08, 0x30);
638 }
639 adv7180_vpp_write(state, 0xa3, 0x70);
640 adv7180_vpp_write(state, 0x5b, 0x80);
641 adv7180_vpp_write(state, 0x55, 0x00);
642 }
643
644 return 0;
645}
646
d5d51a82 647static int adv7180_get_pad_format(struct v4l2_subdev *sd,
f7234138 648 struct v4l2_subdev_pad_config *cfg,
d5d51a82
LPC		 649 struct v4l2_subdev_format *format)
650{
851a54ef
LPC		 651 struct adv7180_state *state = to_state(sd);
652
653 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
f7234138 654 format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
851a54ef
LPC		 655 } else {
656 adv7180_mbus_fmt(sd, &format->format);
657 format->format.field = state->field;
658 }
659
660 return 0;
d5d51a82
LPC		 661}
662
663static int adv7180_set_pad_format(struct v4l2_subdev *sd,
f7234138 664 struct v4l2_subdev_pad_config *cfg,
d5d51a82
LPC		 665 struct v4l2_subdev_format *format)
666{
851a54ef
LPC		 667 struct adv7180_state *state = to_state(sd);
668 struct v4l2_mbus_framefmt *framefmt;
669
670 switch (format->format.field) {
671 case V4L2_FIELD_NONE:
672 if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
673 format->format.field = V4L2_FIELD_INTERLACED;
674 break;
675 default:
676 format->format.field = V4L2_FIELD_INTERLACED;
677 break;
678 }
679
680 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
681 framefmt = &format->format;
682 if (state->field != format->format.field) {
683 state->field = format->format.field;
684 adv7180_set_power(state, false);
685 adv7180_set_field_mode(state);
686 adv7180_set_power(state, true);
687 }
688 } else {
f7234138 689 framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
851a54ef
LPC		 690 *framefmt = format->format;
691 }
692
693 return adv7180_mbus_fmt(sd, framefmt);
d5d51a82
LPC		 694}
695
cccb83f7
VB		 696static int adv7180_g_mbus_config(struct v4l2_subdev *sd,
697 struct v4l2_mbus_config *cfg)
698{
b37135e3
LPC		 699 struct adv7180_state *state = to_state(sd);
700
701 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
702 cfg->type = V4L2_MBUS_CSI2;
703 cfg->flags = V4L2_MBUS_CSI2_1_LANE |
704 V4L2_MBUS_CSI2_CHANNEL_0 |
705 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
706 } else {
707 /*
708 * The ADV7180 sensor supports BT.601/656 output modes.
709 * The BT.656 is default and not yet configurable by s/w.
710 */
711 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
712 V4L2_MBUS_DATA_ACTIVE_HIGH;
713 cfg->type = V4L2_MBUS_BT656;
714 }
cccb83f7
VB		 715
716 return 0;
717}
718
6789cb52 719static const struct v4l2_subdev_video_ops adv7180_video_ops = {
8774bed9 720 .s_std = adv7180_s_std,
6789cb52 721 .querystd = adv7180_querystd,
d3124294 722 .g_input_status = adv7180_g_input_status,
bca7ad1a 723 .s_routing = adv7180_s_routing,
cccb83f7 724 .g_mbus_config = adv7180_g_mbus_config,
6789cb52
RR		 725};
726
f5dde49b 727
6789cb52 728static const struct v4l2_subdev_core_ops adv7180_core_ops = {
e246c333 729 .s_power = adv7180_s_power,
6789cb52
RR		 730};
731
d5d51a82
LPC		 732static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
733 .enum_mbus_code = adv7180_enum_mbus_code,
734 .set_fmt = adv7180_set_pad_format,
735 .get_fmt = adv7180_get_pad_format,
736};
737
6789cb52
RR		 738static const struct v4l2_subdev_ops adv7180_ops = {
739 .core = &adv7180_core_ops,
740 .video = &adv7180_video_ops,
d5d51a82 741 .pad = &adv7180_pad_ops,
6789cb52
RR		 742};
743
0c25534d 744static irqreturn_t adv7180_irq(int irq, void *devid)
42752f7a 745{
0c25534d 746 struct adv7180_state *state = devid;
42752f7a
RR		 747 u8 isr3;
748
749 mutex_lock(&state->mutex);
3999e5d0 750 isr3 = adv7180_read(state, ADV7180_REG_ISR3);
42752f7a 751 /* clear */
3999e5d0 752 adv7180_write(state, ADV7180_REG_ICR3, isr3);
42752f7a
RR		 753
754 if (isr3 & ADV7180_IRQ3_AD_CHANGE && state->autodetect)
3999e5d0 755 __adv7180_status(state, NULL, &state->curr_norm);
42752f7a
RR		 756 mutex_unlock(&state->mutex);
757
42752f7a
RR		 758 return IRQ_HANDLED;
759}
760
f5dde49b 761static int adv7180_init(struct adv7180_state *state)
6789cb52 762{
6789cb52
RR		 763 int ret;
764
42752f7a 765 /* ITU-R BT.656-4 compatible */
3999e5d0 766 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
bca7ad1a 767 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
42752f7a 768 if (ret < 0)
f5dde49b 769 return ret;
bca7ad1a
FV		 770
771 /* Manually set V bit end position in NTSC mode */
f5dde49b 772 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
bca7ad1a 773 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
f5dde49b
LPC		 774}
775
776static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
777{
778 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
779 (std << 4) | state->input);
780}
781
782static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
783{
784 int ret;
785
786 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
bca7ad1a 787 if (ret < 0)
f5dde49b
LPC		 788 return ret;
789
790 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
791 ret |= input;
792 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
793}
794
c5ef8f8c
LPC		 795static int adv7182_init(struct adv7180_state *state)
796{
b37135e3
LPC		 797 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
798 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
799 ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
800
851a54ef
LPC		 801 if (state->chip_info->flags & ADV7180_FLAG_I2P)
802 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
803 ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
804
bf7dcb80
LPC		 805 if (state->chip_info->flags & ADV7180_FLAG_V2) {
806 /* ADI recommended writes for improved video quality */
807 adv7180_write(state, 0x0080, 0x51);
808 adv7180_write(state, 0x0081, 0x51);
809 adv7180_write(state, 0x0082, 0x68);
bf7dcb80
LPC		 810 }
811
c5ef8f8c 812 /* ADI required writes */
b37135e3
LPC		 813 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
814 adv7180_write(state, 0x0003, 0x4e);
815 adv7180_write(state, 0x0004, 0x57);
816 adv7180_write(state, 0x001d, 0xc0);
817 } else {
818 if (state->chip_info->flags & ADV7180_FLAG_V2)
819 adv7180_write(state, 0x0004, 0x17);
820 else
821 adv7180_write(state, 0x0004, 0x07);
822 adv7180_write(state, 0x0003, 0x0c);
823 adv7180_write(state, 0x001d, 0x40);
824 }
825
c5ef8f8c 826 adv7180_write(state, 0x0013, 0x00);
c5ef8f8c
LPC		 827
828 return 0;
829}
830
831static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
832{
833 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
834}
835
836enum adv7182_input_type {
837 ADV7182_INPUT_TYPE_CVBS,
838 ADV7182_INPUT_TYPE_DIFF_CVBS,
839 ADV7182_INPUT_TYPE_SVIDEO,
840 ADV7182_INPUT_TYPE_YPBPR,
841};
842
843static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
844{
845 switch (input) {
846 case ADV7182_INPUT_CVBS_AIN1:
847 case ADV7182_INPUT_CVBS_AIN2:
848 case ADV7182_INPUT_CVBS_AIN3:
849 case ADV7182_INPUT_CVBS_AIN4:
850 case ADV7182_INPUT_CVBS_AIN5:
851 case ADV7182_INPUT_CVBS_AIN6:
852 case ADV7182_INPUT_CVBS_AIN7:
853 case ADV7182_INPUT_CVBS_AIN8:
854 return ADV7182_INPUT_TYPE_CVBS;
855 case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
856 case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
857 case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
858 case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
859 return ADV7182_INPUT_TYPE_SVIDEO;
860 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
861 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
862 return ADV7182_INPUT_TYPE_YPBPR;
863 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
864 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
865 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
866 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
867 return ADV7182_INPUT_TYPE_DIFF_CVBS;
868 default: /* Will never happen */
869 return 0;
870 }
871}
872
873/* ADI recommended writes to registers 0x52, 0x53, 0x54 */
874static unsigned int adv7182_lbias_settings[][3] = {
875 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
876 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
877 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
878 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
879};
880
bf7dcb80
LPC		 881static unsigned int adv7280_lbias_settings[][3] = {
882 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
883 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
884 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
885 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
886};
887
c5ef8f8c
LPC		 888static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
889{
890 enum adv7182_input_type input_type;
891 unsigned int *lbias;
892 unsigned int i;
893 int ret;
894
895 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
896 if (ret)
897 return ret;
898
899 /* Reset clamp circuitry - ADI recommended writes */
900 adv7180_write(state, 0x809c, 0x00);
901 adv7180_write(state, 0x809c, 0xff);
902
903 input_type = adv7182_get_input_type(input);
904
905 switch (input_type) {
906 case ADV7182_INPUT_TYPE_CVBS:
907 case ADV7182_INPUT_TYPE_DIFF_CVBS:
908 /* ADI recommends to use the SH1 filter */
909 adv7180_write(state, 0x0017, 0x41);
910 break;
911 default:
912 adv7180_write(state, 0x0017, 0x01);
913 break;
914 }
915
bf7dcb80
LPC		 916 if (state->chip_info->flags & ADV7180_FLAG_V2)
917 lbias = adv7280_lbias_settings[input_type];
918 else
919 lbias = adv7182_lbias_settings[input_type];
c5ef8f8c
LPC		 920
921 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
922 adv7180_write(state, 0x0052 + i, lbias[i]);
923
924 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
925 /* ADI required writes to make differential CVBS work */
926 adv7180_write(state, 0x005f, 0xa8);
927 adv7180_write(state, 0x005a, 0x90);
928 adv7180_write(state, 0x0060, 0xb0);
929 adv7180_write(state, 0x80b6, 0x08);
930 adv7180_write(state, 0x80c0, 0xa0);
931 } else {
932 adv7180_write(state, 0x005f, 0xf0);
933 adv7180_write(state, 0x005a, 0xd0);
934 adv7180_write(state, 0x0060, 0x10);
935 adv7180_write(state, 0x80b6, 0x9c);
936 adv7180_write(state, 0x80c0, 0x00);
937 }
938
939 return 0;
940}
941
f5dde49b
LPC		 942static const struct adv7180_chip_info adv7180_info = {
943 .flags = ADV7180_FLAG_RESET_POWERED,
944 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
945 * all inputs and let the card driver take care of validation
946 */
947 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
948 BIT(ADV7180_INPUT_CVBS_AIN2) |
949 BIT(ADV7180_INPUT_CVBS_AIN3) |
950 BIT(ADV7180_INPUT_CVBS_AIN4) |
951 BIT(ADV7180_INPUT_CVBS_AIN5) |
952 BIT(ADV7180_INPUT_CVBS_AIN6) |
953 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
954 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
955 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
956 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
957 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
958 .init = adv7180_init,
959 .set_std = adv7180_set_std,
960 .select_input = adv7180_select_input,
961};
962
c5ef8f8c
LPC		 963static const struct adv7180_chip_info adv7182_info = {
964 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
965 BIT(ADV7182_INPUT_CVBS_AIN2) |
966 BIT(ADV7182_INPUT_CVBS_AIN3) |
967 BIT(ADV7182_INPUT_CVBS_AIN4) |
968 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
969 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
970 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
971 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
972 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
973 .init = adv7182_init,
974 .set_std = adv7182_set_std,
975 .select_input = adv7182_select_input,
976};
977
bf7dcb80 978static const struct adv7180_chip_info adv7280_info = {
851a54ef 979 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
bf7dcb80
LPC		 980 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
981 BIT(ADV7182_INPUT_CVBS_AIN2) |
982 BIT(ADV7182_INPUT_CVBS_AIN3) |
983 BIT(ADV7182_INPUT_CVBS_AIN4) |
984 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
985 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
986 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
987 .init = adv7182_init,
988 .set_std = adv7182_set_std,
989 .select_input = adv7182_select_input,
990};
991
b37135e3 992static const struct adv7180_chip_info adv7280_m_info = {
851a54ef 993 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
b37135e3
LPC		 994 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
995 BIT(ADV7182_INPUT_CVBS_AIN2) |
996 BIT(ADV7182_INPUT_CVBS_AIN3) |
997 BIT(ADV7182_INPUT_CVBS_AIN4) |
998 BIT(ADV7182_INPUT_CVBS_AIN5) |
999 BIT(ADV7182_INPUT_CVBS_AIN6) |
1000 BIT(ADV7182_INPUT_CVBS_AIN7) |
1001 BIT(ADV7182_INPUT_CVBS_AIN8) |
1002 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1003 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1004 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1005 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1006 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1007 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
1008 .init = adv7182_init,
1009 .set_std = adv7182_set_std,
1010 .select_input = adv7182_select_input,
1011};
1012
bf7dcb80 1013static const struct adv7180_chip_info adv7281_info = {
b37135e3
LPC		 1014 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1015 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1016 BIT(ADV7182_INPUT_CVBS_AIN2) |
1017 BIT(ADV7182_INPUT_CVBS_AIN7) |
1018 BIT(ADV7182_INPUT_CVBS_AIN8) |
1019 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1020 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1021 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1022 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1023 .init = adv7182_init,
1024 .set_std = adv7182_set_std,
1025 .select_input = adv7182_select_input,
1026};
1027
1028static const struct adv7180_chip_info adv7281_m_info = {
1029 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1030 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1031 BIT(ADV7182_INPUT_CVBS_AIN2) |
1032 BIT(ADV7182_INPUT_CVBS_AIN3) |
1033 BIT(ADV7182_INPUT_CVBS_AIN4) |
1034 BIT(ADV7182_INPUT_CVBS_AIN7) |
1035 BIT(ADV7182_INPUT_CVBS_AIN8) |
1036 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1037 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1038 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1039 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1040 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1041 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1042 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1043 .init = adv7182_init,
1044 .set_std = adv7182_set_std,
1045 .select_input = adv7182_select_input,
1046};
1047
1048static const struct adv7180_chip_info adv7281_ma_info = {
1049 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
bf7dcb80
LPC		 1050 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1051 BIT(ADV7182_INPUT_CVBS_AIN2) |
b37135e3
LPC		 1052 BIT(ADV7182_INPUT_CVBS_AIN3) |
1053 BIT(ADV7182_INPUT_CVBS_AIN4) |
1054 BIT(ADV7182_INPUT_CVBS_AIN5) |
1055 BIT(ADV7182_INPUT_CVBS_AIN6) |
bf7dcb80
LPC		 1056 BIT(ADV7182_INPUT_CVBS_AIN7) |
1057 BIT(ADV7182_INPUT_CVBS_AIN8) |
1058 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
b37135e3
LPC		 1059 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1060 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
bf7dcb80 1061 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
b37135e3
LPC		 1062 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1063 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
bf7dcb80 1064 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
b37135e3
LPC		 1065 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1066 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
bf7dcb80
LPC		 1067 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1068 .init = adv7182_init,
1069 .set_std = adv7182_set_std,
1070 .select_input = adv7182_select_input,
1071};
1072
851a54ef
LPC		 1073static const struct adv7180_chip_info adv7282_info = {
1074 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
1075 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1076 BIT(ADV7182_INPUT_CVBS_AIN2) |
1077 BIT(ADV7182_INPUT_CVBS_AIN7) |
1078 BIT(ADV7182_INPUT_CVBS_AIN8) |
1079 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1080 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1081 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1082 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1083 .init = adv7182_init,
1084 .set_std = adv7182_set_std,
1085 .select_input = adv7182_select_input,
1086};
1087
1088static const struct adv7180_chip_info adv7282_m_info = {
1089 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
1090 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1091 BIT(ADV7182_INPUT_CVBS_AIN2) |
1092 BIT(ADV7182_INPUT_CVBS_AIN3) |
1093 BIT(ADV7182_INPUT_CVBS_AIN4) |
1094 BIT(ADV7182_INPUT_CVBS_AIN7) |
1095 BIT(ADV7182_INPUT_CVBS_AIN8) |
1096 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1097 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1098 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1099 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1100 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1101 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1102 .init = adv7182_init,
1103 .set_std = adv7182_set_std,
1104 .select_input = adv7182_select_input,
1105};
1106
f5dde49b
LPC		 1107static int init_device(struct adv7180_state *state)
1108{
1109 int ret;
1110
1111 mutex_lock(&state->mutex);
1112
1113 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
1114 usleep_range(2000, 10000);
1115
1116 ret = state->chip_info->init(state);
1117 if (ret)
3999e5d0 1118 goto out_unlock;
42752f7a 1119
f5dde49b
LPC		 1120 ret = adv7180_program_std(state);
1121 if (ret)
1122 goto out_unlock;
42752f7a 1123
851a54ef
LPC		 1124 adv7180_set_field_mode(state);
1125
42752f7a
RR		 1126 /* register for interrupts */
1127 if (state->irq > 0) {
42752f7a 1128 /* config the Interrupt pin to be active low */
3999e5d0 1129 ret = adv7180_write(state, ADV7180_REG_ICONF1,
bca7ad1a
FV		 1130 ADV7180_ICONF1_ACTIVE_LOW |
1131 ADV7180_ICONF1_PSYNC_ONLY);
42752f7a 1132 if (ret < 0)
3999e5d0 1133 goto out_unlock;
42752f7a 1134
3999e5d0 1135 ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
42752f7a 1136 if (ret < 0)
3999e5d0 1137 goto out_unlock;
42752f7a 1138
3999e5d0 1139 ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
42752f7a 1140 if (ret < 0)
3999e5d0 1141 goto out_unlock;
42752f7a
RR		 1142
1143 /* enable AD change interrupts interrupts */
3999e5d0 1144 ret = adv7180_write(state, ADV7180_REG_IMR3,
bca7ad1a 1145 ADV7180_IRQ3_AD_CHANGE);
42752f7a 1146 if (ret < 0)
3999e5d0 1147 goto out_unlock;
42752f7a 1148
3999e5d0 1149 ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
42752f7a 1150 if (ret < 0)
3999e5d0 1151 goto out_unlock;
6789cb52
RR		 1152 }
1153
3999e5d0
LPC		 1154out_unlock:
1155 mutex_unlock(&state->mutex);
df065b37 1156
df065b37 1157 return ret;
bca7ad1a
FV		 1158}
1159
4c62e976
GKH		 1160static int adv7180_probe(struct i2c_client *client,
1161 const struct i2c_device_id *id)
bca7ad1a
FV		 1162{
1163 struct adv7180_state *state;
1164 struct v4l2_subdev *sd;
1165 int ret;
1166
1167 /* Check if the adapter supports the needed features */
1168 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1169 return -EIO;
1170
1171 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1172 client->addr, client->adapter->name);
1173
c02b211d 1174 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
7657e064
FE		 1175 if (state == NULL)
1176 return -ENOMEM;
bca7ad1a 1177
3999e5d0 1178 state->client = client;
851a54ef 1179 state->field = V4L2_FIELD_INTERLACED;
f5dde49b 1180 state->chip_info = (struct adv7180_chip_info *)id->driver_data;
3999e5d0 1181
b37135e3
LPC		 1182 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1183 state->csi_client = i2c_new_dummy(client->adapter,
1184 ADV7180_DEFAULT_CSI_I2C_ADDR);
1185 if (!state->csi_client)
1186 return -ENOMEM;
1187 }
1188
851a54ef
LPC		 1189 if (state->chip_info->flags & ADV7180_FLAG_I2P) {
1190 state->vpp_client = i2c_new_dummy(client->adapter,
1191 ADV7180_DEFAULT_VPP_I2C_ADDR);
1192 if (!state->vpp_client) {
1193 ret = -ENOMEM;
1194 goto err_unregister_csi_client;
1195 }
1196 }
1197
bca7ad1a 1198 state->irq = client->irq;
bca7ad1a
FV		 1199 mutex_init(&state->mutex);
1200 state->autodetect = true;
f5dde49b
LPC		 1201 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
1202 state->powered = true;
1203 else
1204 state->powered = false;
bca7ad1a
FV		 1205 state->input = 0;
1206 sd = &state->sd;
1207 v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
d5d51a82 1208 sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
bca7ad1a 1209
c9fbeddd
FV		 1210 ret = adv7180_init_controls(state);
1211 if (ret)
851a54ef 1212 goto err_unregister_vpp_client;
d5d51a82
LPC		 1213
1214 state->pad.flags = MEDIA_PAD_FL_SOURCE;
1215 sd->entity.flags |= MEDIA_ENT_T_V4L2_SUBDEV_DECODER;
1216 ret = media_entity_init(&sd->entity, 1, &state->pad, 0);
c9fbeddd
FV		 1217 if (ret)
1218 goto err_free_ctrl;
fa5b7945 1219
d5d51a82
LPC		 1220 ret = init_device(state);
1221 if (ret)
1222 goto err_media_entity_cleanup;
1223
fa5721d1
LPC		 1224 if (state->irq) {
1225 ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
f3e991d4
LPC		 1226 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
1227 KBUILD_MODNAME, state);
fa5721d1 1228 if (ret)
d5d51a82 1229 goto err_media_entity_cleanup;
fa5721d1
LPC		 1230 }
1231
fa5b7945
LPC		 1232 ret = v4l2_async_register_subdev(sd);
1233 if (ret)
1234 goto err_free_irq;
1235
6789cb52 1236 return 0;
42752f7a 1237
fa5b7945
LPC		 1238err_free_irq:
1239 if (state->irq > 0)
1240 free_irq(client->irq, state);
d5d51a82
LPC		 1241err_media_entity_cleanup:
1242 media_entity_cleanup(&sd->entity);
c9fbeddd
FV		 1243err_free_ctrl:
1244 adv7180_exit_controls(state);
851a54ef
LPC		 1245err_unregister_vpp_client:
1246 if (state->chip_info->flags & ADV7180_FLAG_I2P)
1247 i2c_unregister_device(state->vpp_client);
b37135e3
LPC		 1248err_unregister_csi_client:
1249 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
1250 i2c_unregister_device(state->csi_client);
297a0ae3 1251 mutex_destroy(&state->mutex);
42752f7a 1252 return ret;
6789cb52
RR		 1253}
1254
4c62e976 1255static int adv7180_remove(struct i2c_client *client)
6789cb52
RR		 1256{
1257 struct v4l2_subdev *sd = i2c_get_clientdata(client);
42752f7a
RR		 1258 struct adv7180_state *state = to_state(sd);
1259
fa5b7945
LPC		 1260 v4l2_async_unregister_subdev(sd);
1261
0c25534d 1262 if (state->irq > 0)
42752f7a 1263 free_irq(client->irq, state);
6789cb52 1264
d5d51a82 1265 media_entity_cleanup(&sd->entity);
b13f4af2 1266 adv7180_exit_controls(state);
b37135e3 1267
851a54ef
LPC		 1268 if (state->chip_info->flags & ADV7180_FLAG_I2P)
1269 i2c_unregister_device(state->vpp_client);
b37135e3
LPC		 1270 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
1271 i2c_unregister_device(state->csi_client);
1272
297a0ae3 1273 mutex_destroy(&state->mutex);
b37135e3 1274
6789cb52
RR		 1275 return 0;
1276}
1277
1278static const struct i2c_device_id adv7180_id[] = {
f5dde49b 1279 { "adv7180", (kernel_ulong_t)&adv7180_info },
c5ef8f8c 1280 { "adv7182", (kernel_ulong_t)&adv7182_info },
bf7dcb80 1281 { "adv7280", (kernel_ulong_t)&adv7280_info },
b37135e3 1282 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
bf7dcb80 1283 { "adv7281", (kernel_ulong_t)&adv7281_info },
b37135e3
LPC		 1284 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
1285 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
851a54ef
LPC		 1286 { "adv7282", (kernel_ulong_t)&adv7282_info },
1287 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
6789cb52
RR		 1288 {},
1289};
f5dde49b 1290MODULE_DEVICE_TABLE(i2c, adv7180_id);
6789cb52 1291
cc1088dc
LPC		 1292#ifdef CONFIG_PM_SLEEP
1293static int adv7180_suspend(struct device *dev)
bca7ad1a 1294{
cc1088dc 1295 struct i2c_client *client = to_i2c_client(dev);
e246c333
LPC		 1296 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1297 struct adv7180_state *state = to_state(sd);
bca7ad1a 1298
3999e5d0 1299 return adv7180_set_power(state, false);
bca7ad1a
FV		 1300}
1301
cc1088dc 1302static int adv7180_resume(struct device *dev)
bca7ad1a 1303{
cc1088dc 1304 struct i2c_client *client = to_i2c_client(dev);
bca7ad1a
FV		 1305 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1306 struct adv7180_state *state = to_state(sd);
1307 int ret;
1308
3999e5d0 1309 ret = init_device(state);
bca7ad1a
FV		 1310 if (ret < 0)
1311 return ret;
c18818e9
LPC		 1312
1313 ret = adv7180_set_power(state, state->powered);
1314 if (ret)
1315 return ret;
1316
bca7ad1a
FV		 1317 return 0;
1318}
cc1088dc
LPC		 1319
1320static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
1321#define ADV7180_PM_OPS (&adv7180_pm_ops)
1322
1323#else
1324#define ADV7180_PM_OPS NULL
bca7ad1a
FV		 1325#endif
1326
6789cb52
RR		 1327static struct i2c_driver adv7180_driver = {
1328 .driver = {
bca7ad1a 1329 .owner = THIS_MODULE,
c9fbeddd 1330 .name = KBUILD_MODNAME,
cc1088dc 1331 .pm = ADV7180_PM_OPS,
bca7ad1a
FV		 1332 },
1333 .probe = adv7180_probe,
4c62e976 1334 .remove = adv7180_remove,
bca7ad1a 1335 .id_table = adv7180_id,
6789cb52
RR		 1336};
1337
c6e8d86f 1338module_i2c_driver(adv7180_driver);
6789cb52
RR		 1339
1340MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
1341MODULE_AUTHOR("Mocean Laboratories");
1342MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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