Commit | Line | Data |
---|---|---|
6789cb52 RR |
1 | /* |
2 | * adv7180.c Analog Devices ADV7180 video decoder driver | |
3 | * Copyright (c) 2009 Intel Corporation | |
cccb83f7 VB |
4 | * Copyright (C) 2013 Cogent Embedded, Inc. |
5 | * Copyright (C) 2013 Renesas Solutions Corp. | |
6789cb52 RR |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/i2c.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
250121d3 | 28 | #include <linux/of.h> |
65d9e14a | 29 | #include <linux/gpio/consumer.h> |
6789cb52 | 30 | #include <linux/videodev2.h> |
937feeed HV |
31 | #include <media/v4l2-ioctl.h> |
32 | #include <media/v4l2-event.h> | |
6789cb52 | 33 | #include <media/v4l2-device.h> |
c9fbeddd | 34 | #include <media/v4l2-ctrls.h> |
42752f7a | 35 | #include <linux/mutex.h> |
c18818e9 | 36 | #include <linux/delay.h> |
6789cb52 | 37 | |
f5dde49b LPC |
38 | #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0 |
39 | #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1 | |
40 | #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2 | |
41 | #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3 | |
42 | #define ADV7180_STD_NTSC_J 0x4 | |
43 | #define ADV7180_STD_NTSC_M 0x5 | |
44 | #define ADV7180_STD_PAL60 0x6 | |
45 | #define ADV7180_STD_NTSC_443 0x7 | |
46 | #define ADV7180_STD_PAL_BG 0x8 | |
47 | #define ADV7180_STD_PAL_N 0x9 | |
48 | #define ADV7180_STD_PAL_M 0xa | |
49 | #define ADV7180_STD_PAL_M_PED 0xb | |
50 | #define ADV7180_STD_PAL_COMB_N 0xc | |
51 | #define ADV7180_STD_PAL_COMB_N_PED 0xd | |
52 | #define ADV7180_STD_PAL_SECAM 0xe | |
53 | #define ADV7180_STD_PAL_SECAM_PED 0xf | |
54 | ||
3999e5d0 | 55 | #define ADV7180_REG_INPUT_CONTROL 0x0000 |
bca7ad1a | 56 | #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f |
d3124294 | 57 | |
c5ef8f8c LPC |
58 | #define ADV7182_REG_INPUT_VIDSEL 0x0002 |
59 | ||
ce5d6290 | 60 | #define ADV7180_REG_OUTPUT_CONTROL 0x0003 |
3999e5d0 | 61 | #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004 |
42752f7a | 62 | #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5 |
6789cb52 | 63 | |
ce5d6290 | 64 | #define ADV7180_REG_AUTODETECT_ENABLE 0x0007 |
42752f7a | 65 | #define ADV7180_AUTODETECT_DEFAULT 0x7f |
c9fbeddd | 66 | /* Contrast */ |
3999e5d0 | 67 | #define ADV7180_REG_CON 0x0008 /*Unsigned */ |
c9fbeddd FV |
68 | #define ADV7180_CON_MIN 0 |
69 | #define ADV7180_CON_DEF 128 | |
70 | #define ADV7180_CON_MAX 255 | |
71 | /* Brightness*/ | |
3999e5d0 | 72 | #define ADV7180_REG_BRI 0x000a /*Signed */ |
c9fbeddd FV |
73 | #define ADV7180_BRI_MIN -128 |
74 | #define ADV7180_BRI_DEF 0 | |
75 | #define ADV7180_BRI_MAX 127 | |
76 | /* Hue */ | |
3999e5d0 | 77 | #define ADV7180_REG_HUE 0x000b /*Signed, inverted */ |
c9fbeddd FV |
78 | #define ADV7180_HUE_MIN -127 |
79 | #define ADV7180_HUE_DEF 0 | |
80 | #define ADV7180_HUE_MAX 128 | |
bca7ad1a | 81 | |
3999e5d0 | 82 | #define ADV7180_REG_CTRL 0x000e |
029d6177 | 83 | #define ADV7180_CTRL_IRQ_SPACE 0x20 |
6789cb52 | 84 | |
029d6177 | 85 | #define ADV7180_REG_PWR_MAN 0x0f |
bca7ad1a FV |
86 | #define ADV7180_PWR_MAN_ON 0x04 |
87 | #define ADV7180_PWR_MAN_OFF 0x24 | |
88 | #define ADV7180_PWR_MAN_RES 0x80 | |
89 | ||
3999e5d0 | 90 | #define ADV7180_REG_STATUS1 0x0010 |
d3124294 RR |
91 | #define ADV7180_STATUS1_IN_LOCK 0x01 |
92 | #define ADV7180_STATUS1_AUTOD_MASK 0x70 | |
6789cb52 RR |
93 | #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00 |
94 | #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10 | |
95 | #define ADV7180_STATUS1_AUTOD_PAL_M 0x20 | |
96 | #define ADV7180_STATUS1_AUTOD_PAL_60 0x30 | |
97 | #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40 | |
98 | #define ADV7180_STATUS1_AUTOD_SECAM 0x50 | |
99 | #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60 | |
100 | #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70 | |
101 | ||
3999e5d0 | 102 | #define ADV7180_REG_IDENT 0x0011 |
6789cb52 RR |
103 | #define ADV7180_ID_7180 0x18 |
104 | ||
ce5d6290 SL |
105 | #define ADV7180_REG_STATUS3 0x0013 |
106 | #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014 | |
107 | #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017 | |
108 | #define ADV7180_REG_CTRL_2 0x001d | |
109 | #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031 | |
110 | #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d | |
111 | #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e | |
112 | #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f | |
113 | #define ADV7180_REG_LOCK_CNT 0x0051 | |
114 | #define ADV7180_REG_CVBS_TRIM 0x0052 | |
115 | #define ADV7180_REG_CLAMP_ADJ 0x005a | |
116 | #define ADV7180_REG_RES_CIR 0x005f | |
117 | #define ADV7180_REG_DIFF_MODE 0x0060 | |
118 | ||
52e37f0a | 119 | #define ADV7180_REG_ICONF1 0x2040 |
42752f7a RR |
120 | #define ADV7180_ICONF1_ACTIVE_LOW 0x01 |
121 | #define ADV7180_ICONF1_PSYNC_ONLY 0x10 | |
122 | #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0 | |
c9fbeddd | 123 | /* Saturation */ |
3999e5d0 LPC |
124 | #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */ |
125 | #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */ | |
c9fbeddd FV |
126 | #define ADV7180_SAT_MIN 0 |
127 | #define ADV7180_SAT_DEF 128 | |
128 | #define ADV7180_SAT_MAX 255 | |
bca7ad1a | 129 | |
42752f7a RR |
130 | #define ADV7180_IRQ1_LOCK 0x01 |
131 | #define ADV7180_IRQ1_UNLOCK 0x02 | |
52e37f0a SL |
132 | #define ADV7180_REG_ISR1 0x2042 |
133 | #define ADV7180_REG_ICR1 0x2043 | |
134 | #define ADV7180_REG_IMR1 0x2044 | |
135 | #define ADV7180_REG_IMR2 0x2048 | |
42752f7a | 136 | #define ADV7180_IRQ3_AD_CHANGE 0x08 |
52e37f0a SL |
137 | #define ADV7180_REG_ISR3 0x204A |
138 | #define ADV7180_REG_ICR3 0x204B | |
139 | #define ADV7180_REG_IMR3 0x204C | |
140 | #define ADV7180_REG_IMR4 0x2050 | |
6789cb52 | 141 | |
3999e5d0 | 142 | #define ADV7180_REG_NTSC_V_BIT_END 0x00E6 |
bca7ad1a FV |
143 | #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F |
144 | ||
851a54ef | 145 | #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD |
b37135e3 LPC |
146 | #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE |
147 | ||
ce5d6290 SL |
148 | #define ADV7180_REG_ACE_CTRL1 0x4080 |
149 | #define ADV7180_REG_ACE_CTRL5 0x4084 | |
150 | #define ADV7180_REG_FLCONTROL 0x40e0 | |
08b717c2 LPC |
151 | #define ADV7180_FLCONTROL_FL_ENABLE 0x1 |
152 | ||
ce5d6290 SL |
153 | #define ADV7180_REG_RST_CLAMP 0x809c |
154 | #define ADV7180_REG_AGC_ADJ1 0x80b6 | |
155 | #define ADV7180_REG_AGC_ADJ2 0x80c0 | |
156 | ||
b37135e3 LPC |
157 | #define ADV7180_CSI_REG_PWRDN 0x00 |
158 | #define ADV7180_CSI_PWRDN 0x80 | |
159 | ||
f5dde49b LPC |
160 | #define ADV7180_INPUT_CVBS_AIN1 0x00 |
161 | #define ADV7180_INPUT_CVBS_AIN2 0x01 | |
162 | #define ADV7180_INPUT_CVBS_AIN3 0x02 | |
163 | #define ADV7180_INPUT_CVBS_AIN4 0x03 | |
164 | #define ADV7180_INPUT_CVBS_AIN5 0x04 | |
165 | #define ADV7180_INPUT_CVBS_AIN6 0x05 | |
166 | #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06 | |
167 | #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07 | |
168 | #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08 | |
169 | #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09 | |
170 | #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a | |
171 | ||
c5ef8f8c LPC |
172 | #define ADV7182_INPUT_CVBS_AIN1 0x00 |
173 | #define ADV7182_INPUT_CVBS_AIN2 0x01 | |
174 | #define ADV7182_INPUT_CVBS_AIN3 0x02 | |
175 | #define ADV7182_INPUT_CVBS_AIN4 0x03 | |
176 | #define ADV7182_INPUT_CVBS_AIN5 0x04 | |
177 | #define ADV7182_INPUT_CVBS_AIN6 0x05 | |
178 | #define ADV7182_INPUT_CVBS_AIN7 0x06 | |
179 | #define ADV7182_INPUT_CVBS_AIN8 0x07 | |
180 | #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08 | |
181 | #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09 | |
182 | #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a | |
183 | #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b | |
184 | #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c | |
185 | #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d | |
186 | #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e | |
187 | #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f | |
188 | #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10 | |
189 | #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11 | |
190 | ||
b37135e3 | 191 | #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44 |
851a54ef | 192 | #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42 |
b37135e3 | 193 | |
08b717c2 LPC |
194 | #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00) |
195 | ||
f5dde49b LPC |
196 | struct adv7180_state; |
197 | ||
198 | #define ADV7180_FLAG_RESET_POWERED BIT(0) | |
bf7dcb80 | 199 | #define ADV7180_FLAG_V2 BIT(1) |
b37135e3 | 200 | #define ADV7180_FLAG_MIPI_CSI2 BIT(2) |
851a54ef | 201 | #define ADV7180_FLAG_I2P BIT(3) |
f5dde49b LPC |
202 | |
203 | struct adv7180_chip_info { | |
204 | unsigned int flags; | |
205 | unsigned int valid_input_mask; | |
206 | int (*set_std)(struct adv7180_state *st, unsigned int std); | |
207 | int (*select_input)(struct adv7180_state *st, unsigned int input); | |
208 | int (*init)(struct adv7180_state *state); | |
209 | }; | |
210 | ||
6789cb52 | 211 | struct adv7180_state { |
c9fbeddd | 212 | struct v4l2_ctrl_handler ctrl_hdl; |
c277b60a | 213 | struct v4l2_subdev sd; |
d5d51a82 | 214 | struct media_pad pad; |
42752f7a RR |
215 | struct mutex mutex; /* mutual excl. when accessing chip */ |
216 | int irq; | |
65d9e14a | 217 | struct gpio_desc *pwdn_gpio; |
c277b60a | 218 | v4l2_std_id curr_norm; |
e246c333 | 219 | bool powered; |
937feeed | 220 | bool streaming; |
bca7ad1a | 221 | u8 input; |
3999e5d0 LPC |
222 | |
223 | struct i2c_client *client; | |
224 | unsigned int register_page; | |
b37135e3 | 225 | struct i2c_client *csi_client; |
851a54ef | 226 | struct i2c_client *vpp_client; |
f5dde49b | 227 | const struct adv7180_chip_info *chip_info; |
851a54ef | 228 | enum v4l2_field field; |
6789cb52 | 229 | }; |
c9fbeddd FV |
230 | #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ |
231 | struct adv7180_state, \ | |
232 | ctrl_hdl)->sd) | |
6789cb52 | 233 | |
3999e5d0 LPC |
234 | static int adv7180_select_page(struct adv7180_state *state, unsigned int page) |
235 | { | |
236 | if (state->register_page != page) { | |
237 | i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL, | |
238 | page); | |
239 | state->register_page = page; | |
240 | } | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static int adv7180_write(struct adv7180_state *state, unsigned int reg, | |
246 | unsigned int value) | |
247 | { | |
248 | lockdep_assert_held(&state->mutex); | |
249 | adv7180_select_page(state, reg >> 8); | |
250 | return i2c_smbus_write_byte_data(state->client, reg & 0xff, value); | |
251 | } | |
252 | ||
253 | static int adv7180_read(struct adv7180_state *state, unsigned int reg) | |
254 | { | |
255 | lockdep_assert_held(&state->mutex); | |
256 | adv7180_select_page(state, reg >> 8); | |
257 | return i2c_smbus_read_byte_data(state->client, reg & 0xff); | |
258 | } | |
259 | ||
b37135e3 LPC |
260 | static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg, |
261 | unsigned int value) | |
262 | { | |
263 | return i2c_smbus_write_byte_data(state->csi_client, reg, value); | |
264 | } | |
265 | ||
f5dde49b LPC |
266 | static int adv7180_set_video_standard(struct adv7180_state *state, |
267 | unsigned int std) | |
268 | { | |
269 | return state->chip_info->set_std(state, std); | |
270 | } | |
3999e5d0 | 271 | |
851a54ef LPC |
272 | static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg, |
273 | unsigned int value) | |
274 | { | |
275 | return i2c_smbus_write_byte_data(state->vpp_client, reg, value); | |
276 | } | |
277 | ||
d3124294 | 278 | static v4l2_std_id adv7180_std_to_v4l2(u8 status1) |
6789cb52 | 279 | { |
b294a192 VB |
280 | /* in case V4L2_IN_ST_NO_SIGNAL */ |
281 | if (!(status1 & ADV7180_STATUS1_IN_LOCK)) | |
282 | return V4L2_STD_UNKNOWN; | |
283 | ||
6789cb52 RR |
284 | switch (status1 & ADV7180_STATUS1_AUTOD_MASK) { |
285 | case ADV7180_STATUS1_AUTOD_NTSM_M_J: | |
d3124294 | 286 | return V4L2_STD_NTSC; |
6789cb52 RR |
287 | case ADV7180_STATUS1_AUTOD_NTSC_4_43: |
288 | return V4L2_STD_NTSC_443; | |
289 | case ADV7180_STATUS1_AUTOD_PAL_M: | |
290 | return V4L2_STD_PAL_M; | |
291 | case ADV7180_STATUS1_AUTOD_PAL_60: | |
292 | return V4L2_STD_PAL_60; | |
293 | case ADV7180_STATUS1_AUTOD_PAL_B_G: | |
294 | return V4L2_STD_PAL; | |
295 | case ADV7180_STATUS1_AUTOD_SECAM: | |
296 | return V4L2_STD_SECAM; | |
297 | case ADV7180_STATUS1_AUTOD_PAL_COMB: | |
298 | return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N; | |
299 | case ADV7180_STATUS1_AUTOD_SECAM_525: | |
300 | return V4L2_STD_SECAM; | |
301 | default: | |
302 | return V4L2_STD_UNKNOWN; | |
303 | } | |
304 | } | |
305 | ||
c277b60a RR |
306 | static int v4l2_std_to_adv7180(v4l2_std_id std) |
307 | { | |
308 | if (std == V4L2_STD_PAL_60) | |
f5dde49b | 309 | return ADV7180_STD_PAL60; |
c277b60a | 310 | if (std == V4L2_STD_NTSC_443) |
f5dde49b | 311 | return ADV7180_STD_NTSC_443; |
c277b60a | 312 | if (std == V4L2_STD_PAL_N) |
f5dde49b | 313 | return ADV7180_STD_PAL_N; |
c277b60a | 314 | if (std == V4L2_STD_PAL_M) |
f5dde49b | 315 | return ADV7180_STD_PAL_M; |
c277b60a | 316 | if (std == V4L2_STD_PAL_Nc) |
f5dde49b | 317 | return ADV7180_STD_PAL_COMB_N; |
c277b60a RR |
318 | |
319 | if (std & V4L2_STD_PAL) | |
f5dde49b | 320 | return ADV7180_STD_PAL_BG; |
c277b60a | 321 | if (std & V4L2_STD_NTSC) |
f5dde49b | 322 | return ADV7180_STD_NTSC_M; |
c277b60a | 323 | if (std & V4L2_STD_SECAM) |
f5dde49b | 324 | return ADV7180_STD_PAL_SECAM; |
c277b60a RR |
325 | |
326 | return -EINVAL; | |
327 | } | |
328 | ||
d3124294 RR |
329 | static u32 adv7180_status_to_v4l2(u8 status1) |
330 | { | |
331 | if (!(status1 & ADV7180_STATUS1_IN_LOCK)) | |
332 | return V4L2_IN_ST_NO_SIGNAL; | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
3999e5d0 | 337 | static int __adv7180_status(struct adv7180_state *state, u32 *status, |
bca7ad1a | 338 | v4l2_std_id *std) |
d3124294 | 339 | { |
3999e5d0 | 340 | int status1 = adv7180_read(state, ADV7180_REG_STATUS1); |
d3124294 RR |
341 | |
342 | if (status1 < 0) | |
343 | return status1; | |
344 | ||
345 | if (status) | |
346 | *status = adv7180_status_to_v4l2(status1); | |
347 | if (std) | |
348 | *std = adv7180_std_to_v4l2(status1); | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
6789cb52 RR |
353 | static inline struct adv7180_state *to_state(struct v4l2_subdev *sd) |
354 | { | |
355 | return container_of(sd, struct adv7180_state, sd); | |
356 | } | |
357 | ||
358 | static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) | |
359 | { | |
c277b60a | 360 | struct adv7180_state *state = to_state(sd); |
42752f7a RR |
361 | int err = mutex_lock_interruptible(&state->mutex); |
362 | if (err) | |
363 | return err; | |
c277b60a | 364 | |
937feeed HV |
365 | if (state->streaming) { |
366 | err = -EBUSY; | |
367 | goto unlock; | |
368 | } | |
369 | ||
370 | err = adv7180_set_video_standard(state, | |
371 | ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM); | |
372 | if (err) | |
373 | goto unlock; | |
c277b60a | 374 | |
937feeed HV |
375 | msleep(100); |
376 | __adv7180_status(state, NULL, std); | |
377 | ||
378 | err = v4l2_std_to_adv7180(state->curr_norm); | |
379 | if (err < 0) | |
380 | goto unlock; | |
381 | ||
382 | err = adv7180_set_video_standard(state, err); | |
383 | ||
384 | unlock: | |
42752f7a | 385 | mutex_unlock(&state->mutex); |
c277b60a | 386 | return err; |
d3124294 | 387 | } |
6789cb52 | 388 | |
bca7ad1a FV |
389 | static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input, |
390 | u32 output, u32 config) | |
391 | { | |
392 | struct adv7180_state *state = to_state(sd); | |
393 | int ret = mutex_lock_interruptible(&state->mutex); | |
bca7ad1a FV |
394 | |
395 | if (ret) | |
396 | return ret; | |
397 | ||
f5dde49b LPC |
398 | if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { |
399 | ret = -EINVAL; | |
bca7ad1a | 400 | goto out; |
f5dde49b | 401 | } |
bca7ad1a | 402 | |
f5dde49b | 403 | ret = state->chip_info->select_input(state, input); |
bca7ad1a | 404 | |
f5dde49b LPC |
405 | if (ret == 0) |
406 | state->input = input; | |
bca7ad1a FV |
407 | out: |
408 | mutex_unlock(&state->mutex); | |
409 | return ret; | |
410 | } | |
411 | ||
d3124294 RR |
412 | static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status) |
413 | { | |
42752f7a RR |
414 | struct adv7180_state *state = to_state(sd); |
415 | int ret = mutex_lock_interruptible(&state->mutex); | |
416 | if (ret) | |
417 | return ret; | |
418 | ||
3999e5d0 | 419 | ret = __adv7180_status(state, status, NULL); |
42752f7a RR |
420 | mutex_unlock(&state->mutex); |
421 | return ret; | |
6789cb52 RR |
422 | } |
423 | ||
3e35e33c | 424 | static int adv7180_program_std(struct adv7180_state *state) |
c277b60a | 425 | { |
3e35e33c | 426 | int ret; |
c277b60a | 427 | |
937feeed HV |
428 | ret = v4l2_std_to_adv7180(state->curr_norm); |
429 | if (ret < 0) | |
430 | return ret; | |
3e35e33c | 431 | |
937feeed HV |
432 | ret = adv7180_set_video_standard(state, ret); |
433 | if (ret < 0) | |
434 | return ret; | |
3e35e33c LPC |
435 | return 0; |
436 | } | |
437 | ||
438 | static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std) | |
439 | { | |
440 | struct adv7180_state *state = to_state(sd); | |
441 | int ret = mutex_lock_interruptible(&state->mutex); | |
442 | ||
443 | if (ret) | |
444 | return ret; | |
445 | ||
937feeed HV |
446 | /* Make sure we can support this std */ |
447 | ret = v4l2_std_to_adv7180(std); | |
448 | if (ret < 0) | |
449 | goto out; | |
c277b60a | 450 | |
937feeed | 451 | state->curr_norm = std; |
3e35e33c LPC |
452 | |
453 | ret = adv7180_program_std(state); | |
c277b60a | 454 | out: |
42752f7a | 455 | mutex_unlock(&state->mutex); |
c277b60a RR |
456 | return ret; |
457 | } | |
458 | ||
d0fadc86 NS |
459 | static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) |
460 | { | |
461 | struct adv7180_state *state = to_state(sd); | |
462 | ||
463 | *norm = state->curr_norm; | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
65d9e14a SL |
468 | static void adv7180_set_power_pin(struct adv7180_state *state, bool on) |
469 | { | |
470 | if (!state->pwdn_gpio) | |
471 | return; | |
472 | ||
473 | if (on) { | |
474 | gpiod_set_value_cansleep(state->pwdn_gpio, 0); | |
475 | usleep_range(5000, 10000); | |
476 | } else { | |
477 | gpiod_set_value_cansleep(state->pwdn_gpio, 1); | |
478 | } | |
479 | } | |
480 | ||
3999e5d0 | 481 | static int adv7180_set_power(struct adv7180_state *state, bool on) |
e246c333 LPC |
482 | { |
483 | u8 val; | |
b37135e3 | 484 | int ret; |
e246c333 LPC |
485 | |
486 | if (on) | |
487 | val = ADV7180_PWR_MAN_ON; | |
488 | else | |
489 | val = ADV7180_PWR_MAN_OFF; | |
490 | ||
b37135e3 LPC |
491 | ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); |
492 | if (ret) | |
493 | return ret; | |
494 | ||
495 | if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { | |
496 | if (on) { | |
497 | adv7180_csi_write(state, 0xDE, 0x02); | |
498 | adv7180_csi_write(state, 0xD2, 0xF7); | |
499 | adv7180_csi_write(state, 0xD8, 0x65); | |
500 | adv7180_csi_write(state, 0xE0, 0x09); | |
501 | adv7180_csi_write(state, 0x2C, 0x00); | |
851a54ef LPC |
502 | if (state->field == V4L2_FIELD_NONE) |
503 | adv7180_csi_write(state, 0x1D, 0x80); | |
b37135e3 LPC |
504 | adv7180_csi_write(state, 0x00, 0x00); |
505 | } else { | |
506 | adv7180_csi_write(state, 0x00, 0x80); | |
507 | } | |
508 | } | |
509 | ||
510 | return 0; | |
e246c333 LPC |
511 | } |
512 | ||
513 | static int adv7180_s_power(struct v4l2_subdev *sd, int on) | |
514 | { | |
515 | struct adv7180_state *state = to_state(sd); | |
e246c333 LPC |
516 | int ret; |
517 | ||
518 | ret = mutex_lock_interruptible(&state->mutex); | |
519 | if (ret) | |
520 | return ret; | |
521 | ||
3999e5d0 | 522 | ret = adv7180_set_power(state, on); |
e246c333 LPC |
523 | if (ret == 0) |
524 | state->powered = on; | |
525 | ||
526 | mutex_unlock(&state->mutex); | |
527 | return ret; | |
528 | } | |
529 | ||
c9fbeddd | 530 | static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) |
bca7ad1a | 531 | { |
c9fbeddd | 532 | struct v4l2_subdev *sd = to_adv7180_sd(ctrl); |
bca7ad1a | 533 | struct adv7180_state *state = to_state(sd); |
bca7ad1a | 534 | int ret = mutex_lock_interruptible(&state->mutex); |
c9fbeddd FV |
535 | int val; |
536 | ||
bca7ad1a FV |
537 | if (ret) |
538 | return ret; | |
c9fbeddd | 539 | val = ctrl->val; |
bca7ad1a FV |
540 | switch (ctrl->id) { |
541 | case V4L2_CID_BRIGHTNESS: | |
3999e5d0 | 542 | ret = adv7180_write(state, ADV7180_REG_BRI, val); |
bca7ad1a FV |
543 | break; |
544 | case V4L2_CID_HUE: | |
bca7ad1a | 545 | /*Hue is inverted according to HSL chart */ |
3999e5d0 | 546 | ret = adv7180_write(state, ADV7180_REG_HUE, -val); |
bca7ad1a FV |
547 | break; |
548 | case V4L2_CID_CONTRAST: | |
3999e5d0 | 549 | ret = adv7180_write(state, ADV7180_REG_CON, val); |
bca7ad1a FV |
550 | break; |
551 | case V4L2_CID_SATURATION: | |
bca7ad1a FV |
552 | /* |
553 | *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE | |
554 | *Let's not confuse the user, everybody understands saturation | |
555 | */ | |
3999e5d0 | 556 | ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); |
bca7ad1a FV |
557 | if (ret < 0) |
558 | break; | |
3999e5d0 | 559 | ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); |
bca7ad1a | 560 | break; |
08b717c2 LPC |
561 | case V4L2_CID_ADV_FAST_SWITCH: |
562 | if (ctrl->val) { | |
563 | /* ADI required write */ | |
564 | adv7180_write(state, 0x80d9, 0x44); | |
565 | adv7180_write(state, ADV7180_REG_FLCONTROL, | |
566 | ADV7180_FLCONTROL_FL_ENABLE); | |
567 | } else { | |
568 | /* ADI required write */ | |
569 | adv7180_write(state, 0x80d9, 0xc4); | |
570 | adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); | |
571 | } | |
572 | break; | |
bca7ad1a FV |
573 | default: |
574 | ret = -EINVAL; | |
575 | } | |
576 | ||
577 | mutex_unlock(&state->mutex); | |
578 | return ret; | |
579 | } | |
580 | ||
c9fbeddd FV |
581 | static const struct v4l2_ctrl_ops adv7180_ctrl_ops = { |
582 | .s_ctrl = adv7180_s_ctrl, | |
583 | }; | |
584 | ||
08b717c2 LPC |
585 | static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = { |
586 | .ops = &adv7180_ctrl_ops, | |
587 | .id = V4L2_CID_ADV_FAST_SWITCH, | |
588 | .name = "Fast Switching", | |
589 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
590 | .min = 0, | |
591 | .max = 1, | |
592 | .step = 1, | |
593 | }; | |
594 | ||
c9fbeddd FV |
595 | static int adv7180_init_controls(struct adv7180_state *state) |
596 | { | |
597 | v4l2_ctrl_handler_init(&state->ctrl_hdl, 4); | |
598 | ||
599 | v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, | |
600 | V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN, | |
601 | ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF); | |
602 | v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, | |
603 | V4L2_CID_CONTRAST, ADV7180_CON_MIN, | |
604 | ADV7180_CON_MAX, 1, ADV7180_CON_DEF); | |
605 | v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, | |
606 | V4L2_CID_SATURATION, ADV7180_SAT_MIN, | |
607 | ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF); | |
608 | v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, | |
609 | V4L2_CID_HUE, ADV7180_HUE_MIN, | |
610 | ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF); | |
08b717c2 LPC |
611 | v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL); |
612 | ||
c9fbeddd FV |
613 | state->sd.ctrl_handler = &state->ctrl_hdl; |
614 | if (state->ctrl_hdl.error) { | |
615 | int err = state->ctrl_hdl.error; | |
616 | ||
617 | v4l2_ctrl_handler_free(&state->ctrl_hdl); | |
618 | return err; | |
619 | } | |
620 | v4l2_ctrl_handler_setup(&state->ctrl_hdl); | |
621 | ||
622 | return 0; | |
623 | } | |
624 | static void adv7180_exit_controls(struct adv7180_state *state) | |
625 | { | |
626 | v4l2_ctrl_handler_free(&state->ctrl_hdl); | |
627 | } | |
628 | ||
d5d51a82 | 629 | static int adv7180_enum_mbus_code(struct v4l2_subdev *sd, |
f7234138 | 630 | struct v4l2_subdev_pad_config *cfg, |
d5d51a82 | 631 | struct v4l2_subdev_mbus_code_enum *code) |
cccb83f7 | 632 | { |
d5d51a82 | 633 | if (code->index != 0) |
cccb83f7 VB |
634 | return -EINVAL; |
635 | ||
d5d51a82 | 636 | code->code = MEDIA_BUS_FMT_YUYV8_2X8; |
cccb83f7 VB |
637 | |
638 | return 0; | |
639 | } | |
640 | ||
641 | static int adv7180_mbus_fmt(struct v4l2_subdev *sd, | |
642 | struct v4l2_mbus_framefmt *fmt) | |
643 | { | |
644 | struct adv7180_state *state = to_state(sd); | |
645 | ||
f5fe58fd | 646 | fmt->code = MEDIA_BUS_FMT_YUYV8_2X8; |
cccb83f7 | 647 | fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; |
cccb83f7 VB |
648 | fmt->width = 720; |
649 | fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576; | |
650 | ||
651 | return 0; | |
652 | } | |
653 | ||
851a54ef LPC |
654 | static int adv7180_set_field_mode(struct adv7180_state *state) |
655 | { | |
656 | if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) | |
657 | return 0; | |
658 | ||
659 | if (state->field == V4L2_FIELD_NONE) { | |
660 | if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { | |
661 | adv7180_csi_write(state, 0x01, 0x20); | |
662 | adv7180_csi_write(state, 0x02, 0x28); | |
663 | adv7180_csi_write(state, 0x03, 0x38); | |
664 | adv7180_csi_write(state, 0x04, 0x30); | |
665 | adv7180_csi_write(state, 0x05, 0x30); | |
666 | adv7180_csi_write(state, 0x06, 0x80); | |
667 | adv7180_csi_write(state, 0x07, 0x70); | |
668 | adv7180_csi_write(state, 0x08, 0x50); | |
669 | } | |
670 | adv7180_vpp_write(state, 0xa3, 0x00); | |
671 | adv7180_vpp_write(state, 0x5b, 0x00); | |
672 | adv7180_vpp_write(state, 0x55, 0x80); | |
673 | } else { | |
674 | if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { | |
675 | adv7180_csi_write(state, 0x01, 0x18); | |
676 | adv7180_csi_write(state, 0x02, 0x18); | |
677 | adv7180_csi_write(state, 0x03, 0x30); | |
678 | adv7180_csi_write(state, 0x04, 0x20); | |
679 | adv7180_csi_write(state, 0x05, 0x28); | |
680 | adv7180_csi_write(state, 0x06, 0x40); | |
681 | adv7180_csi_write(state, 0x07, 0x58); | |
682 | adv7180_csi_write(state, 0x08, 0x30); | |
683 | } | |
684 | adv7180_vpp_write(state, 0xa3, 0x70); | |
685 | adv7180_vpp_write(state, 0x5b, 0x80); | |
686 | adv7180_vpp_write(state, 0x55, 0x00); | |
687 | } | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
d5d51a82 | 692 | static int adv7180_get_pad_format(struct v4l2_subdev *sd, |
f7234138 | 693 | struct v4l2_subdev_pad_config *cfg, |
d5d51a82 LPC |
694 | struct v4l2_subdev_format *format) |
695 | { | |
851a54ef LPC |
696 | struct adv7180_state *state = to_state(sd); |
697 | ||
698 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
f7234138 | 699 | format->format = *v4l2_subdev_get_try_format(sd, cfg, 0); |
851a54ef LPC |
700 | } else { |
701 | adv7180_mbus_fmt(sd, &format->format); | |
702 | format->format.field = state->field; | |
703 | } | |
704 | ||
705 | return 0; | |
d5d51a82 LPC |
706 | } |
707 | ||
708 | static int adv7180_set_pad_format(struct v4l2_subdev *sd, | |
f7234138 | 709 | struct v4l2_subdev_pad_config *cfg, |
d5d51a82 LPC |
710 | struct v4l2_subdev_format *format) |
711 | { | |
851a54ef LPC |
712 | struct adv7180_state *state = to_state(sd); |
713 | struct v4l2_mbus_framefmt *framefmt; | |
714 | ||
715 | switch (format->format.field) { | |
716 | case V4L2_FIELD_NONE: | |
717 | if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) | |
718 | format->format.field = V4L2_FIELD_INTERLACED; | |
719 | break; | |
720 | default: | |
721 | format->format.field = V4L2_FIELD_INTERLACED; | |
722 | break; | |
723 | } | |
724 | ||
725 | if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { | |
726 | framefmt = &format->format; | |
727 | if (state->field != format->format.field) { | |
728 | state->field = format->format.field; | |
729 | adv7180_set_power(state, false); | |
730 | adv7180_set_field_mode(state); | |
731 | adv7180_set_power(state, true); | |
732 | } | |
733 | } else { | |
f7234138 | 734 | framefmt = v4l2_subdev_get_try_format(sd, cfg, 0); |
851a54ef LPC |
735 | *framefmt = format->format; |
736 | } | |
737 | ||
738 | return adv7180_mbus_fmt(sd, framefmt); | |
d5d51a82 LPC |
739 | } |
740 | ||
cccb83f7 VB |
741 | static int adv7180_g_mbus_config(struct v4l2_subdev *sd, |
742 | struct v4l2_mbus_config *cfg) | |
743 | { | |
b37135e3 LPC |
744 | struct adv7180_state *state = to_state(sd); |
745 | ||
746 | if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { | |
747 | cfg->type = V4L2_MBUS_CSI2; | |
748 | cfg->flags = V4L2_MBUS_CSI2_1_LANE | | |
749 | V4L2_MBUS_CSI2_CHANNEL_0 | | |
750 | V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; | |
751 | } else { | |
752 | /* | |
753 | * The ADV7180 sensor supports BT.601/656 output modes. | |
754 | * The BT.656 is default and not yet configurable by s/w. | |
755 | */ | |
756 | cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
757 | V4L2_MBUS_DATA_ACTIVE_HIGH; | |
758 | cfg->type = V4L2_MBUS_BT656; | |
759 | } | |
cccb83f7 VB |
760 | |
761 | return 0; | |
762 | } | |
763 | ||
ecf37493 | 764 | static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect) |
64b3df92 NS |
765 | { |
766 | struct adv7180_state *state = to_state(sd); | |
767 | ||
768 | if (state->curr_norm & V4L2_STD_525_60) { | |
ecf37493 HV |
769 | aspect->numerator = 11; |
770 | aspect->denominator = 10; | |
64b3df92 | 771 | } else { |
ecf37493 HV |
772 | aspect->numerator = 54; |
773 | aspect->denominator = 59; | |
64b3df92 NS |
774 | } |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
bae4c757 NS |
779 | static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm) |
780 | { | |
781 | *norm = V4L2_STD_ALL; | |
782 | return 0; | |
783 | } | |
784 | ||
937feeed HV |
785 | static int adv7180_s_stream(struct v4l2_subdev *sd, int enable) |
786 | { | |
787 | struct adv7180_state *state = to_state(sd); | |
788 | int ret; | |
789 | ||
790 | /* It's always safe to stop streaming, no need to take the lock */ | |
791 | if (!enable) { | |
792 | state->streaming = enable; | |
793 | return 0; | |
794 | } | |
795 | ||
796 | /* Must wait until querystd released the lock */ | |
797 | ret = mutex_lock_interruptible(&state->mutex); | |
798 | if (ret) | |
799 | return ret; | |
800 | state->streaming = enable; | |
801 | mutex_unlock(&state->mutex); | |
802 | return 0; | |
803 | } | |
804 | ||
805 | static int adv7180_subscribe_event(struct v4l2_subdev *sd, | |
806 | struct v4l2_fh *fh, | |
807 | struct v4l2_event_subscription *sub) | |
808 | { | |
809 | switch (sub->type) { | |
810 | case V4L2_EVENT_SOURCE_CHANGE: | |
811 | return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); | |
812 | case V4L2_EVENT_CTRL: | |
813 | return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); | |
814 | default: | |
815 | return -EINVAL; | |
816 | } | |
817 | } | |
818 | ||
6789cb52 | 819 | static const struct v4l2_subdev_video_ops adv7180_video_ops = { |
8774bed9 | 820 | .s_std = adv7180_s_std, |
d0fadc86 | 821 | .g_std = adv7180_g_std, |
6789cb52 | 822 | .querystd = adv7180_querystd, |
d3124294 | 823 | .g_input_status = adv7180_g_input_status, |
bca7ad1a | 824 | .s_routing = adv7180_s_routing, |
cccb83f7 | 825 | .g_mbus_config = adv7180_g_mbus_config, |
ecf37493 | 826 | .g_pixelaspect = adv7180_g_pixelaspect, |
bae4c757 | 827 | .g_tvnorms = adv7180_g_tvnorms, |
937feeed | 828 | .s_stream = adv7180_s_stream, |
6789cb52 RR |
829 | }; |
830 | ||
831 | static const struct v4l2_subdev_core_ops adv7180_core_ops = { | |
e246c333 | 832 | .s_power = adv7180_s_power, |
937feeed HV |
833 | .subscribe_event = adv7180_subscribe_event, |
834 | .unsubscribe_event = v4l2_event_subdev_unsubscribe, | |
6789cb52 RR |
835 | }; |
836 | ||
d5d51a82 LPC |
837 | static const struct v4l2_subdev_pad_ops adv7180_pad_ops = { |
838 | .enum_mbus_code = adv7180_enum_mbus_code, | |
839 | .set_fmt = adv7180_set_pad_format, | |
840 | .get_fmt = adv7180_get_pad_format, | |
841 | }; | |
842 | ||
6789cb52 RR |
843 | static const struct v4l2_subdev_ops adv7180_ops = { |
844 | .core = &adv7180_core_ops, | |
845 | .video = &adv7180_video_ops, | |
d5d51a82 | 846 | .pad = &adv7180_pad_ops, |
6789cb52 RR |
847 | }; |
848 | ||
0c25534d | 849 | static irqreturn_t adv7180_irq(int irq, void *devid) |
42752f7a | 850 | { |
0c25534d | 851 | struct adv7180_state *state = devid; |
42752f7a RR |
852 | u8 isr3; |
853 | ||
854 | mutex_lock(&state->mutex); | |
3999e5d0 | 855 | isr3 = adv7180_read(state, ADV7180_REG_ISR3); |
42752f7a | 856 | /* clear */ |
3999e5d0 | 857 | adv7180_write(state, ADV7180_REG_ICR3, isr3); |
42752f7a | 858 | |
937feeed HV |
859 | if (isr3 & ADV7180_IRQ3_AD_CHANGE) { |
860 | static const struct v4l2_event src_ch = { | |
861 | .type = V4L2_EVENT_SOURCE_CHANGE, | |
862 | .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, | |
863 | }; | |
864 | ||
865 | v4l2_subdev_notify_event(&state->sd, &src_ch); | |
866 | } | |
42752f7a RR |
867 | mutex_unlock(&state->mutex); |
868 | ||
42752f7a RR |
869 | return IRQ_HANDLED; |
870 | } | |
871 | ||
f5dde49b | 872 | static int adv7180_init(struct adv7180_state *state) |
6789cb52 | 873 | { |
6789cb52 RR |
874 | int ret; |
875 | ||
42752f7a | 876 | /* ITU-R BT.656-4 compatible */ |
3999e5d0 | 877 | ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, |
bca7ad1a | 878 | ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); |
42752f7a | 879 | if (ret < 0) |
f5dde49b | 880 | return ret; |
bca7ad1a FV |
881 | |
882 | /* Manually set V bit end position in NTSC mode */ | |
f5dde49b | 883 | return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END, |
bca7ad1a | 884 | ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); |
f5dde49b LPC |
885 | } |
886 | ||
887 | static int adv7180_set_std(struct adv7180_state *state, unsigned int std) | |
888 | { | |
889 | return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, | |
890 | (std << 4) | state->input); | |
891 | } | |
892 | ||
893 | static int adv7180_select_input(struct adv7180_state *state, unsigned int input) | |
894 | { | |
895 | int ret; | |
896 | ||
897 | ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL); | |
bca7ad1a | 898 | if (ret < 0) |
f5dde49b LPC |
899 | return ret; |
900 | ||
901 | ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK; | |
902 | ret |= input; | |
903 | return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret); | |
904 | } | |
905 | ||
c5ef8f8c LPC |
906 | static int adv7182_init(struct adv7180_state *state) |
907 | { | |
b37135e3 LPC |
908 | if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) |
909 | adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR, | |
910 | ADV7180_DEFAULT_CSI_I2C_ADDR << 1); | |
911 | ||
851a54ef LPC |
912 | if (state->chip_info->flags & ADV7180_FLAG_I2P) |
913 | adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR, | |
914 | ADV7180_DEFAULT_VPP_I2C_ADDR << 1); | |
915 | ||
bf7dcb80 LPC |
916 | if (state->chip_info->flags & ADV7180_FLAG_V2) { |
917 | /* ADI recommended writes for improved video quality */ | |
918 | adv7180_write(state, 0x0080, 0x51); | |
919 | adv7180_write(state, 0x0081, 0x51); | |
920 | adv7180_write(state, 0x0082, 0x68); | |
bf7dcb80 LPC |
921 | } |
922 | ||
c5ef8f8c | 923 | /* ADI required writes */ |
b37135e3 | 924 | if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { |
ce5d6290 SL |
925 | adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e); |
926 | adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57); | |
927 | adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0); | |
b37135e3 LPC |
928 | } else { |
929 | if (state->chip_info->flags & ADV7180_FLAG_V2) | |
ce5d6290 SL |
930 | adv7180_write(state, |
931 | ADV7180_REG_EXTENDED_OUTPUT_CONTROL, | |
932 | 0x17); | |
b37135e3 | 933 | else |
ce5d6290 SL |
934 | adv7180_write(state, |
935 | ADV7180_REG_EXTENDED_OUTPUT_CONTROL, | |
936 | 0x07); | |
937 | adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c); | |
938 | adv7180_write(state, ADV7180_REG_CTRL_2, 0x40); | |
b37135e3 LPC |
939 | } |
940 | ||
c5ef8f8c | 941 | adv7180_write(state, 0x0013, 0x00); |
c5ef8f8c LPC |
942 | |
943 | return 0; | |
944 | } | |
945 | ||
946 | static int adv7182_set_std(struct adv7180_state *state, unsigned int std) | |
947 | { | |
948 | return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4); | |
949 | } | |
950 | ||
951 | enum adv7182_input_type { | |
952 | ADV7182_INPUT_TYPE_CVBS, | |
953 | ADV7182_INPUT_TYPE_DIFF_CVBS, | |
954 | ADV7182_INPUT_TYPE_SVIDEO, | |
955 | ADV7182_INPUT_TYPE_YPBPR, | |
956 | }; | |
957 | ||
958 | static enum adv7182_input_type adv7182_get_input_type(unsigned int input) | |
959 | { | |
960 | switch (input) { | |
961 | case ADV7182_INPUT_CVBS_AIN1: | |
962 | case ADV7182_INPUT_CVBS_AIN2: | |
963 | case ADV7182_INPUT_CVBS_AIN3: | |
964 | case ADV7182_INPUT_CVBS_AIN4: | |
965 | case ADV7182_INPUT_CVBS_AIN5: | |
966 | case ADV7182_INPUT_CVBS_AIN6: | |
967 | case ADV7182_INPUT_CVBS_AIN7: | |
968 | case ADV7182_INPUT_CVBS_AIN8: | |
969 | return ADV7182_INPUT_TYPE_CVBS; | |
970 | case ADV7182_INPUT_SVIDEO_AIN1_AIN2: | |
971 | case ADV7182_INPUT_SVIDEO_AIN3_AIN4: | |
972 | case ADV7182_INPUT_SVIDEO_AIN5_AIN6: | |
973 | case ADV7182_INPUT_SVIDEO_AIN7_AIN8: | |
974 | return ADV7182_INPUT_TYPE_SVIDEO; | |
975 | case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3: | |
976 | case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6: | |
977 | return ADV7182_INPUT_TYPE_YPBPR; | |
978 | case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2: | |
979 | case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4: | |
980 | case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6: | |
981 | case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8: | |
982 | return ADV7182_INPUT_TYPE_DIFF_CVBS; | |
983 | default: /* Will never happen */ | |
984 | return 0; | |
985 | } | |
986 | } | |
987 | ||
988 | /* ADI recommended writes to registers 0x52, 0x53, 0x54 */ | |
989 | static unsigned int adv7182_lbias_settings[][3] = { | |
990 | [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 }, | |
991 | [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, | |
992 | [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, | |
993 | [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, | |
994 | }; | |
995 | ||
bf7dcb80 LPC |
996 | static unsigned int adv7280_lbias_settings[][3] = { |
997 | [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 }, | |
998 | [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, | |
999 | [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, | |
1000 | [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, | |
1001 | }; | |
1002 | ||
c5ef8f8c LPC |
1003 | static int adv7182_select_input(struct adv7180_state *state, unsigned int input) |
1004 | { | |
1005 | enum adv7182_input_type input_type; | |
1006 | unsigned int *lbias; | |
1007 | unsigned int i; | |
1008 | int ret; | |
1009 | ||
1010 | ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input); | |
1011 | if (ret) | |
1012 | return ret; | |
1013 | ||
1014 | /* Reset clamp circuitry - ADI recommended writes */ | |
ce5d6290 SL |
1015 | adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00); |
1016 | adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff); | |
c5ef8f8c LPC |
1017 | |
1018 | input_type = adv7182_get_input_type(input); | |
1019 | ||
1020 | switch (input_type) { | |
1021 | case ADV7182_INPUT_TYPE_CVBS: | |
1022 | case ADV7182_INPUT_TYPE_DIFF_CVBS: | |
1023 | /* ADI recommends to use the SH1 filter */ | |
ce5d6290 | 1024 | adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41); |
c5ef8f8c LPC |
1025 | break; |
1026 | default: | |
ce5d6290 | 1027 | adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01); |
c5ef8f8c LPC |
1028 | break; |
1029 | } | |
1030 | ||
bf7dcb80 LPC |
1031 | if (state->chip_info->flags & ADV7180_FLAG_V2) |
1032 | lbias = adv7280_lbias_settings[input_type]; | |
1033 | else | |
1034 | lbias = adv7182_lbias_settings[input_type]; | |
c5ef8f8c LPC |
1035 | |
1036 | for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++) | |
ce5d6290 | 1037 | adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]); |
c5ef8f8c LPC |
1038 | |
1039 | if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) { | |
1040 | /* ADI required writes to make differential CVBS work */ | |
ce5d6290 SL |
1041 | adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8); |
1042 | adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90); | |
1043 | adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0); | |
1044 | adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08); | |
1045 | adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0); | |
c5ef8f8c | 1046 | } else { |
ce5d6290 SL |
1047 | adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0); |
1048 | adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0); | |
1049 | adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10); | |
1050 | adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c); | |
1051 | adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00); | |
c5ef8f8c LPC |
1052 | } |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
f5dde49b LPC |
1057 | static const struct adv7180_chip_info adv7180_info = { |
1058 | .flags = ADV7180_FLAG_RESET_POWERED, | |
1059 | /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept | |
1060 | * all inputs and let the card driver take care of validation | |
1061 | */ | |
1062 | .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) | | |
1063 | BIT(ADV7180_INPUT_CVBS_AIN2) | | |
1064 | BIT(ADV7180_INPUT_CVBS_AIN3) | | |
1065 | BIT(ADV7180_INPUT_CVBS_AIN4) | | |
1066 | BIT(ADV7180_INPUT_CVBS_AIN5) | | |
1067 | BIT(ADV7180_INPUT_CVBS_AIN6) | | |
1068 | BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) | | |
1069 | BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) | | |
1070 | BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) | | |
1071 | BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) | | |
1072 | BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6), | |
1073 | .init = adv7180_init, | |
1074 | .set_std = adv7180_set_std, | |
1075 | .select_input = adv7180_select_input, | |
1076 | }; | |
1077 | ||
c5ef8f8c LPC |
1078 | static const struct adv7180_chip_info adv7182_info = { |
1079 | .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | | |
1080 | BIT(ADV7182_INPUT_CVBS_AIN2) | | |
1081 | BIT(ADV7182_INPUT_CVBS_AIN3) | | |
1082 | BIT(ADV7182_INPUT_CVBS_AIN4) | | |
1083 | BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | | |
1084 | BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | | |
1085 | BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | | |
1086 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | | |
1087 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4), | |
1088 | .init = adv7182_init, | |
1089 | .set_std = adv7182_set_std, | |
1090 | .select_input = adv7182_select_input, | |
1091 | }; | |
1092 | ||
bf7dcb80 | 1093 | static const struct adv7180_chip_info adv7280_info = { |
851a54ef | 1094 | .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, |
bf7dcb80 LPC |
1095 | .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | |
1096 | BIT(ADV7182_INPUT_CVBS_AIN2) | | |
1097 | BIT(ADV7182_INPUT_CVBS_AIN3) | | |
1098 | BIT(ADV7182_INPUT_CVBS_AIN4) | | |
1099 | BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | | |
1100 | BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | | |
1101 | BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3), | |
1102 | .init = adv7182_init, | |
1103 | .set_std = adv7182_set_std, | |
1104 | .select_input = adv7182_select_input, | |
1105 | }; | |
1106 | ||
b37135e3 | 1107 | static const struct adv7180_chip_info adv7280_m_info = { |
851a54ef | 1108 | .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, |
b37135e3 LPC |
1109 | .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | |
1110 | BIT(ADV7182_INPUT_CVBS_AIN2) | | |
1111 | BIT(ADV7182_INPUT_CVBS_AIN3) | | |
1112 | BIT(ADV7182_INPUT_CVBS_AIN4) | | |
1113 | BIT(ADV7182_INPUT_CVBS_AIN5) | | |
1114 | BIT(ADV7182_INPUT_CVBS_AIN6) | | |
1115 | BIT(ADV7182_INPUT_CVBS_AIN7) | | |
1116 | BIT(ADV7182_INPUT_CVBS_AIN8) | | |
1117 | BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | | |
1118 | BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | | |
1119 | BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | | |
1120 | BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | | |
1121 | BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | | |
1122 | BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6), | |
1123 | .init = adv7182_init, | |
1124 | .set_std = adv7182_set_std, | |
1125 | .select_input = adv7182_select_input, | |
1126 | }; | |
1127 | ||
bf7dcb80 | 1128 | static const struct adv7180_chip_info adv7281_info = { |
b37135e3 LPC |
1129 | .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, |
1130 | .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | | |
1131 | BIT(ADV7182_INPUT_CVBS_AIN2) | | |
1132 | BIT(ADV7182_INPUT_CVBS_AIN7) | | |
1133 | BIT(ADV7182_INPUT_CVBS_AIN8) | | |
1134 | BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | | |
1135 | BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | | |
1136 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | | |
1137 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), | |
1138 | .init = adv7182_init, | |
1139 | .set_std = adv7182_set_std, | |
1140 | .select_input = adv7182_select_input, | |
1141 | }; | |
1142 | ||
1143 | static const struct adv7180_chip_info adv7281_m_info = { | |
1144 | .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, | |
1145 | .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | | |
1146 | BIT(ADV7182_INPUT_CVBS_AIN2) | | |
1147 | BIT(ADV7182_INPUT_CVBS_AIN3) | | |
1148 | BIT(ADV7182_INPUT_CVBS_AIN4) | | |
1149 | BIT(ADV7182_INPUT_CVBS_AIN7) | | |
1150 | BIT(ADV7182_INPUT_CVBS_AIN8) | | |
1151 | BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | | |
1152 | BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | | |
1153 | BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | | |
1154 | BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | | |
1155 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | | |
1156 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | | |
1157 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), | |
1158 | .init = adv7182_init, | |
1159 | .set_std = adv7182_set_std, | |
1160 | .select_input = adv7182_select_input, | |
1161 | }; | |
1162 | ||
1163 | static const struct adv7180_chip_info adv7281_ma_info = { | |
1164 | .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, | |
bf7dcb80 LPC |
1165 | .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | |
1166 | BIT(ADV7182_INPUT_CVBS_AIN2) | | |
b37135e3 LPC |
1167 | BIT(ADV7182_INPUT_CVBS_AIN3) | |
1168 | BIT(ADV7182_INPUT_CVBS_AIN4) | | |
1169 | BIT(ADV7182_INPUT_CVBS_AIN5) | | |
1170 | BIT(ADV7182_INPUT_CVBS_AIN6) | | |
bf7dcb80 LPC |
1171 | BIT(ADV7182_INPUT_CVBS_AIN7) | |
1172 | BIT(ADV7182_INPUT_CVBS_AIN8) | | |
1173 | BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | | |
b37135e3 LPC |
1174 | BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | |
1175 | BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | | |
bf7dcb80 | 1176 | BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | |
b37135e3 LPC |
1177 | BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | |
1178 | BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) | | |
bf7dcb80 | 1179 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | |
b37135e3 LPC |
1180 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | |
1181 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) | | |
bf7dcb80 LPC |
1182 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), |
1183 | .init = adv7182_init, | |
1184 | .set_std = adv7182_set_std, | |
1185 | .select_input = adv7182_select_input, | |
1186 | }; | |
1187 | ||
851a54ef LPC |
1188 | static const struct adv7180_chip_info adv7282_info = { |
1189 | .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, | |
1190 | .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | | |
1191 | BIT(ADV7182_INPUT_CVBS_AIN2) | | |
1192 | BIT(ADV7182_INPUT_CVBS_AIN7) | | |
1193 | BIT(ADV7182_INPUT_CVBS_AIN8) | | |
1194 | BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | | |
1195 | BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | | |
1196 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | | |
1197 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), | |
1198 | .init = adv7182_init, | |
1199 | .set_std = adv7182_set_std, | |
1200 | .select_input = adv7182_select_input, | |
1201 | }; | |
1202 | ||
1203 | static const struct adv7180_chip_info adv7282_m_info = { | |
1204 | .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, | |
1205 | .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | | |
1206 | BIT(ADV7182_INPUT_CVBS_AIN2) | | |
1207 | BIT(ADV7182_INPUT_CVBS_AIN3) | | |
1208 | BIT(ADV7182_INPUT_CVBS_AIN4) | | |
1209 | BIT(ADV7182_INPUT_CVBS_AIN7) | | |
1210 | BIT(ADV7182_INPUT_CVBS_AIN8) | | |
1211 | BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | | |
1212 | BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | | |
1213 | BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | | |
1214 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | | |
1215 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | | |
1216 | BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), | |
1217 | .init = adv7182_init, | |
1218 | .set_std = adv7182_set_std, | |
1219 | .select_input = adv7182_select_input, | |
1220 | }; | |
1221 | ||
f5dde49b LPC |
1222 | static int init_device(struct adv7180_state *state) |
1223 | { | |
1224 | int ret; | |
1225 | ||
1226 | mutex_lock(&state->mutex); | |
1227 | ||
65d9e14a SL |
1228 | adv7180_set_power_pin(state, true); |
1229 | ||
f5dde49b | 1230 | adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES); |
16dfe72f | 1231 | usleep_range(5000, 10000); |
f5dde49b LPC |
1232 | |
1233 | ret = state->chip_info->init(state); | |
1234 | if (ret) | |
3999e5d0 | 1235 | goto out_unlock; |
42752f7a | 1236 | |
f5dde49b LPC |
1237 | ret = adv7180_program_std(state); |
1238 | if (ret) | |
1239 | goto out_unlock; | |
42752f7a | 1240 | |
851a54ef LPC |
1241 | adv7180_set_field_mode(state); |
1242 | ||
42752f7a RR |
1243 | /* register for interrupts */ |
1244 | if (state->irq > 0) { | |
42752f7a | 1245 | /* config the Interrupt pin to be active low */ |
3999e5d0 | 1246 | ret = adv7180_write(state, ADV7180_REG_ICONF1, |
bca7ad1a FV |
1247 | ADV7180_ICONF1_ACTIVE_LOW | |
1248 | ADV7180_ICONF1_PSYNC_ONLY); | |
42752f7a | 1249 | if (ret < 0) |
3999e5d0 | 1250 | goto out_unlock; |
42752f7a | 1251 | |
3999e5d0 | 1252 | ret = adv7180_write(state, ADV7180_REG_IMR1, 0); |
42752f7a | 1253 | if (ret < 0) |
3999e5d0 | 1254 | goto out_unlock; |
42752f7a | 1255 | |
3999e5d0 | 1256 | ret = adv7180_write(state, ADV7180_REG_IMR2, 0); |
42752f7a | 1257 | if (ret < 0) |
3999e5d0 | 1258 | goto out_unlock; |
42752f7a RR |
1259 | |
1260 | /* enable AD change interrupts interrupts */ | |
3999e5d0 | 1261 | ret = adv7180_write(state, ADV7180_REG_IMR3, |
bca7ad1a | 1262 | ADV7180_IRQ3_AD_CHANGE); |
42752f7a | 1263 | if (ret < 0) |
3999e5d0 | 1264 | goto out_unlock; |
42752f7a | 1265 | |
3999e5d0 | 1266 | ret = adv7180_write(state, ADV7180_REG_IMR4, 0); |
42752f7a | 1267 | if (ret < 0) |
3999e5d0 | 1268 | goto out_unlock; |
6789cb52 RR |
1269 | } |
1270 | ||
3999e5d0 LPC |
1271 | out_unlock: |
1272 | mutex_unlock(&state->mutex); | |
df065b37 | 1273 | |
df065b37 | 1274 | return ret; |
bca7ad1a FV |
1275 | } |
1276 | ||
4c62e976 GKH |
1277 | static int adv7180_probe(struct i2c_client *client, |
1278 | const struct i2c_device_id *id) | |
bca7ad1a FV |
1279 | { |
1280 | struct adv7180_state *state; | |
1281 | struct v4l2_subdev *sd; | |
1282 | int ret; | |
1283 | ||
1284 | /* Check if the adapter supports the needed features */ | |
1285 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) | |
1286 | return -EIO; | |
1287 | ||
1288 | v4l_info(client, "chip found @ 0x%02x (%s)\n", | |
1289 | client->addr, client->adapter->name); | |
1290 | ||
c02b211d | 1291 | state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); |
7657e064 FE |
1292 | if (state == NULL) |
1293 | return -ENOMEM; | |
bca7ad1a | 1294 | |
3999e5d0 | 1295 | state->client = client; |
851a54ef | 1296 | state->field = V4L2_FIELD_INTERLACED; |
f5dde49b | 1297 | state->chip_info = (struct adv7180_chip_info *)id->driver_data; |
3999e5d0 | 1298 | |
65d9e14a SL |
1299 | state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", |
1300 | GPIOD_OUT_HIGH); | |
1301 | if (IS_ERR(state->pwdn_gpio)) { | |
1302 | ret = PTR_ERR(state->pwdn_gpio); | |
1303 | v4l_err(client, "request for power pin failed: %d\n", ret); | |
1304 | return ret; | |
1305 | } | |
1306 | ||
b37135e3 LPC |
1307 | if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { |
1308 | state->csi_client = i2c_new_dummy(client->adapter, | |
1309 | ADV7180_DEFAULT_CSI_I2C_ADDR); | |
1310 | if (!state->csi_client) | |
1311 | return -ENOMEM; | |
1312 | } | |
1313 | ||
851a54ef LPC |
1314 | if (state->chip_info->flags & ADV7180_FLAG_I2P) { |
1315 | state->vpp_client = i2c_new_dummy(client->adapter, | |
1316 | ADV7180_DEFAULT_VPP_I2C_ADDR); | |
1317 | if (!state->vpp_client) { | |
1318 | ret = -ENOMEM; | |
1319 | goto err_unregister_csi_client; | |
1320 | } | |
1321 | } | |
1322 | ||
bca7ad1a | 1323 | state->irq = client->irq; |
bca7ad1a | 1324 | mutex_init(&state->mutex); |
937feeed | 1325 | state->curr_norm = V4L2_STD_NTSC; |
f5dde49b LPC |
1326 | if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) |
1327 | state->powered = true; | |
1328 | else | |
1329 | state->powered = false; | |
bca7ad1a FV |
1330 | state->input = 0; |
1331 | sd = &state->sd; | |
1332 | v4l2_i2c_subdev_init(sd, client, &adv7180_ops); | |
937feeed | 1333 | sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; |
bca7ad1a | 1334 | |
c9fbeddd FV |
1335 | ret = adv7180_init_controls(state); |
1336 | if (ret) | |
851a54ef | 1337 | goto err_unregister_vpp_client; |
d5d51a82 LPC |
1338 | |
1339 | state->pad.flags = MEDIA_PAD_FL_SOURCE; | |
4ca72efa | 1340 | sd->entity.flags |= MEDIA_ENT_F_ATV_DECODER; |
ab22e77c | 1341 | ret = media_entity_pads_init(&sd->entity, 1, &state->pad); |
c9fbeddd FV |
1342 | if (ret) |
1343 | goto err_free_ctrl; | |
fa5b7945 | 1344 | |
d5d51a82 LPC |
1345 | ret = init_device(state); |
1346 | if (ret) | |
1347 | goto err_media_entity_cleanup; | |
1348 | ||
fa5721d1 LPC |
1349 | if (state->irq) { |
1350 | ret = request_threaded_irq(client->irq, NULL, adv7180_irq, | |
f3e991d4 LPC |
1351 | IRQF_ONESHOT | IRQF_TRIGGER_FALLING, |
1352 | KBUILD_MODNAME, state); | |
fa5721d1 | 1353 | if (ret) |
d5d51a82 | 1354 | goto err_media_entity_cleanup; |
fa5721d1 LPC |
1355 | } |
1356 | ||
fa5b7945 LPC |
1357 | ret = v4l2_async_register_subdev(sd); |
1358 | if (ret) | |
1359 | goto err_free_irq; | |
1360 | ||
6789cb52 | 1361 | return 0; |
42752f7a | 1362 | |
fa5b7945 LPC |
1363 | err_free_irq: |
1364 | if (state->irq > 0) | |
1365 | free_irq(client->irq, state); | |
d5d51a82 LPC |
1366 | err_media_entity_cleanup: |
1367 | media_entity_cleanup(&sd->entity); | |
c9fbeddd FV |
1368 | err_free_ctrl: |
1369 | adv7180_exit_controls(state); | |
851a54ef LPC |
1370 | err_unregister_vpp_client: |
1371 | if (state->chip_info->flags & ADV7180_FLAG_I2P) | |
1372 | i2c_unregister_device(state->vpp_client); | |
b37135e3 LPC |
1373 | err_unregister_csi_client: |
1374 | if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) | |
1375 | i2c_unregister_device(state->csi_client); | |
297a0ae3 | 1376 | mutex_destroy(&state->mutex); |
42752f7a | 1377 | return ret; |
6789cb52 RR |
1378 | } |
1379 | ||
4c62e976 | 1380 | static int adv7180_remove(struct i2c_client *client) |
6789cb52 RR |
1381 | { |
1382 | struct v4l2_subdev *sd = i2c_get_clientdata(client); | |
42752f7a RR |
1383 | struct adv7180_state *state = to_state(sd); |
1384 | ||
fa5b7945 LPC |
1385 | v4l2_async_unregister_subdev(sd); |
1386 | ||
0c25534d | 1387 | if (state->irq > 0) |
42752f7a | 1388 | free_irq(client->irq, state); |
6789cb52 | 1389 | |
d5d51a82 | 1390 | media_entity_cleanup(&sd->entity); |
b13f4af2 | 1391 | adv7180_exit_controls(state); |
b37135e3 | 1392 | |
851a54ef LPC |
1393 | if (state->chip_info->flags & ADV7180_FLAG_I2P) |
1394 | i2c_unregister_device(state->vpp_client); | |
b37135e3 LPC |
1395 | if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) |
1396 | i2c_unregister_device(state->csi_client); | |
1397 | ||
65d9e14a SL |
1398 | adv7180_set_power_pin(state, false); |
1399 | ||
297a0ae3 | 1400 | mutex_destroy(&state->mutex); |
b37135e3 | 1401 | |
6789cb52 RR |
1402 | return 0; |
1403 | } | |
1404 | ||
1405 | static const struct i2c_device_id adv7180_id[] = { | |
f5dde49b | 1406 | { "adv7180", (kernel_ulong_t)&adv7180_info }, |
c5ef8f8c | 1407 | { "adv7182", (kernel_ulong_t)&adv7182_info }, |
bf7dcb80 | 1408 | { "adv7280", (kernel_ulong_t)&adv7280_info }, |
b37135e3 | 1409 | { "adv7280-m", (kernel_ulong_t)&adv7280_m_info }, |
bf7dcb80 | 1410 | { "adv7281", (kernel_ulong_t)&adv7281_info }, |
b37135e3 LPC |
1411 | { "adv7281-m", (kernel_ulong_t)&adv7281_m_info }, |
1412 | { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info }, | |
851a54ef LPC |
1413 | { "adv7282", (kernel_ulong_t)&adv7282_info }, |
1414 | { "adv7282-m", (kernel_ulong_t)&adv7282_m_info }, | |
6789cb52 RR |
1415 | {}, |
1416 | }; | |
f5dde49b | 1417 | MODULE_DEVICE_TABLE(i2c, adv7180_id); |
6789cb52 | 1418 | |
cc1088dc LPC |
1419 | #ifdef CONFIG_PM_SLEEP |
1420 | static int adv7180_suspend(struct device *dev) | |
bca7ad1a | 1421 | { |
cc1088dc | 1422 | struct i2c_client *client = to_i2c_client(dev); |
e246c333 LPC |
1423 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
1424 | struct adv7180_state *state = to_state(sd); | |
bca7ad1a | 1425 | |
3999e5d0 | 1426 | return adv7180_set_power(state, false); |
bca7ad1a FV |
1427 | } |
1428 | ||
cc1088dc | 1429 | static int adv7180_resume(struct device *dev) |
bca7ad1a | 1430 | { |
cc1088dc | 1431 | struct i2c_client *client = to_i2c_client(dev); |
bca7ad1a FV |
1432 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
1433 | struct adv7180_state *state = to_state(sd); | |
1434 | int ret; | |
1435 | ||
3999e5d0 | 1436 | ret = init_device(state); |
bca7ad1a FV |
1437 | if (ret < 0) |
1438 | return ret; | |
c18818e9 LPC |
1439 | |
1440 | ret = adv7180_set_power(state, state->powered); | |
1441 | if (ret) | |
1442 | return ret; | |
1443 | ||
bca7ad1a FV |
1444 | return 0; |
1445 | } | |
cc1088dc LPC |
1446 | |
1447 | static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume); | |
1448 | #define ADV7180_PM_OPS (&adv7180_pm_ops) | |
1449 | ||
1450 | #else | |
1451 | #define ADV7180_PM_OPS NULL | |
bca7ad1a FV |
1452 | #endif |
1453 | ||
250121d3 BD |
1454 | #ifdef CONFIG_OF |
1455 | static const struct of_device_id adv7180_of_id[] = { | |
1456 | { .compatible = "adi,adv7180", }, | |
bf14e74c JS |
1457 | { .compatible = "adi,adv7182", }, |
1458 | { .compatible = "adi,adv7280", }, | |
1459 | { .compatible = "adi,adv7280-m", }, | |
1460 | { .compatible = "adi,adv7281", }, | |
1461 | { .compatible = "adi,adv7281-m", }, | |
1462 | { .compatible = "adi,adv7281-ma", }, | |
1463 | { .compatible = "adi,adv7282", }, | |
1464 | { .compatible = "adi,adv7282-m", }, | |
250121d3 BD |
1465 | { }, |
1466 | }; | |
1467 | ||
1468 | MODULE_DEVICE_TABLE(of, adv7180_of_id); | |
1469 | #endif | |
1470 | ||
6789cb52 RR |
1471 | static struct i2c_driver adv7180_driver = { |
1472 | .driver = { | |
c9fbeddd | 1473 | .name = KBUILD_MODNAME, |
cc1088dc | 1474 | .pm = ADV7180_PM_OPS, |
250121d3 | 1475 | .of_match_table = of_match_ptr(adv7180_of_id), |
bca7ad1a FV |
1476 | }, |
1477 | .probe = adv7180_probe, | |
4c62e976 | 1478 | .remove = adv7180_remove, |
bca7ad1a | 1479 | .id_table = adv7180_id, |
6789cb52 RR |
1480 | }; |
1481 | ||
c6e8d86f | 1482 | module_i2c_driver(adv7180_driver); |
6789cb52 RR |
1483 | |
1484 | MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver"); | |
1485 | MODULE_AUTHOR("Mocean Laboratories"); | |
1486 | MODULE_LICENSE("GPL v2"); |