[deliverable/linux.git] / drivers / media / i2c / adv7343.c

/*
 * adv7343 - ADV7343 Video Encoder Driver
 *
 * The encoder hardware does not support SECAM.
 *
 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ctype.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/videodev2.h>
#include <linux/uaccess.h>

#include <media/adv7343.h>
#include <media/v4l2-async.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>

#include "adv7343_regs.h"

MODULE_DESCRIPTION("ADV7343 video encoder driver");
MODULE_LICENSE("GPL");

static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Debug level 0-1");

struct adv7343_state {
	struct v4l2_subdev sd;
	struct v4l2_ctrl_handler hdl;
	const struct adv7343_platform_data *pdata;
	u8 reg00;
	u8 reg01;
	u8 reg02;
	u8 reg35;
	u8 reg80;
	u8 reg82;
	u32 output;
	v4l2_std_id std;
};

static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
{
	return container_of(sd, struct adv7343_state, sd);
}

static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
{
	return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
}

static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	return i2c_smbus_write_byte_data(client, reg, value);
}

static const u8 adv7343_init_reg_val[] = {
	ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
	ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,

	ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
	ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
	ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
	ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
	ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
	ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
	ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,

	ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
	ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
	ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
	ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
	ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
	ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
	ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
	ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,

	ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
	ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
	ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
};

/*
 * 			    2^32
 * FSC(reg) =  FSC (HZ) * --------
 *			  27000000
 */
static const struct adv7343_std_info stdinfo[] = {
	{
		/* FSC(Hz) = 3,579,545.45 Hz */
		SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
	}, {
		/* FSC(Hz) = 3,575,611.00 Hz */
		SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
	}, {
		/* FSC(Hz) = 3,582,056.00 */
		SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
	}, {
		/* FSC(Hz) = 4,433,618.75 Hz */
		SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
	}, {
		/* FSC(Hz) = 4,433,618.75 Hz */
		SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
	}, {
		/* FSC(Hz) = 4,433,618.75 Hz */
		SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
	}, {
		/* FSC(Hz) = 4,433,618.75 Hz */
		SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
	},
};

static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
{
	struct adv7343_state *state = to_state(sd);
	struct adv7343_std_info *std_info;
	int num_std;
	char *fsc_ptr;
	u8 reg, val;
	int err = 0;
	int i = 0;

	std_info = (struct adv7343_std_info *)stdinfo;
	num_std = ARRAY_SIZE(stdinfo);

	for (i = 0; i < num_std; i++) {
		if (std_info[i].stdid & std)
			break;
	}

	if (i == num_std) {
		v4l2_dbg(1, debug, sd,
				"Invalid std or std is not supported: %llx\n",
						(unsigned long long)std);
		return -EINVAL;
	}

	/* Set the standard */
	val = state->reg80 & (~(SD_STD_MASK));
	val |= std_info[i].standard_val3;
	err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
	if (err < 0)
		goto setstd_exit;

	state->reg80 = val;

	/* Configure the input mode register */
	val = state->reg01 & (~((u8) INPUT_MODE_MASK));
	val |= SD_INPUT_MODE;
	err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
	if (err < 0)
		goto setstd_exit;

	state->reg01 = val;

	/* Program the sub carrier frequency registers */
	fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
	reg = ADV7343_FSC_REG0;
	for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
		err = adv7343_write(sd, reg, *fsc_ptr);
		if (err < 0)
			goto setstd_exit;
	}

	val = state->reg80;

	/* Filter settings */
	if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
		val &= 0x03;
	else if (std & ~V4L2_STD_SECAM)
		val |= 0x04;

	err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
	if (err < 0)
		goto setstd_exit;

	state->reg80 = val;

setstd_exit:
	if (err != 0)
		v4l2_err(sd, "Error setting std, write failed\n");

	return err;
}

static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
{
	struct adv7343_state *state = to_state(sd);
	unsigned char val;
	int err = 0;

	if (output_type > ADV7343_SVIDEO_ID) {
		v4l2_dbg(1, debug, sd,
			"Invalid output type or output type not supported:%d\n",
								output_type);
		return -EINVAL;
	}

	/* Enable Appropriate DAC */
	val = state->reg00 & 0x03;

	/* configure default configuration */
	if (!state->pdata)
		if (output_type == ADV7343_COMPOSITE_ID)
			val |= ADV7343_COMPOSITE_POWER_VALUE;
		else if (output_type == ADV7343_COMPONENT_ID)
			val |= ADV7343_COMPONENT_POWER_VALUE;
		else
			val |= ADV7343_SVIDEO_POWER_VALUE;
	else
		val = state->pdata->mode_config.sleep_mode << 0 |
		      state->pdata->mode_config.pll_control << 1 |
		      state->pdata->mode_config.dac[2] << 2 |
		      state->pdata->mode_config.dac[1] << 3 |
		      state->pdata->mode_config.dac[0] << 4 |
		      state->pdata->mode_config.dac[5] << 5 |
		      state->pdata->mode_config.dac[4] << 6 |
		      state->pdata->mode_config.dac[3] << 7;

	err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
	if (err < 0)
		goto setoutput_exit;

	state->reg00 = val;

	/* Enable YUV output */
	val = state->reg02 | YUV_OUTPUT_SELECT;
	err = adv7343_write(sd, ADV7343_MODE_REG0, val);
	if (err < 0)
		goto setoutput_exit;

	state->reg02 = val;

	/* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
	val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);

	if (state->pdata && state->pdata->sd_config.sd_dac_out[0])
		val = val | (state->pdata->sd_config.sd_dac_out[0] << 1);
	else if (state->pdata && !state->pdata->sd_config.sd_dac_out[0])
		val = val & ~(state->pdata->sd_config.sd_dac_out[0] << 1);

	if (state->pdata && state->pdata->sd_config.sd_dac_out[1])
		val = val | (state->pdata->sd_config.sd_dac_out[1] << 2);
	else if (state->pdata && !state->pdata->sd_config.sd_dac_out[1])
		val = val & ~(state->pdata->sd_config.sd_dac_out[1] << 2);

	err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
	if (err < 0)
		goto setoutput_exit;

	state->reg82 = val;

	/* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
	 * zero */
	val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
	err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
	if (err < 0)
		goto setoutput_exit;

	state->reg35 = val;

setoutput_exit:
	if (err != 0)
		v4l2_err(sd, "Error setting output, write failed\n");

	return err;
}

static int adv7343_log_status(struct v4l2_subdev *sd)
{
	struct adv7343_state *state = to_state(sd);

	v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
	v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
			((state->output == 1) ? "Component" : "S-Video"));
	return 0;
}

static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
{
	struct v4l2_subdev *sd = to_sd(ctrl);

	switch (ctrl->id) {
	case V4L2_CID_BRIGHTNESS:
		return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
					ctrl->val);

	case V4L2_CID_HUE:
		return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);

	case V4L2_CID_GAIN:
		return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
	}
	return -EINVAL;
}

static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
	.s_ctrl = adv7343_s_ctrl,
};

static const struct v4l2_subdev_core_ops adv7343_core_ops = {
	.log_status = adv7343_log_status,
	.g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
	.try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
	.s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
	.g_ctrl = v4l2_subdev_g_ctrl,
	.s_ctrl = v4l2_subdev_s_ctrl,
	.queryctrl = v4l2_subdev_queryctrl,
	.querymenu = v4l2_subdev_querymenu,
};

static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
{
	struct adv7343_state *state = to_state(sd);
	int err = 0;

	if (state->std == std)
		return 0;

	err = adv7343_setstd(sd, std);
	if (!err)
		state->std = std;

	return err;
}

static int adv7343_s_routing(struct v4l2_subdev *sd,
		u32 input, u32 output, u32 config)
{
	struct adv7343_state *state = to_state(sd);
	int err = 0;

	if (state->output == output)
		return 0;

	err = adv7343_setoutput(sd, output);
	if (!err)
		state->output = output;

	return err;
}

static const struct v4l2_subdev_video_ops adv7343_video_ops = {
	.s_std_output	= adv7343_s_std_output,
	.s_routing	= adv7343_s_routing,
};

static const struct v4l2_subdev_ops adv7343_ops = {
	.core	= &adv7343_core_ops,
	.video	= &adv7343_video_ops,
};

static int adv7343_initialize(struct v4l2_subdev *sd)
{
	struct adv7343_state *state = to_state(sd);
	int err = 0;
	int i;

	for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {

		err = adv7343_write(sd, adv7343_init_reg_val[i],
					adv7343_init_reg_val[i+1]);
		if (err) {
			v4l2_err(sd, "Error initializing\n");
			return err;
		}
	}

	/* Configure for default video standard */
	err = adv7343_setoutput(sd, state->output);
	if (err < 0) {
		v4l2_err(sd, "Error setting output during init\n");
		return -EINVAL;
	}

	err = adv7343_setstd(sd, state->std);
	if (err < 0) {
		v4l2_err(sd, "Error setting std during init\n");
		return -EINVAL;
	}

	return err;
}

static int adv7343_probe(struct i2c_client *client,
				const struct i2c_device_id *id)
{
	struct adv7343_state *state;
	int err;

	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
		return -ENODEV;

	v4l_info(client, "chip found @ 0x%x (%s)\n",
			client->addr << 1, client->adapter->name);

	state = devm_kzalloc(&client->dev, sizeof(struct adv7343_state),
			     GFP_KERNEL);
	if (state == NULL)
		return -ENOMEM;

	/* Copy board specific information here */
	state->pdata = client->dev.platform_data;

	state->reg00	= 0x80;
	state->reg01	= 0x00;
	state->reg02	= 0x20;
	state->reg35	= 0x00;
	state->reg80	= ADV7343_SD_MODE_REG1_DEFAULT;
	state->reg82	= ADV7343_SD_MODE_REG2_DEFAULT;

	state->output = ADV7343_COMPOSITE_ID;
	state->std = V4L2_STD_NTSC;

	v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);

	v4l2_ctrl_handler_init(&state->hdl, 2);
	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
			V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
					     ADV7343_BRIGHTNESS_MAX, 1,
					     ADV7343_BRIGHTNESS_DEF);
	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
			V4L2_CID_HUE, ADV7343_HUE_MIN,
				      ADV7343_HUE_MAX, 1,
				      ADV7343_HUE_DEF);
	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
			V4L2_CID_GAIN, ADV7343_GAIN_MIN,
				       ADV7343_GAIN_MAX, 1,
				       ADV7343_GAIN_DEF);
	state->sd.ctrl_handler = &state->hdl;
	if (state->hdl.error) {
		err = state->hdl.error;
		goto done;
	}
	v4l2_ctrl_handler_setup(&state->hdl);

	err = adv7343_initialize(&state->sd);
	if (err)
		goto done;

	err = v4l2_async_register_subdev(&state->sd);

done:
	if (err < 0)
		v4l2_ctrl_handler_free(&state->hdl);

	return err;
}

static int adv7343_remove(struct i2c_client *client)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);
	struct adv7343_state *state = to_state(sd);

	v4l2_async_unregister_subdev(&state->sd);
	v4l2_device_unregister_subdev(sd);
	v4l2_ctrl_handler_free(&state->hdl);

	return 0;
}

static const struct i2c_device_id adv7343_id[] = {
	{"adv7343", 0},
	{},
};

MODULE_DEVICE_TABLE(i2c, adv7343_id);

static struct i2c_driver adv7343_driver = {
	.driver = {
		.owner	= THIS_MODULE,
		.name	= "adv7343",
	},
	.probe		= adv7343_probe,
	.remove		= adv7343_remove,
	.id_table	= adv7343_id,
};

module_i2c_driver(adv7343_driver);
Commit	Line	Data
06e61f8d C	1	/*
	2	* adv7343 - ADV7343 Video Encoder Driver
	3	*
	4	* The encoder hardware does not support SECAM.
	5	*
	6	* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation version 2.
	11	*
	12	* This program is distributed .as is. WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/ctype.h>
5a0e3ad6	21	#include <linux/slab.h>
06e61f8d C	22	#include <linux/i2c.h>
	23	#include <linux/device.h>
	24	#include <linux/delay.h>
	25	#include <linux/module.h>
	26	#include <linux/videodev2.h>
	27	#include <linux/uaccess.h>
06e61f8d C	28
06e61f8d C	29	#include <media/adv7343.h>
6555cfc5	30	#include <media/v4l2-async.h>
06e61f8d	31	#include <media/v4l2-device.h>
ceed52d6	32	#include <media/v4l2-ctrls.h>
06e61f8d C	33
	34	#include "adv7343_regs.h"
	35
	36	MODULE_DESCRIPTION("ADV7343 video encoder driver");
	37	MODULE_LICENSE("GPL");
	38
	39	static int debug;
	40	module_param(debug, int, 0644);
	41	MODULE_PARM_DESC(debug, "Debug level 0-1");
	42
	43	struct adv7343_state {
	44	struct v4l2_subdev sd;
ceed52d6	45	struct v4l2_ctrl_handler hdl;
0b302d88	46	const struct adv7343_platform_data *pdata;
06e61f8d C	47	u8 reg00;
	48	u8 reg01;
	49	u8 reg02;
	50	u8 reg35;
	51	u8 reg80;
	52	u8 reg82;
06e61f8d C	53	u32 output;
	54	v4l2_std_id std;
	55	};
	56
	57	static inline struct adv7343_state to_state(struct v4l2_subdev sd)
	58	{
	59	return container_of(sd, struct adv7343_state, sd);
	60	}
	61
ceed52d6 HV	62	static inline struct v4l2_subdev to_sd(struct v4l2_ctrl ctrl)
	63	{
	64	return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
	65	}
	66
06e61f8d C	67	static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
	68	{
	69	struct i2c_client *client = v4l2_get_subdevdata(sd);
	70
	71	return i2c_smbus_write_byte_data(client, reg, value);
	72	}
	73
	74	static const u8 adv7343_init_reg_val[] = {
	75	ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
	76	ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
	77
	78	ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
	79	ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
	80	ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
	81	ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
	82	ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
	83	ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
	84	ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
	85
	86	ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
	87	ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
	88	ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
	89	ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
	90	ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
	91	ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
	92	ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
	93	ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
	94
	95	ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
	96	ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
	97	ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
	98	};
	99
	100	/*
	101	* 2^32
	102	* FSC(reg) = FSC (HZ) * --------
	103	* 27000000
	104	*/
	105	static const struct adv7343_std_info stdinfo[] = {
	106	{
	107	/* FSC(Hz) = 3,579,545.45 Hz */
	108	SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
	109	}, {
	110	/* FSC(Hz) = 3,575,611.00 Hz */
	111	SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
	112	}, {
	113	/* FSC(Hz) = 3,582,056.00 */
	114	SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
	115	}, {
	116	/* FSC(Hz) = 4,433,618.75 Hz */
	117	SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
	118	}, {
	119	/* FSC(Hz) = 4,433,618.75 Hz */
	120	SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
	121	}, {
	122	/* FSC(Hz) = 4,433,618.75 Hz */
	123	SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
	124	}, {
	125	/* FSC(Hz) = 4,433,618.75 Hz */
	126	SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
	127	},
	128	};
	129
	130	static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
131	{
132	struct adv7343_state *state = to_state(sd);
133	struct adv7343_std_info *std_info;
8173090a	134	int num_std;
06e61f8d C	135	char *fsc_ptr;
	136	u8 reg, val;
	137	int err = 0;
	138	int i = 0;
	139
06e61f8d C	140	std_info = (struct adv7343_std_info *)stdinfo;
	141	num_std = ARRAY_SIZE(stdinfo);
	142
	143	for (i = 0; i < num_std; i++) {
	144	if (std_info[i].stdid & std)
	145	break;
	146	}
	147
	148	if (i == num_std) {
	149	v4l2_dbg(1, debug, sd,
	150	"Invalid std or std is not supported: %llx\n",
	151	(unsigned long long)std);
	152	return -EINVAL;
	153	}
	154
	155	/* Set the standard */
	156	val = state->reg80 & (~(SD_STD_MASK));
	157	val \|= std_info[i].standard_val3;
	158	err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
	159	if (err < 0)
	160	goto setstd_exit;
	161
	162	state->reg80 = val;
	163
	164	/* Configure the input mode register */
	165	val = state->reg01 & (~((u8) INPUT_MODE_MASK));
	166	val \|= SD_INPUT_MODE;
	167	err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
	168	if (err < 0)
	169	goto setstd_exit;
	170
	171	state->reg01 = val;
	172
	173	/* Program the sub carrier frequency registers */
	174	fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
	175	reg = ADV7343_FSC_REG0;
	176	for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
	177	err = adv7343_write(sd, reg, *fsc_ptr);
	178	if (err < 0)
	179	goto setstd_exit;
	180	}
	181
	182	val = state->reg80;
	183
	184	/* Filter settings */
	185	if (std & (V4L2_STD_NTSC \| V4L2_STD_NTSC_443))
	186	val &= 0x03;
	187	else if (std & ~V4L2_STD_SECAM)
	188	val \|= 0x04;
	189
	190	err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
	191	if (err < 0)
	192	goto setstd_exit;
	193
	194	state->reg80 = val;
	195
	196	setstd_exit:
	197	if (err != 0)
	198	v4l2_err(sd, "Error setting std, write failed\n");
	199
	200	return err;
	201	}
	202
	203	static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
204	{
205	struct adv7343_state *state = to_state(sd);
206	unsigned char val;
207	int err = 0;
208
209	if (output_type > ADV7343_SVIDEO_ID) {
210	v4l2_dbg(1, debug, sd,
211	"Invalid output type or output type not supported:%d\n",
212	output_type);
213	return -EINVAL;
214	}
215
216	/* Enable Appropriate DAC */
217	val = state->reg00 & 0x03;
218
0b302d88 LP	219	/* configure default configuration */
	220	if (!state->pdata)
	221	if (output_type == ADV7343_COMPOSITE_ID)
	222	val \|= ADV7343_COMPOSITE_POWER_VALUE;
	223	else if (output_type == ADV7343_COMPONENT_ID)
	224	val \|= ADV7343_COMPONENT_POWER_VALUE;
	225	else
	226	val \|= ADV7343_SVIDEO_POWER_VALUE;
06e61f8d	227	else
0b302d88 LP	228	val = state->pdata->mode_config.sleep_mode << 0 \|
0b302d88 LP	229	state->pdata->mode_config.pll_control << 1 \|
5e95814f LP	230	state->pdata->mode_config.dac[2] << 2 \|
	231	state->pdata->mode_config.dac[1] << 3 \|
	232	state->pdata->mode_config.dac[0] << 4 \|
	233	state->pdata->mode_config.dac[5] << 5 \|
	234	state->pdata->mode_config.dac[4] << 6 \|
	235	state->pdata->mode_config.dac[3] << 7;
06e61f8d C	236
	237	err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
	238	if (err < 0)
	239	goto setoutput_exit;
	240
	241	state->reg00 = val;
	242
	243	/* Enable YUV output */
	244	val = state->reg02 \| YUV_OUTPUT_SELECT;
	245	err = adv7343_write(sd, ADV7343_MODE_REG0, val);
	246	if (err < 0)
	247	goto setoutput_exit;
	248
	249	state->reg02 = val;
	250
	251	/* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
	252	val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
0b302d88	253
5e95814f LP	254	if (state->pdata && state->pdata->sd_config.sd_dac_out[0])
	255	val = val \| (state->pdata->sd_config.sd_dac_out[0] << 1);
	256	else if (state->pdata && !state->pdata->sd_config.sd_dac_out[0])
	257	val = val & ~(state->pdata->sd_config.sd_dac_out[0] << 1);
0b302d88	258
5e95814f LP	259	if (state->pdata && state->pdata->sd_config.sd_dac_out[1])
	260	val = val \| (state->pdata->sd_config.sd_dac_out[1] << 2);
	261	else if (state->pdata && !state->pdata->sd_config.sd_dac_out[1])
	262	val = val & ~(state->pdata->sd_config.sd_dac_out[1] << 2);
0b302d88	263
06e61f8d C	264	err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
	265	if (err < 0)
	266	goto setoutput_exit;
	267
	268	state->reg82 = val;
	269
	270	/* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
	271	* zero */
	272	val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
	273	err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
	274	if (err < 0)
	275	goto setoutput_exit;
	276
	277	state->reg35 = val;
	278
	279	setoutput_exit:
	280	if (err != 0)
	281	v4l2_err(sd, "Error setting output, write failed\n");
	282
	283	return err;
	284	}
	285
	286	static int adv7343_log_status(struct v4l2_subdev *sd)
	287	{
	288	struct adv7343_state *state = to_state(sd);
	289
	290	v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
	291	v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
	292	((state->output == 1) ? "Component" : "S-Video"));
	293	return 0;
	294	}
	295
ceed52d6	296	static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
06e61f8d	297	{
ceed52d6	298	struct v4l2_subdev *sd = to_sd(ctrl);
06e61f8d C	299
	300	switch (ctrl->id) {
	301	case V4L2_CID_BRIGHTNESS:
ceed52d6 HV	302	return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
ceed52d6 HV	303	ctrl->val);
06e61f8d C	304
06e61f8d C	305	case V4L2_CID_HUE:
ceed52d6	306	return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);
06e61f8d C	307
06e61f8d C	308	case V4L2_CID_GAIN:
ceed52d6	309	return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
06e61f8d	310	}
ceed52d6	311	return -EINVAL;
06e61f8d C	312	}
06e61f8d C	313
ceed52d6 HV	314	static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
	315	.s_ctrl = adv7343_s_ctrl,
	316	};
	317
06e61f8d	318	static const struct v4l2_subdev_core_ops adv7343_core_ops = {
ceed52d6	319	.log_status = adv7343_log_status,
ceed52d6 HV	320	.g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
	321	.try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
	322	.s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
	323	.g_ctrl = v4l2_subdev_g_ctrl,
	324	.s_ctrl = v4l2_subdev_s_ctrl,
	325	.queryctrl = v4l2_subdev_queryctrl,
	326	.querymenu = v4l2_subdev_querymenu,
06e61f8d C	327	};
	328
	329	static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
	330	{
	331	struct adv7343_state *state = to_state(sd);
	332	int err = 0;
	333
	334	if (state->std == std)
	335	return 0;
	336
	337	err = adv7343_setstd(sd, std);
	338	if (!err)
	339	state->std = std;
	340
	341	return err;
	342	}
	343
	344	static int adv7343_s_routing(struct v4l2_subdev *sd,
	345	u32 input, u32 output, u32 config)
	346	{
	347	struct adv7343_state *state = to_state(sd);
	348	int err = 0;
	349
	350	if (state->output == output)
	351	return 0;
	352
	353	err = adv7343_setoutput(sd, output);
	354	if (!err)
	355	state->output = output;
	356
	357	return err;
	358	}
	359
	360	static const struct v4l2_subdev_video_ops adv7343_video_ops = {
	361	.s_std_output = adv7343_s_std_output,
	362	.s_routing = adv7343_s_routing,
	363	};
	364
	365	static const struct v4l2_subdev_ops adv7343_ops = {
	366	.core = &adv7343_core_ops,
	367	.video = &adv7343_video_ops,
	368	};
	369
	370	static int adv7343_initialize(struct v4l2_subdev *sd)
	371	{
	372	struct adv7343_state *state = to_state(sd);
	373	int err = 0;
	374	int i;
	375
	376	for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
	377
	378	err = adv7343_write(sd, adv7343_init_reg_val[i],
	379	adv7343_init_reg_val[i+1]);
	380	if (err) {
	381	v4l2_err(sd, "Error initializing\n");
	382	return err;
	383	}
	384	}
	385
	386	/* Configure for default video standard */
	387	err = adv7343_setoutput(sd, state->output);
	388	if (err < 0) {
	389	v4l2_err(sd, "Error setting output during init\n");
	390	return -EINVAL;
391	}
392
393	err = adv7343_setstd(sd, state->std);
394	if (err < 0) {
395	v4l2_err(sd, "Error setting std during init\n");
396	return -EINVAL;
397	}
398
399	return err;
400	}
401
402	static int adv7343_probe(struct i2c_client *client,
403	const struct i2c_device_id *id)
404	{
405	struct adv7343_state *state;
ceed52d6	406	int err;
06e61f8d C	407
	408	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
	409	return -ENODEV;
	410
	411	v4l_info(client, "chip found @ 0x%x (%s)\n",
	412	client->addr << 1, client->adapter->name);
	413
c7a857a0 LP	414	state = devm_kzalloc(&client->dev, sizeof(struct adv7343_state),
c7a857a0 LP	415	GFP_KERNEL);
06e61f8d C	416	if (state == NULL)
	417	return -ENOMEM;
	418
0b302d88 LP	419	/* Copy board specific information here */
	420	state->pdata = client->dev.platform_data;
	421
06e61f8d C	422	state->reg00 = 0x80;
	423	state->reg01 = 0x00;
	424	state->reg02 = 0x20;
	425	state->reg35 = 0x00;
	426	state->reg80 = ADV7343_SD_MODE_REG1_DEFAULT;
	427	state->reg82 = ADV7343_SD_MODE_REG2_DEFAULT;
	428
	429	state->output = ADV7343_COMPOSITE_ID;
	430	state->std = V4L2_STD_NTSC;
	431
	432	v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
ceed52d6 HV	433
	434	v4l2_ctrl_handler_init(&state->hdl, 2);
	435	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
	436	V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
	437	ADV7343_BRIGHTNESS_MAX, 1,
	438	ADV7343_BRIGHTNESS_DEF);
	439	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
	440	V4L2_CID_HUE, ADV7343_HUE_MIN,
	441	ADV7343_HUE_MAX, 1,
	442	ADV7343_HUE_DEF);
	443	v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
	444	V4L2_CID_GAIN, ADV7343_GAIN_MIN,
	445	ADV7343_GAIN_MAX, 1,
	446	ADV7343_GAIN_DEF);
	447	state->sd.ctrl_handler = &state->hdl;
	448	if (state->hdl.error) {
6555cfc5 LP	449	err = state->hdl.error;
6555cfc5 LP	450	goto done;
ceed52d6 HV	451	}
	452	v4l2_ctrl_handler_setup(&state->hdl);
	453
	454	err = adv7343_initialize(&state->sd);
c7a857a0	455	if (err)
6555cfc5 LP	456	goto done;
	457
	458	err = v4l2_async_register_subdev(&state->sd);
	459
	460	done:
	461	if (err < 0)
ceed52d6	462	v4l2_ctrl_handler_free(&state->hdl);
6555cfc5	463
ceed52d6	464	return err;
06e61f8d C	465	}
	466
	467	static int adv7343_remove(struct i2c_client *client)
	468	{
	469	struct v4l2_subdev *sd = i2c_get_clientdata(client);
ceed52d6	470	struct adv7343_state *state = to_state(sd);
06e61f8d	471
6555cfc5	472	v4l2_async_unregister_subdev(&state->sd);
06e61f8d	473	v4l2_device_unregister_subdev(sd);
ceed52d6	474	v4l2_ctrl_handler_free(&state->hdl);
06e61f8d C	475
	476	return 0;
	477	}
	478
	479	static const struct i2c_device_id adv7343_id[] = {
	480	{"adv7343", 0},
	481	{},
	482	};
	483
	484	MODULE_DEVICE_TABLE(i2c, adv7343_id);
	485
	486	static struct i2c_driver adv7343_driver = {
	487	.driver = {
	488	.owner = THIS_MODULE,
	489	.name = "adv7343",
	490	},
	491	.probe = adv7343_probe,
	492	.remove = adv7343_remove,
	493	.id_table = adv7343_id,
	494	};
	495
c6e8d86f	496	module_i2c_driver(adv7343_driver);