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[media] adv7604: set restart_stdi_once flag when signal is lost
[deliverable/linux.git] / drivers / media / i2c / adv7604.c
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54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/slab.h>
34#include <linux/i2c.h>
35#include <linux/delay.h>
36#include <linux/videodev2.h>
37#include <linux/workqueue.h>
38#include <linux/v4l2-dv-timings.h>
39#include <media/v4l2-device.h>
40#include <media/v4l2-ctrls.h>
25764158 41#include <media/v4l2-dv-timings.h>
54450f59
HV		 42#include <media/adv7604.h>
43
44static int debug;
45module_param(debug, int, 0644);
46MODULE_PARM_DESC(debug, "debug level (0-2)");
47
48MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
49MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
50MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
51MODULE_LICENSE("GPL");
52
53/* ADV7604 system clock frequency */
54#define ADV7604_fsc (28636360)
55
54450f59
HV		 56/*
57 **********************************************************************
58 *
59 * Arrays with configuration parameters for the ADV7604
60 *
61 **********************************************************************
62 */
63struct adv7604_state {
64 struct adv7604_platform_data pdata;
65 struct v4l2_subdev sd;
66 struct media_pad pad;
67 struct v4l2_ctrl_handler hdl;
4a31a93a 68 enum adv7604_input_port selected_input;
54450f59 69 struct v4l2_dv_timings timings;
4a31a93a
MR		 70 struct {
71 u8 edid[256];
72 u32 present;
73 unsigned blocks;
74 } edid;
dd08beb9 75 u16 spa_port_a[2];
54450f59
HV		 76 struct v4l2_fract aspect_ratio;
77 u32 rgb_quantization_range;
78 struct workqueue_struct *work_queues;
79 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 80 bool restart_stdi_once;
54450f59
HV		 81
82 /* i2c clients */
83 struct i2c_client *i2c_avlink;
84 struct i2c_client *i2c_cec;
85 struct i2c_client *i2c_infoframe;
86 struct i2c_client *i2c_esdp;
87 struct i2c_client *i2c_dpp;
88 struct i2c_client *i2c_afe;
89 struct i2c_client *i2c_repeater;
90 struct i2c_client *i2c_edid;
91 struct i2c_client *i2c_hdmi;
92 struct i2c_client *i2c_test;
93 struct i2c_client *i2c_cp;
94 struct i2c_client *i2c_vdp;
95
96 /* controls */
97 struct v4l2_ctrl *detect_tx_5v_ctrl;
98 struct v4l2_ctrl *analog_sampling_phase_ctrl;
99 struct v4l2_ctrl *free_run_color_manual_ctrl;
100 struct v4l2_ctrl *free_run_color_ctrl;
101 struct v4l2_ctrl *rgb_quantization_range_ctrl;
102};
103
104/* Supported CEA and DMT timings */
105static const struct v4l2_dv_timings adv7604_timings[] = {
106 V4L2_DV_BT_CEA_720X480P59_94,
107 V4L2_DV_BT_CEA_720X576P50,
108 V4L2_DV_BT_CEA_1280X720P24,
109 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 110 V4L2_DV_BT_CEA_1280X720P50,
111 V4L2_DV_BT_CEA_1280X720P60,
112 V4L2_DV_BT_CEA_1920X1080P24,
113 V4L2_DV_BT_CEA_1920X1080P25,
114 V4L2_DV_BT_CEA_1920X1080P30,
115 V4L2_DV_BT_CEA_1920X1080P50,
116 V4L2_DV_BT_CEA_1920X1080P60,
117
ccbd5bc4 118 /* sorted by DMT ID */
54450f59
HV		 119 V4L2_DV_BT_DMT_640X350P85,
120 V4L2_DV_BT_DMT_640X400P85,
121 V4L2_DV_BT_DMT_720X400P85,
122 V4L2_DV_BT_DMT_640X480P60,
123 V4L2_DV_BT_DMT_640X480P72,
124 V4L2_DV_BT_DMT_640X480P75,
125 V4L2_DV_BT_DMT_640X480P85,
126 V4L2_DV_BT_DMT_800X600P56,
127 V4L2_DV_BT_DMT_800X600P60,
128 V4L2_DV_BT_DMT_800X600P72,
129 V4L2_DV_BT_DMT_800X600P75,
130 V4L2_DV_BT_DMT_800X600P85,
131 V4L2_DV_BT_DMT_848X480P60,
132 V4L2_DV_BT_DMT_1024X768P60,
133 V4L2_DV_BT_DMT_1024X768P70,
134 V4L2_DV_BT_DMT_1024X768P75,
135 V4L2_DV_BT_DMT_1024X768P85,
136 V4L2_DV_BT_DMT_1152X864P75,
137 V4L2_DV_BT_DMT_1280X768P60_RB,
138 V4L2_DV_BT_DMT_1280X768P60,
139 V4L2_DV_BT_DMT_1280X768P75,
140 V4L2_DV_BT_DMT_1280X768P85,
141 V4L2_DV_BT_DMT_1280X800P60_RB,
142 V4L2_DV_BT_DMT_1280X800P60,
143 V4L2_DV_BT_DMT_1280X800P75,
144 V4L2_DV_BT_DMT_1280X800P85,
145 V4L2_DV_BT_DMT_1280X960P60,
146 V4L2_DV_BT_DMT_1280X960P85,
147 V4L2_DV_BT_DMT_1280X1024P60,
148 V4L2_DV_BT_DMT_1280X1024P75,
149 V4L2_DV_BT_DMT_1280X1024P85,
150 V4L2_DV_BT_DMT_1360X768P60,
151 V4L2_DV_BT_DMT_1400X1050P60_RB,
152 V4L2_DV_BT_DMT_1400X1050P60,
153 V4L2_DV_BT_DMT_1400X1050P75,
154 V4L2_DV_BT_DMT_1400X1050P85,
155 V4L2_DV_BT_DMT_1440X900P60_RB,
156 V4L2_DV_BT_DMT_1440X900P60,
157 V4L2_DV_BT_DMT_1600X1200P60,
158 V4L2_DV_BT_DMT_1680X1050P60_RB,
159 V4L2_DV_BT_DMT_1680X1050P60,
160 V4L2_DV_BT_DMT_1792X1344P60,
161 V4L2_DV_BT_DMT_1856X1392P60,
162 V4L2_DV_BT_DMT_1920X1200P60_RB,
547ed542 163 V4L2_DV_BT_DMT_1366X768P60_RB,
54450f59
HV		 164 V4L2_DV_BT_DMT_1366X768P60,
165 V4L2_DV_BT_DMT_1920X1080P60,
166 { },
167};
168
ccbd5bc4
HV		 169struct adv7604_video_standards {
170 struct v4l2_dv_timings timings;
171 u8 vid_std;
172 u8 v_freq;
173};
174
175/* sorted by number of lines */
176static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
177 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
178 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
179 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
180 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
181 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
182 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
183 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
184 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
185 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
186 /* TODO add 1920x1080P60_RB (CVT timing) */
187 { },
188};
189
190/* sorted by number of lines */
191static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
192 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
193 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
205 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
207 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
208 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
209 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
210 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
211 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
212 /* TODO add 1600X1200P60_RB (not a DMT timing) */
213 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
214 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
215 { },
216};
217
218/* sorted by number of lines */
219static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
220 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
221 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
222 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
223 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
224 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
225 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
226 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
227 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
228 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
229 { },
230};
231
232/* sorted by number of lines */
233static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
234 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
235 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
236 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
237 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
238 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
241 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
242 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
243 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
245 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
246 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
247 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
248 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
249 { },
250};
251
54450f59
HV		 252/* ----------------------------------------------------------------------- */
253
254static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
255{
256 return container_of(sd, struct adv7604_state, sd);
257}
258
259static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
260{
261 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
262}
263
264static inline unsigned hblanking(const struct v4l2_bt_timings *t)
265{
eacf8f9a 266 return V4L2_DV_BT_BLANKING_WIDTH(t);
54450f59
HV		 267}
268
269static inline unsigned htotal(const struct v4l2_bt_timings *t)
270{
eacf8f9a 271 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 272}
273
274static inline unsigned vblanking(const struct v4l2_bt_timings *t)
275{
eacf8f9a 276 return V4L2_DV_BT_BLANKING_HEIGHT(t);
54450f59
HV		 277}
278
279static inline unsigned vtotal(const struct v4l2_bt_timings *t)
280{
eacf8f9a 281 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 282}
283
284/* ----------------------------------------------------------------------- */
285
286static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
287 u8 command, bool check)
288{
289 union i2c_smbus_data data;
290
291 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
292 I2C_SMBUS_READ, command,
293 I2C_SMBUS_BYTE_DATA, &data))
294 return data.byte;
295 if (check)
296 v4l_err(client, "error reading %02x, %02x\n",
297 client->addr, command);
298 return -EIO;
299}
300
301static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
302{
303 return adv_smbus_read_byte_data_check(client, command, true);
304}
305
306static s32 adv_smbus_write_byte_data(struct i2c_client *client,
307 u8 command, u8 value)
308{
309 union i2c_smbus_data data;
310 int err;
311 int i;
312
313 data.byte = value;
314 for (i = 0; i < 3; i++) {
315 err = i2c_smbus_xfer(client->adapter, client->addr,
316 client->flags,
317 I2C_SMBUS_WRITE, command,
318 I2C_SMBUS_BYTE_DATA, &data);
319 if (!err)
320 break;
321 }
322 if (err < 0)
323 v4l_err(client, "error writing %02x, %02x, %02x\n",
324 client->addr, command, value);
325 return err;
326}
327
328static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
329 u8 command, unsigned length, const u8 *values)
330{
331 union i2c_smbus_data data;
332
333 if (length > I2C_SMBUS_BLOCK_MAX)
334 length = I2C_SMBUS_BLOCK_MAX;
335 data.block[0] = length;
336 memcpy(data.block + 1, values, length);
337 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
338 I2C_SMBUS_WRITE, command,
339 I2C_SMBUS_I2C_BLOCK_DATA, &data);
340}
341
342/* ----------------------------------------------------------------------- */
343
344static inline int io_read(struct v4l2_subdev *sd, u8 reg)
345{
346 struct i2c_client *client = v4l2_get_subdevdata(sd);
347
348 return adv_smbus_read_byte_data(client, reg);
349}
350
351static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
352{
353 struct i2c_client *client = v4l2_get_subdevdata(sd);
354
355 return adv_smbus_write_byte_data(client, reg, val);
356}
357
358static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
359{
360 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
361}
362
363static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
364{
365 struct adv7604_state *state = to_state(sd);
366
367 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
368}
369
370static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
371{
372 struct adv7604_state *state = to_state(sd);
373
374 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
375}
376
377static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
378{
379 struct adv7604_state *state = to_state(sd);
380
381 return adv_smbus_read_byte_data(state->i2c_cec, reg);
382}
383
384static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
385{
386 struct adv7604_state *state = to_state(sd);
387
388 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
389}
390
391static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
392{
393 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
394}
395
396static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
397{
398 struct adv7604_state *state = to_state(sd);
399
400 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
401}
402
403static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
404{
405 struct adv7604_state *state = to_state(sd);
406
407 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
408}
409
410static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
411{
412 struct adv7604_state *state = to_state(sd);
413
414 return adv_smbus_read_byte_data(state->i2c_esdp, reg);
415}
416
417static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
418{
419 struct adv7604_state *state = to_state(sd);
420
421 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
422}
423
424static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
425{
426 struct adv7604_state *state = to_state(sd);
427
428 return adv_smbus_read_byte_data(state->i2c_dpp, reg);
429}
430
431static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
432{
433 struct adv7604_state *state = to_state(sd);
434
435 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
436}
437
438static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
439{
440 struct adv7604_state *state = to_state(sd);
441
442 return adv_smbus_read_byte_data(state->i2c_afe, reg);
443}
444
445static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
446{
447 struct adv7604_state *state = to_state(sd);
448
449 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
450}
451
452static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
453{
454 struct adv7604_state *state = to_state(sd);
455
456 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
457}
458
459static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
460{
461 struct adv7604_state *state = to_state(sd);
462
463 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
464}
465
466static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
467{
468 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
469}
470
471static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
472{
473 struct adv7604_state *state = to_state(sd);
474
475 return adv_smbus_read_byte_data(state->i2c_edid, reg);
476}
477
478static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
479{
480 struct adv7604_state *state = to_state(sd);
481
482 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
483}
484
485static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
486{
487 struct adv7604_state *state = to_state(sd);
488 struct i2c_client *client = state->i2c_edid;
489 u8 msgbuf0[1] = { 0 };
490 u8 msgbuf1[256];
09f29673
S		 491 struct i2c_msg msg[2] = {
492 {
493 .addr = client->addr,
494 .len = 1,
495 .buf = msgbuf0
496 },
497 {
498 .addr = client->addr,
499 .flags = I2C_M_RD,
500 .len = len,
501 .buf = msgbuf1
502 },
503 };
54450f59
HV		 504
505 if (i2c_transfer(client->adapter, msg, 2) < 0)
506 return -EIO;
507 memcpy(val, msgbuf1, len);
508 return 0;
509}
510
54450f59
HV		 511static inline int edid_write_block(struct v4l2_subdev *sd,
512 unsigned len, const u8 *val)
513{
54450f59
HV		 514 struct adv7604_state *state = to_state(sd);
515 int err = 0;
516 int i;
517
518 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
519
54450f59
HV		 520 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
521 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
522 I2C_SMBUS_BLOCK_MAX, val + i);
dd08beb9
MR		 523 return err;
524}
54450f59 525
dd08beb9
MR		 526static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
527{
528 struct delayed_work *dwork = to_delayed_work(work);
529 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
530 delayed_work_enable_hotplug);
531 struct v4l2_subdev *sd = &state->sd;
54450f59 532
dd08beb9 533 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 534
dd08beb9 535 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
54450f59
HV		 536}
537
538static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
539{
540 struct adv7604_state *state = to_state(sd);
541
542 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
543}
544
545static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
546{
547 struct adv7604_state *state = to_state(sd);
548
549 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
550}
551
4a31a93a
MR		 552static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
553{
554 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
555}
556
54450f59
HV		 557static inline int test_read(struct v4l2_subdev *sd, u8 reg)
558{
559 struct adv7604_state *state = to_state(sd);
560
561 return adv_smbus_read_byte_data(state->i2c_test, reg);
562}
563
564static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
565{
566 struct adv7604_state *state = to_state(sd);
567
568 return adv_smbus_write_byte_data(state->i2c_test, reg, val);
569}
570
571static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
572{
573 struct adv7604_state *state = to_state(sd);
574
575 return adv_smbus_read_byte_data(state->i2c_cp, reg);
576}
577
578static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
579{
580 struct adv7604_state *state = to_state(sd);
581
582 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
583}
584
585static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
586{
587 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
588}
589
590static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
591{
592 struct adv7604_state *state = to_state(sd);
593
594 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
595}
596
597static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
598{
599 struct adv7604_state *state = to_state(sd);
600
601 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
602}
603
604/* ----------------------------------------------------------------------- */
605
4a31a93a
MR		 606static inline bool is_analog_input(struct v4l2_subdev *sd)
607{
608 struct adv7604_state *state = to_state(sd);
609
610 return state->selected_input == ADV7604_INPUT_VGA_RGB ||
611 state->selected_input == ADV7604_INPUT_VGA_COMP;
612}
613
614static inline bool is_digital_input(struct v4l2_subdev *sd)
615{
616 struct adv7604_state *state = to_state(sd);
617
618 return state->selected_input == ADV7604_INPUT_HDMI_PORT_A ||
619 state->selected_input == ADV7604_INPUT_HDMI_PORT_B ||
620 state->selected_input == ADV7604_INPUT_HDMI_PORT_C ||
621 state->selected_input == ADV7604_INPUT_HDMI_PORT_D;
622}
623
624/* ----------------------------------------------------------------------- */
625
54450f59
HV		 626#ifdef CONFIG_VIDEO_ADV_DEBUG
627static void adv7604_inv_register(struct v4l2_subdev *sd)
628{
629 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
630 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
631 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
632 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
633 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
634 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
635 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
636 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
637 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
638 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
639 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
640 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
641 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
642}
643
644static int adv7604_g_register(struct v4l2_subdev *sd,
645 struct v4l2_dbg_register *reg)
646{
54450f59
HV		 647 reg->size = 1;
648 switch (reg->reg >> 8) {
649 case 0:
650 reg->val = io_read(sd, reg->reg & 0xff);
651 break;
652 case 1:
653 reg->val = avlink_read(sd, reg->reg & 0xff);
654 break;
655 case 2:
656 reg->val = cec_read(sd, reg->reg & 0xff);
657 break;
658 case 3:
659 reg->val = infoframe_read(sd, reg->reg & 0xff);
660 break;
661 case 4:
662 reg->val = esdp_read(sd, reg->reg & 0xff);
663 break;
664 case 5:
665 reg->val = dpp_read(sd, reg->reg & 0xff);
666 break;
667 case 6:
668 reg->val = afe_read(sd, reg->reg & 0xff);
669 break;
670 case 7:
671 reg->val = rep_read(sd, reg->reg & 0xff);
672 break;
673 case 8:
674 reg->val = edid_read(sd, reg->reg & 0xff);
675 break;
676 case 9:
677 reg->val = hdmi_read(sd, reg->reg & 0xff);
678 break;
679 case 0xa:
680 reg->val = test_read(sd, reg->reg & 0xff);
681 break;
682 case 0xb:
683 reg->val = cp_read(sd, reg->reg & 0xff);
684 break;
685 case 0xc:
686 reg->val = vdp_read(sd, reg->reg & 0xff);
687 break;
688 default:
689 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
690 adv7604_inv_register(sd);
691 break;
692 }
693 return 0;
694}
695
696static int adv7604_s_register(struct v4l2_subdev *sd,
977ba3b1 697 const struct v4l2_dbg_register *reg)
54450f59 698{
1577461b
HV		 699 u8 val = reg->val & 0xff;
700
54450f59
HV		 701 switch (reg->reg >> 8) {
702 case 0:
1577461b 703 io_write(sd, reg->reg & 0xff, val);
54450f59
HV		 704 break;
705 case 1:
1577461b 706 avlink_write(sd, reg->reg & 0xff, val);
54450f59
HV		 707 break;
708 case 2:
1577461b 709 cec_write(sd, reg->reg & 0xff, val);
54450f59
HV		 710 break;
711 case 3:
1577461b 712 infoframe_write(sd, reg->reg & 0xff, val);
54450f59
HV		 713 break;
714 case 4:
1577461b 715 esdp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 716 break;
717 case 5:
1577461b 718 dpp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 719 break;
720 case 6:
1577461b 721 afe_write(sd, reg->reg & 0xff, val);
54450f59
HV		 722 break;
723 case 7:
1577461b 724 rep_write(sd, reg->reg & 0xff, val);
54450f59
HV		 725 break;
726 case 8:
1577461b 727 edid_write(sd, reg->reg & 0xff, val);
54450f59
HV		 728 break;
729 case 9:
1577461b 730 hdmi_write(sd, reg->reg & 0xff, val);
54450f59
HV		 731 break;
732 case 0xa:
1577461b 733 test_write(sd, reg->reg & 0xff, val);
54450f59
HV		 734 break;
735 case 0xb:
1577461b 736 cp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 737 break;
738 case 0xc:
1577461b 739 vdp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 740 break;
741 default:
742 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
743 adv7604_inv_register(sd);
744 break;
745 }
746 return 0;
747}
748#endif
749
750static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
751{
752 struct adv7604_state *state = to_state(sd);
4a31a93a 753 u8 reg_io_6f = io_read(sd, 0x6f);
54450f59 754
54450f59 755 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
4a31a93a
MR		 756 ((reg_io_6f & 0x10) >> 4) |
757 ((reg_io_6f & 0x08) >> 2) |
758 (reg_io_6f & 0x04) |
759 ((reg_io_6f & 0x02) << 2));
54450f59
HV		 760}
761
ccbd5bc4
HV		 762static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
763 u8 prim_mode,
764 const struct adv7604_video_standards *predef_vid_timings,
765 const struct v4l2_dv_timings *timings)
766{
ccbd5bc4
HV		 767 int i;
768
769 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 770 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
4a31a93a 771 is_digital_input(sd) ? 250000 : 1000000))
ccbd5bc4
HV		 772 continue;
773 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
774 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
775 prim_mode); /* v_freq and prim mode */
776 return 0;
777 }
778
779 return -1;
780}
781
782static int configure_predefined_video_timings(struct v4l2_subdev *sd,
783 struct v4l2_dv_timings *timings)
54450f59 784{
ccbd5bc4
HV		 785 struct adv7604_state *state = to_state(sd);
786 int err;
787
788 v4l2_dbg(1, debug, sd, "%s", __func__);
789
790 /* reset to default values */
791 io_write(sd, 0x16, 0x43);
792 io_write(sd, 0x17, 0x5a);
793 /* disable embedded syncs for auto graphics mode */
794 cp_write_and_or(sd, 0x81, 0xef, 0x00);
795 cp_write(sd, 0x8f, 0x00);
796 cp_write(sd, 0x90, 0x00);
797 cp_write(sd, 0xa2, 0x00);
798 cp_write(sd, 0xa3, 0x00);
799 cp_write(sd, 0xa4, 0x00);
800 cp_write(sd, 0xa5, 0x00);
801 cp_write(sd, 0xa6, 0x00);
802 cp_write(sd, 0xa7, 0x00);
803 cp_write(sd, 0xab, 0x00);
804 cp_write(sd, 0xac, 0x00);
805
4a31a93a 806 if (is_analog_input(sd)) {
ccbd5bc4
HV		 807 err = find_and_set_predefined_video_timings(sd,
808 0x01, adv7604_prim_mode_comp, timings);
809 if (err)
810 err = find_and_set_predefined_video_timings(sd,
811 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 812 } else if (is_digital_input(sd)) {
ccbd5bc4
HV		 813 err = find_and_set_predefined_video_timings(sd,
814 0x05, adv7604_prim_mode_hdmi_comp, timings);
815 if (err)
816 err = find_and_set_predefined_video_timings(sd,
817 0x06, adv7604_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 818 } else {
819 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
820 __func__, state->selected_input);
ccbd5bc4 821 err = -1;
ccbd5bc4
HV		 822 }
823
824
825 return err;
826}
827
828static void configure_custom_video_timings(struct v4l2_subdev *sd,
829 const struct v4l2_bt_timings *bt)
830{
831 struct adv7604_state *state = to_state(sd);
54450f59 832 struct i2c_client *client = v4l2_get_subdevdata(sd);
ccbd5bc4
HV		 833 u32 width = htotal(bt);
834 u32 height = vtotal(bt);
835 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
836 u16 cp_start_eav = width - bt->hfrontporch;
837 u16 cp_start_vbi = height - bt->vfrontporch;
838 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
839 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
840 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
841 const u8 pll[2] = {
842 0xc0 | ((width >> 8) & 0x1f),
843 width & 0xff
844 };
54450f59
HV		 845
846 v4l2_dbg(2, debug, sd, "%s\n", __func__);
847
4a31a93a 848 if (is_analog_input(sd)) {
ccbd5bc4
HV		 849 /* auto graphics */
850 io_write(sd, 0x00, 0x07); /* video std */
851 io_write(sd, 0x01, 0x02); /* prim mode */
852 /* enable embedded syncs for auto graphics mode */
853 cp_write_and_or(sd, 0x81, 0xef, 0x10);
54450f59 854
ccbd5bc4 855 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 856 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
857 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
4a31a93a 858 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll))
54450f59 859 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 860
861 /* active video - horizontal timing */
54450f59 862 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 863 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 864 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 865 cp_write(sd, 0xa4, cp_start_eav & 0xff);
866
867 /* active video - vertical timing */
54450f59 868 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 869 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 870 ((cp_end_vbi >> 8) & 0xf));
54450f59 871 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 872 } else if (is_digital_input(sd)) {
ccbd5bc4 873 /* set default prim_mode/vid_std for HDMI
39c1cb2b 874 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 875 io_write(sd, 0x00, 0x02); /* video std */
876 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 877 } else {
878 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
879 __func__, state->selected_input);
54450f59 880 }
54450f59 881
ccbd5bc4
HV		 882 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
883 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
884 cp_write(sd, 0xab, (height >> 4) & 0xff);
885 cp_write(sd, 0xac, (height & 0x0f) << 4);
886}
54450f59
HV		 887
888static void set_rgb_quantization_range(struct v4l2_subdev *sd)
889{
890 struct adv7604_state *state = to_state(sd);
891
9833239e
MR		 892 v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n",
893 __func__, state->rgb_quantization_range);
894
54450f59
HV		 895 switch (state->rgb_quantization_range) {
896 case V4L2_DV_RGB_RANGE_AUTO:
9833239e
MR		 897 if (state->selected_input == ADV7604_INPUT_VGA_RGB) {
898 /* Receiving analog RGB signal
899 * Set RGB full range (0-255) */
900 io_write_and_or(sd, 0x02, 0x0f, 0x10);
901 break;
902 }
903
904 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
905 /* Receiving analog YPbPr signal
906 * Set automode */
907 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
908 break;
909 }
910
911 if (hdmi_read(sd, 0x05) & 0x80) {
912 /* Receiving HDMI signal
913 * Set automode */
6b0d5d34 914 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
9833239e
MR		 915 break;
916 }
917
918 /* Receiving DVI-D signal
919 * ADV7604 selects RGB limited range regardless of
920 * input format (CE/IT) in automatic mode */
921 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
922 /* RGB limited range (16-235) */
923 io_write_and_or(sd, 0x02, 0x0f, 0x00);
924 } else {
925 /* RGB full range (0-255) */
926 io_write_and_or(sd, 0x02, 0x0f, 0x10);
54450f59
HV		 927 }
928 break;
929 case V4L2_DV_RGB_RANGE_LIMITED:
d261e842
MR		 930 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
931 /* YCrCb limited range (16-235) */
932 io_write_and_or(sd, 0x02, 0x0f, 0x20);
933 } else {
934 /* RGB limited range (16-235) */
935 io_write_and_or(sd, 0x02, 0x0f, 0x00);
936 }
54450f59
HV		 937 break;
938 case V4L2_DV_RGB_RANGE_FULL:
d261e842
MR		 939 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
940 /* YCrCb full range (0-255) */
941 io_write_and_or(sd, 0x02, 0x0f, 0x60);
942 } else {
943 /* RGB full range (0-255) */
944 io_write_and_or(sd, 0x02, 0x0f, 0x10);
945 }
54450f59
HV		 946 break;
947 }
948}
949
54450f59
HV		 950static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
951{
952 struct v4l2_subdev *sd = to_sd(ctrl);
953 struct adv7604_state *state = to_state(sd);
954
955 switch (ctrl->id) {
956 case V4L2_CID_BRIGHTNESS:
957 cp_write(sd, 0x3c, ctrl->val);
958 return 0;
959 case V4L2_CID_CONTRAST:
960 cp_write(sd, 0x3a, ctrl->val);
961 return 0;
962 case V4L2_CID_SATURATION:
963 cp_write(sd, 0x3b, ctrl->val);
964 return 0;
965 case V4L2_CID_HUE:
966 cp_write(sd, 0x3d, ctrl->val);
967 return 0;
968 case V4L2_CID_DV_RX_RGB_RANGE:
969 state->rgb_quantization_range = ctrl->val;
970 set_rgb_quantization_range(sd);
971 return 0;
972 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
973 /* Set the analog sampling phase. This is needed to find the
974 best sampling phase for analog video: an application or
975 driver has to try a number of phases and analyze the picture
976 quality before settling on the best performing phase. */
977 afe_write(sd, 0xc8, ctrl->val);
978 return 0;
979 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
980 /* Use the default blue color for free running mode,
981 or supply your own. */
982 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
983 return 0;
984 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
985 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
986 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
987 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
988 return 0;
989 }
990 return -EINVAL;
991}
992
54450f59
HV		 993/* ----------------------------------------------------------------------- */
994
995static inline bool no_power(struct v4l2_subdev *sd)
996{
997 /* Entire chip or CP powered off */
998 return io_read(sd, 0x0c) & 0x24;
999}
1000
1001static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1002{
4a31a93a
MR		 1003 struct adv7604_state *state = to_state(sd);
1004
1005 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1006}
1007
1008static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1009{
1010 return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1011}
1012
bb88f325
MB		 1013static inline bool is_hdmi(struct v4l2_subdev *sd)
1014{
1015 return hdmi_read(sd, 0x05) & 0x80;
1016}
1017
54450f59
HV		 1018static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1019{
1020 /* TODO channel 2 */
1021 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1022}
1023
1024static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1025{
1026 /* TODO channel 2 */
1027 return !(cp_read(sd, 0xb1) & 0x80);
1028}
1029
1030static inline bool no_signal(struct v4l2_subdev *sd)
1031{
54450f59
HV		 1032 bool ret;
1033
1034 ret = no_power(sd);
1035
1036 ret |= no_lock_stdi(sd);
1037 ret |= no_lock_sspd(sd);
1038
4a31a93a 1039 if (is_digital_input(sd)) {
54450f59
HV		 1040 ret |= no_lock_tmds(sd);
1041 ret |= no_signal_tmds(sd);
1042 }
1043
1044 return ret;
1045}
1046
1047static inline bool no_lock_cp(struct v4l2_subdev *sd)
1048{
1049 /* CP has detected a non standard number of lines on the incoming
1050 video compared to what it is configured to receive by s_dv_timings */
1051 return io_read(sd, 0x12) & 0x01;
1052}
1053
1054static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1055{
54450f59
HV		 1056 *status = 0;
1057 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1058 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1059 if (no_lock_cp(sd))
4a31a93a 1060 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1061
1062 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1063
1064 return 0;
1065}
1066
1067/* ----------------------------------------------------------------------- */
1068
54450f59
HV		 1069struct stdi_readback {
1070 u16 bl, lcf, lcvs;
1071 u8 hs_pol, vs_pol;
1072 bool interlaced;
1073};
1074
1075static int stdi2dv_timings(struct v4l2_subdev *sd,
1076 struct stdi_readback *stdi,
1077 struct v4l2_dv_timings *timings)
1078{
1079 struct adv7604_state *state = to_state(sd);
1080 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1081 u32 pix_clk;
1082 int i;
1083
1084 for (i = 0; adv7604_timings[i].bt.height; i++) {
1085 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1086 continue;
1087 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1088 continue;
1089
1090 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1091
1092 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1093 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1094 *timings = adv7604_timings[i];
1095 return 0;
1096 }
1097 }
1098
1099 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1100 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1101 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1102 timings))
1103 return 0;
1104 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1105 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1106 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1107 state->aspect_ratio, timings))
1108 return 0;
1109
ccbd5bc4
HV		 1110 v4l2_dbg(2, debug, sd,
1111 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1112 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1113 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1114 return -1;
1115}
1116
1117static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1118{
1119 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1120 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1121 return -1;
1122 }
1123
1124 /* read STDI */
1125 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1126 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1127 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1128 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1129
1130 /* read SSPD */
1131 if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1132 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1133 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1134 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1135 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1136 } else {
1137 stdi->hs_pol = 'x';
1138 stdi->vs_pol = 'x';
1139 }
1140
1141 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1142 v4l2_dbg(2, debug, sd,
1143 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1144 return -1;
1145 }
1146
1147 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1148 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1149 memset(stdi, 0, sizeof(struct stdi_readback));
1150 return -1;
1151 }
1152
1153 v4l2_dbg(2, debug, sd,
1154 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1155 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1156 stdi->hs_pol, stdi->vs_pol,
1157 stdi->interlaced ? "interlaced" : "progressive");
1158
1159 return 0;
1160}
1161
1162static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1163 struct v4l2_enum_dv_timings *timings)
1164{
1165 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1166 return -EINVAL;
1167 memset(timings->reserved, 0, sizeof(timings->reserved));
1168 timings->timings = adv7604_timings[timings->index];
1169 return 0;
1170}
1171
1172static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1173 struct v4l2_dv_timings_cap *cap)
1174{
54450f59
HV		 1175 cap->type = V4L2_DV_BT_656_1120;
1176 cap->bt.max_width = 1920;
1177 cap->bt.max_height = 1200;
fe9c2564 1178 cap->bt.min_pixelclock = 25000000;
4a31a93a 1179 if (is_digital_input(sd))
54450f59
HV		 1180 cap->bt.max_pixelclock = 225000000;
1181 else
1182 cap->bt.max_pixelclock = 170000000;
1183 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1184 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1185 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1186 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1187 return 0;
1188}
1189
1190/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1191 if the format is listed in adv7604_timings[] */
1192static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1193 struct v4l2_dv_timings *timings)
1194{
54450f59
HV		 1195 int i;
1196
1197 for (i = 0; adv7604_timings[i].bt.width; i++) {
ef1ed8f5 1198 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
4a31a93a 1199 is_digital_input(sd) ? 250000 : 1000000)) {
54450f59
HV		 1200 *timings = adv7604_timings[i];
1201 break;
1202 }
1203 }
1204}
1205
1206static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1207 struct v4l2_dv_timings *timings)
1208{
1209 struct adv7604_state *state = to_state(sd);
1210 struct v4l2_bt_timings *bt = &timings->bt;
1211 struct stdi_readback stdi;
1212
1213 if (!timings)
1214 return -EINVAL;
1215
1216 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1217
1218 if (no_signal(sd)) {
1e0b9156 1219 state->restart_stdi_once = true;
54450f59
HV		 1220 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1221 return -ENOLINK;
1222 }
1223
1224 /* read STDI */
1225 if (read_stdi(sd, &stdi)) {
1226 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1227 return -ENOLINK;
1228 }
1229 bt->interlaced = stdi.interlaced ?
1230 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1231
4a31a93a 1232 if (is_digital_input(sd)) {
bb88f325
MB		 1233 uint32_t freq;
1234
54450f59
HV		 1235 timings->type = V4L2_DV_BT_656_1120;
1236
1237 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1238 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
bb88f325 1239 freq = (hdmi_read(sd, 0x06) * 1000000) +
54450f59 1240 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
bb88f325
MB		 1241 if (is_hdmi(sd)) {
1242 /* adjust for deep color mode */
1243 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1244
1245 freq = freq * 8 / bits_per_channel;
1246 }
1247 bt->pixelclock = freq;
54450f59
HV		 1248 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1249 hdmi_read(sd, 0x21);
1250 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1251 hdmi_read(sd, 0x23);
1252 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1253 hdmi_read(sd, 0x25);
1254 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1255 hdmi_read(sd, 0x2b)) / 2;
1256 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1257 hdmi_read(sd, 0x2f)) / 2;
1258 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1259 hdmi_read(sd, 0x33)) / 2;
1260 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1261 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1262 if (bt->interlaced == V4L2_DV_INTERLACED) {
1263 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1264 hdmi_read(sd, 0x0c);
1265 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1266 hdmi_read(sd, 0x2d)) / 2;
1267 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1268 hdmi_read(sd, 0x31)) / 2;
1269 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1270 hdmi_read(sd, 0x35)) / 2;
1271 }
1272 adv7604_fill_optional_dv_timings_fields(sd, timings);
1273 } else {
1274 /* find format
80939647 1275 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1276 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1277 */
1278 if (!stdi2dv_timings(sd, &stdi, timings))
1279 goto found;
1280 stdi.lcvs += 1;
1281 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1282 if (!stdi2dv_timings(sd, &stdi, timings))
1283 goto found;
1284 stdi.lcvs -= 2;
1285 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1286 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1287 /*
1288 * The STDI block may measure wrong values, especially
1289 * for lcvs and lcf. If the driver can not find any
1290 * valid timing, the STDI block is restarted to measure
1291 * the video timings again. The function will return an
1292 * error, but the restart of STDI will generate a new
1293 * STDI interrupt and the format detection process will
1294 * restart.
1295 */
1296 if (state->restart_stdi_once) {
1297 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1298 /* TODO restart STDI for Sync Channel 2 */
1299 /* enter one-shot mode */
1300 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1301 /* trigger STDI restart */
1302 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1303 /* reset to continuous mode */
1304 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1305 state->restart_stdi_once = false;
1306 return -ENOLINK;
1307 }
54450f59
HV		 1308 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1309 return -ERANGE;
1310 }
cf9afb1d 1311 state->restart_stdi_once = true;
54450f59
HV		 1312 }
1313found:
1314
1315 if (no_signal(sd)) {
1316 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1317 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1318 return -ENOLINK;
1319 }
1320
4a31a93a
MR		 1321 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1322 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1323 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1324 __func__, (u32)bt->pixelclock);
1325 return -ERANGE;
1326 }
1327
1328 if (debug > 1)
11d034c8
HV		 1329 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1330 timings, true);
54450f59
HV		 1331
1332 return 0;
1333}
1334
1335static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1336 struct v4l2_dv_timings *timings)
1337{
1338 struct adv7604_state *state = to_state(sd);
1339 struct v4l2_bt_timings *bt;
ccbd5bc4 1340 int err;
54450f59
HV		 1341
1342 if (!timings)
1343 return -EINVAL;
1344
1345 bt = &timings->bt;
1346
4a31a93a
MR		 1347 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1348 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1349 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1350 __func__, (u32)bt->pixelclock);
1351 return -ERANGE;
1352 }
ccbd5bc4 1353
54450f59
HV		 1354 adv7604_fill_optional_dv_timings_fields(sd, timings);
1355
1356 state->timings = *timings;
1357
ccbd5bc4
HV		 1358 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1359
1360 /* Use prim_mode and vid_std when available */
1361 err = configure_predefined_video_timings(sd, timings);
1362 if (err) {
1363 /* custom settings when the video format
1364 does not have prim_mode/vid_std */
1365 configure_custom_video_timings(sd, bt);
1366 }
54450f59
HV		 1367
1368 set_rgb_quantization_range(sd);
1369
1370
1371 if (debug > 1)
11d034c8
HV		 1372 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1373 timings, true);
54450f59
HV		 1374 return 0;
1375}
1376
1377static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1378 struct v4l2_dv_timings *timings)
1379{
1380 struct adv7604_state *state = to_state(sd);
1381
1382 *timings = state->timings;
1383 return 0;
1384}
1385
6b0d5d34 1386static void enable_input(struct v4l2_subdev *sd)
54450f59 1387{
6b0d5d34
HV		 1388 struct adv7604_state *state = to_state(sd);
1389
4a31a93a 1390 if (is_analog_input(sd)) {
54450f59 1391 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1392 } else if (is_digital_input(sd)) {
4a31a93a 1393 hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input);
54450f59
HV		 1394 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1395 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
5474b983 1396 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
4a31a93a
MR		 1397 } else {
1398 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1399 __func__, state->selected_input);
54450f59
HV		 1400 }
1401}
1402
1403static void disable_input(struct v4l2_subdev *sd)
1404{
5474b983
MR		 1405 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio */
1406 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1407 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
54450f59
HV		 1408 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1409}
1410
6b0d5d34 1411static void select_input(struct v4l2_subdev *sd)
54450f59 1412{
6b0d5d34 1413 struct adv7604_state *state = to_state(sd);
54450f59 1414
4a31a93a 1415 if (is_analog_input(sd)) {
54450f59
HV		 1416 /* reset ADI recommended settings for HDMI: */
1417 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1418 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1419 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1420 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1421 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1422 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1423 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1424 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1425 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1426 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1427 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1428 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1429
1430 afe_write(sd, 0x00, 0x08); /* power up ADC */
1431 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1432 afe_write(sd, 0xc8, 0x00); /* phase control */
1433
1434 /* set ADI recommended settings for digitizer */
1435 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1436 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1437 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1438 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1439 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1440 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1441 } else if (is_digital_input(sd)) {
1442 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1443
54450f59
HV		 1444 /* set ADI recommended settings for HDMI: */
1445 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1446 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1447 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1448 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1449 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1450 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1451 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1452 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1453 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1454 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1455 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1456 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1457
1458 afe_write(sd, 0x00, 0xff); /* power down ADC */
1459 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1460 afe_write(sd, 0xc8, 0x40); /* phase control */
1461
1462 /* reset ADI recommended settings for digitizer */
1463 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1464 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1465 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1466 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1467 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1468 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1469 } else {
1470 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1471 __func__, state->selected_input);
54450f59
HV		 1472 }
1473}
1474
1475static int adv7604_s_routing(struct v4l2_subdev *sd,
1476 u32 input, u32 output, u32 config)
1477{
1478 struct adv7604_state *state = to_state(sd);
1479
ff4f80fd
MR		 1480 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1481 __func__, input, state->selected_input);
1482
1483 if (input == state->selected_input)
1484 return 0;
54450f59 1485
4a31a93a 1486 state->selected_input = input;
54450f59
HV		 1487
1488 disable_input(sd);
1489
6b0d5d34 1490 select_input(sd);
54450f59 1491
6b0d5d34 1492 enable_input(sd);
54450f59
HV		 1493
1494 return 0;
1495}
1496
1497static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1498 enum v4l2_mbus_pixelcode *code)
1499{
1500 if (index)
1501 return -EINVAL;
1502 /* Good enough for now */
1503 *code = V4L2_MBUS_FMT_FIXED;
1504 return 0;
1505}
1506
1507static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1508 struct v4l2_mbus_framefmt *fmt)
1509{
1510 struct adv7604_state *state = to_state(sd);
1511
1512 fmt->width = state->timings.bt.width;
1513 fmt->height = state->timings.bt.height;
1514 fmt->code = V4L2_MBUS_FMT_FIXED;
1515 fmt->field = V4L2_FIELD_NONE;
1516 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1517 fmt->colorspace = (state->timings.bt.height <= 576) ?
1518 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1519 }
1520 return 0;
1521}
1522
1523static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1524{
54450f59
HV		 1525 u8 fmt_change, fmt_change_digital, tx_5v;
1526
ff4f80fd
MR		 1527 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1528
54450f59
HV		 1529 /* format change */
1530 fmt_change = io_read(sd, 0x43) & 0x98;
1531 if (fmt_change)
1532 io_write(sd, 0x44, fmt_change);
14d03233 1533
4a31a93a 1534 fmt_change_digital = is_digital_input(sd) ? (io_read(sd, 0x6b) & 0xc0) : 0;
54450f59
HV		 1535 if (fmt_change_digital)
1536 io_write(sd, 0x6c, fmt_change_digital);
14d03233 1537
54450f59
HV		 1538 if (fmt_change || fmt_change_digital) {
1539 v4l2_dbg(1, debug, sd,
25a64ac9 1540 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1541 __func__, fmt_change, fmt_change_digital);
25a64ac9 1542
14d03233 1543 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
25a64ac9 1544
54450f59
HV		 1545 if (handled)
1546 *handled = true;
1547 }
1548 /* tx 5v detect */
4a31a93a 1549 tx_5v = io_read(sd, 0x70) & 0x1e;
54450f59
HV		 1550 if (tx_5v) {
1551 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1552 io_write(sd, 0x71, tx_5v);
1553 adv7604_s_detect_tx_5v_ctrl(sd);
1554 if (handled)
1555 *handled = true;
1556 }
1557 return 0;
1558}
1559
1560static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1561{
1562 struct adv7604_state *state = to_state(sd);
4a31a93a 1563 u8 *data = NULL;
54450f59 1564
4a31a93a 1565 if (edid->pad > ADV7604_EDID_PORT_D)
54450f59
HV		 1566 return -EINVAL;
1567 if (edid->blocks == 0)
1568 return -EINVAL;
4a31a93a 1569 if (edid->blocks > 2)
54450f59 1570 return -EINVAL;
4a31a93a
MR		 1571 if (edid->start_block > 1)
1572 return -EINVAL;
1573 if (edid->start_block == 1)
1574 edid->blocks = 1;
54450f59
HV		 1575 if (!edid->edid)
1576 return -EINVAL;
4a31a93a
MR		 1577
1578 if (edid->blocks > state->edid.blocks)
1579 edid->blocks = state->edid.blocks;
1580
1581 switch (edid->pad) {
1582 case ADV7604_EDID_PORT_A:
1583 case ADV7604_EDID_PORT_B:
1584 case ADV7604_EDID_PORT_C:
1585 case ADV7604_EDID_PORT_D:
1586 if (state->edid.present & (1 << edid->pad))
1587 data = state->edid.edid;
1588 break;
1589 default:
1590 return -EINVAL;
1591 break;
1592 }
1593 if (!data)
1594 return -ENODATA;
1595
1596 memcpy(edid->edid,
1597 data + edid->start_block * 128,
54450f59
HV		 1598 edid->blocks * 128);
1599 return 0;
1600}
1601
dd08beb9 1602static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 1603{
1604 u8 d;
1605
1606 if ((edid[0x7e] != 1) ||
1607 (edid[0x80] != 0x02) ||
1608 (edid[0x81] != 0x03)) {
1609 return -1;
1610 }
1611
1612 /* search Vendor Specific Data Block (tag 3) */
1613 d = edid[0x82] & 0x7f;
1614 if (d > 4) {
1615 int i = 0x84;
1616 int end = 0x80 + d;
1617
1618 do {
1619 u8 tag = edid[i] >> 5;
1620 u8 len = edid[i] & 0x1f;
1621
1622 if ((tag == 3) && (len >= 5))
1623 return i + 4;
1624 i += len + 1;
1625 } while (i < end);
1626 }
1627 return -1;
1628}
1629
54450f59
HV		 1630static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1631{
1632 struct adv7604_state *state = to_state(sd);
dd08beb9 1633 int spa_loc;
3e86aa85 1634 int tmp = 0;
54450f59 1635 int err;
dd08beb9 1636 int i;
54450f59 1637
4a31a93a 1638 if (edid->pad > ADV7604_EDID_PORT_D)
54450f59
HV		 1639 return -EINVAL;
1640 if (edid->start_block != 0)
1641 return -EINVAL;
1642 if (edid->blocks == 0) {
3e86aa85 1643 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a
MR		 1644 state->edid.present &= ~(1 << edid->pad);
1645 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
3e86aa85
MR		 1646 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1647
54450f59
HV		 1648 /* Fall back to a 16:9 aspect ratio */
1649 state->aspect_ratio.numerator = 16;
1650 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 1651
1652 if (!state->edid.present)
1653 state->edid.blocks = 0;
1654
1655 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
1656 __func__, edid->pad, state->edid.present);
54450f59
HV		 1657 return 0;
1658 }
4a31a93a
MR		 1659 if (edid->blocks > 2) {
1660 edid->blocks = 2;
54450f59 1661 return -E2BIG;
4a31a93a 1662 }
54450f59
HV		 1663 if (!edid->edid)
1664 return -EINVAL;
4a31a93a 1665
dd08beb9
MR		 1666 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
1667 __func__, edid->pad, state->edid.present);
1668
3e86aa85 1669 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 1670 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3e86aa85
MR		 1671 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp);
1672 rep_write_and_or(sd, 0x77, 0xf0, 0x00);
1673
dd08beb9
MR		 1674 spa_loc = get_edid_spa_location(edid->edid);
1675 if (spa_loc < 0)
1676 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
1677
3e86aa85
MR		 1678 switch (edid->pad) {
1679 case ADV7604_EDID_PORT_A:
dd08beb9
MR		 1680 state->spa_port_a[0] = edid->edid[spa_loc];
1681 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85
MR		 1682 break;
1683 case ADV7604_EDID_PORT_B:
dd08beb9
MR		 1684 rep_write(sd, 0x70, edid->edid[spa_loc]);
1685 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85
MR		 1686 break;
1687 case ADV7604_EDID_PORT_C:
dd08beb9
MR		 1688 rep_write(sd, 0x72, edid->edid[spa_loc]);
1689 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85
MR		 1690 break;
1691 case ADV7604_EDID_PORT_D:
dd08beb9
MR		 1692 rep_write(sd, 0x74, edid->edid[spa_loc]);
1693 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 1694 break;
dd08beb9
MR		 1695 default:
1696 return -EINVAL;
3e86aa85 1697 }
dd08beb9
MR		 1698 rep_write(sd, 0x76, spa_loc & 0xff);
1699 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
3e86aa85 1700
dd08beb9
MR		 1701 edid->edid[spa_loc] = state->spa_port_a[0];
1702 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 1703
1704 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
1705 state->edid.blocks = edid->blocks;
54450f59
HV		 1706 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1707 edid->edid[0x16]);
3e86aa85 1708 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 1709
1710 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
1711 if (err < 0) {
3e86aa85 1712 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 1713 return err;
1714 }
1715
dd08beb9
MR		 1716 /* adv7604 calculates the checksums and enables I2C access to internal
1717 EDID RAM from DDC port. */
1718 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1719
1720 for (i = 0; i < 1000; i++) {
1721 if (rep_read(sd, 0x7d) & state->edid.present)
1722 break;
1723 mdelay(1);
1724 }
1725 if (i == 1000) {
1726 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
1727 return -EIO;
1728 }
1729
1730
4a31a93a
MR		 1731 /* enable hotplug after 100 ms */
1732 queue_delayed_work(state->work_queues,
1733 &state->delayed_work_enable_hotplug, HZ / 10);
1734 return 0;
54450f59
HV		 1735}
1736
1737/*********** avi info frame CEA-861-E **************/
1738
1739static void print_avi_infoframe(struct v4l2_subdev *sd)
1740{
1741 int i;
1742 u8 buf[14];
1743 u8 avi_len;
1744 u8 avi_ver;
1745
bb88f325 1746 if (!is_hdmi(sd)) {
54450f59
HV		 1747 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1748 return;
1749 }
1750 if (!(io_read(sd, 0x60) & 0x01)) {
1751 v4l2_info(sd, "AVI infoframe not received\n");
1752 return;
1753 }
1754
1755 if (io_read(sd, 0x83) & 0x01) {
1756 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1757 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1758 if (io_read(sd, 0x83) & 0x01) {
1759 v4l2_info(sd, "AVI infoframe checksum error still present\n");
1760 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1761 }
1762 }
1763
1764 avi_len = infoframe_read(sd, 0xe2);
1765 avi_ver = infoframe_read(sd, 0xe1);
1766 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1767 avi_ver, avi_len);
1768
1769 if (avi_ver != 0x02)
1770 return;
1771
1772 for (i = 0; i < 14; i++)
1773 buf[i] = infoframe_read(sd, i);
1774
1775 v4l2_info(sd,
1776 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1777 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1778 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1779}
1780
1781static int adv7604_log_status(struct v4l2_subdev *sd)
1782{
1783 struct adv7604_state *state = to_state(sd);
1784 struct v4l2_dv_timings timings;
1785 struct stdi_readback stdi;
1786 u8 reg_io_0x02 = io_read(sd, 0x02);
1787
1788 char *csc_coeff_sel_rb[16] = {
1789 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1790 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1791 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1792 "reserved", "reserved", "reserved", "reserved", "manual"
1793 };
1794 char *input_color_space_txt[16] = {
1795 "RGB limited range (16-235)", "RGB full range (0-255)",
1796 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 1797 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 1798 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1799 "invalid", "invalid", "invalid", "invalid", "invalid",
1800 "invalid", "invalid", "automatic"
1801 };
1802 char *rgb_quantization_range_txt[] = {
1803 "Automatic",
1804 "RGB limited range (16-235)",
1805 "RGB full range (0-255)",
1806 };
bb88f325
MB		 1807 char *deep_color_mode_txt[4] = {
1808 "8-bits per channel",
1809 "10-bits per channel",
1810 "12-bits per channel",
1811 "16-bits per channel (not supported)"
1812 };
54450f59
HV		 1813
1814 v4l2_info(sd, "-----Chip status-----\n");
1815 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
4a31a93a
MR		 1816 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
1817 ((rep_read(sd, 0x7d) & 0x01) ? "Yes" : "No"),
1818 ((rep_read(sd, 0x7d) & 0x02) ? "Yes" : "No"),
1819 ((rep_read(sd, 0x7d) & 0x04) ? "Yes" : "No"),
1820 ((rep_read(sd, 0x7d) & 0x08) ? "Yes" : "No"));
54450f59
HV		 1821 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1822 "enabled" : "disabled");
1823
1824 v4l2_info(sd, "-----Signal status-----\n");
4a31a93a
MR		 1825 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
1826 ((io_read(sd, 0x6f) & 0x10) ? "Yes" : "No"),
1827 ((io_read(sd, 0x6f) & 0x08) ? "Yes" : "No"),
1828 ((io_read(sd, 0x6f) & 0x04) ? "Yes" : "No"),
1829 ((io_read(sd, 0x6f) & 0x02) ? "Yes" : "No"));
54450f59
HV		 1830 v4l2_info(sd, "TMDS signal detected: %s\n",
1831 no_signal_tmds(sd) ? "false" : "true");
1832 v4l2_info(sd, "TMDS signal locked: %s\n",
1833 no_lock_tmds(sd) ? "false" : "true");
1834 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1835 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1836 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1837 v4l2_info(sd, "CP free run: %s\n",
1838 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
ccbd5bc4
HV		 1839 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1840 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1841 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 1842
1843 v4l2_info(sd, "-----Video Timings-----\n");
1844 if (read_stdi(sd, &stdi))
1845 v4l2_info(sd, "STDI: not locked\n");
1846 else
1847 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1848 stdi.lcf, stdi.bl, stdi.lcvs,
1849 stdi.interlaced ? "interlaced" : "progressive",
1850 stdi.hs_pol, stdi.vs_pol);
1851 if (adv7604_query_dv_timings(sd, &timings))
1852 v4l2_info(sd, "No video detected\n");
1853 else
11d034c8
HV		 1854 v4l2_print_dv_timings(sd->name, "Detected format: ",
1855 &timings, true);
1856 v4l2_print_dv_timings(sd->name, "Configured format: ",
1857 &state->timings, true);
54450f59 1858
76eb2d30
MR		 1859 if (no_signal(sd))
1860 return 0;
1861
54450f59
HV		 1862 v4l2_info(sd, "-----Color space-----\n");
1863 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1864 rgb_quantization_range_txt[state->rgb_quantization_range]);
1865 v4l2_info(sd, "Input color space: %s\n",
1866 input_color_space_txt[reg_io_0x02 >> 4]);
1867 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1868 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1869 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1870 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
76eb2d30 1871 "enabled" : "disabled");
54450f59
HV		 1872 v4l2_info(sd, "Color space conversion: %s\n",
1873 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1874
4a31a93a 1875 if (!is_digital_input(sd))
76eb2d30
MR		 1876 return 0;
1877
1878 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 1879 v4l2_info(sd, "Digital video port selected: %c\n",
1880 (hdmi_read(sd, 0x00) & 0x03) + 'A');
1881 v4l2_info(sd, "HDCP encrypted content: %s\n",
1882 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 1883 v4l2_info(sd, "HDCP keys read: %s%s\n",
1884 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
1885 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
1886 if (!is_hdmi(sd)) {
1887 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
1888 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
1889 bool audio_mute = io_read(sd, 0x65) & 0x40;
1890
1891 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
1892 audio_pll_locked ? "locked" : "not locked",
1893 audio_sample_packet_detect ? "detected" : "not detected",
1894 audio_mute ? "muted" : "enabled");
1895 if (audio_pll_locked && audio_sample_packet_detect) {
1896 v4l2_info(sd, "Audio format: %s\n",
1897 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
1898 }
1899 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
1900 (hdmi_read(sd, 0x5c) << 8) +
1901 (hdmi_read(sd, 0x5d) & 0xf0));
1902 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
1903 (hdmi_read(sd, 0x5e) << 8) +
1904 hdmi_read(sd, 0x5f));
1905 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
1906
1907 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
1908
54450f59
HV		 1909 print_avi_infoframe(sd);
1910 }
1911
1912 return 0;
1913}
1914
1915/* ----------------------------------------------------------------------- */
1916
1917static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1918 .s_ctrl = adv7604_s_ctrl,
1919};
1920
1921static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1922 .log_status = adv7604_log_status,
1923 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1924 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1925 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1926 .g_ctrl = v4l2_subdev_g_ctrl,
1927 .s_ctrl = v4l2_subdev_s_ctrl,
1928 .queryctrl = v4l2_subdev_queryctrl,
1929 .querymenu = v4l2_subdev_querymenu,
54450f59
HV		 1930 .interrupt_service_routine = adv7604_isr,
1931#ifdef CONFIG_VIDEO_ADV_DEBUG
1932 .g_register = adv7604_g_register,
1933 .s_register = adv7604_s_register,
1934#endif
1935};
1936
1937static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1938 .s_routing = adv7604_s_routing,
1939 .g_input_status = adv7604_g_input_status,
1940 .s_dv_timings = adv7604_s_dv_timings,
1941 .g_dv_timings = adv7604_g_dv_timings,
1942 .query_dv_timings = adv7604_query_dv_timings,
1943 .enum_dv_timings = adv7604_enum_dv_timings,
1944 .dv_timings_cap = adv7604_dv_timings_cap,
1945 .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1946 .g_mbus_fmt = adv7604_g_mbus_fmt,
1947 .try_mbus_fmt = adv7604_g_mbus_fmt,
1948 .s_mbus_fmt = adv7604_g_mbus_fmt,
1949};
1950
1951static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1952 .get_edid = adv7604_get_edid,
1953 .set_edid = adv7604_set_edid,
1954};
1955
1956static const struct v4l2_subdev_ops adv7604_ops = {
1957 .core = &adv7604_core_ops,
1958 .video = &adv7604_video_ops,
1959 .pad = &adv7604_pad_ops,
1960};
1961
1962/* -------------------------- custom ctrls ---------------------------------- */
1963
1964static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1965 .ops = &adv7604_ctrl_ops,
1966 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1967 .name = "Analog Sampling Phase",
1968 .type = V4L2_CTRL_TYPE_INTEGER,
1969 .min = 0,
1970 .max = 0x1f,
1971 .step = 1,
1972 .def = 0,
1973};
1974
1975static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1976 .ops = &adv7604_ctrl_ops,
1977 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1978 .name = "Free Running Color, Manual",
1979 .type = V4L2_CTRL_TYPE_BOOLEAN,
1980 .min = false,
1981 .max = true,
1982 .step = 1,
1983 .def = false,
1984};
1985
1986static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1987 .ops = &adv7604_ctrl_ops,
1988 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1989 .name = "Free Running Color",
1990 .type = V4L2_CTRL_TYPE_INTEGER,
1991 .min = 0x0,
1992 .max = 0xffffff,
1993 .step = 0x1,
1994 .def = 0x0,
1995};
1996
1997/* ----------------------------------------------------------------------- */
1998
1999static int adv7604_core_init(struct v4l2_subdev *sd)
2000{
2001 struct adv7604_state *state = to_state(sd);
2002 struct adv7604_platform_data *pdata = &state->pdata;
2003
2004 hdmi_write(sd, 0x48,
2005 (pdata->disable_pwrdnb ? 0x80 : 0) |
2006 (pdata->disable_cable_det_rst ? 0x40 : 0));
2007
2008 disable_input(sd);
2009
2010 /* power */
2011 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2012 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2013 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2014
2015 /* video format */
2016 io_write_and_or(sd, 0x02, 0xf0,
2017 pdata->alt_gamma << 3 |
2018 pdata->op_656_range << 2 |
2019 pdata->rgb_out << 1 |
2020 pdata->alt_data_sat << 0);
2021 io_write(sd, 0x03, pdata->op_format_sel);
2022 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2023 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2024 pdata->insert_av_codes << 2 |
2025 pdata->replicate_av_codes << 1 |
2026 pdata->invert_cbcr << 0);
2027
2028 /* TODO from platform data */
2029 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
2030 io_write(sd, 0x06, 0xa6); /* positive VS and HS */
f31b62e1
MK		 2031
2032 /* Adjust drive strength */
2033 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2034 pdata->dr_str_clk << 2 |
2035 pdata->dr_str_sync);
2036
54450f59
HV		 2037 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2038 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2039 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2040 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2041 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2042 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2043 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2044 for digital formats */
2045
5474b983
MR		 2046 /* HDMI audio */
2047 hdmi_write_and_or(sd, 0x15, 0xfc, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2048 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2049 hdmi_write_and_or(sd, 0x68, 0xf9, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2050
54450f59
HV		 2051 /* TODO from platform data */
2052 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2053
2054 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2055 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2056
54450f59
HV		 2057 /* interrupts */
2058 io_write(sd, 0x40, 0xc2); /* Configure INT1 */
2059 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2060 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2061 io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
4a31a93a 2062 io_write(sd, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */
54450f59
HV		 2063
2064 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2065}
2066
2067static void adv7604_unregister_clients(struct adv7604_state *state)
2068{
2069 if (state->i2c_avlink)
2070 i2c_unregister_device(state->i2c_avlink);
2071 if (state->i2c_cec)
2072 i2c_unregister_device(state->i2c_cec);
2073 if (state->i2c_infoframe)
2074 i2c_unregister_device(state->i2c_infoframe);
2075 if (state->i2c_esdp)
2076 i2c_unregister_device(state->i2c_esdp);
2077 if (state->i2c_dpp)
2078 i2c_unregister_device(state->i2c_dpp);
2079 if (state->i2c_afe)
2080 i2c_unregister_device(state->i2c_afe);
2081 if (state->i2c_repeater)
2082 i2c_unregister_device(state->i2c_repeater);
2083 if (state->i2c_edid)
2084 i2c_unregister_device(state->i2c_edid);
2085 if (state->i2c_hdmi)
2086 i2c_unregister_device(state->i2c_hdmi);
2087 if (state->i2c_test)
2088 i2c_unregister_device(state->i2c_test);
2089 if (state->i2c_cp)
2090 i2c_unregister_device(state->i2c_cp);
2091 if (state->i2c_vdp)
2092 i2c_unregister_device(state->i2c_vdp);
2093}
2094
2095static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2096 u8 addr, u8 io_reg)
2097{
2098 struct i2c_client *client = v4l2_get_subdevdata(sd);
2099
2100 if (addr)
2101 io_write(sd, io_reg, addr << 1);
2102 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2103}
2104
2105static int adv7604_probe(struct i2c_client *client,
2106 const struct i2c_device_id *id)
2107{
2108 struct adv7604_state *state;
2109 struct adv7604_platform_data *pdata = client->dev.platform_data;
2110 struct v4l2_ctrl_handler *hdl;
2111 struct v4l2_subdev *sd;
2112 int err;
2113
2114 /* Check if the adapter supports the needed features */
2115 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2116 return -EIO;
2117 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2118 client->addr << 1);
2119
c02b211d 2120 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59
HV		 2121 if (!state) {
2122 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2123 return -ENOMEM;
2124 }
2125
25a64ac9
MR		 2126 /* initialize variables */
2127 state->restart_stdi_once = true;
ff4f80fd 2128 state->selected_input = ~0;
25a64ac9 2129
54450f59
HV		 2130 /* platform data */
2131 if (!pdata) {
2132 v4l_err(client, "No platform data!\n");
c02b211d 2133 return -ENODEV;
54450f59
HV		 2134 }
2135 memcpy(&state->pdata, pdata, sizeof(state->pdata));
2136
2137 sd = &state->sd;
2138 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2139 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
54450f59
HV		 2140
2141 /* i2c access to adv7604? */
2142 if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
2143 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2144 client->addr << 1);
c02b211d 2145 return -ENODEV;
54450f59
HV		 2146 }
2147
2148 /* control handlers */
2149 hdl = &state->hdl;
2150 v4l2_ctrl_handler_init(hdl, 9);
2151
2152 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2153 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2154 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2155 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2156 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2157 V4L2_CID_SATURATION, 0, 255, 1, 128);
2158 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2159 V4L2_CID_HUE, 0, 128, 1, 0);
2160
2161 /* private controls */
2162 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
4a31a93a 2163 V4L2_CID_DV_RX_POWER_PRESENT, 0, 0x0f, 0, 0);
54450f59
HV		 2164 state->rgb_quantization_range_ctrl =
2165 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2166 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2167 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 2168
2169 /* custom controls */
2170 state->analog_sampling_phase_ctrl =
2171 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59
HV		 2172 state->free_run_color_manual_ctrl =
2173 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
54450f59
HV		 2174 state->free_run_color_ctrl =
2175 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
54450f59
HV		 2176
2177 sd->ctrl_handler = hdl;
2178 if (hdl->error) {
2179 err = hdl->error;
2180 goto err_hdl;
2181 }
8c0eadb8
HV		 2182 state->detect_tx_5v_ctrl->is_private = true;
2183 state->rgb_quantization_range_ctrl->is_private = true;
2184 state->analog_sampling_phase_ctrl->is_private = true;
2185 state->free_run_color_manual_ctrl->is_private = true;
2186 state->free_run_color_ctrl->is_private = true;
2187
54450f59
HV		 2188 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2189 err = -ENODEV;
2190 goto err_hdl;
2191 }
2192
2193 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2194 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2195 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2196 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2197 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2198 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2199 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2200 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2201 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2202 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2203 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2204 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2205 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2206 !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2207 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2208 !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2209 err = -ENOMEM;
2210 v4l2_err(sd, "failed to create all i2c clients\n");
2211 goto err_i2c;
2212 }
2213
2214 /* work queues */
2215 state->work_queues = create_singlethread_workqueue(client->name);
2216 if (!state->work_queues) {
2217 v4l2_err(sd, "Could not create work queue\n");
2218 err = -ENOMEM;
2219 goto err_i2c;
2220 }
2221
2222 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2223 adv7604_delayed_work_enable_hotplug);
2224
2225 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2226 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2227 if (err)
2228 goto err_work_queues;
2229
2230 err = adv7604_core_init(sd);
2231 if (err)
2232 goto err_entity;
2233 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2234 client->addr << 1, client->adapter->name);
2235 return 0;
2236
2237err_entity:
2238 media_entity_cleanup(&sd->entity);
2239err_work_queues:
2240 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2241 destroy_workqueue(state->work_queues);
2242err_i2c:
2243 adv7604_unregister_clients(state);
2244err_hdl:
2245 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 2246 return err;
2247}
2248
2249/* ----------------------------------------------------------------------- */
2250
2251static int adv7604_remove(struct i2c_client *client)
2252{
2253 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2254 struct adv7604_state *state = to_state(sd);
2255
2256 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2257 destroy_workqueue(state->work_queues);
2258 v4l2_device_unregister_subdev(sd);
2259 media_entity_cleanup(&sd->entity);
2260 adv7604_unregister_clients(to_state(sd));
2261 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 2262 return 0;
2263}
2264
2265/* ----------------------------------------------------------------------- */
2266
2267static struct i2c_device_id adv7604_id[] = {
2268 { "adv7604", 0 },
2269 { }
2270};
2271MODULE_DEVICE_TABLE(i2c, adv7604_id);
2272
2273static struct i2c_driver adv7604_driver = {
2274 .driver = {
2275 .owner = THIS_MODULE,
2276 .name = "adv7604",
2277 },
2278 .probe = adv7604_probe,
2279 .remove = adv7604_remove,
2280 .id_table = adv7604_id,
2281};
2282
2283module_i2c_driver(adv7604_driver);
Linux kernel - Deliverables
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