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54450f59 HV |
1 | /* |
2 | * adv7604 - Analog Devices ADV7604 video decoder driver | |
3 | * | |
4 | * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. | |
5 | * | |
6 | * This program is free software; you may redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
11 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
12 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
13 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
14 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
15 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
16 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
17 | * SOFTWARE. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * References (c = chapter, p = page): | |
23 | * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, | |
24 | * Revision 2.5, June 2010 | |
25 | * REF_02 - Analog devices, Register map documentation, Documentation of | |
26 | * the register maps, Software manual, Rev. F, June 2010 | |
27 | * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 | |
28 | */ | |
29 | ||
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/i2c.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/videodev2.h> | |
37 | #include <linux/workqueue.h> | |
38 | #include <linux/v4l2-dv-timings.h> | |
39 | #include <media/v4l2-device.h> | |
40 | #include <media/v4l2-ctrls.h> | |
25764158 | 41 | #include <media/v4l2-dv-timings.h> |
54450f59 HV |
42 | #include <media/adv7604.h> |
43 | ||
44 | static int debug; | |
45 | module_param(debug, int, 0644); | |
46 | MODULE_PARM_DESC(debug, "debug level (0-2)"); | |
47 | ||
48 | MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); | |
49 | MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); | |
50 | MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); | |
51 | MODULE_LICENSE("GPL"); | |
52 | ||
53 | /* ADV7604 system clock frequency */ | |
54 | #define ADV7604_fsc (28636360) | |
55 | ||
539b33b0 LP |
56 | #define ADV7604_RGB_OUT (1 << 1) |
57 | ||
58 | #define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0) | |
59 | #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) | |
60 | #define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0) | |
61 | ||
62 | #define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5) | |
63 | #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) | |
64 | #define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5) | |
65 | #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) | |
66 | #define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5) | |
67 | #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) | |
68 | ||
69 | #define ADV7604_OP_CH_SEL_GBR (0 << 5) | |
70 | #define ADV7604_OP_CH_SEL_GRB (1 << 5) | |
71 | #define ADV7604_OP_CH_SEL_BGR (2 << 5) | |
72 | #define ADV7604_OP_CH_SEL_RGB (3 << 5) | |
73 | #define ADV7604_OP_CH_SEL_BRG (4 << 5) | |
74 | #define ADV7604_OP_CH_SEL_RBG (5 << 5) | |
75 | ||
76 | #define ADV7604_OP_SWAP_CB_CR (1 << 0) | |
77 | ||
d42010a1 LPC |
78 | enum adv7604_type { |
79 | ADV7604, | |
80 | ADV7611, | |
81 | }; | |
82 | ||
83 | struct adv7604_reg_seq { | |
84 | unsigned int reg; | |
85 | u8 val; | |
86 | }; | |
87 | ||
539b33b0 LP |
88 | struct adv7604_format_info { |
89 | enum v4l2_mbus_pixelcode code; | |
90 | u8 op_ch_sel; | |
91 | bool rgb_out; | |
92 | bool swap_cb_cr; | |
93 | u8 op_format_sel; | |
94 | }; | |
95 | ||
d42010a1 LPC |
96 | struct adv7604_chip_info { |
97 | enum adv7604_type type; | |
98 | ||
99 | bool has_afe; | |
100 | unsigned int max_port; | |
101 | unsigned int num_dv_ports; | |
102 | ||
103 | unsigned int edid_enable_reg; | |
104 | unsigned int edid_status_reg; | |
105 | unsigned int lcf_reg; | |
106 | ||
107 | unsigned int cable_det_mask; | |
108 | unsigned int tdms_lock_mask; | |
109 | unsigned int fmt_change_digital_mask; | |
110 | ||
539b33b0 LP |
111 | const struct adv7604_format_info *formats; |
112 | unsigned int nformats; | |
113 | ||
d42010a1 LPC |
114 | void (*set_termination)(struct v4l2_subdev *sd, bool enable); |
115 | void (*setup_irqs)(struct v4l2_subdev *sd); | |
116 | unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); | |
117 | unsigned int (*read_cable_det)(struct v4l2_subdev *sd); | |
118 | ||
119 | /* 0 = AFE, 1 = HDMI */ | |
120 | const struct adv7604_reg_seq *recommended_settings[2]; | |
121 | unsigned int num_recommended_settings[2]; | |
122 | ||
123 | unsigned long page_mask; | |
124 | }; | |
125 | ||
54450f59 HV |
126 | /* |
127 | ********************************************************************** | |
128 | * | |
129 | * Arrays with configuration parameters for the ADV7604 | |
130 | * | |
131 | ********************************************************************** | |
132 | */ | |
c784b1e2 | 133 | |
54450f59 | 134 | struct adv7604_state { |
d42010a1 | 135 | const struct adv7604_chip_info *info; |
54450f59 | 136 | struct adv7604_platform_data pdata; |
539b33b0 | 137 | |
54450f59 | 138 | struct v4l2_subdev sd; |
c784b1e2 LP |
139 | struct media_pad pads[ADV7604_PAD_MAX]; |
140 | unsigned int source_pad; | |
539b33b0 | 141 | |
54450f59 | 142 | struct v4l2_ctrl_handler hdl; |
539b33b0 | 143 | |
c784b1e2 | 144 | enum adv7604_pad selected_input; |
539b33b0 | 145 | |
54450f59 | 146 | struct v4l2_dv_timings timings; |
539b33b0 LP |
147 | const struct adv7604_format_info *format; |
148 | ||
4a31a93a MR |
149 | struct { |
150 | u8 edid[256]; | |
151 | u32 present; | |
152 | unsigned blocks; | |
153 | } edid; | |
dd08beb9 | 154 | u16 spa_port_a[2]; |
54450f59 HV |
155 | struct v4l2_fract aspect_ratio; |
156 | u32 rgb_quantization_range; | |
157 | struct workqueue_struct *work_queues; | |
158 | struct delayed_work delayed_work_enable_hotplug; | |
cf9afb1d | 159 | bool restart_stdi_once; |
54450f59 HV |
160 | |
161 | /* i2c clients */ | |
162 | struct i2c_client *i2c_avlink; | |
163 | struct i2c_client *i2c_cec; | |
164 | struct i2c_client *i2c_infoframe; | |
165 | struct i2c_client *i2c_esdp; | |
166 | struct i2c_client *i2c_dpp; | |
167 | struct i2c_client *i2c_afe; | |
168 | struct i2c_client *i2c_repeater; | |
169 | struct i2c_client *i2c_edid; | |
170 | struct i2c_client *i2c_hdmi; | |
171 | struct i2c_client *i2c_test; | |
172 | struct i2c_client *i2c_cp; | |
173 | struct i2c_client *i2c_vdp; | |
174 | ||
175 | /* controls */ | |
176 | struct v4l2_ctrl *detect_tx_5v_ctrl; | |
177 | struct v4l2_ctrl *analog_sampling_phase_ctrl; | |
178 | struct v4l2_ctrl *free_run_color_manual_ctrl; | |
179 | struct v4l2_ctrl *free_run_color_ctrl; | |
180 | struct v4l2_ctrl *rgb_quantization_range_ctrl; | |
181 | }; | |
182 | ||
d42010a1 LPC |
183 | static bool adv7604_has_afe(struct adv7604_state *state) |
184 | { | |
185 | return state->info->has_afe; | |
186 | } | |
187 | ||
54450f59 HV |
188 | /* Supported CEA and DMT timings */ |
189 | static const struct v4l2_dv_timings adv7604_timings[] = { | |
190 | V4L2_DV_BT_CEA_720X480P59_94, | |
191 | V4L2_DV_BT_CEA_720X576P50, | |
192 | V4L2_DV_BT_CEA_1280X720P24, | |
193 | V4L2_DV_BT_CEA_1280X720P25, | |
54450f59 HV |
194 | V4L2_DV_BT_CEA_1280X720P50, |
195 | V4L2_DV_BT_CEA_1280X720P60, | |
196 | V4L2_DV_BT_CEA_1920X1080P24, | |
197 | V4L2_DV_BT_CEA_1920X1080P25, | |
198 | V4L2_DV_BT_CEA_1920X1080P30, | |
199 | V4L2_DV_BT_CEA_1920X1080P50, | |
200 | V4L2_DV_BT_CEA_1920X1080P60, | |
201 | ||
ccbd5bc4 | 202 | /* sorted by DMT ID */ |
54450f59 HV |
203 | V4L2_DV_BT_DMT_640X350P85, |
204 | V4L2_DV_BT_DMT_640X400P85, | |
205 | V4L2_DV_BT_DMT_720X400P85, | |
206 | V4L2_DV_BT_DMT_640X480P60, | |
207 | V4L2_DV_BT_DMT_640X480P72, | |
208 | V4L2_DV_BT_DMT_640X480P75, | |
209 | V4L2_DV_BT_DMT_640X480P85, | |
210 | V4L2_DV_BT_DMT_800X600P56, | |
211 | V4L2_DV_BT_DMT_800X600P60, | |
212 | V4L2_DV_BT_DMT_800X600P72, | |
213 | V4L2_DV_BT_DMT_800X600P75, | |
214 | V4L2_DV_BT_DMT_800X600P85, | |
215 | V4L2_DV_BT_DMT_848X480P60, | |
216 | V4L2_DV_BT_DMT_1024X768P60, | |
217 | V4L2_DV_BT_DMT_1024X768P70, | |
218 | V4L2_DV_BT_DMT_1024X768P75, | |
219 | V4L2_DV_BT_DMT_1024X768P85, | |
220 | V4L2_DV_BT_DMT_1152X864P75, | |
221 | V4L2_DV_BT_DMT_1280X768P60_RB, | |
222 | V4L2_DV_BT_DMT_1280X768P60, | |
223 | V4L2_DV_BT_DMT_1280X768P75, | |
224 | V4L2_DV_BT_DMT_1280X768P85, | |
225 | V4L2_DV_BT_DMT_1280X800P60_RB, | |
226 | V4L2_DV_BT_DMT_1280X800P60, | |
227 | V4L2_DV_BT_DMT_1280X800P75, | |
228 | V4L2_DV_BT_DMT_1280X800P85, | |
229 | V4L2_DV_BT_DMT_1280X960P60, | |
230 | V4L2_DV_BT_DMT_1280X960P85, | |
231 | V4L2_DV_BT_DMT_1280X1024P60, | |
232 | V4L2_DV_BT_DMT_1280X1024P75, | |
233 | V4L2_DV_BT_DMT_1280X1024P85, | |
234 | V4L2_DV_BT_DMT_1360X768P60, | |
235 | V4L2_DV_BT_DMT_1400X1050P60_RB, | |
236 | V4L2_DV_BT_DMT_1400X1050P60, | |
237 | V4L2_DV_BT_DMT_1400X1050P75, | |
238 | V4L2_DV_BT_DMT_1400X1050P85, | |
239 | V4L2_DV_BT_DMT_1440X900P60_RB, | |
240 | V4L2_DV_BT_DMT_1440X900P60, | |
241 | V4L2_DV_BT_DMT_1600X1200P60, | |
242 | V4L2_DV_BT_DMT_1680X1050P60_RB, | |
243 | V4L2_DV_BT_DMT_1680X1050P60, | |
244 | V4L2_DV_BT_DMT_1792X1344P60, | |
245 | V4L2_DV_BT_DMT_1856X1392P60, | |
246 | V4L2_DV_BT_DMT_1920X1200P60_RB, | |
547ed542 | 247 | V4L2_DV_BT_DMT_1366X768P60_RB, |
54450f59 HV |
248 | V4L2_DV_BT_DMT_1366X768P60, |
249 | V4L2_DV_BT_DMT_1920X1080P60, | |
250 | { }, | |
251 | }; | |
252 | ||
ccbd5bc4 HV |
253 | struct adv7604_video_standards { |
254 | struct v4l2_dv_timings timings; | |
255 | u8 vid_std; | |
256 | u8 v_freq; | |
257 | }; | |
258 | ||
259 | /* sorted by number of lines */ | |
260 | static const struct adv7604_video_standards adv7604_prim_mode_comp[] = { | |
261 | /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ | |
262 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
263 | { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, | |
264 | { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, | |
265 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
266 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
267 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
268 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
269 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
270 | /* TODO add 1920x1080P60_RB (CVT timing) */ | |
271 | { }, | |
272 | }; | |
273 | ||
274 | /* sorted by number of lines */ | |
275 | static const struct adv7604_video_standards adv7604_prim_mode_gr[] = { | |
276 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, | |
277 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
278 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
279 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
280 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
281 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
282 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
283 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
284 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
285 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
286 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
287 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
288 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
289 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
290 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
291 | { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, | |
292 | { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, | |
293 | { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, | |
294 | { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, | |
295 | { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ | |
296 | /* TODO add 1600X1200P60_RB (not a DMT timing) */ | |
297 | { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, | |
298 | { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ | |
299 | { }, | |
300 | }; | |
301 | ||
302 | /* sorted by number of lines */ | |
303 | static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = { | |
304 | { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, | |
305 | { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, | |
306 | { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, | |
307 | { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, | |
308 | { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, | |
309 | { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, | |
310 | { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, | |
311 | { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, | |
312 | { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, | |
313 | { }, | |
314 | }; | |
315 | ||
316 | /* sorted by number of lines */ | |
317 | static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = { | |
318 | { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, | |
319 | { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, | |
320 | { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, | |
321 | { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, | |
322 | { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, | |
323 | { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, | |
324 | { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, | |
325 | { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, | |
326 | { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, | |
327 | { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, | |
328 | { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, | |
329 | { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, | |
330 | { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, | |
331 | { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, | |
332 | { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, | |
333 | { }, | |
334 | }; | |
335 | ||
54450f59 HV |
336 | /* ----------------------------------------------------------------------- */ |
337 | ||
338 | static inline struct adv7604_state *to_state(struct v4l2_subdev *sd) | |
339 | { | |
340 | return container_of(sd, struct adv7604_state, sd); | |
341 | } | |
342 | ||
343 | static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) | |
344 | { | |
345 | return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd; | |
346 | } | |
347 | ||
348 | static inline unsigned hblanking(const struct v4l2_bt_timings *t) | |
349 | { | |
eacf8f9a | 350 | return V4L2_DV_BT_BLANKING_WIDTH(t); |
54450f59 HV |
351 | } |
352 | ||
353 | static inline unsigned htotal(const struct v4l2_bt_timings *t) | |
354 | { | |
eacf8f9a | 355 | return V4L2_DV_BT_FRAME_WIDTH(t); |
54450f59 HV |
356 | } |
357 | ||
358 | static inline unsigned vblanking(const struct v4l2_bt_timings *t) | |
359 | { | |
eacf8f9a | 360 | return V4L2_DV_BT_BLANKING_HEIGHT(t); |
54450f59 HV |
361 | } |
362 | ||
363 | static inline unsigned vtotal(const struct v4l2_bt_timings *t) | |
364 | { | |
eacf8f9a | 365 | return V4L2_DV_BT_FRAME_HEIGHT(t); |
54450f59 HV |
366 | } |
367 | ||
368 | /* ----------------------------------------------------------------------- */ | |
369 | ||
370 | static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, | |
371 | u8 command, bool check) | |
372 | { | |
373 | union i2c_smbus_data data; | |
374 | ||
375 | if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, | |
376 | I2C_SMBUS_READ, command, | |
377 | I2C_SMBUS_BYTE_DATA, &data)) | |
378 | return data.byte; | |
379 | if (check) | |
380 | v4l_err(client, "error reading %02x, %02x\n", | |
381 | client->addr, command); | |
382 | return -EIO; | |
383 | } | |
384 | ||
385 | static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) | |
386 | { | |
387 | return adv_smbus_read_byte_data_check(client, command, true); | |
388 | } | |
389 | ||
390 | static s32 adv_smbus_write_byte_data(struct i2c_client *client, | |
391 | u8 command, u8 value) | |
392 | { | |
393 | union i2c_smbus_data data; | |
394 | int err; | |
395 | int i; | |
396 | ||
397 | data.byte = value; | |
398 | for (i = 0; i < 3; i++) { | |
399 | err = i2c_smbus_xfer(client->adapter, client->addr, | |
400 | client->flags, | |
401 | I2C_SMBUS_WRITE, command, | |
402 | I2C_SMBUS_BYTE_DATA, &data); | |
403 | if (!err) | |
404 | break; | |
405 | } | |
406 | if (err < 0) | |
407 | v4l_err(client, "error writing %02x, %02x, %02x\n", | |
408 | client->addr, command, value); | |
409 | return err; | |
410 | } | |
411 | ||
412 | static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client, | |
413 | u8 command, unsigned length, const u8 *values) | |
414 | { | |
415 | union i2c_smbus_data data; | |
416 | ||
417 | if (length > I2C_SMBUS_BLOCK_MAX) | |
418 | length = I2C_SMBUS_BLOCK_MAX; | |
419 | data.block[0] = length; | |
420 | memcpy(data.block + 1, values, length); | |
421 | return i2c_smbus_xfer(client->adapter, client->addr, client->flags, | |
422 | I2C_SMBUS_WRITE, command, | |
423 | I2C_SMBUS_I2C_BLOCK_DATA, &data); | |
424 | } | |
425 | ||
426 | /* ----------------------------------------------------------------------- */ | |
427 | ||
428 | static inline int io_read(struct v4l2_subdev *sd, u8 reg) | |
429 | { | |
430 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
431 | ||
432 | return adv_smbus_read_byte_data(client, reg); | |
433 | } | |
434 | ||
435 | static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
436 | { | |
437 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
438 | ||
439 | return adv_smbus_write_byte_data(client, reg, val); | |
440 | } | |
441 | ||
442 | static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
443 | { | |
444 | return io_write(sd, reg, (io_read(sd, reg) & mask) | val); | |
445 | } | |
446 | ||
447 | static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) | |
448 | { | |
449 | struct adv7604_state *state = to_state(sd); | |
450 | ||
451 | return adv_smbus_read_byte_data(state->i2c_avlink, reg); | |
452 | } | |
453 | ||
454 | static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
455 | { | |
456 | struct adv7604_state *state = to_state(sd); | |
457 | ||
458 | return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); | |
459 | } | |
460 | ||
461 | static inline int cec_read(struct v4l2_subdev *sd, u8 reg) | |
462 | { | |
463 | struct adv7604_state *state = to_state(sd); | |
464 | ||
465 | return adv_smbus_read_byte_data(state->i2c_cec, reg); | |
466 | } | |
467 | ||
468 | static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
469 | { | |
470 | struct adv7604_state *state = to_state(sd); | |
471 | ||
472 | return adv_smbus_write_byte_data(state->i2c_cec, reg, val); | |
473 | } | |
474 | ||
475 | static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
476 | { | |
477 | return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val); | |
478 | } | |
479 | ||
480 | static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) | |
481 | { | |
482 | struct adv7604_state *state = to_state(sd); | |
483 | ||
484 | return adv_smbus_read_byte_data(state->i2c_infoframe, reg); | |
485 | } | |
486 | ||
487 | static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
488 | { | |
489 | struct adv7604_state *state = to_state(sd); | |
490 | ||
491 | return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); | |
492 | } | |
493 | ||
494 | static inline int esdp_read(struct v4l2_subdev *sd, u8 reg) | |
495 | { | |
496 | struct adv7604_state *state = to_state(sd); | |
497 | ||
498 | return adv_smbus_read_byte_data(state->i2c_esdp, reg); | |
499 | } | |
500 | ||
501 | static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
502 | { | |
503 | struct adv7604_state *state = to_state(sd); | |
504 | ||
505 | return adv_smbus_write_byte_data(state->i2c_esdp, reg, val); | |
506 | } | |
507 | ||
508 | static inline int dpp_read(struct v4l2_subdev *sd, u8 reg) | |
509 | { | |
510 | struct adv7604_state *state = to_state(sd); | |
511 | ||
512 | return adv_smbus_read_byte_data(state->i2c_dpp, reg); | |
513 | } | |
514 | ||
515 | static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
516 | { | |
517 | struct adv7604_state *state = to_state(sd); | |
518 | ||
519 | return adv_smbus_write_byte_data(state->i2c_dpp, reg, val); | |
520 | } | |
521 | ||
522 | static inline int afe_read(struct v4l2_subdev *sd, u8 reg) | |
523 | { | |
524 | struct adv7604_state *state = to_state(sd); | |
525 | ||
526 | return adv_smbus_read_byte_data(state->i2c_afe, reg); | |
527 | } | |
528 | ||
529 | static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
530 | { | |
531 | struct adv7604_state *state = to_state(sd); | |
532 | ||
533 | return adv_smbus_write_byte_data(state->i2c_afe, reg, val); | |
534 | } | |
535 | ||
536 | static inline int rep_read(struct v4l2_subdev *sd, u8 reg) | |
537 | { | |
538 | struct adv7604_state *state = to_state(sd); | |
539 | ||
540 | return adv_smbus_read_byte_data(state->i2c_repeater, reg); | |
541 | } | |
542 | ||
543 | static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
544 | { | |
545 | struct adv7604_state *state = to_state(sd); | |
546 | ||
547 | return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); | |
548 | } | |
549 | ||
550 | static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
551 | { | |
552 | return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); | |
553 | } | |
554 | ||
555 | static inline int edid_read(struct v4l2_subdev *sd, u8 reg) | |
556 | { | |
557 | struct adv7604_state *state = to_state(sd); | |
558 | ||
559 | return adv_smbus_read_byte_data(state->i2c_edid, reg); | |
560 | } | |
561 | ||
562 | static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
563 | { | |
564 | struct adv7604_state *state = to_state(sd); | |
565 | ||
566 | return adv_smbus_write_byte_data(state->i2c_edid, reg, val); | |
567 | } | |
568 | ||
569 | static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val) | |
570 | { | |
571 | struct adv7604_state *state = to_state(sd); | |
572 | struct i2c_client *client = state->i2c_edid; | |
573 | u8 msgbuf0[1] = { 0 }; | |
574 | u8 msgbuf1[256]; | |
09f29673 S |
575 | struct i2c_msg msg[2] = { |
576 | { | |
577 | .addr = client->addr, | |
578 | .len = 1, | |
579 | .buf = msgbuf0 | |
580 | }, | |
581 | { | |
582 | .addr = client->addr, | |
583 | .flags = I2C_M_RD, | |
584 | .len = len, | |
585 | .buf = msgbuf1 | |
586 | }, | |
587 | }; | |
54450f59 HV |
588 | |
589 | if (i2c_transfer(client->adapter, msg, 2) < 0) | |
590 | return -EIO; | |
591 | memcpy(val, msgbuf1, len); | |
592 | return 0; | |
593 | } | |
594 | ||
54450f59 HV |
595 | static inline int edid_write_block(struct v4l2_subdev *sd, |
596 | unsigned len, const u8 *val) | |
597 | { | |
54450f59 HV |
598 | struct adv7604_state *state = to_state(sd); |
599 | int err = 0; | |
600 | int i; | |
601 | ||
602 | v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); | |
603 | ||
54450f59 HV |
604 | for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) |
605 | err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, | |
606 | I2C_SMBUS_BLOCK_MAX, val + i); | |
dd08beb9 MR |
607 | return err; |
608 | } | |
54450f59 | 609 | |
dd08beb9 MR |
610 | static void adv7604_delayed_work_enable_hotplug(struct work_struct *work) |
611 | { | |
612 | struct delayed_work *dwork = to_delayed_work(work); | |
613 | struct adv7604_state *state = container_of(dwork, struct adv7604_state, | |
614 | delayed_work_enable_hotplug); | |
615 | struct v4l2_subdev *sd = &state->sd; | |
54450f59 | 616 | |
dd08beb9 | 617 | v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); |
54450f59 | 618 | |
dd08beb9 | 619 | v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); |
54450f59 HV |
620 | } |
621 | ||
622 | static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) | |
623 | { | |
624 | struct adv7604_state *state = to_state(sd); | |
625 | ||
626 | return adv_smbus_read_byte_data(state->i2c_hdmi, reg); | |
627 | } | |
628 | ||
51182a94 LP |
629 | static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) |
630 | { | |
631 | return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; | |
632 | } | |
633 | ||
54450f59 HV |
634 | static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
635 | { | |
636 | struct adv7604_state *state = to_state(sd); | |
637 | ||
638 | return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); | |
639 | } | |
640 | ||
4a31a93a MR |
641 | static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) |
642 | { | |
643 | return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); | |
644 | } | |
645 | ||
54450f59 HV |
646 | static inline int test_read(struct v4l2_subdev *sd, u8 reg) |
647 | { | |
648 | struct adv7604_state *state = to_state(sd); | |
649 | ||
650 | return adv_smbus_read_byte_data(state->i2c_test, reg); | |
651 | } | |
652 | ||
653 | static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
654 | { | |
655 | struct adv7604_state *state = to_state(sd); | |
656 | ||
657 | return adv_smbus_write_byte_data(state->i2c_test, reg, val); | |
658 | } | |
659 | ||
660 | static inline int cp_read(struct v4l2_subdev *sd, u8 reg) | |
661 | { | |
662 | struct adv7604_state *state = to_state(sd); | |
663 | ||
664 | return adv_smbus_read_byte_data(state->i2c_cp, reg); | |
665 | } | |
666 | ||
51182a94 LP |
667 | static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) |
668 | { | |
669 | return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; | |
670 | } | |
671 | ||
54450f59 HV |
672 | static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
673 | { | |
674 | struct adv7604_state *state = to_state(sd); | |
675 | ||
676 | return adv_smbus_write_byte_data(state->i2c_cp, reg, val); | |
677 | } | |
678 | ||
679 | static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) | |
680 | { | |
681 | return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); | |
682 | } | |
683 | ||
684 | static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) | |
685 | { | |
686 | struct adv7604_state *state = to_state(sd); | |
687 | ||
688 | return adv_smbus_read_byte_data(state->i2c_vdp, reg); | |
689 | } | |
690 | ||
691 | static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) | |
692 | { | |
693 | struct adv7604_state *state = to_state(sd); | |
694 | ||
695 | return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); | |
696 | } | |
697 | ||
d42010a1 LPC |
698 | enum { |
699 | ADV7604_PAGE_IO, | |
700 | ADV7604_PAGE_AVLINK, | |
701 | ADV7604_PAGE_CEC, | |
702 | ADV7604_PAGE_INFOFRAME, | |
703 | ADV7604_PAGE_ESDP, | |
704 | ADV7604_PAGE_DPP, | |
705 | ADV7604_PAGE_AFE, | |
706 | ADV7604_PAGE_REP, | |
707 | ADV7604_PAGE_EDID, | |
708 | ADV7604_PAGE_HDMI, | |
709 | ADV7604_PAGE_TEST, | |
710 | ADV7604_PAGE_CP, | |
711 | ADV7604_PAGE_VDP, | |
712 | ADV7604_PAGE_TERM, | |
713 | }; | |
714 | ||
715 | #define ADV7604_REG(page, offset) (((page) << 8) | (offset)) | |
716 | #define ADV7604_REG_SEQ_TERM 0xffff | |
717 | ||
718 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
719 | static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg) | |
720 | { | |
721 | struct adv7604_state *state = to_state(sd); | |
722 | unsigned int page = reg >> 8; | |
723 | ||
724 | if (!(BIT(page) & state->info->page_mask)) | |
725 | return -EINVAL; | |
726 | ||
727 | reg &= 0xff; | |
728 | ||
729 | switch (page) { | |
730 | case ADV7604_PAGE_IO: | |
731 | return io_read(sd, reg); | |
732 | case ADV7604_PAGE_AVLINK: | |
733 | return avlink_read(sd, reg); | |
734 | case ADV7604_PAGE_CEC: | |
735 | return cec_read(sd, reg); | |
736 | case ADV7604_PAGE_INFOFRAME: | |
737 | return infoframe_read(sd, reg); | |
738 | case ADV7604_PAGE_ESDP: | |
739 | return esdp_read(sd, reg); | |
740 | case ADV7604_PAGE_DPP: | |
741 | return dpp_read(sd, reg); | |
742 | case ADV7604_PAGE_AFE: | |
743 | return afe_read(sd, reg); | |
744 | case ADV7604_PAGE_REP: | |
745 | return rep_read(sd, reg); | |
746 | case ADV7604_PAGE_EDID: | |
747 | return edid_read(sd, reg); | |
748 | case ADV7604_PAGE_HDMI: | |
749 | return hdmi_read(sd, reg); | |
750 | case ADV7604_PAGE_TEST: | |
751 | return test_read(sd, reg); | |
752 | case ADV7604_PAGE_CP: | |
753 | return cp_read(sd, reg); | |
754 | case ADV7604_PAGE_VDP: | |
755 | return vdp_read(sd, reg); | |
756 | } | |
757 | ||
758 | return -EINVAL; | |
759 | } | |
760 | #endif | |
761 | ||
762 | static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) | |
763 | { | |
764 | struct adv7604_state *state = to_state(sd); | |
765 | unsigned int page = reg >> 8; | |
766 | ||
767 | if (!(BIT(page) & state->info->page_mask)) | |
768 | return -EINVAL; | |
769 | ||
770 | reg &= 0xff; | |
771 | ||
772 | switch (page) { | |
773 | case ADV7604_PAGE_IO: | |
774 | return io_write(sd, reg, val); | |
775 | case ADV7604_PAGE_AVLINK: | |
776 | return avlink_write(sd, reg, val); | |
777 | case ADV7604_PAGE_CEC: | |
778 | return cec_write(sd, reg, val); | |
779 | case ADV7604_PAGE_INFOFRAME: | |
780 | return infoframe_write(sd, reg, val); | |
781 | case ADV7604_PAGE_ESDP: | |
782 | return esdp_write(sd, reg, val); | |
783 | case ADV7604_PAGE_DPP: | |
784 | return dpp_write(sd, reg, val); | |
785 | case ADV7604_PAGE_AFE: | |
786 | return afe_write(sd, reg, val); | |
787 | case ADV7604_PAGE_REP: | |
788 | return rep_write(sd, reg, val); | |
789 | case ADV7604_PAGE_EDID: | |
790 | return edid_write(sd, reg, val); | |
791 | case ADV7604_PAGE_HDMI: | |
792 | return hdmi_write(sd, reg, val); | |
793 | case ADV7604_PAGE_TEST: | |
794 | return test_write(sd, reg, val); | |
795 | case ADV7604_PAGE_CP: | |
796 | return cp_write(sd, reg, val); | |
797 | case ADV7604_PAGE_VDP: | |
798 | return vdp_write(sd, reg, val); | |
799 | } | |
800 | ||
801 | return -EINVAL; | |
802 | } | |
803 | ||
804 | static void adv7604_write_reg_seq(struct v4l2_subdev *sd, | |
805 | const struct adv7604_reg_seq *reg_seq) | |
806 | { | |
807 | unsigned int i; | |
808 | ||
809 | for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++) | |
810 | adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); | |
811 | } | |
812 | ||
539b33b0 LP |
813 | /* ----------------------------------------------------------------------------- |
814 | * Format helpers | |
815 | */ | |
816 | ||
817 | static const struct adv7604_format_info adv7604_formats[] = { | |
818 | { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, | |
819 | ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
820 | { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, | |
821 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
822 | { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, | |
823 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
824 | { V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false, | |
825 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, | |
826 | { V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true, | |
827 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, | |
828 | { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, | |
829 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
830 | { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, | |
831 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
832 | { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, | |
833 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
834 | { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, | |
835 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
836 | { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, | |
837 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
838 | { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, | |
839 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
840 | { V4L2_MBUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false, | |
841 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
842 | { V4L2_MBUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true, | |
843 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
844 | { V4L2_MBUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false, | |
845 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
846 | { V4L2_MBUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true, | |
847 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, | |
848 | { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, | |
849 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
850 | { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, | |
851 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
852 | { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, | |
853 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
854 | { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, | |
855 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
856 | }; | |
857 | ||
858 | static const struct adv7604_format_info adv7611_formats[] = { | |
859 | { V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, | |
860 | ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
861 | { V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, | |
862 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
863 | { V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, | |
864 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, | |
865 | { V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, | |
866 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
867 | { V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, | |
868 | ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, | |
869 | { V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, | |
870 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
871 | { V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, | |
872 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
873 | { V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, | |
874 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
875 | { V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, | |
876 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, | |
877 | { V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, | |
878 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
879 | { V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, | |
880 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
881 | { V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, | |
882 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
883 | { V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, | |
884 | ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, | |
885 | }; | |
886 | ||
887 | static const struct adv7604_format_info * | |
888 | adv7604_format_info(struct adv7604_state *state, enum v4l2_mbus_pixelcode code) | |
889 | { | |
890 | unsigned int i; | |
891 | ||
892 | for (i = 0; i < state->info->nformats; ++i) { | |
893 | if (state->info->formats[i].code == code) | |
894 | return &state->info->formats[i]; | |
895 | } | |
896 | ||
897 | return NULL; | |
898 | } | |
899 | ||
54450f59 HV |
900 | /* ----------------------------------------------------------------------- */ |
901 | ||
4a31a93a MR |
902 | static inline bool is_analog_input(struct v4l2_subdev *sd) |
903 | { | |
904 | struct adv7604_state *state = to_state(sd); | |
905 | ||
c784b1e2 LP |
906 | return state->selected_input == ADV7604_PAD_VGA_RGB || |
907 | state->selected_input == ADV7604_PAD_VGA_COMP; | |
4a31a93a MR |
908 | } |
909 | ||
910 | static inline bool is_digital_input(struct v4l2_subdev *sd) | |
911 | { | |
912 | struct adv7604_state *state = to_state(sd); | |
913 | ||
c784b1e2 LP |
914 | return state->selected_input == ADV7604_PAD_HDMI_PORT_A || |
915 | state->selected_input == ADV7604_PAD_HDMI_PORT_B || | |
916 | state->selected_input == ADV7604_PAD_HDMI_PORT_C || | |
917 | state->selected_input == ADV7604_PAD_HDMI_PORT_D; | |
4a31a93a MR |
918 | } |
919 | ||
920 | /* ----------------------------------------------------------------------- */ | |
921 | ||
54450f59 HV |
922 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
923 | static void adv7604_inv_register(struct v4l2_subdev *sd) | |
924 | { | |
925 | v4l2_info(sd, "0x000-0x0ff: IO Map\n"); | |
926 | v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); | |
927 | v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); | |
928 | v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); | |
929 | v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); | |
930 | v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); | |
931 | v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); | |
932 | v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); | |
933 | v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); | |
934 | v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); | |
935 | v4l2_info(sd, "0xa00-0xaff: Test Map\n"); | |
936 | v4l2_info(sd, "0xb00-0xbff: CP Map\n"); | |
937 | v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); | |
938 | } | |
939 | ||
940 | static int adv7604_g_register(struct v4l2_subdev *sd, | |
941 | struct v4l2_dbg_register *reg) | |
942 | { | |
d42010a1 LPC |
943 | int ret; |
944 | ||
945 | ret = adv7604_read_reg(sd, reg->reg); | |
946 | if (ret < 0) { | |
54450f59 HV |
947 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); |
948 | adv7604_inv_register(sd); | |
d42010a1 | 949 | return ret; |
54450f59 | 950 | } |
d42010a1 LPC |
951 | |
952 | reg->size = 1; | |
953 | reg->val = ret; | |
954 | ||
54450f59 HV |
955 | return 0; |
956 | } | |
957 | ||
958 | static int adv7604_s_register(struct v4l2_subdev *sd, | |
977ba3b1 | 959 | const struct v4l2_dbg_register *reg) |
54450f59 | 960 | { |
d42010a1 | 961 | int ret; |
1577461b | 962 | |
d42010a1 LPC |
963 | ret = adv7604_write_reg(sd, reg->reg, reg->val); |
964 | if (ret < 0) { | |
54450f59 HV |
965 | v4l2_info(sd, "Register %03llx not supported\n", reg->reg); |
966 | adv7604_inv_register(sd); | |
d42010a1 | 967 | return ret; |
54450f59 | 968 | } |
d42010a1 | 969 | |
54450f59 HV |
970 | return 0; |
971 | } | |
972 | #endif | |
973 | ||
d42010a1 LPC |
974 | static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) |
975 | { | |
976 | u8 value = io_read(sd, 0x6f); | |
977 | ||
978 | return ((value & 0x10) >> 4) | |
979 | | ((value & 0x08) >> 2) | |
980 | | ((value & 0x04) << 0) | |
981 | | ((value & 0x02) << 2); | |
982 | } | |
983 | ||
984 | static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) | |
985 | { | |
986 | u8 value = io_read(sd, 0x6f); | |
987 | ||
988 | return value & 1; | |
989 | } | |
990 | ||
54450f59 HV |
991 | static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) |
992 | { | |
993 | struct adv7604_state *state = to_state(sd); | |
d42010a1 | 994 | const struct adv7604_chip_info *info = state->info; |
54450f59 | 995 | |
54450f59 | 996 | return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, |
d42010a1 | 997 | info->read_cable_det(sd)); |
54450f59 HV |
998 | } |
999 | ||
ccbd5bc4 HV |
1000 | static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, |
1001 | u8 prim_mode, | |
1002 | const struct adv7604_video_standards *predef_vid_timings, | |
1003 | const struct v4l2_dv_timings *timings) | |
1004 | { | |
ccbd5bc4 HV |
1005 | int i; |
1006 | ||
1007 | for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { | |
ef1ed8f5 | 1008 | if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, |
4a31a93a | 1009 | is_digital_input(sd) ? 250000 : 1000000)) |
ccbd5bc4 HV |
1010 | continue; |
1011 | io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ | |
1012 | io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + | |
1013 | prim_mode); /* v_freq and prim mode */ | |
1014 | return 0; | |
1015 | } | |
1016 | ||
1017 | return -1; | |
1018 | } | |
1019 | ||
1020 | static int configure_predefined_video_timings(struct v4l2_subdev *sd, | |
1021 | struct v4l2_dv_timings *timings) | |
54450f59 | 1022 | { |
ccbd5bc4 HV |
1023 | struct adv7604_state *state = to_state(sd); |
1024 | int err; | |
1025 | ||
1026 | v4l2_dbg(1, debug, sd, "%s", __func__); | |
1027 | ||
d42010a1 LPC |
1028 | if (adv7604_has_afe(state)) { |
1029 | /* reset to default values */ | |
1030 | io_write(sd, 0x16, 0x43); | |
1031 | io_write(sd, 0x17, 0x5a); | |
1032 | } | |
ccbd5bc4 HV |
1033 | /* disable embedded syncs for auto graphics mode */ |
1034 | cp_write_and_or(sd, 0x81, 0xef, 0x00); | |
1035 | cp_write(sd, 0x8f, 0x00); | |
1036 | cp_write(sd, 0x90, 0x00); | |
1037 | cp_write(sd, 0xa2, 0x00); | |
1038 | cp_write(sd, 0xa3, 0x00); | |
1039 | cp_write(sd, 0xa4, 0x00); | |
1040 | cp_write(sd, 0xa5, 0x00); | |
1041 | cp_write(sd, 0xa6, 0x00); | |
1042 | cp_write(sd, 0xa7, 0x00); | |
1043 | cp_write(sd, 0xab, 0x00); | |
1044 | cp_write(sd, 0xac, 0x00); | |
1045 | ||
4a31a93a | 1046 | if (is_analog_input(sd)) { |
ccbd5bc4 HV |
1047 | err = find_and_set_predefined_video_timings(sd, |
1048 | 0x01, adv7604_prim_mode_comp, timings); | |
1049 | if (err) | |
1050 | err = find_and_set_predefined_video_timings(sd, | |
1051 | 0x02, adv7604_prim_mode_gr, timings); | |
4a31a93a | 1052 | } else if (is_digital_input(sd)) { |
ccbd5bc4 HV |
1053 | err = find_and_set_predefined_video_timings(sd, |
1054 | 0x05, adv7604_prim_mode_hdmi_comp, timings); | |
1055 | if (err) | |
1056 | err = find_and_set_predefined_video_timings(sd, | |
1057 | 0x06, adv7604_prim_mode_hdmi_gr, timings); | |
4a31a93a MR |
1058 | } else { |
1059 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1060 | __func__, state->selected_input); | |
ccbd5bc4 | 1061 | err = -1; |
ccbd5bc4 HV |
1062 | } |
1063 | ||
1064 | ||
1065 | return err; | |
1066 | } | |
1067 | ||
1068 | static void configure_custom_video_timings(struct v4l2_subdev *sd, | |
1069 | const struct v4l2_bt_timings *bt) | |
1070 | { | |
1071 | struct adv7604_state *state = to_state(sd); | |
54450f59 | 1072 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
ccbd5bc4 HV |
1073 | u32 width = htotal(bt); |
1074 | u32 height = vtotal(bt); | |
1075 | u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; | |
1076 | u16 cp_start_eav = width - bt->hfrontporch; | |
1077 | u16 cp_start_vbi = height - bt->vfrontporch; | |
1078 | u16 cp_end_vbi = bt->vsync + bt->vbackporch; | |
1079 | u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? | |
1080 | ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; | |
1081 | const u8 pll[2] = { | |
1082 | 0xc0 | ((width >> 8) & 0x1f), | |
1083 | width & 0xff | |
1084 | }; | |
54450f59 HV |
1085 | |
1086 | v4l2_dbg(2, debug, sd, "%s\n", __func__); | |
1087 | ||
4a31a93a | 1088 | if (is_analog_input(sd)) { |
ccbd5bc4 HV |
1089 | /* auto graphics */ |
1090 | io_write(sd, 0x00, 0x07); /* video std */ | |
1091 | io_write(sd, 0x01, 0x02); /* prim mode */ | |
1092 | /* enable embedded syncs for auto graphics mode */ | |
1093 | cp_write_and_or(sd, 0x81, 0xef, 0x10); | |
54450f59 | 1094 | |
ccbd5bc4 | 1095 | /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ |
54450f59 HV |
1096 | /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ |
1097 | /* IO-map reg. 0x16 and 0x17 should be written in sequence */ | |
4a31a93a | 1098 | if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) |
54450f59 | 1099 | v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); |
54450f59 HV |
1100 | |
1101 | /* active video - horizontal timing */ | |
54450f59 | 1102 | cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); |
ccbd5bc4 | 1103 | cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | |
4a31a93a | 1104 | ((cp_start_eav >> 8) & 0x0f)); |
54450f59 HV |
1105 | cp_write(sd, 0xa4, cp_start_eav & 0xff); |
1106 | ||
1107 | /* active video - vertical timing */ | |
54450f59 | 1108 | cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); |
ccbd5bc4 | 1109 | cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | |
4a31a93a | 1110 | ((cp_end_vbi >> 8) & 0xf)); |
54450f59 | 1111 | cp_write(sd, 0xa7, cp_end_vbi & 0xff); |
4a31a93a | 1112 | } else if (is_digital_input(sd)) { |
ccbd5bc4 | 1113 | /* set default prim_mode/vid_std for HDMI |
39c1cb2b | 1114 | according to [REF_03, c. 4.2] */ |
ccbd5bc4 HV |
1115 | io_write(sd, 0x00, 0x02); /* video std */ |
1116 | io_write(sd, 0x01, 0x06); /* prim mode */ | |
4a31a93a MR |
1117 | } else { |
1118 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1119 | __func__, state->selected_input); | |
54450f59 | 1120 | } |
54450f59 | 1121 | |
ccbd5bc4 HV |
1122 | cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); |
1123 | cp_write(sd, 0x90, ch1_fr_ll & 0xff); | |
1124 | cp_write(sd, 0xab, (height >> 4) & 0xff); | |
1125 | cp_write(sd, 0xac, (height & 0x0f) << 4); | |
1126 | } | |
54450f59 | 1127 | |
5c6c6349 MR |
1128 | static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) |
1129 | { | |
1130 | struct adv7604_state *state = to_state(sd); | |
1131 | u8 offset_buf[4]; | |
1132 | ||
1133 | if (auto_offset) { | |
1134 | offset_a = 0x3ff; | |
1135 | offset_b = 0x3ff; | |
1136 | offset_c = 0x3ff; | |
1137 | } | |
1138 | ||
1139 | v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", | |
1140 | __func__, auto_offset ? "Auto" : "Manual", | |
1141 | offset_a, offset_b, offset_c); | |
1142 | ||
1143 | offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); | |
1144 | offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); | |
1145 | offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); | |
1146 | offset_buf[3] = offset_c & 0x0ff; | |
1147 | ||
1148 | /* Registers must be written in this order with no i2c access in between */ | |
1149 | if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) | |
1150 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); | |
1151 | } | |
1152 | ||
1153 | static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) | |
1154 | { | |
1155 | struct adv7604_state *state = to_state(sd); | |
1156 | u8 gain_buf[4]; | |
1157 | u8 gain_man = 1; | |
1158 | u8 agc_mode_man = 1; | |
1159 | ||
1160 | if (auto_gain) { | |
1161 | gain_man = 0; | |
1162 | agc_mode_man = 0; | |
1163 | gain_a = 0x100; | |
1164 | gain_b = 0x100; | |
1165 | gain_c = 0x100; | |
1166 | } | |
1167 | ||
1168 | v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", | |
1169 | __func__, auto_gain ? "Auto" : "Manual", | |
1170 | gain_a, gain_b, gain_c); | |
1171 | ||
1172 | gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); | |
1173 | gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); | |
1174 | gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); | |
1175 | gain_buf[3] = ((gain_c & 0x0ff)); | |
1176 | ||
1177 | /* Registers must be written in this order with no i2c access in between */ | |
1178 | if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) | |
1179 | v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); | |
1180 | } | |
1181 | ||
54450f59 HV |
1182 | static void set_rgb_quantization_range(struct v4l2_subdev *sd) |
1183 | { | |
1184 | struct adv7604_state *state = to_state(sd); | |
5c6c6349 MR |
1185 | bool rgb_output = io_read(sd, 0x02) & 0x02; |
1186 | bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; | |
1187 | ||
1188 | v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", | |
1189 | __func__, state->rgb_quantization_range, | |
1190 | rgb_output, hdmi_signal); | |
54450f59 | 1191 | |
5c6c6349 MR |
1192 | adv7604_set_gain(sd, true, 0x0, 0x0, 0x0); |
1193 | adv7604_set_offset(sd, true, 0x0, 0x0, 0x0); | |
9833239e | 1194 | |
54450f59 HV |
1195 | switch (state->rgb_quantization_range) { |
1196 | case V4L2_DV_RGB_RANGE_AUTO: | |
c784b1e2 | 1197 | if (state->selected_input == ADV7604_PAD_VGA_RGB) { |
9833239e MR |
1198 | /* Receiving analog RGB signal |
1199 | * Set RGB full range (0-255) */ | |
1200 | io_write_and_or(sd, 0x02, 0x0f, 0x10); | |
1201 | break; | |
1202 | } | |
1203 | ||
c784b1e2 | 1204 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
9833239e MR |
1205 | /* Receiving analog YPbPr signal |
1206 | * Set automode */ | |
1207 | io_write_and_or(sd, 0x02, 0x0f, 0xf0); | |
1208 | break; | |
1209 | } | |
1210 | ||
5c6c6349 | 1211 | if (hdmi_signal) { |
9833239e MR |
1212 | /* Receiving HDMI signal |
1213 | * Set automode */ | |
6b0d5d34 | 1214 | io_write_and_or(sd, 0x02, 0x0f, 0xf0); |
9833239e MR |
1215 | break; |
1216 | } | |
1217 | ||
1218 | /* Receiving DVI-D signal | |
1219 | * ADV7604 selects RGB limited range regardless of | |
1220 | * input format (CE/IT) in automatic mode */ | |
1221 | if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { | |
1222 | /* RGB limited range (16-235) */ | |
1223 | io_write_and_or(sd, 0x02, 0x0f, 0x00); | |
1224 | } else { | |
1225 | /* RGB full range (0-255) */ | |
1226 | io_write_and_or(sd, 0x02, 0x0f, 0x10); | |
5c6c6349 MR |
1227 | |
1228 | if (is_digital_input(sd) && rgb_output) { | |
1229 | adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); | |
1230 | } else { | |
1231 | adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); | |
1232 | adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); | |
1233 | } | |
54450f59 HV |
1234 | } |
1235 | break; | |
1236 | case V4L2_DV_RGB_RANGE_LIMITED: | |
c784b1e2 | 1237 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
d261e842 MR |
1238 | /* YCrCb limited range (16-235) */ |
1239 | io_write_and_or(sd, 0x02, 0x0f, 0x20); | |
5c6c6349 | 1240 | break; |
d261e842 | 1241 | } |
5c6c6349 MR |
1242 | |
1243 | /* RGB limited range (16-235) */ | |
1244 | io_write_and_or(sd, 0x02, 0x0f, 0x00); | |
1245 | ||
54450f59 HV |
1246 | break; |
1247 | case V4L2_DV_RGB_RANGE_FULL: | |
c784b1e2 | 1248 | if (state->selected_input == ADV7604_PAD_VGA_COMP) { |
d261e842 MR |
1249 | /* YCrCb full range (0-255) */ |
1250 | io_write_and_or(sd, 0x02, 0x0f, 0x60); | |
5c6c6349 MR |
1251 | break; |
1252 | } | |
1253 | ||
1254 | /* RGB full range (0-255) */ | |
1255 | io_write_and_or(sd, 0x02, 0x0f, 0x10); | |
1256 | ||
1257 | if (is_analog_input(sd) || hdmi_signal) | |
1258 | break; | |
1259 | ||
1260 | /* Adjust gain/offset for DVI-D signals only */ | |
1261 | if (rgb_output) { | |
1262 | adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); | |
d261e842 | 1263 | } else { |
5c6c6349 MR |
1264 | adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); |
1265 | adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); | |
d261e842 | 1266 | } |
54450f59 HV |
1267 | break; |
1268 | } | |
1269 | } | |
1270 | ||
54450f59 HV |
1271 | static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl) |
1272 | { | |
1273 | struct v4l2_subdev *sd = to_sd(ctrl); | |
1274 | struct adv7604_state *state = to_state(sd); | |
1275 | ||
1276 | switch (ctrl->id) { | |
1277 | case V4L2_CID_BRIGHTNESS: | |
1278 | cp_write(sd, 0x3c, ctrl->val); | |
1279 | return 0; | |
1280 | case V4L2_CID_CONTRAST: | |
1281 | cp_write(sd, 0x3a, ctrl->val); | |
1282 | return 0; | |
1283 | case V4L2_CID_SATURATION: | |
1284 | cp_write(sd, 0x3b, ctrl->val); | |
1285 | return 0; | |
1286 | case V4L2_CID_HUE: | |
1287 | cp_write(sd, 0x3d, ctrl->val); | |
1288 | return 0; | |
1289 | case V4L2_CID_DV_RX_RGB_RANGE: | |
1290 | state->rgb_quantization_range = ctrl->val; | |
1291 | set_rgb_quantization_range(sd); | |
1292 | return 0; | |
1293 | case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: | |
d42010a1 LPC |
1294 | if (!adv7604_has_afe(state)) |
1295 | return -EINVAL; | |
54450f59 HV |
1296 | /* Set the analog sampling phase. This is needed to find the |
1297 | best sampling phase for analog video: an application or | |
1298 | driver has to try a number of phases and analyze the picture | |
1299 | quality before settling on the best performing phase. */ | |
1300 | afe_write(sd, 0xc8, ctrl->val); | |
1301 | return 0; | |
1302 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: | |
1303 | /* Use the default blue color for free running mode, | |
1304 | or supply your own. */ | |
1305 | cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); | |
1306 | return 0; | |
1307 | case V4L2_CID_ADV_RX_FREE_RUN_COLOR: | |
1308 | cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); | |
1309 | cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); | |
1310 | cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); | |
1311 | return 0; | |
1312 | } | |
1313 | return -EINVAL; | |
1314 | } | |
1315 | ||
54450f59 HV |
1316 | /* ----------------------------------------------------------------------- */ |
1317 | ||
1318 | static inline bool no_power(struct v4l2_subdev *sd) | |
1319 | { | |
1320 | /* Entire chip or CP powered off */ | |
1321 | return io_read(sd, 0x0c) & 0x24; | |
1322 | } | |
1323 | ||
1324 | static inline bool no_signal_tmds(struct v4l2_subdev *sd) | |
1325 | { | |
4a31a93a MR |
1326 | struct adv7604_state *state = to_state(sd); |
1327 | ||
1328 | return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); | |
54450f59 HV |
1329 | } |
1330 | ||
1331 | static inline bool no_lock_tmds(struct v4l2_subdev *sd) | |
1332 | { | |
d42010a1 LPC |
1333 | struct adv7604_state *state = to_state(sd); |
1334 | const struct adv7604_chip_info *info = state->info; | |
1335 | ||
1336 | return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; | |
54450f59 HV |
1337 | } |
1338 | ||
bb88f325 MB |
1339 | static inline bool is_hdmi(struct v4l2_subdev *sd) |
1340 | { | |
1341 | return hdmi_read(sd, 0x05) & 0x80; | |
1342 | } | |
1343 | ||
54450f59 HV |
1344 | static inline bool no_lock_sspd(struct v4l2_subdev *sd) |
1345 | { | |
d42010a1 LPC |
1346 | struct adv7604_state *state = to_state(sd); |
1347 | ||
1348 | /* | |
1349 | * Chips without a AFE don't expose registers for the SSPD, so just assume | |
1350 | * that we have a lock. | |
1351 | */ | |
1352 | if (adv7604_has_afe(state)) | |
1353 | return false; | |
1354 | ||
54450f59 HV |
1355 | /* TODO channel 2 */ |
1356 | return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); | |
1357 | } | |
1358 | ||
1359 | static inline bool no_lock_stdi(struct v4l2_subdev *sd) | |
1360 | { | |
1361 | /* TODO channel 2 */ | |
1362 | return !(cp_read(sd, 0xb1) & 0x80); | |
1363 | } | |
1364 | ||
1365 | static inline bool no_signal(struct v4l2_subdev *sd) | |
1366 | { | |
54450f59 HV |
1367 | bool ret; |
1368 | ||
1369 | ret = no_power(sd); | |
1370 | ||
1371 | ret |= no_lock_stdi(sd); | |
1372 | ret |= no_lock_sspd(sd); | |
1373 | ||
4a31a93a | 1374 | if (is_digital_input(sd)) { |
54450f59 HV |
1375 | ret |= no_lock_tmds(sd); |
1376 | ret |= no_signal_tmds(sd); | |
1377 | } | |
1378 | ||
1379 | return ret; | |
1380 | } | |
1381 | ||
1382 | static inline bool no_lock_cp(struct v4l2_subdev *sd) | |
1383 | { | |
d42010a1 LPC |
1384 | struct adv7604_state *state = to_state(sd); |
1385 | ||
1386 | if (!adv7604_has_afe(state)) | |
1387 | return false; | |
1388 | ||
54450f59 HV |
1389 | /* CP has detected a non standard number of lines on the incoming |
1390 | video compared to what it is configured to receive by s_dv_timings */ | |
1391 | return io_read(sd, 0x12) & 0x01; | |
1392 | } | |
1393 | ||
1394 | static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status) | |
1395 | { | |
54450f59 HV |
1396 | *status = 0; |
1397 | *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; | |
1398 | *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; | |
1399 | if (no_lock_cp(sd)) | |
4a31a93a | 1400 | *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; |
54450f59 HV |
1401 | |
1402 | v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); | |
1403 | ||
1404 | return 0; | |
1405 | } | |
1406 | ||
1407 | /* ----------------------------------------------------------------------- */ | |
1408 | ||
54450f59 HV |
1409 | struct stdi_readback { |
1410 | u16 bl, lcf, lcvs; | |
1411 | u8 hs_pol, vs_pol; | |
1412 | bool interlaced; | |
1413 | }; | |
1414 | ||
1415 | static int stdi2dv_timings(struct v4l2_subdev *sd, | |
1416 | struct stdi_readback *stdi, | |
1417 | struct v4l2_dv_timings *timings) | |
1418 | { | |
1419 | struct adv7604_state *state = to_state(sd); | |
1420 | u32 hfreq = (ADV7604_fsc * 8) / stdi->bl; | |
1421 | u32 pix_clk; | |
1422 | int i; | |
1423 | ||
1424 | for (i = 0; adv7604_timings[i].bt.height; i++) { | |
1425 | if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1) | |
1426 | continue; | |
1427 | if (adv7604_timings[i].bt.vsync != stdi->lcvs) | |
1428 | continue; | |
1429 | ||
1430 | pix_clk = hfreq * htotal(&adv7604_timings[i].bt); | |
1431 | ||
1432 | if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) && | |
1433 | (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) { | |
1434 | *timings = adv7604_timings[i]; | |
1435 | return 0; | |
1436 | } | |
1437 | } | |
1438 | ||
1439 | if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, | |
1440 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | | |
1441 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
1442 | timings)) | |
1443 | return 0; | |
1444 | if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, | |
1445 | (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | | |
1446 | (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), | |
1447 | state->aspect_ratio, timings)) | |
1448 | return 0; | |
1449 | ||
ccbd5bc4 HV |
1450 | v4l2_dbg(2, debug, sd, |
1451 | "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", | |
1452 | __func__, stdi->lcvs, stdi->lcf, stdi->bl, | |
1453 | stdi->hs_pol, stdi->vs_pol); | |
54450f59 HV |
1454 | return -1; |
1455 | } | |
1456 | ||
d42010a1 | 1457 | |
54450f59 HV |
1458 | static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) |
1459 | { | |
d42010a1 LPC |
1460 | struct adv7604_state *state = to_state(sd); |
1461 | const struct adv7604_chip_info *info = state->info; | |
4a2ccdd2 LP |
1462 | u8 polarity; |
1463 | ||
54450f59 HV |
1464 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { |
1465 | v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); | |
1466 | return -1; | |
1467 | } | |
1468 | ||
1469 | /* read STDI */ | |
51182a94 | 1470 | stdi->bl = cp_read16(sd, 0xb1, 0x3fff); |
d42010a1 | 1471 | stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); |
54450f59 HV |
1472 | stdi->lcvs = cp_read(sd, 0xb3) >> 3; |
1473 | stdi->interlaced = io_read(sd, 0x12) & 0x10; | |
1474 | ||
d42010a1 LPC |
1475 | if (adv7604_has_afe(state)) { |
1476 | /* read SSPD */ | |
1477 | polarity = cp_read(sd, 0xb5); | |
1478 | if ((polarity & 0x03) == 0x01) { | |
1479 | stdi->hs_pol = polarity & 0x10 | |
1480 | ? (polarity & 0x08 ? '+' : '-') : 'x'; | |
1481 | stdi->vs_pol = polarity & 0x40 | |
1482 | ? (polarity & 0x20 ? '+' : '-') : 'x'; | |
1483 | } else { | |
1484 | stdi->hs_pol = 'x'; | |
1485 | stdi->vs_pol = 'x'; | |
1486 | } | |
54450f59 | 1487 | } else { |
d42010a1 LPC |
1488 | polarity = hdmi_read(sd, 0x05); |
1489 | stdi->hs_pol = polarity & 0x20 ? '+' : '-'; | |
1490 | stdi->vs_pol = polarity & 0x10 ? '+' : '-'; | |
54450f59 HV |
1491 | } |
1492 | ||
1493 | if (no_lock_stdi(sd) || no_lock_sspd(sd)) { | |
1494 | v4l2_dbg(2, debug, sd, | |
1495 | "%s: signal lost during readout of STDI/SSPD\n", __func__); | |
1496 | return -1; | |
1497 | } | |
1498 | ||
1499 | if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { | |
1500 | v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); | |
1501 | memset(stdi, 0, sizeof(struct stdi_readback)); | |
1502 | return -1; | |
1503 | } | |
1504 | ||
1505 | v4l2_dbg(2, debug, sd, | |
1506 | "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", | |
1507 | __func__, stdi->lcf, stdi->bl, stdi->lcvs, | |
1508 | stdi->hs_pol, stdi->vs_pol, | |
1509 | stdi->interlaced ? "interlaced" : "progressive"); | |
1510 | ||
1511 | return 0; | |
1512 | } | |
1513 | ||
1514 | static int adv7604_enum_dv_timings(struct v4l2_subdev *sd, | |
1515 | struct v4l2_enum_dv_timings *timings) | |
1516 | { | |
afec5599 LP |
1517 | struct adv7604_state *state = to_state(sd); |
1518 | ||
54450f59 HV |
1519 | if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1) |
1520 | return -EINVAL; | |
afec5599 LP |
1521 | |
1522 | if (timings->pad >= state->source_pad) | |
1523 | return -EINVAL; | |
1524 | ||
54450f59 HV |
1525 | memset(timings->reserved, 0, sizeof(timings->reserved)); |
1526 | timings->timings = adv7604_timings[timings->index]; | |
1527 | return 0; | |
1528 | } | |
1529 | ||
7515e096 LP |
1530 | static int adv7604_dv_timings_cap(struct v4l2_subdev *sd, |
1531 | struct v4l2_dv_timings_cap *cap) | |
54450f59 | 1532 | { |
7515e096 LP |
1533 | struct adv7604_state *state = to_state(sd); |
1534 | ||
1535 | if (cap->pad >= state->source_pad) | |
1536 | return -EINVAL; | |
1537 | ||
54450f59 HV |
1538 | cap->type = V4L2_DV_BT_656_1120; |
1539 | cap->bt.max_width = 1920; | |
1540 | cap->bt.max_height = 1200; | |
fe9c2564 | 1541 | cap->bt.min_pixelclock = 25000000; |
afec5599 | 1542 | |
7515e096 | 1543 | switch (cap->pad) { |
afec5599 LP |
1544 | case ADV7604_PAD_HDMI_PORT_A: |
1545 | case ADV7604_PAD_HDMI_PORT_B: | |
1546 | case ADV7604_PAD_HDMI_PORT_C: | |
1547 | case ADV7604_PAD_HDMI_PORT_D: | |
54450f59 | 1548 | cap->bt.max_pixelclock = 225000000; |
afec5599 LP |
1549 | break; |
1550 | case ADV7604_PAD_VGA_RGB: | |
1551 | case ADV7604_PAD_VGA_COMP: | |
1552 | default: | |
54450f59 | 1553 | cap->bt.max_pixelclock = 170000000; |
afec5599 LP |
1554 | break; |
1555 | } | |
1556 | ||
54450f59 HV |
1557 | cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | |
1558 | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; | |
1559 | cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | | |
1560 | V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; | |
1561 | return 0; | |
1562 | } | |
1563 | ||
1564 | /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings | |
1565 | if the format is listed in adv7604_timings[] */ | |
1566 | static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, | |
1567 | struct v4l2_dv_timings *timings) | |
1568 | { | |
54450f59 HV |
1569 | int i; |
1570 | ||
1571 | for (i = 0; adv7604_timings[i].bt.width; i++) { | |
ef1ed8f5 | 1572 | if (v4l2_match_dv_timings(timings, &adv7604_timings[i], |
4a31a93a | 1573 | is_digital_input(sd) ? 250000 : 1000000)) { |
54450f59 HV |
1574 | *timings = adv7604_timings[i]; |
1575 | break; | |
1576 | } | |
1577 | } | |
1578 | } | |
1579 | ||
d42010a1 LPC |
1580 | static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) |
1581 | { | |
1582 | unsigned int freq; | |
1583 | int a, b; | |
1584 | ||
1585 | a = hdmi_read(sd, 0x06); | |
1586 | b = hdmi_read(sd, 0x3b); | |
1587 | if (a < 0 || b < 0) | |
1588 | return 0; | |
1589 | freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; | |
1590 | ||
1591 | if (is_hdmi(sd)) { | |
1592 | /* adjust for deep color mode */ | |
1593 | unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; | |
1594 | ||
1595 | freq = freq * 8 / bits_per_channel; | |
1596 | } | |
1597 | ||
1598 | return freq; | |
1599 | } | |
1600 | ||
1601 | static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) | |
1602 | { | |
1603 | int a, b; | |
1604 | ||
1605 | a = hdmi_read(sd, 0x51); | |
1606 | b = hdmi_read(sd, 0x52); | |
1607 | if (a < 0 || b < 0) | |
1608 | return 0; | |
1609 | return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; | |
1610 | } | |
1611 | ||
54450f59 HV |
1612 | static int adv7604_query_dv_timings(struct v4l2_subdev *sd, |
1613 | struct v4l2_dv_timings *timings) | |
1614 | { | |
1615 | struct adv7604_state *state = to_state(sd); | |
d42010a1 | 1616 | const struct adv7604_chip_info *info = state->info; |
54450f59 HV |
1617 | struct v4l2_bt_timings *bt = &timings->bt; |
1618 | struct stdi_readback stdi; | |
1619 | ||
1620 | if (!timings) | |
1621 | return -EINVAL; | |
1622 | ||
1623 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1624 | ||
1625 | if (no_signal(sd)) { | |
1e0b9156 | 1626 | state->restart_stdi_once = true; |
54450f59 HV |
1627 | v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); |
1628 | return -ENOLINK; | |
1629 | } | |
1630 | ||
1631 | /* read STDI */ | |
1632 | if (read_stdi(sd, &stdi)) { | |
1633 | v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); | |
1634 | return -ENOLINK; | |
1635 | } | |
1636 | bt->interlaced = stdi.interlaced ? | |
1637 | V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; | |
1638 | ||
4a31a93a | 1639 | if (is_digital_input(sd)) { |
54450f59 HV |
1640 | timings->type = V4L2_DV_BT_656_1120; |
1641 | ||
d42010a1 | 1642 | /* FIXME: All masks are incorrect for ADV7611 */ |
51182a94 LP |
1643 | bt->width = hdmi_read16(sd, 0x07, 0xfff); |
1644 | bt->height = hdmi_read16(sd, 0x09, 0xfff); | |
d42010a1 | 1645 | bt->pixelclock = info->read_hdmi_pixelclock(sd); |
51182a94 LP |
1646 | bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff); |
1647 | bt->hsync = hdmi_read16(sd, 0x22, 0x3ff); | |
1648 | bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff); | |
1649 | bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2; | |
1650 | bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2; | |
1651 | bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2; | |
54450f59 HV |
1652 | bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | |
1653 | ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); | |
1654 | if (bt->interlaced == V4L2_DV_INTERLACED) { | |
51182a94 LP |
1655 | bt->height += hdmi_read16(sd, 0x0b, 0xfff); |
1656 | bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2; | |
1657 | bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2; | |
1658 | bt->vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2; | |
54450f59 HV |
1659 | } |
1660 | adv7604_fill_optional_dv_timings_fields(sd, timings); | |
1661 | } else { | |
1662 | /* find format | |
80939647 | 1663 | * Since LCVS values are inaccurate [REF_03, p. 275-276], |
54450f59 HV |
1664 | * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. |
1665 | */ | |
1666 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1667 | goto found; | |
1668 | stdi.lcvs += 1; | |
1669 | v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); | |
1670 | if (!stdi2dv_timings(sd, &stdi, timings)) | |
1671 | goto found; | |
1672 | stdi.lcvs -= 2; | |
1673 | v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); | |
1674 | if (stdi2dv_timings(sd, &stdi, timings)) { | |
cf9afb1d HV |
1675 | /* |
1676 | * The STDI block may measure wrong values, especially | |
1677 | * for lcvs and lcf. If the driver can not find any | |
1678 | * valid timing, the STDI block is restarted to measure | |
1679 | * the video timings again. The function will return an | |
1680 | * error, but the restart of STDI will generate a new | |
1681 | * STDI interrupt and the format detection process will | |
1682 | * restart. | |
1683 | */ | |
1684 | if (state->restart_stdi_once) { | |
1685 | v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); | |
1686 | /* TODO restart STDI for Sync Channel 2 */ | |
1687 | /* enter one-shot mode */ | |
1688 | cp_write_and_or(sd, 0x86, 0xf9, 0x00); | |
1689 | /* trigger STDI restart */ | |
1690 | cp_write_and_or(sd, 0x86, 0xf9, 0x04); | |
1691 | /* reset to continuous mode */ | |
1692 | cp_write_and_or(sd, 0x86, 0xf9, 0x02); | |
1693 | state->restart_stdi_once = false; | |
1694 | return -ENOLINK; | |
1695 | } | |
54450f59 HV |
1696 | v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); |
1697 | return -ERANGE; | |
1698 | } | |
cf9afb1d | 1699 | state->restart_stdi_once = true; |
54450f59 HV |
1700 | } |
1701 | found: | |
1702 | ||
1703 | if (no_signal(sd)) { | |
1704 | v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); | |
1705 | memset(timings, 0, sizeof(struct v4l2_dv_timings)); | |
1706 | return -ENOLINK; | |
1707 | } | |
1708 | ||
4a31a93a MR |
1709 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || |
1710 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
54450f59 HV |
1711 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", |
1712 | __func__, (u32)bt->pixelclock); | |
1713 | return -ERANGE; | |
1714 | } | |
1715 | ||
1716 | if (debug > 1) | |
11d034c8 HV |
1717 | v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ", |
1718 | timings, true); | |
54450f59 HV |
1719 | |
1720 | return 0; | |
1721 | } | |
1722 | ||
1723 | static int adv7604_s_dv_timings(struct v4l2_subdev *sd, | |
1724 | struct v4l2_dv_timings *timings) | |
1725 | { | |
1726 | struct adv7604_state *state = to_state(sd); | |
1727 | struct v4l2_bt_timings *bt; | |
ccbd5bc4 | 1728 | int err; |
54450f59 HV |
1729 | |
1730 | if (!timings) | |
1731 | return -EINVAL; | |
1732 | ||
d48eb48c MR |
1733 | if (v4l2_match_dv_timings(&state->timings, timings, 0)) { |
1734 | v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); | |
1735 | return 0; | |
1736 | } | |
1737 | ||
54450f59 HV |
1738 | bt = &timings->bt; |
1739 | ||
4a31a93a MR |
1740 | if ((is_analog_input(sd) && bt->pixelclock > 170000000) || |
1741 | (is_digital_input(sd) && bt->pixelclock > 225000000)) { | |
54450f59 HV |
1742 | v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", |
1743 | __func__, (u32)bt->pixelclock); | |
1744 | return -ERANGE; | |
1745 | } | |
ccbd5bc4 | 1746 | |
54450f59 HV |
1747 | adv7604_fill_optional_dv_timings_fields(sd, timings); |
1748 | ||
1749 | state->timings = *timings; | |
1750 | ||
d42010a1 | 1751 | cp_write_and_or(sd, 0x91, 0xbf, bt->interlaced ? 0x40 : 0x00); |
ccbd5bc4 HV |
1752 | |
1753 | /* Use prim_mode and vid_std when available */ | |
1754 | err = configure_predefined_video_timings(sd, timings); | |
1755 | if (err) { | |
1756 | /* custom settings when the video format | |
1757 | does not have prim_mode/vid_std */ | |
1758 | configure_custom_video_timings(sd, bt); | |
1759 | } | |
54450f59 HV |
1760 | |
1761 | set_rgb_quantization_range(sd); | |
1762 | ||
54450f59 | 1763 | if (debug > 1) |
11d034c8 HV |
1764 | v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ", |
1765 | timings, true); | |
54450f59 HV |
1766 | return 0; |
1767 | } | |
1768 | ||
1769 | static int adv7604_g_dv_timings(struct v4l2_subdev *sd, | |
1770 | struct v4l2_dv_timings *timings) | |
1771 | { | |
1772 | struct adv7604_state *state = to_state(sd); | |
1773 | ||
1774 | *timings = state->timings; | |
1775 | return 0; | |
1776 | } | |
1777 | ||
d42010a1 LPC |
1778 | static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) |
1779 | { | |
1780 | hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); | |
1781 | } | |
1782 | ||
1783 | static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) | |
1784 | { | |
1785 | hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); | |
1786 | } | |
1787 | ||
6b0d5d34 | 1788 | static void enable_input(struct v4l2_subdev *sd) |
54450f59 | 1789 | { |
6b0d5d34 HV |
1790 | struct adv7604_state *state = to_state(sd); |
1791 | ||
4a31a93a | 1792 | if (is_analog_input(sd)) { |
54450f59 | 1793 | io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ |
4a31a93a | 1794 | } else if (is_digital_input(sd)) { |
4a31a93a | 1795 | hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input); |
d42010a1 | 1796 | state->info->set_termination(sd, true); |
54450f59 | 1797 | io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ |
5474b983 | 1798 | hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ |
4a31a93a MR |
1799 | } else { |
1800 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1801 | __func__, state->selected_input); | |
54450f59 HV |
1802 | } |
1803 | } | |
1804 | ||
1805 | static void disable_input(struct v4l2_subdev *sd) | |
1806 | { | |
d42010a1 LPC |
1807 | struct adv7604_state *state = to_state(sd); |
1808 | ||
5474b983 MR |
1809 | hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio */ |
1810 | msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ | |
54450f59 | 1811 | io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ |
d42010a1 | 1812 | state->info->set_termination(sd, false); |
54450f59 HV |
1813 | } |
1814 | ||
6b0d5d34 | 1815 | static void select_input(struct v4l2_subdev *sd) |
54450f59 | 1816 | { |
6b0d5d34 | 1817 | struct adv7604_state *state = to_state(sd); |
d42010a1 | 1818 | const struct adv7604_chip_info *info = state->info; |
54450f59 | 1819 | |
4a31a93a | 1820 | if (is_analog_input(sd)) { |
d42010a1 | 1821 | adv7604_write_reg_seq(sd, info->recommended_settings[0]); |
54450f59 HV |
1822 | |
1823 | afe_write(sd, 0x00, 0x08); /* power up ADC */ | |
1824 | afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ | |
1825 | afe_write(sd, 0xc8, 0x00); /* phase control */ | |
4a31a93a MR |
1826 | } else if (is_digital_input(sd)) { |
1827 | hdmi_write(sd, 0x00, state->selected_input & 0x03); | |
54450f59 | 1828 | |
d42010a1 LPC |
1829 | adv7604_write_reg_seq(sd, info->recommended_settings[1]); |
1830 | ||
1831 | if (adv7604_has_afe(state)) { | |
1832 | afe_write(sd, 0x00, 0xff); /* power down ADC */ | |
1833 | afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ | |
1834 | afe_write(sd, 0xc8, 0x40); /* phase control */ | |
1835 | } | |
1836 | ||
54450f59 HV |
1837 | cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ |
1838 | cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ | |
1839 | cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ | |
4a31a93a MR |
1840 | } else { |
1841 | v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", | |
1842 | __func__, state->selected_input); | |
54450f59 HV |
1843 | } |
1844 | } | |
1845 | ||
1846 | static int adv7604_s_routing(struct v4l2_subdev *sd, | |
1847 | u32 input, u32 output, u32 config) | |
1848 | { | |
1849 | struct adv7604_state *state = to_state(sd); | |
1850 | ||
ff4f80fd MR |
1851 | v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", |
1852 | __func__, input, state->selected_input); | |
1853 | ||
1854 | if (input == state->selected_input) | |
1855 | return 0; | |
54450f59 | 1856 | |
d42010a1 LPC |
1857 | if (input > state->info->max_port) |
1858 | return -EINVAL; | |
1859 | ||
4a31a93a | 1860 | state->selected_input = input; |
54450f59 HV |
1861 | |
1862 | disable_input(sd); | |
1863 | ||
6b0d5d34 | 1864 | select_input(sd); |
54450f59 | 1865 | |
6b0d5d34 | 1866 | enable_input(sd); |
54450f59 HV |
1867 | |
1868 | return 0; | |
1869 | } | |
1870 | ||
539b33b0 LP |
1871 | static int adv7604_enum_mbus_code(struct v4l2_subdev *sd, |
1872 | struct v4l2_subdev_fh *fh, | |
1873 | struct v4l2_subdev_mbus_code_enum *code) | |
54450f59 | 1874 | { |
539b33b0 LP |
1875 | struct adv7604_state *state = to_state(sd); |
1876 | ||
1877 | if (code->index >= state->info->nformats) | |
54450f59 | 1878 | return -EINVAL; |
539b33b0 LP |
1879 | |
1880 | code->code = state->info->formats[code->index].code; | |
1881 | ||
54450f59 HV |
1882 | return 0; |
1883 | } | |
1884 | ||
539b33b0 LP |
1885 | static void adv7604_fill_format(struct adv7604_state *state, |
1886 | struct v4l2_mbus_framefmt *format) | |
54450f59 | 1887 | { |
539b33b0 | 1888 | memset(format, 0, sizeof(*format)); |
54450f59 | 1889 | |
539b33b0 LP |
1890 | format->width = state->timings.bt.width; |
1891 | format->height = state->timings.bt.height; | |
1892 | format->field = V4L2_FIELD_NONE; | |
1893 | ||
1894 | if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) | |
1895 | format->colorspace = (state->timings.bt.height <= 576) ? | |
54450f59 | 1896 | V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; |
539b33b0 LP |
1897 | } |
1898 | ||
1899 | /* | |
1900 | * Compute the op_ch_sel value required to obtain on the bus the component order | |
1901 | * corresponding to the selected format taking into account bus reordering | |
1902 | * applied by the board at the output of the device. | |
1903 | * | |
1904 | * The following table gives the op_ch_value from the format component order | |
1905 | * (expressed as op_ch_sel value in column) and the bus reordering (expressed as | |
1906 | * adv7604_bus_order value in row). | |
1907 | * | |
1908 | * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) | |
1909 | * ----------+------------------------------------------------- | |
1910 | * RGB (NOP) | GBR GRB BGR RGB BRG RBG | |
1911 | * GRB (1-2) | BGR RGB GBR GRB RBG BRG | |
1912 | * RBG (2-3) | GRB GBR BRG RBG BGR RGB | |
1913 | * BGR (1-3) | RBG BRG RGB BGR GRB GBR | |
1914 | * BRG (ROR) | BRG RBG GRB GBR RGB BGR | |
1915 | * GBR (ROL) | RGB BGR RBG BRG GBR GRB | |
1916 | */ | |
1917 | static unsigned int adv7604_op_ch_sel(struct adv7604_state *state) | |
1918 | { | |
1919 | #define _SEL(a,b,c,d,e,f) { \ | |
1920 | ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \ | |
1921 | ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f } | |
1922 | #define _BUS(x) [ADV7604_BUS_ORDER_##x] | |
1923 | ||
1924 | static const unsigned int op_ch_sel[6][6] = { | |
1925 | _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), | |
1926 | _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), | |
1927 | _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), | |
1928 | _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), | |
1929 | _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), | |
1930 | _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), | |
1931 | }; | |
1932 | ||
1933 | return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; | |
1934 | } | |
1935 | ||
1936 | static void adv7604_setup_format(struct adv7604_state *state) | |
1937 | { | |
1938 | struct v4l2_subdev *sd = &state->sd; | |
1939 | ||
1940 | io_write_and_or(sd, 0x02, 0xfd, | |
1941 | state->format->rgb_out ? ADV7604_RGB_OUT : 0); | |
1942 | io_write(sd, 0x03, state->format->op_format_sel | | |
1943 | state->pdata.op_format_mode_sel); | |
1944 | io_write_and_or(sd, 0x04, 0x1f, adv7604_op_ch_sel(state)); | |
1945 | io_write_and_or(sd, 0x05, 0xfe, | |
1946 | state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0); | |
1947 | } | |
1948 | ||
1949 | static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
1950 | struct v4l2_subdev_format *format) | |
1951 | { | |
1952 | struct adv7604_state *state = to_state(sd); | |
1953 | ||
1954 | if (format->pad != state->source_pad) | |
1955 | return -EINVAL; | |
1956 | ||
1957 | adv7604_fill_format(state, &format->format); | |
1958 | ||
1959 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1960 | struct v4l2_mbus_framefmt *fmt; | |
1961 | ||
1962 | fmt = v4l2_subdev_get_try_format(fh, format->pad); | |
1963 | format->format.code = fmt->code; | |
1964 | } else { | |
1965 | format->format.code = state->format->code; | |
54450f59 | 1966 | } |
539b33b0 LP |
1967 | |
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
1972 | struct v4l2_subdev_format *format) | |
1973 | { | |
1974 | struct adv7604_state *state = to_state(sd); | |
1975 | const struct adv7604_format_info *info; | |
1976 | ||
1977 | if (format->pad != state->source_pad) | |
1978 | return -EINVAL; | |
1979 | ||
1980 | info = adv7604_format_info(state, format->format.code); | |
1981 | if (info == NULL) | |
1982 | info = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8); | |
1983 | ||
1984 | adv7604_fill_format(state, &format->format); | |
1985 | format->format.code = info->code; | |
1986 | ||
1987 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { | |
1988 | struct v4l2_mbus_framefmt *fmt; | |
1989 | ||
1990 | fmt = v4l2_subdev_get_try_format(fh, format->pad); | |
1991 | fmt->code = format->format.code; | |
1992 | } else { | |
1993 | state->format = info; | |
1994 | adv7604_setup_format(state); | |
1995 | } | |
1996 | ||
54450f59 HV |
1997 | return 0; |
1998 | } | |
1999 | ||
2000 | static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) | |
2001 | { | |
d42010a1 LPC |
2002 | struct adv7604_state *state = to_state(sd); |
2003 | const struct adv7604_chip_info *info = state->info; | |
f24d229c MR |
2004 | const u8 irq_reg_0x43 = io_read(sd, 0x43); |
2005 | const u8 irq_reg_0x6b = io_read(sd, 0x6b); | |
2006 | const u8 irq_reg_0x70 = io_read(sd, 0x70); | |
2007 | u8 fmt_change_digital; | |
2008 | u8 fmt_change; | |
2009 | u8 tx_5v; | |
2010 | ||
2011 | if (irq_reg_0x43) | |
2012 | io_write(sd, 0x44, irq_reg_0x43); | |
2013 | if (irq_reg_0x70) | |
2014 | io_write(sd, 0x71, irq_reg_0x70); | |
2015 | if (irq_reg_0x6b) | |
2016 | io_write(sd, 0x6c, irq_reg_0x6b); | |
54450f59 | 2017 | |
ff4f80fd MR |
2018 | v4l2_dbg(2, debug, sd, "%s: ", __func__); |
2019 | ||
54450f59 | 2020 | /* format change */ |
f24d229c | 2021 | fmt_change = irq_reg_0x43 & 0x98; |
d42010a1 LPC |
2022 | fmt_change_digital = is_digital_input(sd) |
2023 | ? irq_reg_0x6b & info->fmt_change_digital_mask | |
2024 | : 0; | |
14d03233 | 2025 | |
54450f59 HV |
2026 | if (fmt_change || fmt_change_digital) { |
2027 | v4l2_dbg(1, debug, sd, | |
25a64ac9 | 2028 | "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", |
54450f59 | 2029 | __func__, fmt_change, fmt_change_digital); |
25a64ac9 | 2030 | |
14d03233 | 2031 | v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL); |
25a64ac9 | 2032 | |
54450f59 HV |
2033 | if (handled) |
2034 | *handled = true; | |
2035 | } | |
f24d229c MR |
2036 | /* HDMI/DVI mode */ |
2037 | if (irq_reg_0x6b & 0x01) { | |
2038 | v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, | |
2039 | (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); | |
2040 | set_rgb_quantization_range(sd); | |
2041 | if (handled) | |
2042 | *handled = true; | |
2043 | } | |
2044 | ||
54450f59 | 2045 | /* tx 5v detect */ |
d42010a1 | 2046 | tx_5v = io_read(sd, 0x70) & info->cable_det_mask; |
54450f59 HV |
2047 | if (tx_5v) { |
2048 | v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); | |
2049 | io_write(sd, 0x71, tx_5v); | |
2050 | adv7604_s_detect_tx_5v_ctrl(sd); | |
2051 | if (handled) | |
2052 | *handled = true; | |
2053 | } | |
2054 | return 0; | |
2055 | } | |
2056 | ||
b09dfac8 | 2057 | static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) |
54450f59 HV |
2058 | { |
2059 | struct adv7604_state *state = to_state(sd); | |
4a31a93a | 2060 | u8 *data = NULL; |
54450f59 | 2061 | |
c784b1e2 | 2062 | if (edid->pad > ADV7604_PAD_HDMI_PORT_D) |
54450f59 HV |
2063 | return -EINVAL; |
2064 | if (edid->blocks == 0) | |
2065 | return -EINVAL; | |
4a31a93a | 2066 | if (edid->blocks > 2) |
54450f59 | 2067 | return -EINVAL; |
4a31a93a MR |
2068 | if (edid->start_block > 1) |
2069 | return -EINVAL; | |
2070 | if (edid->start_block == 1) | |
2071 | edid->blocks = 1; | |
4a31a93a MR |
2072 | |
2073 | if (edid->blocks > state->edid.blocks) | |
2074 | edid->blocks = state->edid.blocks; | |
2075 | ||
2076 | switch (edid->pad) { | |
c784b1e2 LP |
2077 | case ADV7604_PAD_HDMI_PORT_A: |
2078 | case ADV7604_PAD_HDMI_PORT_B: | |
2079 | case ADV7604_PAD_HDMI_PORT_C: | |
2080 | case ADV7604_PAD_HDMI_PORT_D: | |
4a31a93a MR |
2081 | if (state->edid.present & (1 << edid->pad)) |
2082 | data = state->edid.edid; | |
2083 | break; | |
2084 | default: | |
2085 | return -EINVAL; | |
2086 | break; | |
2087 | } | |
2088 | if (!data) | |
2089 | return -ENODATA; | |
2090 | ||
2091 | memcpy(edid->edid, | |
2092 | data + edid->start_block * 128, | |
54450f59 HV |
2093 | edid->blocks * 128); |
2094 | return 0; | |
2095 | } | |
2096 | ||
dd08beb9 | 2097 | static int get_edid_spa_location(const u8 *edid) |
3e86aa85 MR |
2098 | { |
2099 | u8 d; | |
2100 | ||
2101 | if ((edid[0x7e] != 1) || | |
2102 | (edid[0x80] != 0x02) || | |
2103 | (edid[0x81] != 0x03)) { | |
2104 | return -1; | |
2105 | } | |
2106 | ||
2107 | /* search Vendor Specific Data Block (tag 3) */ | |
2108 | d = edid[0x82] & 0x7f; | |
2109 | if (d > 4) { | |
2110 | int i = 0x84; | |
2111 | int end = 0x80 + d; | |
2112 | ||
2113 | do { | |
2114 | u8 tag = edid[i] >> 5; | |
2115 | u8 len = edid[i] & 0x1f; | |
2116 | ||
2117 | if ((tag == 3) && (len >= 5)) | |
2118 | return i + 4; | |
2119 | i += len + 1; | |
2120 | } while (i < end); | |
2121 | } | |
2122 | return -1; | |
2123 | } | |
2124 | ||
b09dfac8 | 2125 | static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) |
54450f59 HV |
2126 | { |
2127 | struct adv7604_state *state = to_state(sd); | |
d42010a1 | 2128 | const struct adv7604_chip_info *info = state->info; |
dd08beb9 | 2129 | int spa_loc; |
3e86aa85 | 2130 | int tmp = 0; |
54450f59 | 2131 | int err; |
dd08beb9 | 2132 | int i; |
54450f59 | 2133 | |
c784b1e2 | 2134 | if (edid->pad > ADV7604_PAD_HDMI_PORT_D) |
54450f59 HV |
2135 | return -EINVAL; |
2136 | if (edid->start_block != 0) | |
2137 | return -EINVAL; | |
2138 | if (edid->blocks == 0) { | |
3e86aa85 | 2139 | /* Disable hotplug and I2C access to EDID RAM from DDC port */ |
4a31a93a MR |
2140 | state->edid.present &= ~(1 << edid->pad); |
2141 | v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); | |
d42010a1 | 2142 | rep_write_and_or(sd, info->edid_enable_reg, 0xf0, state->edid.present); |
3e86aa85 | 2143 | |
54450f59 HV |
2144 | /* Fall back to a 16:9 aspect ratio */ |
2145 | state->aspect_ratio.numerator = 16; | |
2146 | state->aspect_ratio.denominator = 9; | |
3e86aa85 MR |
2147 | |
2148 | if (!state->edid.present) | |
2149 | state->edid.blocks = 0; | |
2150 | ||
2151 | v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", | |
2152 | __func__, edid->pad, state->edid.present); | |
54450f59 HV |
2153 | return 0; |
2154 | } | |
4a31a93a MR |
2155 | if (edid->blocks > 2) { |
2156 | edid->blocks = 2; | |
54450f59 | 2157 | return -E2BIG; |
4a31a93a | 2158 | } |
4a31a93a | 2159 | |
dd08beb9 MR |
2160 | v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", |
2161 | __func__, edid->pad, state->edid.present); | |
2162 | ||
3e86aa85 | 2163 | /* Disable hotplug and I2C access to EDID RAM from DDC port */ |
4a31a93a | 2164 | cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); |
3e86aa85 | 2165 | v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp); |
d42010a1 | 2166 | rep_write_and_or(sd, info->edid_enable_reg, 0xf0, 0x00); |
3e86aa85 | 2167 | |
dd08beb9 MR |
2168 | spa_loc = get_edid_spa_location(edid->edid); |
2169 | if (spa_loc < 0) | |
2170 | spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ | |
2171 | ||
3e86aa85 | 2172 | switch (edid->pad) { |
c784b1e2 | 2173 | case ADV7604_PAD_HDMI_PORT_A: |
dd08beb9 MR |
2174 | state->spa_port_a[0] = edid->edid[spa_loc]; |
2175 | state->spa_port_a[1] = edid->edid[spa_loc + 1]; | |
3e86aa85 | 2176 | break; |
c784b1e2 | 2177 | case ADV7604_PAD_HDMI_PORT_B: |
dd08beb9 MR |
2178 | rep_write(sd, 0x70, edid->edid[spa_loc]); |
2179 | rep_write(sd, 0x71, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2180 | break; |
c784b1e2 | 2181 | case ADV7604_PAD_HDMI_PORT_C: |
dd08beb9 MR |
2182 | rep_write(sd, 0x72, edid->edid[spa_loc]); |
2183 | rep_write(sd, 0x73, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2184 | break; |
c784b1e2 | 2185 | case ADV7604_PAD_HDMI_PORT_D: |
dd08beb9 MR |
2186 | rep_write(sd, 0x74, edid->edid[spa_loc]); |
2187 | rep_write(sd, 0x75, edid->edid[spa_loc + 1]); | |
3e86aa85 | 2188 | break; |
dd08beb9 MR |
2189 | default: |
2190 | return -EINVAL; | |
3e86aa85 | 2191 | } |
d42010a1 LPC |
2192 | |
2193 | if (info->type == ADV7604) { | |
2194 | rep_write(sd, 0x76, spa_loc & 0xff); | |
2195 | rep_write_and_or(sd, 0x77, 0xbf, (spa_loc & 0x100) >> 2); | |
2196 | } else { | |
2197 | /* FIXME: Where is the SPA location LSB register ? */ | |
2198 | rep_write_and_or(sd, 0x71, 0xfe, (spa_loc & 0x100) >> 8); | |
2199 | } | |
3e86aa85 | 2200 | |
dd08beb9 MR |
2201 | edid->edid[spa_loc] = state->spa_port_a[0]; |
2202 | edid->edid[spa_loc + 1] = state->spa_port_a[1]; | |
4a31a93a MR |
2203 | |
2204 | memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); | |
2205 | state->edid.blocks = edid->blocks; | |
54450f59 HV |
2206 | state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], |
2207 | edid->edid[0x16]); | |
3e86aa85 | 2208 | state->edid.present |= 1 << edid->pad; |
4a31a93a MR |
2209 | |
2210 | err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); | |
2211 | if (err < 0) { | |
3e86aa85 | 2212 | v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); |
4a31a93a MR |
2213 | return err; |
2214 | } | |
2215 | ||
dd08beb9 MR |
2216 | /* adv7604 calculates the checksums and enables I2C access to internal |
2217 | EDID RAM from DDC port. */ | |
d42010a1 | 2218 | rep_write_and_or(sd, info->edid_enable_reg, 0xf0, state->edid.present); |
dd08beb9 MR |
2219 | |
2220 | for (i = 0; i < 1000; i++) { | |
d42010a1 | 2221 | if (rep_read(sd, info->edid_status_reg) & state->edid.present) |
dd08beb9 MR |
2222 | break; |
2223 | mdelay(1); | |
2224 | } | |
2225 | if (i == 1000) { | |
2226 | v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); | |
2227 | return -EIO; | |
2228 | } | |
2229 | ||
2230 | ||
4a31a93a MR |
2231 | /* enable hotplug after 100 ms */ |
2232 | queue_delayed_work(state->work_queues, | |
2233 | &state->delayed_work_enable_hotplug, HZ / 10); | |
2234 | return 0; | |
54450f59 HV |
2235 | } |
2236 | ||
2237 | /*********** avi info frame CEA-861-E **************/ | |
2238 | ||
2239 | static void print_avi_infoframe(struct v4l2_subdev *sd) | |
2240 | { | |
2241 | int i; | |
2242 | u8 buf[14]; | |
2243 | u8 avi_len; | |
2244 | u8 avi_ver; | |
2245 | ||
bb88f325 | 2246 | if (!is_hdmi(sd)) { |
54450f59 HV |
2247 | v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); |
2248 | return; | |
2249 | } | |
2250 | if (!(io_read(sd, 0x60) & 0x01)) { | |
2251 | v4l2_info(sd, "AVI infoframe not received\n"); | |
2252 | return; | |
2253 | } | |
2254 | ||
2255 | if (io_read(sd, 0x83) & 0x01) { | |
2256 | v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n"); | |
2257 | io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ | |
2258 | if (io_read(sd, 0x83) & 0x01) { | |
2259 | v4l2_info(sd, "AVI infoframe checksum error still present\n"); | |
2260 | io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ | |
2261 | } | |
2262 | } | |
2263 | ||
2264 | avi_len = infoframe_read(sd, 0xe2); | |
2265 | avi_ver = infoframe_read(sd, 0xe1); | |
2266 | v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", | |
2267 | avi_ver, avi_len); | |
2268 | ||
2269 | if (avi_ver != 0x02) | |
2270 | return; | |
2271 | ||
2272 | for (i = 0; i < 14; i++) | |
2273 | buf[i] = infoframe_read(sd, i); | |
2274 | ||
2275 | v4l2_info(sd, | |
2276 | "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", | |
2277 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], | |
2278 | buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); | |
2279 | } | |
2280 | ||
2281 | static int adv7604_log_status(struct v4l2_subdev *sd) | |
2282 | { | |
2283 | struct adv7604_state *state = to_state(sd); | |
d42010a1 | 2284 | const struct adv7604_chip_info *info = state->info; |
54450f59 HV |
2285 | struct v4l2_dv_timings timings; |
2286 | struct stdi_readback stdi; | |
2287 | u8 reg_io_0x02 = io_read(sd, 0x02); | |
4a2ccdd2 LP |
2288 | u8 edid_enabled; |
2289 | u8 cable_det; | |
54450f59 | 2290 | |
f216ccb3 | 2291 | static const char * const csc_coeff_sel_rb[16] = { |
54450f59 HV |
2292 | "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", |
2293 | "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", | |
2294 | "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", | |
2295 | "reserved", "reserved", "reserved", "reserved", "manual" | |
2296 | }; | |
f216ccb3 | 2297 | static const char * const input_color_space_txt[16] = { |
54450f59 HV |
2298 | "RGB limited range (16-235)", "RGB full range (0-255)", |
2299 | "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", | |
9833239e | 2300 | "xvYCC Bt.601", "xvYCC Bt.709", |
54450f59 HV |
2301 | "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", |
2302 | "invalid", "invalid", "invalid", "invalid", "invalid", | |
2303 | "invalid", "invalid", "automatic" | |
2304 | }; | |
f216ccb3 | 2305 | static const char * const rgb_quantization_range_txt[] = { |
54450f59 HV |
2306 | "Automatic", |
2307 | "RGB limited range (16-235)", | |
2308 | "RGB full range (0-255)", | |
2309 | }; | |
f216ccb3 | 2310 | static const char * const deep_color_mode_txt[4] = { |
bb88f325 MB |
2311 | "8-bits per channel", |
2312 | "10-bits per channel", | |
2313 | "12-bits per channel", | |
2314 | "16-bits per channel (not supported)" | |
2315 | }; | |
54450f59 HV |
2316 | |
2317 | v4l2_info(sd, "-----Chip status-----\n"); | |
2318 | v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); | |
d42010a1 | 2319 | edid_enabled = rep_read(sd, info->edid_status_reg); |
4a31a93a | 2320 | v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", |
4a2ccdd2 LP |
2321 | ((edid_enabled & 0x01) ? "Yes" : "No"), |
2322 | ((edid_enabled & 0x02) ? "Yes" : "No"), | |
2323 | ((edid_enabled & 0x04) ? "Yes" : "No"), | |
2324 | ((edid_enabled & 0x08) ? "Yes" : "No")); | |
54450f59 HV |
2325 | v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? |
2326 | "enabled" : "disabled"); | |
2327 | ||
2328 | v4l2_info(sd, "-----Signal status-----\n"); | |
d42010a1 | 2329 | cable_det = info->read_cable_det(sd); |
4a31a93a | 2330 | v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", |
d42010a1 LPC |
2331 | ((cable_det & 0x01) ? "Yes" : "No"), |
2332 | ((cable_det & 0x02) ? "Yes" : "No"), | |
4a2ccdd2 | 2333 | ((cable_det & 0x04) ? "Yes" : "No"), |
d42010a1 | 2334 | ((cable_det & 0x08) ? "Yes" : "No")); |
54450f59 HV |
2335 | v4l2_info(sd, "TMDS signal detected: %s\n", |
2336 | no_signal_tmds(sd) ? "false" : "true"); | |
2337 | v4l2_info(sd, "TMDS signal locked: %s\n", | |
2338 | no_lock_tmds(sd) ? "false" : "true"); | |
2339 | v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); | |
2340 | v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); | |
2341 | v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); | |
2342 | v4l2_info(sd, "CP free run: %s\n", | |
2343 | (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); | |
ccbd5bc4 HV |
2344 | v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", |
2345 | io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, | |
2346 | (io_read(sd, 0x01) & 0x70) >> 4); | |
54450f59 HV |
2347 | |
2348 | v4l2_info(sd, "-----Video Timings-----\n"); | |
2349 | if (read_stdi(sd, &stdi)) | |
2350 | v4l2_info(sd, "STDI: not locked\n"); | |
2351 | else | |
2352 | v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", | |
2353 | stdi.lcf, stdi.bl, stdi.lcvs, | |
2354 | stdi.interlaced ? "interlaced" : "progressive", | |
2355 | stdi.hs_pol, stdi.vs_pol); | |
2356 | if (adv7604_query_dv_timings(sd, &timings)) | |
2357 | v4l2_info(sd, "No video detected\n"); | |
2358 | else | |
11d034c8 HV |
2359 | v4l2_print_dv_timings(sd->name, "Detected format: ", |
2360 | &timings, true); | |
2361 | v4l2_print_dv_timings(sd->name, "Configured format: ", | |
2362 | &state->timings, true); | |
54450f59 | 2363 | |
76eb2d30 MR |
2364 | if (no_signal(sd)) |
2365 | return 0; | |
2366 | ||
54450f59 HV |
2367 | v4l2_info(sd, "-----Color space-----\n"); |
2368 | v4l2_info(sd, "RGB quantization range ctrl: %s\n", | |
2369 | rgb_quantization_range_txt[state->rgb_quantization_range]); | |
2370 | v4l2_info(sd, "Input color space: %s\n", | |
2371 | input_color_space_txt[reg_io_0x02 >> 4]); | |
2372 | v4l2_info(sd, "Output color space: %s %s, saturator %s\n", | |
2373 | (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", | |
2374 | (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", | |
2375 | ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? | |
76eb2d30 | 2376 | "enabled" : "disabled"); |
54450f59 HV |
2377 | v4l2_info(sd, "Color space conversion: %s\n", |
2378 | csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]); | |
2379 | ||
4a31a93a | 2380 | if (!is_digital_input(sd)) |
76eb2d30 MR |
2381 | return 0; |
2382 | ||
2383 | v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); | |
4a31a93a MR |
2384 | v4l2_info(sd, "Digital video port selected: %c\n", |
2385 | (hdmi_read(sd, 0x00) & 0x03) + 'A'); | |
2386 | v4l2_info(sd, "HDCP encrypted content: %s\n", | |
2387 | (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); | |
76eb2d30 MR |
2388 | v4l2_info(sd, "HDCP keys read: %s%s\n", |
2389 | (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", | |
2390 | (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); | |
2391 | if (!is_hdmi(sd)) { | |
2392 | bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; | |
2393 | bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; | |
2394 | bool audio_mute = io_read(sd, 0x65) & 0x40; | |
2395 | ||
2396 | v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", | |
2397 | audio_pll_locked ? "locked" : "not locked", | |
2398 | audio_sample_packet_detect ? "detected" : "not detected", | |
2399 | audio_mute ? "muted" : "enabled"); | |
2400 | if (audio_pll_locked && audio_sample_packet_detect) { | |
2401 | v4l2_info(sd, "Audio format: %s\n", | |
2402 | (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); | |
2403 | } | |
2404 | v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + | |
2405 | (hdmi_read(sd, 0x5c) << 8) + | |
2406 | (hdmi_read(sd, 0x5d) & 0xf0)); | |
2407 | v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + | |
2408 | (hdmi_read(sd, 0x5e) << 8) + | |
2409 | hdmi_read(sd, 0x5f)); | |
2410 | v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); | |
2411 | ||
2412 | v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); | |
2413 | ||
54450f59 HV |
2414 | print_avi_infoframe(sd); |
2415 | } | |
2416 | ||
2417 | return 0; | |
2418 | } | |
2419 | ||
2420 | /* ----------------------------------------------------------------------- */ | |
2421 | ||
2422 | static const struct v4l2_ctrl_ops adv7604_ctrl_ops = { | |
2423 | .s_ctrl = adv7604_s_ctrl, | |
2424 | }; | |
2425 | ||
2426 | static const struct v4l2_subdev_core_ops adv7604_core_ops = { | |
2427 | .log_status = adv7604_log_status, | |
54450f59 HV |
2428 | .interrupt_service_routine = adv7604_isr, |
2429 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
2430 | .g_register = adv7604_g_register, | |
2431 | .s_register = adv7604_s_register, | |
2432 | #endif | |
2433 | }; | |
2434 | ||
2435 | static const struct v4l2_subdev_video_ops adv7604_video_ops = { | |
2436 | .s_routing = adv7604_s_routing, | |
2437 | .g_input_status = adv7604_g_input_status, | |
2438 | .s_dv_timings = adv7604_s_dv_timings, | |
2439 | .g_dv_timings = adv7604_g_dv_timings, | |
2440 | .query_dv_timings = adv7604_query_dv_timings, | |
54450f59 HV |
2441 | }; |
2442 | ||
2443 | static const struct v4l2_subdev_pad_ops adv7604_pad_ops = { | |
539b33b0 LP |
2444 | .enum_mbus_code = adv7604_enum_mbus_code, |
2445 | .get_fmt = adv7604_get_format, | |
2446 | .set_fmt = adv7604_set_format, | |
54450f59 HV |
2447 | .get_edid = adv7604_get_edid, |
2448 | .set_edid = adv7604_set_edid, | |
7515e096 | 2449 | .dv_timings_cap = adv7604_dv_timings_cap, |
afec5599 | 2450 | .enum_dv_timings = adv7604_enum_dv_timings, |
54450f59 HV |
2451 | }; |
2452 | ||
2453 | static const struct v4l2_subdev_ops adv7604_ops = { | |
2454 | .core = &adv7604_core_ops, | |
2455 | .video = &adv7604_video_ops, | |
2456 | .pad = &adv7604_pad_ops, | |
2457 | }; | |
2458 | ||
2459 | /* -------------------------- custom ctrls ---------------------------------- */ | |
2460 | ||
2461 | static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { | |
2462 | .ops = &adv7604_ctrl_ops, | |
2463 | .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, | |
2464 | .name = "Analog Sampling Phase", | |
2465 | .type = V4L2_CTRL_TYPE_INTEGER, | |
2466 | .min = 0, | |
2467 | .max = 0x1f, | |
2468 | .step = 1, | |
2469 | .def = 0, | |
2470 | }; | |
2471 | ||
2472 | static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = { | |
2473 | .ops = &adv7604_ctrl_ops, | |
2474 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, | |
2475 | .name = "Free Running Color, Manual", | |
2476 | .type = V4L2_CTRL_TYPE_BOOLEAN, | |
2477 | .min = false, | |
2478 | .max = true, | |
2479 | .step = 1, | |
2480 | .def = false, | |
2481 | }; | |
2482 | ||
2483 | static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = { | |
2484 | .ops = &adv7604_ctrl_ops, | |
2485 | .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, | |
2486 | .name = "Free Running Color", | |
2487 | .type = V4L2_CTRL_TYPE_INTEGER, | |
2488 | .min = 0x0, | |
2489 | .max = 0xffffff, | |
2490 | .step = 0x1, | |
2491 | .def = 0x0, | |
2492 | }; | |
2493 | ||
2494 | /* ----------------------------------------------------------------------- */ | |
2495 | ||
2496 | static int adv7604_core_init(struct v4l2_subdev *sd) | |
2497 | { | |
2498 | struct adv7604_state *state = to_state(sd); | |
d42010a1 | 2499 | const struct adv7604_chip_info *info = state->info; |
54450f59 HV |
2500 | struct adv7604_platform_data *pdata = &state->pdata; |
2501 | ||
2502 | hdmi_write(sd, 0x48, | |
2503 | (pdata->disable_pwrdnb ? 0x80 : 0) | | |
2504 | (pdata->disable_cable_det_rst ? 0x40 : 0)); | |
2505 | ||
2506 | disable_input(sd); | |
2507 | ||
2508 | /* power */ | |
2509 | io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ | |
2510 | io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ | |
2511 | cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ | |
2512 | ||
2513 | /* video format */ | |
2514 | io_write_and_or(sd, 0x02, 0xf0, | |
2515 | pdata->alt_gamma << 3 | | |
2516 | pdata->op_656_range << 2 | | |
54450f59 | 2517 | pdata->alt_data_sat << 0); |
539b33b0 LP |
2518 | io_write_and_or(sd, 0x05, 0xf1, pdata->blank_data << 3 | |
2519 | pdata->insert_av_codes << 2 | | |
2520 | pdata->replicate_av_codes << 1); | |
2521 | adv7604_setup_format(state); | |
54450f59 | 2522 | |
54450f59 | 2523 | cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ |
98908696 MB |
2524 | |
2525 | /* VS, HS polarities */ | |
2526 | io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | pdata->inv_hs_pol << 1); | |
f31b62e1 MK |
2527 | |
2528 | /* Adjust drive strength */ | |
2529 | io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | | |
2530 | pdata->dr_str_clk << 2 | | |
2531 | pdata->dr_str_sync); | |
2532 | ||
54450f59 HV |
2533 | cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ |
2534 | cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ | |
2535 | cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - | |
80939647 | 2536 | ADI recommended setting [REF_01, c. 2.3.3] */ |
54450f59 | 2537 | cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - |
80939647 | 2538 | ADI recommended setting [REF_01, c. 2.3.3] */ |
54450f59 HV |
2539 | cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution |
2540 | for digital formats */ | |
2541 | ||
5474b983 MR |
2542 | /* HDMI audio */ |
2543 | hdmi_write_and_or(sd, 0x15, 0xfc, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ | |
2544 | hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ | |
2545 | hdmi_write_and_or(sd, 0x68, 0xf9, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ | |
2546 | ||
54450f59 HV |
2547 | /* TODO from platform data */ |
2548 | afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ | |
2549 | ||
d42010a1 LPC |
2550 | if (adv7604_has_afe(state)) { |
2551 | afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ | |
2552 | io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); | |
2553 | } | |
54450f59 | 2554 | |
54450f59 | 2555 | /* interrupts */ |
d42010a1 | 2556 | io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ |
54450f59 | 2557 | io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ |
d42010a1 LPC |
2558 | io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ |
2559 | io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ | |
2560 | info->setup_irqs(sd); | |
54450f59 HV |
2561 | |
2562 | return v4l2_ctrl_handler_setup(sd->ctrl_handler); | |
2563 | } | |
2564 | ||
d42010a1 LPC |
2565 | static void adv7604_setup_irqs(struct v4l2_subdev *sd) |
2566 | { | |
2567 | io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ | |
2568 | } | |
2569 | ||
2570 | static void adv7611_setup_irqs(struct v4l2_subdev *sd) | |
2571 | { | |
2572 | io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ | |
2573 | } | |
2574 | ||
54450f59 HV |
2575 | static void adv7604_unregister_clients(struct adv7604_state *state) |
2576 | { | |
2577 | if (state->i2c_avlink) | |
2578 | i2c_unregister_device(state->i2c_avlink); | |
2579 | if (state->i2c_cec) | |
2580 | i2c_unregister_device(state->i2c_cec); | |
2581 | if (state->i2c_infoframe) | |
2582 | i2c_unregister_device(state->i2c_infoframe); | |
2583 | if (state->i2c_esdp) | |
2584 | i2c_unregister_device(state->i2c_esdp); | |
2585 | if (state->i2c_dpp) | |
2586 | i2c_unregister_device(state->i2c_dpp); | |
2587 | if (state->i2c_afe) | |
2588 | i2c_unregister_device(state->i2c_afe); | |
2589 | if (state->i2c_repeater) | |
2590 | i2c_unregister_device(state->i2c_repeater); | |
2591 | if (state->i2c_edid) | |
2592 | i2c_unregister_device(state->i2c_edid); | |
2593 | if (state->i2c_hdmi) | |
2594 | i2c_unregister_device(state->i2c_hdmi); | |
2595 | if (state->i2c_test) | |
2596 | i2c_unregister_device(state->i2c_test); | |
2597 | if (state->i2c_cp) | |
2598 | i2c_unregister_device(state->i2c_cp); | |
2599 | if (state->i2c_vdp) | |
2600 | i2c_unregister_device(state->i2c_vdp); | |
2601 | } | |
2602 | ||
2603 | static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd, | |
2604 | u8 addr, u8 io_reg) | |
2605 | { | |
2606 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
2607 | ||
2608 | if (addr) | |
2609 | io_write(sd, io_reg, addr << 1); | |
2610 | return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); | |
2611 | } | |
2612 | ||
d42010a1 LPC |
2613 | static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = { |
2614 | /* reset ADI recommended settings for HDMI: */ | |
2615 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
2616 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ | |
2617 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ | |
2618 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ | |
2619 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ | |
2620 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ | |
2621 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ | |
2622 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ | |
2623 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ | |
2624 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ | |
2625 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ | |
2626 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ | |
2627 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ | |
2628 | ||
2629 | /* set ADI recommended settings for digitizer */ | |
2630 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
2631 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ | |
2632 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ | |
2633 | { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ | |
2634 | { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ | |
2635 | { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ | |
2636 | ||
2637 | { ADV7604_REG_SEQ_TERM, 0 }, | |
2638 | }; | |
2639 | ||
2640 | static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = { | |
2641 | /* set ADI recommended settings for HDMI: */ | |
2642 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ | |
2643 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ | |
2644 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ | |
2645 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ | |
2646 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ | |
2647 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ | |
2648 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ | |
2649 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ | |
2650 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ | |
2651 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ | |
2652 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ | |
2653 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ | |
2654 | ||
2655 | /* reset ADI recommended settings for digitizer */ | |
2656 | /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ | |
2657 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ | |
2658 | { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ | |
2659 | ||
2660 | { ADV7604_REG_SEQ_TERM, 0 }, | |
2661 | }; | |
2662 | ||
2663 | static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = { | |
2664 | { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 }, | |
2665 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x0c }, | |
2666 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 }, | |
2667 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda }, | |
2668 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 }, | |
2669 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 }, | |
2670 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 }, | |
2671 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 }, | |
2672 | { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e }, | |
2673 | ||
2674 | { ADV7604_REG_SEQ_TERM, 0 }, | |
2675 | }; | |
2676 | ||
2677 | static const struct adv7604_chip_info adv7604_chip_info[] = { | |
2678 | [ADV7604] = { | |
2679 | .type = ADV7604, | |
2680 | .has_afe = true, | |
c784b1e2 | 2681 | .max_port = ADV7604_PAD_VGA_COMP, |
d42010a1 LPC |
2682 | .num_dv_ports = 4, |
2683 | .edid_enable_reg = 0x77, | |
2684 | .edid_status_reg = 0x7d, | |
2685 | .lcf_reg = 0xb3, | |
2686 | .tdms_lock_mask = 0xe0, | |
2687 | .cable_det_mask = 0x1e, | |
2688 | .fmt_change_digital_mask = 0xc1, | |
539b33b0 LP |
2689 | .formats = adv7604_formats, |
2690 | .nformats = ARRAY_SIZE(adv7604_formats), | |
d42010a1 LPC |
2691 | .set_termination = adv7604_set_termination, |
2692 | .setup_irqs = adv7604_setup_irqs, | |
2693 | .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, | |
2694 | .read_cable_det = adv7604_read_cable_det, | |
2695 | .recommended_settings = { | |
2696 | [0] = adv7604_recommended_settings_afe, | |
2697 | [1] = adv7604_recommended_settings_hdmi, | |
2698 | }, | |
2699 | .num_recommended_settings = { | |
2700 | [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), | |
2701 | [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), | |
2702 | }, | |
2703 | .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | | |
2704 | BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) | | |
2705 | BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | | |
2706 | BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) | | |
2707 | BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) | | |
2708 | BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) | | |
2709 | BIT(ADV7604_PAGE_VDP), | |
2710 | }, | |
2711 | [ADV7611] = { | |
2712 | .type = ADV7611, | |
2713 | .has_afe = false, | |
c784b1e2 | 2714 | .max_port = ADV7604_PAD_HDMI_PORT_A, |
d42010a1 LPC |
2715 | .num_dv_ports = 1, |
2716 | .edid_enable_reg = 0x74, | |
2717 | .edid_status_reg = 0x76, | |
2718 | .lcf_reg = 0xa3, | |
2719 | .tdms_lock_mask = 0x43, | |
2720 | .cable_det_mask = 0x01, | |
2721 | .fmt_change_digital_mask = 0x03, | |
539b33b0 LP |
2722 | .formats = adv7611_formats, |
2723 | .nformats = ARRAY_SIZE(adv7611_formats), | |
d42010a1 LPC |
2724 | .set_termination = adv7611_set_termination, |
2725 | .setup_irqs = adv7611_setup_irqs, | |
2726 | .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, | |
2727 | .read_cable_det = adv7611_read_cable_det, | |
2728 | .recommended_settings = { | |
2729 | [1] = adv7611_recommended_settings_hdmi, | |
2730 | }, | |
2731 | .num_recommended_settings = { | |
2732 | [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), | |
2733 | }, | |
2734 | .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) | | |
2735 | BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) | | |
2736 | BIT(ADV7604_PAGE_REP) | BIT(ADV7604_PAGE_EDID) | | |
2737 | BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP), | |
2738 | }, | |
2739 | }; | |
2740 | ||
54450f59 HV |
2741 | static int adv7604_probe(struct i2c_client *client, |
2742 | const struct i2c_device_id *id) | |
2743 | { | |
591b72fe HV |
2744 | static const struct v4l2_dv_timings cea640x480 = |
2745 | V4L2_DV_BT_CEA_640X480P59_94; | |
54450f59 HV |
2746 | struct adv7604_state *state; |
2747 | struct adv7604_platform_data *pdata = client->dev.platform_data; | |
2748 | struct v4l2_ctrl_handler *hdl; | |
2749 | struct v4l2_subdev *sd; | |
c784b1e2 | 2750 | unsigned int i; |
d42010a1 | 2751 | u16 val; |
54450f59 HV |
2752 | int err; |
2753 | ||
2754 | /* Check if the adapter supports the needed features */ | |
2755 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) | |
2756 | return -EIO; | |
2757 | v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n", | |
2758 | client->addr << 1); | |
2759 | ||
c02b211d | 2760 | state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); |
54450f59 HV |
2761 | if (!state) { |
2762 | v4l_err(client, "Could not allocate adv7604_state memory!\n"); | |
2763 | return -ENOMEM; | |
2764 | } | |
2765 | ||
d42010a1 LPC |
2766 | state->info = &adv7604_chip_info[id->driver_data]; |
2767 | ||
25a64ac9 MR |
2768 | /* initialize variables */ |
2769 | state->restart_stdi_once = true; | |
ff4f80fd | 2770 | state->selected_input = ~0; |
25a64ac9 | 2771 | |
54450f59 HV |
2772 | /* platform data */ |
2773 | if (!pdata) { | |
2774 | v4l_err(client, "No platform data!\n"); | |
c02b211d | 2775 | return -ENODEV; |
54450f59 | 2776 | } |
591b72fe HV |
2777 | state->pdata = *pdata; |
2778 | state->timings = cea640x480; | |
539b33b0 | 2779 | state->format = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8); |
54450f59 HV |
2780 | |
2781 | sd = &state->sd; | |
2782 | v4l2_i2c_subdev_init(sd, client, &adv7604_ops); | |
d42010a1 LPC |
2783 | snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", |
2784 | id->name, i2c_adapter_id(client->adapter), | |
2785 | client->addr); | |
54450f59 | 2786 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
54450f59 | 2787 | |
d42010a1 LPC |
2788 | /* |
2789 | * Verify that the chip is present. On ADV7604 the RD_INFO register only | |
2790 | * identifies the revision, while on ADV7611 it identifies the model as | |
2791 | * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. | |
2792 | */ | |
2793 | if (state->info->type == ADV7604) { | |
2794 | val = adv_smbus_read_byte_data_check(client, 0xfb, false); | |
2795 | if (val != 0x68) { | |
2796 | v4l2_info(sd, "not an adv7604 on address 0x%x\n", | |
2797 | client->addr << 1); | |
2798 | return -ENODEV; | |
2799 | } | |
2800 | } else { | |
2801 | val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8) | |
2802 | | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0); | |
2803 | if (val != 0x2051) { | |
2804 | v4l2_info(sd, "not an adv7611 on address 0x%x\n", | |
2805 | client->addr << 1); | |
2806 | return -ENODEV; | |
2807 | } | |
54450f59 HV |
2808 | } |
2809 | ||
2810 | /* control handlers */ | |
2811 | hdl = &state->hdl; | |
d42010a1 | 2812 | v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8); |
54450f59 HV |
2813 | |
2814 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2815 | V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); | |
2816 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2817 | V4L2_CID_CONTRAST, 0, 255, 1, 128); | |
2818 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2819 | V4L2_CID_SATURATION, 0, 255, 1, 128); | |
2820 | v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, | |
2821 | V4L2_CID_HUE, 0, 128, 1, 0); | |
2822 | ||
2823 | /* private controls */ | |
2824 | state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, | |
d42010a1 LPC |
2825 | V4L2_CID_DV_RX_POWER_PRESENT, 0, |
2826 | (1 << state->info->num_dv_ports) - 1, 0, 0); | |
54450f59 HV |
2827 | state->rgb_quantization_range_ctrl = |
2828 | v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops, | |
2829 | V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, | |
2830 | 0, V4L2_DV_RGB_RANGE_AUTO); | |
54450f59 HV |
2831 | |
2832 | /* custom controls */ | |
d42010a1 LPC |
2833 | if (adv7604_has_afe(state)) |
2834 | state->analog_sampling_phase_ctrl = | |
2835 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); | |
54450f59 HV |
2836 | state->free_run_color_manual_ctrl = |
2837 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL); | |
54450f59 HV |
2838 | state->free_run_color_ctrl = |
2839 | v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL); | |
54450f59 HV |
2840 | |
2841 | sd->ctrl_handler = hdl; | |
2842 | if (hdl->error) { | |
2843 | err = hdl->error; | |
2844 | goto err_hdl; | |
2845 | } | |
8c0eadb8 HV |
2846 | state->detect_tx_5v_ctrl->is_private = true; |
2847 | state->rgb_quantization_range_ctrl->is_private = true; | |
d42010a1 LPC |
2848 | if (adv7604_has_afe(state)) |
2849 | state->analog_sampling_phase_ctrl->is_private = true; | |
8c0eadb8 HV |
2850 | state->free_run_color_manual_ctrl->is_private = true; |
2851 | state->free_run_color_ctrl->is_private = true; | |
2852 | ||
54450f59 HV |
2853 | if (adv7604_s_detect_tx_5v_ctrl(sd)) { |
2854 | err = -ENODEV; | |
2855 | goto err_hdl; | |
2856 | } | |
2857 | ||
54450f59 HV |
2858 | state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4); |
2859 | state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5); | |
54450f59 HV |
2860 | state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8); |
2861 | state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9); | |
2862 | state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa); | |
2863 | state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb); | |
54450f59 | 2864 | state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd); |
d42010a1 | 2865 | if (!state->i2c_cec || !state->i2c_infoframe || !state->i2c_afe || |
54450f59 | 2866 | !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi || |
d42010a1 | 2867 | !state->i2c_cp) { |
54450f59 | 2868 | err = -ENOMEM; |
d42010a1 | 2869 | v4l2_err(sd, "failed to create digital i2c clients\n"); |
54450f59 HV |
2870 | goto err_i2c; |
2871 | } | |
2872 | ||
d42010a1 LPC |
2873 | if (adv7604_has_afe(state)) { |
2874 | state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3); | |
2875 | state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6); | |
2876 | state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7); | |
2877 | state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc); | |
2878 | state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe); | |
2879 | if (!state->i2c_avlink || !state->i2c_esdp || !state->i2c_dpp || | |
2880 | !state->i2c_test || !state->i2c_vdp) { | |
2881 | err = -ENOMEM; | |
2882 | v4l2_err(sd, "failed to create analog i2c clients\n"); | |
2883 | goto err_i2c; | |
2884 | } | |
2885 | } | |
54450f59 HV |
2886 | /* work queues */ |
2887 | state->work_queues = create_singlethread_workqueue(client->name); | |
2888 | if (!state->work_queues) { | |
2889 | v4l2_err(sd, "Could not create work queue\n"); | |
2890 | err = -ENOMEM; | |
2891 | goto err_i2c; | |
2892 | } | |
2893 | ||
2894 | INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, | |
2895 | adv7604_delayed_work_enable_hotplug); | |
2896 | ||
c784b1e2 LP |
2897 | state->source_pad = state->info->num_dv_ports |
2898 | + (state->info->has_afe ? 2 : 0); | |
2899 | for (i = 0; i < state->source_pad; ++i) | |
2900 | state->pads[i].flags = MEDIA_PAD_FL_SINK; | |
2901 | state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; | |
2902 | ||
2903 | err = media_entity_init(&sd->entity, state->source_pad + 1, | |
2904 | state->pads, 0); | |
54450f59 HV |
2905 | if (err) |
2906 | goto err_work_queues; | |
2907 | ||
2908 | err = adv7604_core_init(sd); | |
2909 | if (err) | |
2910 | goto err_entity; | |
2911 | v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, | |
2912 | client->addr << 1, client->adapter->name); | |
bedc3939 LPC |
2913 | |
2914 | err = v4l2_async_register_subdev(sd); | |
2915 | if (err) | |
2916 | goto err_entity; | |
2917 | ||
54450f59 HV |
2918 | return 0; |
2919 | ||
2920 | err_entity: | |
2921 | media_entity_cleanup(&sd->entity); | |
2922 | err_work_queues: | |
2923 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
2924 | destroy_workqueue(state->work_queues); | |
2925 | err_i2c: | |
2926 | adv7604_unregister_clients(state); | |
2927 | err_hdl: | |
2928 | v4l2_ctrl_handler_free(hdl); | |
54450f59 HV |
2929 | return err; |
2930 | } | |
2931 | ||
2932 | /* ----------------------------------------------------------------------- */ | |
2933 | ||
2934 | static int adv7604_remove(struct i2c_client *client) | |
2935 | { | |
2936 | struct v4l2_subdev *sd = i2c_get_clientdata(client); | |
2937 | struct adv7604_state *state = to_state(sd); | |
2938 | ||
2939 | cancel_delayed_work(&state->delayed_work_enable_hotplug); | |
2940 | destroy_workqueue(state->work_queues); | |
bedc3939 | 2941 | v4l2_async_unregister_subdev(sd); |
54450f59 HV |
2942 | v4l2_device_unregister_subdev(sd); |
2943 | media_entity_cleanup(&sd->entity); | |
2944 | adv7604_unregister_clients(to_state(sd)); | |
2945 | v4l2_ctrl_handler_free(sd->ctrl_handler); | |
54450f59 HV |
2946 | return 0; |
2947 | } | |
2948 | ||
2949 | /* ----------------------------------------------------------------------- */ | |
2950 | ||
2951 | static struct i2c_device_id adv7604_id[] = { | |
d42010a1 LPC |
2952 | { "adv7604", ADV7604 }, |
2953 | { "adv7611", ADV7611 }, | |
54450f59 HV |
2954 | { } |
2955 | }; | |
2956 | MODULE_DEVICE_TABLE(i2c, adv7604_id); | |
2957 | ||
2958 | static struct i2c_driver adv7604_driver = { | |
2959 | .driver = { | |
2960 | .owner = THIS_MODULE, | |
2961 | .name = "adv7604", | |
2962 | }, | |
2963 | .probe = adv7604_probe, | |
2964 | .remove = adv7604_remove, | |
2965 | .id_table = adv7604_id, | |
2966 | }; | |
2967 | ||
2968 | module_i2c_driver(adv7604_driver); |